A 45nm implementation with two embedded ROMs for programming the taps of the Finite Impulse Response filter. Cadence and Synopsys EDA tools used. Designed in Verilog at RTL, and simulated for desired operation using Xilinx Vivado.
Please refer to the report for power, timing, and area analyses between technology nodes 45, 90, and 180 nm. Single CNTRL.v verilog file attached consists of all modules into one file for use with RTL Compilers.