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incomplete_alphabetical_listing.json
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incomplete_alphabetical_listing.json
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{
"registers": [
{
"features": ["armv7"],
"reference": "<R%{reg_use}>",
"list": ["r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
"r9", "r10", "r11", "r12", "r13", "r14", "r15"],
"aliases": { "r13": "sp", "r14": "lr", "r15": "pc" }
},
{
"features": ["armv7"],
"reference": "<spec_reg>",
"list": ["aspr", "aspr_%{bits}", "cpsr", "cpsr_%{fields}"]
},
{
"features": ["vfp", "vfpv2", "vfpv3-d16", "vfpv4-d16",
"vfpv3-d32", "vfpv4-d32", "simd"],
"reference": "<S%{reg_use}>",
"list": ["s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8",
"s9", "s10", "s11", "s12", "s13", "s14", "s15"]
},
{
"features": ["vfpv2", "vfpv3-d16", "vfpv4-d16", "vfpv3-d32",
"vfpv4-d32", "simd"],
"reference": "<D%{reg_use}>",
"list": ["d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8",
"d9", "d10", "d11", "d12", "d13", "d14", "d15"]
},
{
"features": ["vfpv3-d32", "vfpv4-d32", "simd"],
"reference": "<D%{reg_use}>",
"list": ["d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
"d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"]
},
{
"features": ["simd"],
"reference": "<Q%{reg_use}>",
"list": ["q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8",
"q9", "q10", "q11", "q12", "q13", "q14", "q15"]
},
{
"features": ["coprocessor"],
"reference": "<coproc>",
"list": ["p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8",
"p9", "p10", "p11", "p12", "p13", "p14", "p15"]
},
{
"features": ["coprocessor"],
"reference": "<CR%{reg_use}>",
"list": ["c0", "c1", "c2", "c3", "c4", "c5", "c6", "c7", "c8",
"c9", "c10", "c11", "c12", "c13", "c14", "c15"]
}
],
"combined_suffixes": {
"reg_use": {
"d": "Destination",
"m": "First operand",
"n": "Second operand",
"s": "Shift amount",
"t": "Source",
"Hi": "Higher 32 bits",
"Lo": "Lower 32 bits"
},
"bits": {
"n": "Negative",
"z": "Zero",
"c": "Carry",
"v": "Overflow",
"q": "Saturating",
},
"fields": {
"f": "",
"s": "",
}
}
"variants": {
"c": {
"": "",
"eq": "(If APSR.Z == 1 [Equal])",
"ne": "(If APSR.Z == 0 [Not Equal])",
"cs": "(If APSR.C == 1 [Carry Set])",
"cc": "(If APSR.C == 0 [Carry Clear])",
"mi": "(If APSR.N == 1 [Minus])",
"pl": "(If APSR.N == 0 [Plus])",
"vs": "(If APSR.V == 1 [Overflow])",
"vc": "(If APSR.V == 0 [No Overflow])",
"hi": "(If APSR.C == 1 AND APSR.Z == 0 [Unsigned Higher])",
"ls": "(If APSR.C == 0 OR APSR.Z == 1 [Unsigned Lower])",
"ge": "(If APSR.N == APSR.V [Signed Greater or Equal])",
"lt": "(If APSR.N != APSR.V [Signed Lesser Than])",
"gt": "(If APSR.N == APSR.V AND APSR.Z == 0 [Signed Greater Than])",
"le": "(If APSR.N != APSR.V OR APSR.Z != 0 [Signed Lesser or Equal])",
"al": "(Always)"
},
"d": {
"": "",
"d": "Dual"
},
"dt": {
".f16": "(16 bits Float components)",
".f32": "(32 bits Float components)",
".f64": "(64 bits Float components)",
".i8": "(8 bits Integer components)",
".i16": "(16 bits Integer components)",
".i32": "(32 bits Integer components)",
".i64": "(64 bits Integer components)",
".s8": "(8 bits Signed Integer components)",
".s16": "(16 bits Signed Integer components)",
".s32": "(32 bits Signed Integer components)",
".s64": "(64 bits Signed Integer components)",
".u8": "(8 bits Unsigned Integer components)",
".u16": "(16 bits Unsigned Integer components)",
".u32": "(32 bits Unsigned Integer components)",
".u64": "(64 bits Unsigned Integer components)"
},
"h": {
"": "",
"h": "Halving"
},
"l": {
"": "",
"l": "Long"
},
"q": {
"": "",
".n": "(T 16bits encoding)",
".w": "(T/A 32bits encoding)"
},
"s": {
"": "",
"s": "(Update APSR)"
},
"u": {
"": "",
"u": "Unsigned"
},
"x": {
"": "",
"x": "with Exchange"
},
"amode": {
"db": "Decrement Before",
"da": "Decrement After",
"ea": "Empty Ascending",
"ed": "Empty Descending",
"fa": "Full Ascending",
"fd": "Full Descending",
"ia": "Increment After",
"ib": "Increment Before"
},
"bsize": {
"": "",
".8": ".8",
".16": ".16",
".32": ".32",
".64": ".64"
},
"bwsize": {
"": "",
".8": "Bytes",
".16": "Halfwords",
".32": "Words",
".64": "Doublewords"
},
"comparaisons": {
"gt": "Greater Than",
"ge": "Greater than or Equal",
"eq": "Equal",
"le": "Lesser than or Equal",
"lt": "Lesser Than"
},
"coproc_2": {
"": "",
"2": "(2nd T/A encoding)"
},
"coproc_l": {
"": "",
"l": "(D == 1 encoding)"
},
"cross_mult": {
"": "(Top x Top | Bottom x Bottom)",
"x": "(Top x Bottom | Bottom x Top)"
},
"exception": {
"": "",
"e": "(trigger Exceptions)"
},
"exclusive": {
"": "",
"ex": "Exclusive"
},
"half_parts": {
"": "",
"b": "(with Bottom half)",
"t": "(with Bottom top)",
"bb": "(Bottom half with Bottom half)",
"bt": "(Bottom half with Top half)",
"tb": "(Top half with Bottom half)",
"tt": "(Top half with Top half)"
},
"interrupt_state": {
"": "",
"ia": "(Enable Interrupt)",
"ID": "(Disable Interrupt)"
},
"it_conditions": {
"": "",
"t": "True",
"e": "False",
"tt": "True True",
"te": "True False",
"et": "False True",
"ee": "False False",
"ttt": "True True True",
"tte": "True True False",
"tet": "True False True",
"tee": "True False False",
"ett": "False True True",
"ete": "False True False",
"eet": "False False True",
"eee": "False False False",
"tttt": "True True True True",
"ttte": "True True True False",
"ttet": "True True False True",
"ttee": "True True False False",
"tett": "True False True True",
"tete": "True False True False",
"teet": "True False False True",
"teee": "True False False False",
"ettt": "False True True True",
"ette": "False True True False",
"etet": "False True False True",
"etee": "False True False False",
"eett": "False False True True",
"eete": "False False True False",
"eeet": "False False False True",
"eeee": "False False False False"
},
"mul_r": {
"": "(truncated results)",
"r": "(Rounded results)"
},
"negate": {
"": "",
"n": "Negate"
},
"non": {
"": "",
"n": "Non-"
},
"operations": {
"add": ["A", "Add"],
"sub": ["S", "Subtract"],
"accumulate": ["A", "Accumulate"],
"min": ["MIN", "Minimum"],
"max": ["MAX", "Maximum"]
},
"opmode": {
"": "",
"h": "Halving",
"q": "Saturating"
},
"pld_w": {
"": "(Read intent)",
"w": "(Write intent)"
},
"with_link": {
"": ""
},
"wsize": {
"": "",
"b": "Byte",
"sb": "Signed Byte",
"h": "Halfword",
"sh": "Signed Halfword",
"w": "Word",
"d": "Doubleword"
},
"vector_conversions": {
"": ""
},
"vsize": {
".8": "(8 bits components)",
".16": "(16 bits components)",
".32": "(32 bits components)",
".64": "(64 bits components)"
},
"shift_types": {
"ASR": "Arithmetic Shift Right",
"LSL": "Logical Shift Left",
"LSR": "Logical Shift Right",
"ROR": "ROtate Right"
},
"barrier_options": {
"": "Shareability domain: Full system, Access: RW",
"SY": "Shareability domain: Full system, Access: RW",
"ST": "Shareability domain: Full system, Access: W",
"SYST": "Shareability domain: Full system, Access: W",
"ISH": "Shareability domain: Inner Shareable, Access: RW",
"SH": "Shareability domain: Inner Shareable, Access: RW",
"ISHST": "Shareability domain: Inner Shareable, Access: W",
"SHST": "Shareability domain: Inner Shareable, Access: W",
"NSH": "Shareability domain: Non-shareable, Access: RW",
"UN": "Shareability domain: Non-shareable, Access: RW",
"NSHST": "Shareability domain: Non-shareable, Access: W",
"UNST": "Shareability domain: Non-shareable, Access: W",
"OSH": "Shareability domain: Outer Shareable, Access: RW",
"OSTST": "Shareability domain: Outer Shareable, Access: W"
}
},
"flags": {
"uncondtionnal": {
"c": {
"": "",
"al": "(Always)"
}
},
"simd_conditions": {
"c": {
"": "",
"al": "(Always)"
},
"q": {
"": "",
".w": ""
}
},
"arm_only": {
"q": {
"": ""
}
}
},
"ARM": {
"ADC%{s}%{c}%{q}": ["Add With Carry %{q} %{c} %{s}", {}, []],
"ADD%{s}%{c}%{q}": ["Add %{q} %{c} %{s}", {}, []],
"ADR%{c}%{q}": ["Add to PC %{q} %{c}", {}, []],
"AND%{s}%{c}%{q}": ["Bitwise AND %{q} %{c} %{s}", {}, []],
"ASR%{s}%{c}%{q}": ["Arithmetic Shift Right %{q} %{c} %{s}", {}, []],
"B%{c}%{q}": ["Branch %{q} %{c}", {}, ["thumb_conditions"]],
"BFC%{c}%{q}": ["Bit Field Clear %{q} %{c}", {}, []],
"BFI%{c}%{q}": ["Bit Field Insert %{q} %{c}", {}, []],
"BIC%{s}%{c}%{q}": ["Bitwise Bit Clear %{q} %{c} %{s}", {}, []],
"BKPT%{q}": ["Breakpoint %{q}", {}, ["unconditionnal"]],
"BL%{x}%{c}%{q}": ["Branch with Link %{x} %{q} %{c}", {}, []],
"BX%{c}%{q}": ["Branch and Exchange %{q} %{c}", {}, []],
"BXJ%{c}%{q}": ["Branch and Exchange Jazelle %{q} %{c}", {}, []],
"CB%{non}Z": ["Compare and Branch on %{non}Zero", {}, ["thumb_only", "unconditionnal"]],
"CDP%{coproc_2}%{c}%{q}": ["Coprocessor Data Processing %{coproc_2} %{q} %{c}", {}, ["unconditionnal"]],
"CHKA%{c}%{q}": ["Check Array %{q} %{c}", {}, ["thumbee_instruction"]],
"CLREX%{c}%{q}": ["Clear-Exclusive %{q} %{c}", {}, ["unconditionnal"]],
"CLZ%{c}%{q}": ["Count Leading Zeros %{q} %{c}", {}, []],
"CMN%{c}%{q}": ["Compare Negative %{q} %{c}", {}, []],
"CMP%{c}%{q}": ["Compare %{q} %{c}", {}, []],
"CPS%{interrupt_state}%{q}": ["Change Processor State %{interrupt_state}", {}, ["unconditionnal"]],
"CPY": ["Copy (pre-UAL equivalent to MOV)", {}, ["pre_ual"]],
"DBG%{c}%{q}": ["Debug Hint %{q} %{c}", {}, ["hint"]],
"DMB%{c}%{q}": ["Data Memory Barrier %{q} %{c}", {}, ["unconditionnal"]],
"DSB%{c}%{q}": ["Data Synchronization Barrier %{q} %{c}", {}, ["unconditionnal"]],
"ENTERX%{q}": ["Change Thumb state to ThumbEE state", {}, ["uncondtionnal", "thumb_only"]],
"EOR%{s}%{c}%{q}": ["Bitwise Exclusive OR %{q} %{c} %{s}", {}, ["flag_updater"]],
"ERET%{c}%{q}": ["Exception Return %{q} %{c}", {}, []],
"HB%{with_link}%{c}%{q}": ["Handler Branch %{with_link} %{q} %{c}", {}, ["thumbee_instruction"]],
"HBLP%{c}%{q}": ["Handler Branch with Link and Parameter %{q} %{c}", {}, ["thumbee_instruction"]],
"HBP%{c}%{q}": ["Handler Branch with Parameter %{q} %{c}", {}, ["thumbee_instruction"]],
"HVC%{q}": ["Hypervisor Call %{q}", {}, ["unconditionnal"]],
"ISB%{c}%{q}": ["Instruction Synchronization Barrier %{q} %{c}", {}, ["unconditionnal"]],
"IT%{it_conditions}%{q}": ["If-Then %{it_conditions} %{q}", {}, ["thumb_only", "it_conditions"]],
"LDC%{coproc_2}%{coproc_l}%{c}%{q}": ["Load Coprocessor %{coproc_2} %{coproc_l} %{q} %{c}", {}, ["coprocessor_encodings", "uncondtionnal"]],
"LDM%{amode}%{c}%{q}": ["Load Multiple %{amode} %{q} %{c}", {"amode": {"": "ia", "ia": "fd", "da": "fa", "db": "ea", "ib": "ed"}}, []],
"LDR%{exclusive}%{wsize}%{c}%{q}": ["Load Register %{exclusive} %{wsize} %{q} %{c}", {"wsize": ["", "b", "h", "d"]}, []],
"LDR%{wsize}T%{c}%{q}": ["Load Register %{wsize} Unprivileged %{q} %{c}", {"wsize": ["", "b", "sb", "h", "sh"]}, []],
"LDR%{wsize}%{c}%{q}": ["Load Register Exclusive %{wsize} %{q} %{c}", {"wsize": ["", "b", "h", "d"]}, []],
"LDRSB%{c}%{q}": ["Load Signed Byte %{q} %{c}", {}, []],
"LDRSH%{c}%{q}": ["Load Signed Halfword %{q} %{c}", {}, []],
"LEAVEX%{q}": ["Change ThumbEE state to Thumb state %{q}", {}, ["uncondtionnal", "thumbee_instruction"]],
"LSL%{s}%{c}%{q}": ["Logical Shift Left %{q} %{c} %{s}", {}, ["flag_updater"]],
"LSR%{s}%{c}%{q}": ["Logical Shift Right %{q} %{c} %{s}", {}, ["flag_updater"]],
"MCR%{coproc_2}%{c}%{q}": ["Move to Coprocessor from ARM core register %{coproc_2} %{q} %{c}", {}, ["coprocessor_encodings", "unconditionnal"]],
"MCRR%{coproc_2}%{c}%{q}": ["Move to Coprocessor from two ARM core registers %{coproc_2} %{q} %{c}", {}, ["coprocessor_encodings", "unconditionnal"]],
"MLA%{s}%{c}%{q}": ["Multiply Accumulate %{q} %{c} %{s}", {}, ["flag_updater"]],
"MLS%{c}%{q}": ["Multiply and Subtract %{q} %{c}", {}, ["flag_updater"]],
"MOV%{s}%{c}%{q}": ["Move %{q} %{c} %{s}", {}, ["flag_updater"]],
"MOVT%{c}%{q}": ["Move Top %{q} %{c}", {}, []],
"MRC%{coproc_2}%{c}%{q}": ["Move to ARM core register from Coprocessor %{coproc_2} %{q} %{c}", {}, ["coprocessor_encodings", "unconditionnal"]],
"MRRC%{coproc_2}%{c}%{q}": ["Move to two ARM core registers from Coprocessor %{coproc_2} %{q} %{c}", {}, ["coprocessor_encodings", "unconditionnal"]],
"MRS%{c}%{q}": ["Move to Register from Special register %{q} %{c}", {}, []],
"MSR%{c}%{q}": ["Move to Special register from ARM core register %{q} %{c}", {}, []],
"MUL%{s}%{c}%{q}": ["Multiply %{q} %{c} %{s}", {}, ["flag_updater"]],
"MVN%{s}%{c}%{q}": ["Bitwise NOT %{q} %{c} %{s}", {}, ["flag_updater"]],
"NEG%{c}%{q}": ["Pre-UAL equivalent to RSB (Right Shift Byte) %{q} %{c}", {}, ["flag_updater"]],
"NOP%{c}%{q}": ["No Operation %{q} %{c}", {}, []],
"ORN%{s}%{c}%{q}": ["Bitwise OR NOT %{q} %{c} %{s}", {}, ["flag_updater"]],
"ORR%{s}%{c}%{q}": ["Bitwise OR %{q} %{c} %{s}", {}, ["flag_updater"]],
"PKH%{half_parts}%{c}%{q}": ["Pack Halfword %{half_parts} %{q} %{c}", {"half_parts": ["bt", "tb"]}, ["half_and_half"]],
"PLD%{pld_w}%{c}%{q}": ["Preload Data %{pld_w} %{q} %{c}", {}, ["unconditionnal"]],
"PLI%{c}%{q}": ["Preload Instruction %{q} %{c}", {}, ["unconditionnal"]],
"POP%{c}%{q}": ["Pop Multiple Registers %{q} %{c}", {}, []],
"PUSH%{c}%{q}": ["Push Multiple Registers %{q} %{c}", {}, []],
"Q%{d}%{operations}%{bsize}%{c}%{q}": ["Saturating %{d} %{operations} %{bsize} %{q} %{c}", {"operations": ["add", "sub"], "bsize": ["", ".8", ".16"]}, ["flag_updater"]],
"QASX%{c}%{q}": ["Saturating Add and Subtract with Exchange %{q} %{c}", {}, []],
"QSAX%{c}%{q}": ["Saturating Subtract and Add with Exchange %{q} %{c}", {}, []],
"RBIT%{c}%{q}": ["Reverse Bits %{q} %{c}", {}, []],
"REV%{c}%{q}": ["Byte-Reverse Word %{q} %{c}", {}, []],
"REV16%{c}%{q}": ["Byte-Reverse Packed Halfword %{q} %{c}", {}, []],
"REVSH%{c}%{q}": ["Byte-Reverse Signed Halfword %{q} %{c}", {}, []],
"RFE%{amode}%{c}%{q}": ["Return From Exception %{amode} %{q} %{c}", {"amode": {"": "ia", "da": "fa", "db": "ea", "ia": "fd", "ib": "ed"}}, []],
"ROR%{s}%{c}%{q}": ["Rotate Right %{q} %{c} %{s}", {}, ["flag_updater"]],
"RRX%{s}%{c}%{q}": ["Rotate Right with Extend %{q} %{c} %{s}", {}, ["flag_updater"]],
"RSB%{s}%{c}%{q}": ["Reverse Subtract %{q} %{c} %{s}", {}, ["flag_updater"]],
"RSC%{s}%{c}%{q}": ["Reverse Subtract with Carry %{q} %{c} %{s}", {}, ["flag_updater"]],
"S%{operations}%{bsize}%{c}%{q}": ["Signed %{operations} %{bsize} %{q} %{c}", {"operations": ["add", "sub"], "bsize": ["", ".8", ".16"]}, []],
"SASX%{c}%{q}": ["Signed Add and Subtract with Exchange %{q} %{c}", {}, []],
"SBC%{c}%{q}": ["Subtract with Carry %{q} %{c}", {}, ["flag_updater"]],
"SBFX%{c}%{q}": ["Signed Bit Field Extract %{q} %{c}", {}, []],
"SDIV%{c}%{q}": ["Signed Divide %{q} %{c}", {}, []],
"SEL%{c}%{q}": ["Select Bytes %{q} %{c}", {}, []],
"SETEND%{c}%{q}": ["Set Endianness %{q} %{c}", {}, ["unconditionnal"]],
"SEV%{c}%{q}": ["Send Event %{q} %{c}", {}, []],
"SHADD16%{c}%{q}": ["Signed Halving Add 16 %{q} %{c}", {}, []],
"SHADD8%{c}%{q}": ["Signed Halving Add 8 %{q} %{c}", {}, []],
"SHASX%{c}%{q}": ["Signed Halving Add and Subtract with Exchange %{q} %{c}", {}, []],
"SHSAX%{c}%{q}": ["Signed Halving Subtract and Add with Exchange %{q} %{c}", {}, []],
"SHSUB16%{c}%{q}": ["Signed Halving Subtract 16 %{q} %{c}", {}, []],
"SHSUB8%{c}%{q}": ["Signed Halving Subtract 8 %{q} %{c}", {}, []],
"SMC%{c}%{q}": ["Secure Monitor Call %{q} %{c}", {}, []],
"SMLA%{half_parts}%{c}%{q}": ["Signed Multiply Accumulate (halfwords) %{half_parts} %{q} %{c}", {"half_parts": ["bb", "bt", "tb", "tt"]}, []],
"SMLA%{l}D%{cross_mult}%{c}%{q}": ["Signed Multiply Accumulate %{l} Dual %{cross_mult} %{q} %{c}", {}, []],
"SMLAL%{s}%{c}%{q}": ["Signed Multiply Accumulate Long %{q} %{c} %{s}", {}, ["flag_updater"]],
"SMLAL%{half_parts}%{c}%{q}": ["Signed Multiply Accumulate Long (halfwords) %{q} %{c}", {"half_parts": ["bb", "bt", "tb", "tt"]}, []],
"SMLAW%{half_parts}%{c}%{q}": ["Signed Multiply Accumulate (word by halfword) %{q} %{c}", {"half_parts": ["b", "t"]}, ["half_parts"]],
"SMLS%{l}D%{cross_mult}%{c}%{q}": ["Signed Multiply Subtract %{l} Dual %{cross_mult} %{q} %{c}", {}, []],
"SMML%{operations}%{mul_r}%{c}%{q}": ["Signed Most Significant Word Multiply %{operations} %{mul_r} %{q} %{c}", {"operations": ["accumulate", "sub"]}, []],
"SMMUL%{mul_r}%{c}%{q}": ["Signed Most Significant Word Multiply %{mul_r} %{q} %{c}", {}, []],
"SMUAD%{cross_mult}%{c}%{q}": ["Signed Dual Multiply Add %{cross_mult} %{q} %{c}", {}, []],
"SMUL%{half_parts}%{c}%{q}": ["Signed Multiply (halfwords) %{half_parts} %{q} %{c}", {}, []],
"SMULL%{s}%{c}%{q}": ["Signed Multiply Long %{s} %{q} %{c}", {}, []],
"SMULW%{half_parts}%{c}%{q}": ["Signed Multiply (word by halfword) %{q} %{c}", {"half_parts": ["b", "t"]}, ["last_half_part"]],
"SMUSD%{cross_mult}%{c}%{q}": ["Signed Multiply Subtract Dual %{cross_mult} %{q} %{c}", {}, []],
"SRS%{amode}%{c}%{q}": ["Store Return State %{q} %{c}", {"amode": {"": "ia", "ia": "ea", "db": "fd"}}, []],
"SSAT%{c}%{q}": ["Signed Saturate %{q} %{c}", {}, []],
"SSAT16%{c}%{q}": ["Signed Saturate 16 %{q} %{c}", {}, []],
"SSAX%{c}%{q}": ["Signed Subtract and Add with Exchange %{q} %{c}", {}, []],
"SSUB16%{c}%{q}": ["Signed Subtract 16 %{q} %{c}", {}, []],
"SSUB8%{c}%{q}": ["Signed Subtract 8 %{q} %{c}", {}, []],
"STC%{coproc_l}%{coproc_2}%{c}%{q}": ["Store Coprocessor %{q} %{c}", {}, ["unconditionnal"]],
"STM%{amode}%{c}%{q}": ["Store Multiple %{amode} %{q} %{c}", {"amode": {"": "ia", "da": "ed", "db": "fd", "ia": "ea", "ib": "fa"}}, []],
"STR%{exclusive}%{wsize}%{c}%{q}": ["Store Register %{exclusive} %{wsize} %{q} %{c}", {"wsize": ["", "b", "h", "d"]}, []],
"STRBT%{c}%{q}": ["Store Register Byte Unprivileged %{q} %{c}", {}, []],
"STRHT%{c}%{q}": ["Store Register Halfword Unprivileged %{q} %{c}", {}, []],
"STRT%{c}%{q}": ["Store Register Unprivileged %{q} %{c}", {}, []],
"SUB%{s}%{c}%{q}": ["Subtract %{q} %{c} %{s}", {}, []],
"SVC%{c}%{q}": ["Supervisor Call %{q} %{c}", {}, []],
"SWP%{wsize}%{c}%{q}": ["Swap %{q} %{c}", {"wsize": ["", "b"]}, ["deprecated", "byte_suffix"]],
"SXTAB%{c}%{q}": ["Signed Extend and Add Byte %{q} %{c}", {}, []],
"SXTAB16%{c}%{q}": ["Signed Extend and Add Byte 16 %{q} %{c}", {}, []],
"SXTAH%{c}%{q}": ["Signed Extend and Add Halfword %{q} %{c}", {}, []],
"SXTB%{c}%{q}": ["Signed Extend Byte %{q} %{c}", {}, []],
"SXTB16%{c}%{q}": ["Signed Extend Byte 16 %{q} %{c}", {}, []],
"SXTH%{c}%{q}": ["Signed Extend Halfword %{q} %{c}", {}, []],
"TBB%{c}%{q}": ["Table Branch Byte", {}, ["thumb_only"]],
"TBH%{c}%{q}": ["Table Branch Halfword", {}, ["thumb_only"]],
"TEQ%{c}%{q}": ["Test Equivalence %{q} %{c}", {}, []],
"TST%{c}%{q}": ["Test %{q} %{c}", {}, []],
"U%{opmode}%{operations}%{bsize}%{c}%{q}": ["Unsigned %{opmode} %{operations} %{bsize} %{q} %{c}", {"opmode": ["", "h", "q"], "operations": ["add", "sub"], "bsize": [".8", ".16"]}, []],
"UASX%{c}%{q}": ["Unsigned Add and Subtract with Exchange %{q} %{c}", {}, []],
"UBFX%{c}%{q}": ["Unsigned Bit Field Extract %{q} %{c}", {}, []],
"UDF%{c}%{q}": ["Undefined %{q} %{c}", {}, ["uncondtionnal", "undefined"]],
"UDIV%{c}%{q}": ["Unsigned Divide %{q} %{c}", {}, []],
"UHASX%{c}%{q}": ["Unsigned Halving Add and Subtract with Exchange %{q} %{c}", {}, []],
"UHSAX%{c}%{q}": ["Unsigned Halving Subtract and Add with Exchange %{q} %{c}", {}, []],
"UMAAL%{c}%{q}": ["Unsigned Multiply Accumulate Accumulate Long %{q} %{c}", {}, []],
"UMLAL%{s}%{c}%{q}": ["Unsigned Multiply Accumulate Long %{q} %{c} %{s}", {}, ["flag_updater"]],
"UMULL%{s}%{c}%{q}": ["Unsigned Multiply Long %{q} %{c} %{s}", {}, ["flag_updater"]],
"UQASX%{c}%{q}": ["Unsigned Saturating Add and Subtract with Exchange %{q} %{c}", {}, []],
"UQSAX%{c}%{q}": ["Unsigned Saturating Subtract and Add with Exchange %{q} %{c}", {}, []],
"USAD8%{c}%{q}": ["Unsigned Sum of Absolute Differences %{q} %{c}", {}, []],
"USADA8%{c}%{q}": ["Unsigned Sum of Absolute Differences and Accumulate %{q} %{c}", {}, []],
"USAT%{c}%{q}": ["Unsigned Saturate %{q} %{c}", {}, []],
"USAT16%{c}%{q}": ["Unsigned Saturate 16 %{q} %{c}", {}, []],
"USAX%{c}%{q}": ["Unsigned Subtract and Add with Exchange %{q} %{c}", {}, []],
"USUB16%{c}%{q}": ["Unsigned Subtract 16 %{q} %{c}", {}, []],
"USUB8%{c}%{q}": ["Unsigned Subtract 8 %{q} %{c}", {}, []],
"UXTAB%{c}%{q}": ["Unsigned Extend and Add Byte %{q} %{c}", {}, []],
"UXTAB16%{c}%{q}": ["Unsigned Extend and Add Byte 16 %{q} %{c}", {}, []],
"UXTAH%{c}%{q}": ["Unsigned Extend and Add Halfword %{q} %{c}", {}, []],
"UXTB%{c}%{q}": ["Unsigned Extend Byte %{q} %{c}", {}, []],
"UXTB16%{c}%{q}": ["Unsigned Extend Byte 16 %{q} %{c}", {}, []],
"UXTH%{c}%{q}": ["Unsigned Extend Halfword %{q} %{c}", {}, []],
"VABA%{l}%{c}%{q}%{dt}": ["Vector Absolute Difference and Accumulate %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VABD%{l}%{c}%{q}%{dt}": ["Vector Absolute Difference %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".f32"]}, ["simd_conditions"]],
"VABS%{c}%{q}%{dt}": ["Vector Absolute %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".f32", ".f64"]}, ["simd_conditions"]],
"VAC%{comparaisons}%{c}%{q}%{dt}": ["Vector Absolute Compare %{comparaisons} %{q} %{c}", {"comparaisons": ["ge", "gt", "le", "lt"], "dt": [".f32"]}, ["simd_conditions"]],
"VADD%{c}%{q}%{dt}": ["Vector Add %{dt} %{q} %{c}", {"dt": [".i8", ".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VADDHN%{c}%{q}%{dt}": ["Vector Add and Narrow %{dt} %{q} %{c}", {"dt": [".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VADDL%{c}%{q}%{dt}": ["Vector Add Long %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VADDW%{c}%{q}%{dt}": ["Vector Add Wide %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VAND%{c}%{q}%{dt}": ["Vector Bitwise AND %{dt} %{q} %{c}", {"dt": ["ignored"]}, ["simd_conditions"]],
"VBIC%{c}%{q}%{dt}": ["Vector Bitwise Bit Clear %{dt} %{q} %{c}", {"dt": [".i16", ".i32"]}, []],
"VBIF%{c}%{q}%{dt}": ["Vector Bitwise Insert if False %{dt} %{q} %{c}", {"dt": ["ignored"]}, ["simd_conditions"]],
"VBIT%{c}%{q}%{dt}": ["Vector Bitwise Insert if True %{dt} %{q} %{c}", {"dt": ["ignored"]}, ["simd_conditions"]],
"VBSL%{c}%{q}%{dt}": ["Vector Bitwise Select %{dt} %{q} %{c}", {"dt": ["ignored"]}, ["simd_conditions"]],
"VC%{comparaisons}%{c}%{q}%{dt}": ["Vector Compare %{comparaisons} %{dt} %{q} %{c}", {"comparaisons": ["eq", "ge", "gt", "le", "lt"], "dt": [".i8", ".i16", ".i32", ".f32"]}, ["simd_conditions"]],
"VCLS%{c}%{q}%{dt}": ["Vector Count Leading Sign Bits %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32"]}, ["simd_conditions"]],
"VCLT%{c}%{q}%{dt}": ["Vector Compare Less Than Zero %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32"]}, ["simd_conditions"]],
"VCLZ%{c}%{q}%{dt}": ["Vector Count Leading Zeros %{dt} %{q} %{c}", {"dt": [".i8", ".i16", ".i32"]}, ["simd_conditions"]],
"VCMP%{exception}%{c}%{q}%{dt}": ["Vector Compare %{exception} %{dt} %{q} %{c}", {"dt": [".f32", ".f64"]}, []],
"VCNT%{c}%{q}.8": ["Vector Count 1 bits %{q} %{c}", {}, ["simd_conditions"]],
"VCVT%{c}%{q}%{vector_conversions}": ["Vector Convert between integer and floating-point %{vector_conversions} %{q} %{c}", {"vector_conversions": [".s32", ".f32", ".u32", ".f32", ".s32", ".f64", ".u32", ".f64", ".f16", ".f32", ".s16", ".f32", ".s16", ".f64", ".u16", ".f32", ".u16", ".f64"]}, []],
"VCVTB%{c}%{q}%{vector_conversions}": ["Vector Convert Bottom %{vector_conversions} %{q} %{c}", {"vector_conversions": [".f16", ".f32"]}, []],
"VCVTR%{c}%{q}%{vector_conversions}": ["Vector Convert Rounding %{vector_conversions} %{q} %{c}", {"vector_conversions": [".s32", ".f32", ".u32", ".f32", ".s32", ".f64", ".u32", ".f64"]}, []],
"VCVTT%{c}%{q}%{vector_conversions}": ["Vector Convert Top %{vector_conversions} %{q} %{c}", {"vector_conversions": [".f16", ".f32"]}, []],
"VDIV%{c}%{q}%{dt}": ["Vector Divide %{dt} %{q} %{c}", {"dt": [".f32", ".f64"]}, []],
"VDUP%{c}%{q}%{vsize}": ["Vector Duplicate %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["vector_size", "simd_conditions"]],
"VEOR%{c}%{q}%{dt}": ["Vector Bitwise Exclusive OR %{dt} %{q} %{c}", {"dt": ["ignored"]}, ["simd_conditions"]],
"VEXT%{c}%{q}%{vsize}": ["Vector Extract %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32", ".64"]}, ["simd_conditions"]],
"VF%{negate}M%{operations}%{c}%{q}%{dt}": ["Vector Fused %{negate} Multiply %{dt} %{q} %{c}", {"operations": ["accumulate", "sub"], "dt": [".f32", ".f64"]}, ["simd_conditions"]],
"VH%{operations}%{c}%{q}%{dt}": ["Vector Halving %{operations} %{dt} %{q} %{c}", {"operations": ["add", "sub"], "dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VLD1%{c}%{q}.%{vsize}": ["Vector Load (multiple single elements) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32", ".64"]}, ["simd_conditions"]],
"VLD2%{c}%{q}.%{vsize}": ["Vector Load (multiple 2-elements structures) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VLD3%{c}%{q}.%{vsize}": ["Vector Load (multiple 3-elements structures) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32", ".64"]}, ["simd_conditions"]],
"VLD4%{c}%{q}.%{vsize}": ["Vector Load (multiple 4-elements structures) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32", ".64"]}, ["simd_conditions"]],
"VLDM%{c}%{q}.%{vsize}": ["Vector Load Multiple %{vsize} %{q} %{c}", {"amode": ["ia", "db"], "vsize": [".32", ".64"]}, []],
"VLDR%{c}%{q}.%{vsize}": ["Vector Load Register %{vsize} %{q} %{c}", {"vsize": [".32", ".64"]}, []],
"VMAX%{c}%{q}%{dt}": ["Vector Maximum %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".f32"]}, ["simd_conditions"]],
"VMIN%{c}%{q}%{dt}": ["Vector Minimum %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".f32"]}, ["simd_conditions"]],
"VML%{operations}%{l}%{c}%{q}%{dt}": ["Vector Multiply and %{operations} %{l} %{dt} %{q} %{c}", {"operations": ["accumulate", "sub"], "dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".i8", ".i16", ".i32", ".f32", ".f64"]}, ["simd_conditions"]],
"VMOV%{c}%{q}%{dt}": ["Vector Move %{dt} %{q} %{c}", {"dt": [".i8", ".i16", ".i32", ".i64", ".f32", ".f64"]}, []],
"VMOVL%{c}%{q}%{dt}": ["Vector Move Long %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VMOVN%{c}%{q}%{dt}": ["Vector Move and Narrow %{dt} %{q} %{c}", {"dt": [".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VMRS%{c}%{q}": ["Vector Move to ARM core register %{q} %{c}", {}, []],
"VMSR%{c}%{q}": ["Vector Move to Advanced SIMD and Floating-Point Extension System Register from ARM core register %{q} %{c}", {}, []],
"VMUL%{c}%{q}%{dt}": ["Vector Multiply %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".i8", ".i16", ".i32", ".p8", ".f32", ".f64"]}, ["simd_conditions"]],
"VMULL%{c}%{q}%{dt}": ["Vector Multiply Long %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".i8", ".i16", ".i32", ".p8", ".f32"]}, ["simd_conditions"]],
"VMVN%{c}%{q}%{dt}": ["Vector Bitwise NOT %{dt} %{q} %{c}", {"dt": ["all"]}, ["simd_conditions"]],
"VNEG%{c}%{q}%{dt}": ["Vector Negate %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".f32", ".f64"]}, ["simd_conditions"]],
"VNML%{operations}%{c}%{q}%{dt}": ["Vector Negate Multiply and %{operations} %{dt} %{q} %{c}", {"operations": ["accumulate", "sub"], "dt": [".f32", ".f64"]}, []],
"VNMUL%{c}%{q}%{dt}": ["Vector Negate Multiply %{dt} %{q} %{c}", {"dt": [".f32", ".f64"]}, []],
"VORN%{c}%{q}%{dt}": ["Vector Bitwise OR NOT %{dt} %{q} %{c}", {"dt": ["ignored"]}, ["simd_conditions"]],
"VORR%{c}%{q}%{dt}": ["Vector Bitwise OR %{dt} %{q} %{c}", {"dt": ["ignored"]}, ["simd_conditions"]],
"VPADAL%{c}%{q}%{dt}": ["Vector Pairwise Add and Accumulate Long %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VPADD%{c}%{q}%{dt}": ["Vector Pairwise Add %{dt} %{q} %{c}", {"dt": [".i8", ".i16", ".i32", ".f32"]}, ["simd_conditions"]],
"VPADDL%{c}%{q}%{dt}": ["Vector Pairwise Add Long %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VP%{operations}%{c}%{q}%{dt}": ["Vector Pairwise %{operations} %{dt} %{q} %{c}", {"operations": ["min", "max"], "dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".f32"]}, ["simd_conditions"]],
"VPOP%{c}%{q}%{vsize}": ["Vector Pop multiple registers %{vsize} %{q} %{c}", {"vsize": ["", ".32", ".64"]}, []],
"VPUSH%{c}%{q}%{vsize}": ["Vector Push multiple registers %{vsize} %{q} %{c}", {"vsize": ["", ".32", ".64"]}, []],
"VQABS%{c}%{q}%{dt}": ["Vector Saturating Absolute %{dt} %{q} %{c}", {"dt": [".s16", ".s32", ".s64"]}, ["simd_conditions"]],
"VQADD%{c}%{q}%{dt}": ["Vector Saturating Add %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VQDML%{operations}L%{c}%{q}%{dt}": ["Vector Saturating Doubling Multiply %{operations} Long %{dt} %{q} %{c}", {"operations": ["accumulate", "sub"], "dt": [".s16", ".s32"]}, ["simd_conditions"]],
"VQDMULH%{c}%{q}%{dt}": ["Vector Saturating Doubling Multiply Returning High Half %{dt} %{q} %{c}", {"dt": [".s16", ".s32"]}, ["simd_conditions"]],
"VQDMULL%{c}%{q}%{dt}": ["Vector Saturating Doubling Multiply Long %{dt} %{q} %{c}", {"dt": [".s16", ".s32"]}, ["simd_conditions"]],
"VQMOVN%{c}%{q}%{dt}": ["Vector Move and Narrow %{dt} %{q} %{c}", {"dt": [".s16", ".s32", ".s64", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VQMOVUN%{c}%{q}%{dt}": ["Vector Move Unsigned and Narrow %{dt} %{q} %{c}", {"dt": [".s16", ".s32", ".s64"]}, ["simd_conditions"]],
"VQNEG%{c}%{q}%{dt}": ["Vector Saturate Negate %{dt} %{q} %{c}", {"dt": [".s16", ".s32", ".s64"]}, ["simd_conditions"]],
"VQRDMULH%{c}%{q}%{dt}": ["Vector Saturating Rounding Doubling Multiply Returning High Half %{dt} %{q} %{c}", {"dt": [".s16", ".s32"]}, ["simd_conditions"]],
"VQRSHL%{c}%{q}%{dt}": ["Vector Saturating Rounding Shift Left %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VQRSHRN%{c}%{q}%{dt}": ["Vector Saturating Rounding Shift Right Narrow %{dt} %{q} %{c}", {"dt": [".s16", ".s32", ".s64", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VQRSHRUN%{c}%{q}%{dt}": ["Vector Saturating Rounding Shift Right Unsigned Narrow %{dt} %{q} %{c}", {"dt": [".s16", ".s32", ".s64"]}, ["simd_conditions"]],
"VQSHL%{c}%{q}%{dt}": ["Vector Saturating Shift Left %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VQSHLU%{c}%{q}%{dt}": ["Vector Saturating Shift Left Unsigned %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64"]}, ["simd_conditions"]],
"VQSHRN%{c}%{q}%{dt}": ["Vector Saturating Shift Right Narrow %{dt} %{q} %{c}", {"dt": [".s16", ".s32", ".s64", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VQSHRUN%{c}%{q}%{dt}": ["Vector Saturating Shift Right Unsigned Narrow %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64"]}, ["simd_conditions"]],
"VQSUB%{c}%{q}%{dt}": ["Vector Saturating Subtract %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VRADDHN%{c}%{q}%{dt}": ["Vector Rounding Add and Narrow %{dt} %{q} %{c}", {"dt": [".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VRECPE%{c}%{q}%{dt}": ["Vector Reciprocal Estimate %{dt} %{q} %{c}", {"dt": [".u32", ".f32"]}, ["simd_conditions"]],
"VRECPS%{c}%{q}%{dt}": ["Vector Reciprocal Step %{dt} %{q} %{c}", {"dt": [".f32"]}, ["simd_conditions"]],
"VREV%{bwsize}%{c}%{q}%{vsize}": ["Vector Reverse in %{bwsize} %{vsize} %{q} %{c}", {"bwsize": [".16", ".32", ".64"], "vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VRHADD%{c}%{q}%{dt}": ["Vector Rounding Halving Add %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VRSHL%{c}%{q}%{dt}": ["Vector Rounding Shift Left %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VRSHR%{c}%{q}%{dt}": ["Vector Rounding Shift Right %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VRSHRN%{c}%{q}%{dt}": ["Vector Rounding Shift Right and Narrow %{dt} %{q} %{c}", {"dt": [".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VRSQRTE%{c}%{q}%{dt}": ["Vector Reciprocal Square Root Estimate %{dt} %{q} %{c}", {"dt": [".u32", ".f32"]}, ["simd_conditions"]],
"VRSQRTS%{c}%{q}%{dt}": ["Vector Reciprocal Square Root Step %{dt} %{q} %{c}", {"dt": [".f32"]}, ["simd_conditions"]],
"VRSRA%{c}%{q}%{dt}": ["Vector Rounding Shift Right and Accumulate %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VRSUBHN%{c}%{q}%{dt}": ["Vector Rounding Subtract and Narrow %{dt} %{q} %{c}", {"dt": [".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VSHL%{c}%{q}%{dt}": ["Vector Shift Left %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64", ".i8", ".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VSHLL%{c}%{q}%{dt}": ["Vector Shift Left Long %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32", ".i8", ".i16", ".i32"]}, ["simd_conditions"]],
"VSHR%{c}%{q}%{dt}": ["Vector Shift Right %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VSHRN%{c}%{q}%{dt}": ["Vector Shift Right Narrow %{dt} %{q} %{c}", {"dt": [".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VSLI%{c}%{q}%{vsize}": ["Vector Shift Left and Insert %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32", ".64"]}, ["simd_conditions"]],
"VSQRT%{c}%{q}%{dt}": ["Vector Square Root %{dt} %{q} %{c}", {"dt": [".f32", ".f64"]}, []],
"VSRA%{c}%{q}%{dt}": ["Vector Shift Right and Accumulate %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".s64", ".u8", ".u16", ".u32", ".u64"]}, ["simd_conditions"]],
"VSRI%{c}%{q}%{vsize}": ["Vector Shift Right and Insert %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32", ".64"]}, ["simd_conditions"]],
"VST1%{c}%{q}%{vsize}": ["Vector Store (multiple single elements) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32", ".64"]}, ["simd_conditions"]],
"VST2%{c}%{q}%{vsize}": ["Vector Store (multiple 2-elements structures) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VST3%{c}%{q}%{vsize}": ["Vector Store (multiple 3-elements structures) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VST4%{c}%{q}%{vsize}": ["Vector Store (multiple 4-elements structures) %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VSTM%{c}%{q}%{vsize}": ["Vector Store Multiple %{vsize} %{q} %{c}", {"amode": ["ia", "db"], "vsize": [".32", ".64"]}, []],
"VSTR%{c}%{q}%{vsize}": ["Vector Store Register %{vsize} %{q} %{c}", {"vsize": [".32", ".64"]}, []],
"VSUB%{c}%{q}%{dt}": ["Vector Subtract %{dt} %{q} %{c}", {"dt": [".i8", ".i16", ".i32", ".i64", ".f32", ".f64"]}, ["simd_conditions"]],
"VSUBHN%{c}%{q}%{dt}": ["Vector Subtract and Narrow %{dt} %{q} %{c}", {"dt": [".i16", ".i32", ".i64"]}, ["simd_conditions"]],
"VSUBL%{c}%{q}%{dt}": ["Vector Subtract Long %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VSUBW%{c}%{q}%{dt}": ["Vector Subtract Wide %{dt} %{q} %{c}", {"dt": [".s8", ".s16", ".s32", ".u8", ".u16", ".u32"]}, ["simd_conditions"]],
"VSWP%{c}%{q}%{dt}": ["Vector Swap %{q} %{c}", {}, ["simd_conditions"]],
"VTBL%{c}%{q}.8": ["Vector Table Lookup %{q} %{c}", {}, ["simd_conditions"]],
"VTBX%{c}%{q}.8": ["Vector Table Extension %{q} %{c}", {}, ["simd_conditions"]],
"VTRN%{c}%{q}%{vsize}": ["Vector Transpose %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VTST%{c}%{q}%{vsize}": ["Vector Test %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VUZP%{c}%{q}%{vsize}": ["Vector Unzip %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"VZIP%{c}%{q}%{vsize}": ["Vector Zip %{vsize} %{q} %{c}", {"vsize": [".8", ".16", ".32"]}, ["simd_conditions"]],
"WFE%{c}%{q}": ["Wait for Event %{q} %{c}", {}, []],
"WFI%{c}%{q}": ["Wait for Interrupt %{q} %{c}", {}, []],
"YIELD%{c}%{q}": ["Yield %{q} %{c}", {}, []]
}
}