From 6265c2dcaa5481bca6876afa62b4ee6d7477dc4b Mon Sep 17 00:00:00 2001
From: Tom Lendacky <thomas.lendacky@amd.com>
Date: Tue, 19 Sep 2023 08:54:51 -0500
Subject: [PATCH] vc: Update unhandled #VC message information

Update to the unhandled #VC message to print the the RIP in hexadecimal
and include the CR2 register, which can be relative to the #VC taken.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
 src/cpu/sys.rs | 13 +++++++++++++
 src/cpu/vc.rs  |  3 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/cpu/sys.rs b/src/cpu/sys.rs
index 56b1956..854f556 100644
--- a/src/cpu/sys.rs
+++ b/src/cpu/sys.rs
@@ -12,6 +12,19 @@ use core::arch::asm;
 /// Bit 12
 pub const EFER_SVME: u64 = BIT!(12);
 
+/// Read Cr2
+pub fn read_cr2() -> u64 {
+    let cr2: u64;
+
+    unsafe {
+        asm!("mov {0}, cr2",
+             out(reg) cr2,
+             options(nostack));
+    }
+
+    cr2
+}
+
 /// Read MSR
 pub fn rdmsr(msr: u32) -> u64 {
     let lo: u32;
diff --git a/src/cpu/vc.rs b/src/cpu/vc.rs
index 22aba95..5b340be 100644
--- a/src/cpu/vc.rs
+++ b/src/cpu/vc.rs
@@ -269,9 +269,10 @@ fn vc_msr_protocol(request: u64) -> u64 {
 
 pub extern "x86-interrupt" fn vc_handler(stack_frame: InterruptStackFrame, error_code: u64) {
     let rip: u64 = stack_frame.instruction_pointer.as_u64();
+    let cr2: u64 = read_cr2();
 
     prints!(
-        "Unhandled #VC exception: {:#?}\n{:#?}\nRIP={rip}\n",
+        "Unhandled #VC exception: {:#x}\n{:#?}\nRIP={rip:#x}, CR2={cr2:#x}\n",
         error_code,
         stack_frame
     );