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christophe0606christophe0606
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CMSIS-DSP: Test framework improvement
Enabled MMU for A32.
1 parent c67252c commit ea3ac96

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9 files changed

+277
-111
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9 files changed

+277
-111
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‎CMSIS/DSP/Platforms/IPSS/ARMCA32/Include/ARMCA32.h

+30-50
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,14 @@
2525
* limitations under the License.
2626
*/
2727

28+
/*
29+
30+
31+
None of above values have been checked !
32+
33+
*/
34+
35+
2836
#ifndef __ARMCA32_H__
2937
#define __ARMCA32_H__
3038

@@ -33,8 +41,24 @@ extern "C" {
3341
#endif
3442

3543

36-
/* ------------------------- Interrupt Number Definition ------------------------ */
44+
/******************************************************************************/
45+
/* Peripheral memory map */
46+
/******************************************************************************/
47+
48+
/* Peripheral and RAM base address */
49+
#define VE_A32_NORMAL (0x00000000UL) /*!< (FLASH0 ) Base Address */
50+
#define VE_A32_PERIPH (0x13000000UL) /*!< (FLASH0 ) Base Address */
51+
#define VE_A32_NORMAL2 (0x14000000UL)
3752

53+
/* -------- Configuration of the Cortex-A32 Processor and Core Peripherals ------- */
54+
#define __CA_REV 0x0000U /*!< Core revision r0p0 */
55+
#define __CORTEX_A 32U /*!< Cortex-A32 Core */
56+
#define __FPU_PRESENT 1U /* FPU present */
57+
#define __GIC_PRESENT 1U /* GIC present */
58+
#define __TIM_PRESENT 1U /* TIM present */
59+
#define __L2C_PRESENT 0U /* L2C present */
60+
61+
/** Device specific Interrupt IDs */
3862
typedef enum IRQn
3963
{
4064
/****** SGI Interrupts Numbers ****************************************/
@@ -55,7 +79,7 @@ typedef enum IRQn
5579
SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */
5680
SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */
5781

58-
/****** Cortex-A5 Processor Exceptions Numbers ****************************************/
82+
/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
5983
GlobalTimer_IRQn = 27, /*!< Global Timer Interrupt */
6084
PrivTimer_IRQn = 29, /*!< Private Timer Interrupt */
6185
PrivWatchdog_IRQn = 30, /*!< Private Watchdog Interrupt */
@@ -79,54 +103,10 @@ typedef enum IRQn
79103
VFS2_IRQn = 73, /*!< VFS2 Interrupt */
80104
} IRQn_Type;
81105

82-
/******************************************************************************/
83-
/* Peripheral memory map */
84-
/******************************************************************************/
85-
86-
/* Peripheral and RAM base address */
87-
#define VE_A5_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
88-
#define VE_A5_MP_FLASH_BASE1 (0x0C000000UL) /*!< (FLASH1 ) Base Address */
89-
#define VE_A5_MP_SRAM_BASE (0x14000000UL) /*!< (SRAM ) Base Address */
90-
#define VE_A5_MP_PERIPH_BASE_CS2 (0x18000000UL) /*!< (Peripheral ) Base Address */
91-
#define VE_A5_MP_VRAM_BASE (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS2) /*!< (VRAM ) Base Address */
92-
#define VE_A5_MP_ETHERNET_BASE (0x02000000UL + VE_A5_MP_PERIPH_BASE_CS2) /*!< (ETHERNET ) Base Address */
93-
#define VE_A5_MP_USB_BASE (0x03000000UL + VE_A5_MP_PERIPH_BASE_CS2) /*!< (USB ) Base Address */
94-
#define VE_A5_MP_PERIPH_BASE_CS3 (0x1C000000UL) /*!< (Peripheral ) Base Address */
95-
#define VE_A5_MP_DAP_BASE (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (LOCAL DAP ) Base Address */
96-
#define VE_A5_MP_SYSTEM_REG_BASE (0x00010000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (SYSTEM REG ) Base Address */
97-
#define VE_A5_MP_SERIAL_BASE (0x00030000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (SERIAL ) Base Address */
98-
#define VE_A5_MP_AACI_BASE (0x00040000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (AACI ) Base Address */
99-
#define VE_A5_MP_MMCI_BASE (0x00050000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (MMCI ) Base Address */
100-
#define VE_A5_MP_KMI0_BASE (0x00060000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (KMI0 ) Base Address */
101-
#define VE_A5_MP_UART_BASE (0x00090000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (UART ) Base Address */
102-
#define VE_A5_MP_WDT_BASE (0x000F0000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (WDT ) Base Address */
103-
#define VE_A5_MP_TIMER_BASE (0x00110000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (TIMER ) Base Address */
104-
#define VE_A5_MP_DVI_BASE (0x00160000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (DVI ) Base Address */
105-
#define VE_A5_MP_RTC_BASE (0x00170000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (RTC ) Base Address */
106-
#define VE_A5_MP_UART4_BASE (0x001B0000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (UART4 ) Base Address */
107-
#define VE_A5_MP_CLCD_BASE (0x001F0000UL + VE_A5_MP_PERIPH_BASE_CS3) /*!< (CLCD ) Base Address */
108-
#define VE_A5_MP_PRIVATE_PERIPH_BASE (0x2C000000UL) /*!< (Peripheral ) Base Address */
109-
#define VE_A5_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST ) Base Address */
110-
#define VE_A5_MP_GIC_INTERFACE_BASE (0x00000100UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */
111-
#define VE_A5_MP_PRIVATE_TIMER (0x00000600UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (PTIM ) Base Address */
112-
#define VE_A5_MP_PL310_BASE (0x000F0000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310 ) Base Address */
113-
#define VE_A5_MP_SSRAM_BASE (0x2E000000UL) /*!< (System SRAM) Base Address */
114-
#define VE_A5_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */
115-
#define GIC_DISTRIBUTOR_BASE VE_A5_MP_GIC_DISTRIBUTOR_BASE
116-
#define GIC_INTERFACE_BASE VE_A5_MP_GIC_INTERFACE_BASE
117-
#define TIMER_BASE VE_A5_MP_PRIVATE_TIMER
118-
119-
//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache.
120-
//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort.
121-
#define L2C_310_BASE VE_A5_MP_PL310_BASE
122-
123-
/* -------- Configuration of the Cortex-A5 Processor and Core Peripherals ------- */
124-
#define __CA_REV 0x0000U /* Core revision r0p0 */
125-
#define __CORTEX_A 5U /* Cortex-A5 Core */
126-
#define __FPU_PRESENT 1U /* FPU present */
127-
#define __GIC_PRESENT 1U /* GIC present */
128-
#define __TIM_PRESENT 1U /* TIM present */
129-
#define __L2C_PRESENT 0U /* L2C present */
106+
// To allow inclusion of core_ca.h but those symbols are not used in our code
107+
#define GIC_DISTRIBUTOR_BASE 0
108+
#define GIC_INTERFACE_BASE 0
109+
#define TIMER_BASE 0
130110

131111
#include "core_ca.h"
132112
#include <system_ARMCA32.h>

‎CMSIS/DSP/Platforms/IPSS/ARMCA32/LinkScripts/AC6/mem_ARMCA32.h

+4-4
Original file line numberDiff line numberDiff line change
@@ -69,14 +69,14 @@
6969
// </h>
7070
*----------------------------------------------------------------------------*/
7171
//#define __RAM_BASE 0x80200000#
72-
#define __RAM_BASE 0x0500000
73-
#define __RAM_SIZE 0x00700000
72+
#define __RAM_BASE 0x00100000
73+
#define __RAM_SIZE 0x00200000
7474

7575
#define __RW_DATA_SIZE 0xF0000
7676
#define __ZI_DATA_SIZE 0x00200000
7777

7878
#define __STACK_SIZE 0x00007000
79-
#define __HEAP_SIZE 0x00200000
79+
#define __HEAP_SIZE 0x00100000
8080

8181
#define __UND_STACK_SIZE 0x00000100
8282
#define __ABT_STACK_SIZE 0x00000100
@@ -95,7 +95,7 @@
9595
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
9696
// </h>
9797
*----------------------------------------------------------------------------*/
98-
#define __TTB_BASE 0x80500000
98+
#define __TTB_BASE 0x00300000
9999
#define __TTB_SIZE 0x00005000
100100

101101

‎CMSIS/DSP/Platforms/IPSS/ARMCA32/Startup/AC6/startup_ARMCA32.c

+15-50
Original file line numberDiff line numberDiff line change
@@ -105,69 +105,34 @@ void Reset_Handler(void) {
105105
"LDR R0, =Vectors \n"
106106
"MCR p15, 0, R0, c12, c0, 0 \n"
107107

108-
"LDR r0,=Image$$TTB$$ZI$$Base \n"
109-
"MCR p15, 0, r0, c2, c0, 0 \n"
110-
111-
"LDR r0, =0xFFFFFFFF \n"
112-
"MCR p15, 0, r0, c3, c0, 0 \n" // Write Domain Access Control Register
113-
114-
);
115-
116-
#if defined(__ARM_NEON) || defined(__ARM_FP)
117-
//----------------------------------------------------------------
118-
// Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
119-
// Enables Full Access i.e. in both privileged and non privileged modes
120-
//----------------------------------------------------------------
121-
__ASM volatile(
122-
"MRC p15, 0, r0, c1, c0, 2 \n" // Read Coprocessor Access Control Register (CPACR)
123-
"ORR r0, r0, #(0xF << 20) \n" // Enable access to CP 10 & 11
124-
"MCR p15, 0, r0, c1, c0, 2 \n" // Write Coprocessor Access Control Register (CPACR)
125-
"ISB \n"
126-
127-
//----------------------------------------------------------------
128-
// Switch on the VFP and NEON hardware
129-
//----------------------------------------------------------------
130-
131-
"MOV r0, #0x40000000 \n"
132-
"VMSR FPEXC, r0 \n" // Write FPEXC register, EN bit set
133-
);
134-
#endif
135-
136-
__ASM volatile(
137-
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
138-
139-
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
140-
"BIC R0, R0, #(0x1 << 12) \n"
141-
"BIC R0, R0, #(0x1 << 2) \n"
142-
"BIC R0, R0, #0x2 \n" // Clear A bit 1 to disable strict alignment fault checking
143-
"ORR R0, R0, #(0x1 << 11) \n" // Set Z bit 11 to enable branch prediction
144-
//"BIC R0, R0, #(0x1 << 13)
145-
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
146-
"ISB \n"
108+
// Setup Stack for each exceptional mode
109+
"CPS #0x11 \n"
110+
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
111+
"CPS #0x12 \n"
112+
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
113+
"CPS #0x13 \n"
114+
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
115+
"CPS #0x17 \n"
116+
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
117+
"CPS #0x1B \n"
118+
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
119+
"CPS #0x1F \n"
120+
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
147121

148122
// Call SystemInit
149123
"BL SystemInit \n"
150124

151125
// Unmask interrupts
152-
//"CPSIE if \n"
126+
"CPSIE if \n"
153127

154128
// Call __main
155129
"BL __main \n"
156130
);
157131
}
158132

159-
void enable_caches(void)
160-
{
161-
__ASM volatile(
162133

163-
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
164-
"ORR R0, R0, #(0x1 << 12) \n" // Set I bit 12 to enable I Cache
165-
"ORR R0, R0, #(0x1 << 2) \n" // Set C bit 2 to enable D Cache
166-
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
167-
"ISB \n"
168134

169-
);
170-
}
135+
171136
/*----------------------------------------------------------------------------
172137
Default Handler for Exceptions / Interrupts
173138
*----------------------------------------------------------------------------*/

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