From cd1f9bc7b7db47f5c767cc5cd7c3c99e2b384279 Mon Sep 17 00:00:00 2001 From: Albert Huang <58316522+AlbertHuang-CPU@users.noreply.github.com> Date: Wed, 21 Jul 2021 17:15:50 +0800 Subject: [PATCH 1/2] Update core_cm33.h Correct a typo. --- CMSIS/Core/Include/core_cm33.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMSIS/Core/Include/core_cm33.h b/CMSIS/Core/Include/core_cm33.h index f9cf6ab183..83ea311851 100644 --- a/CMSIS/Core/Include/core_cm33.h +++ b/CMSIS/Core/Include/core_cm33.h @@ -519,7 +519,7 @@ typedef struct __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ From 57a5b1f926c7fa06b7113f2d6c6f7c301b54fdf7 Mon Sep 17 00:00:00 2001 From: Albert Huang <58316522+AlbertHuang-CPU@users.noreply.github.com> Date: Fri, 24 Jun 2022 15:45:53 +0800 Subject: [PATCH 2/2] Update core_cm33.h update file header --- CMSIS/Core/Include/core_cm33.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMSIS/Core/Include/core_cm33.h b/CMSIS/Core/Include/core_cm33.h index 83ea311851..a6fcc315c1 100644 --- a/CMSIS/Core/Include/core_cm33.h +++ b/CMSIS/Core/Include/core_cm33.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.2.2 - * @date 04. June 2021 + * @version V5.2.3 + * @date 24. June 2022 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved.