From a405989e14d76dd14a100e9103f0f97d8041abf0 Mon Sep 17 00:00:00 2001 From: Mingming Liu Date: Tue, 20 Sep 2022 08:57:39 -0700 Subject: [PATCH] [main] Add feature macro __ARM_FEATURE_RCPC (#199) To guard the usage of Load-AcquirePC instructions in inline assembly, https://reviews.llvm.org/D127798 introduces macro __ARM_FEATURE_RCPC in Clang/LLVM. This patch documents the existence of the feature MACRO, and its use case. Co-authored-by: Sam Elliott Co-authored-by: Sam Elliott --- main/acle.md | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/main/acle.md b/main/acle.md index ac22257e..36d1adf6 100644 --- a/main/acle.md +++ b/main/acle.md @@ -3,8 +3,8 @@ title: Arm C Language Extensions version: 2022Q2 date-of-issue: 01 Jul 2022 # LaTeX specific variables -copyright-text: Copyright 2011-2022 Arm Limited and/or its affiliates . -draftversion: false +copyright-text: "Copyright: see section \\texorpdfstring{\\nameref{copyright}}{Copyright}." +draftversion: true # Jekyll specific variables header_counter: true toc: true @@ -12,6 +12,7 @@ toc: true @@ -113,7 +114,8 @@ about Arm’s trademarks. ## Copyright -Copyright 2011-2022 Arm Limited and/or its affiliates . +* Copyright 2011-2022 Arm Limited and/or its affiliates . +* Copyright 2022 Google LLC. ## About this document @@ -312,6 +314,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin * Fixes for [Function Multi Versioning](#function-multi-versioning): * typo in `FEAT_DPB2`. * added `FEAT_LS64*`. +* Added feature detection macro `__ARM_FEATURE_RCPC` for RCpc (Release Consistent processor consistent) model at [RCpc](#rcpc). ### References @@ -1505,6 +1508,25 @@ execution state. Intrinsics for the use of these instructions are specified in [memcpy family of operations intrinsics - MOPS](#memcpy-family-of-operations-intrinsics---mops) +### RCPC + +`__ARM_FEATURE_RCPC` is set if the weaker RCpc (Release Consistent +processor consistent) model is supported. It is undefined otherwise. +The value indicates the set of Load-Acquire and Store-Release +instructions available. The intention is to allow programmers to guard +the usage of these instructions in inline assembly. + +| **Value** | **Feature** | **Instructions** | **Availability** | +| --------- | ----------- |-------------------------------- | ------------------------- | +| 1 | FEAT_LRCPC | LDAPR* instructions | Armv8.4, optional Armv8.2 | +| 2 | FEAT_LRCPC2 | LDAPUR* and STLUR* instructions | Armv8.3, optional Armv8.2 | + +If defined, the value of `__ARM_FEATURE_RCPC` remains consistent with the decimal +value of `LRCPC` field (bits [23:20]) in the `ID_AA64ISAR1_EL1` register. + +The `__ARM_FEATURE_RCPC` macro can only be implemented in the AArch64 +execution state. + ## Floating-point and vector hardware ### Hardware floating point @@ -2136,6 +2158,7 @@ be found in [[BA]](#BA). | [`__ARM_FEATURE_PAC_DEFAULT`](#pointer-authentication) | Pointer authentication | 0x5 | | [`__ARM_FEATURE_QBIT`](#q-saturation-flag) | Q (saturation) flag (32-bit-only) | 1 | | [`__ARM_FEATURE_QRDMX`](#rounding-doubling-multiplies) | SQRDMLxH instructions and associated intrinsics availability | 1 | +| [`__ARM_FEATURE_RCPC`](#rcpc) | Release Consistent processor consistent Model (64-bit-only) | 1 | | [`__ARM_FEATURE_RNG`](#random-number-generation-extension) | Random Number Generation Extension (Armv8.5-A) | 1 | | [`__ARM_FEATURE_SAT`](#saturation-instructions) | Width-specified saturation instructions (32-bit-only) | 1 | | [`__ARM_FEATURE_SHA2`](#sha2-extension) | SHA2 Crypto extension (Arm v8-A) | 1 |