DAPLink with NXP MK20DX128VFM5: pinout question

[ericbhs]

Hello,

I found the following schematic for the DAPLink debugger with NXP MK20DX128VFM5:
https://github.com/ARMmbed/mbed-HDK-Eagle-Projects/tree/master/DAPLink/Interface%20Schematics/K20DX/v1.0.0

I also found the source code that I was able to compile without problem with Keil uVision:
https://github.com/ARMmbed/DAPLink

However looking on the "IO_config.h" header file...
https://github.com/ARMmbed/DAPLink/blob/main/source/hic_hal/freescale/k20dx/IO_Config.h
...I found the pinout definitions rather confusing. While the 3 most important pins are the same (SWCLK, SWDIO and nRESET), there are some other pins that I do not see defined on the schematic:

• SWDIO In Pin (PTC7)
• SWDIO Neg. Output Enable Pin (PTB0)
• SWD Neg. Enable Pin (PTA4)

What are those pins for ?

The LEDs are also not defined at the same pins but I guess those are regular GPIO pins that can me mapped to any pins.

Thanx in advance !

Best regards

Eric

[flit]

These extra signals are present on the NXP OpenSDA version of the schematic (OpenSDA is what the Mbed HDK circuit was derived from), and are used for voltage translator control.

You can see this circuit in the schematic for the NXP FRDM-K64F board, available here:
https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F

I didn't actually realise that the Mbed HDK version of the K20 circuit was missing the voltage translators. Apparently it will still work, just with some toggling of unconnected pins.

[ericbhs]

Thanks a lot for your answer Chris !
I thought about using a bi-directional TI TXB0106 level-shifter in order to not have to worry about signal direction.
Best regards