-
Notifications
You must be signed in to change notification settings - Fork 53
/
Copy pathcortex-m.ts
291 lines (251 loc) · 9.86 KB
/
cortex-m.ts
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
/*
* DAPjs
* Copyright Arm Limited 2018
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
import { ADI } from '../dap';
import {
DebugRegister,
CoreRegister,
DhcsrMask,
DfsrMask,
DcrsrMask,
CoreState,
NvicRegister,
AircrMask,
DemcrMask
} from './enums';
import { Processor } from './';
import { DAPOperation } from '../proxy';
/**
* @hidden
*/
const EXECUTE_TIMEOUT = 10000;
/**
* @hidden
*/
const BKPT_INSTRUCTION = 0xBE2A;
/**
* @hidden
*/
const GENERAL_REGISTER_COUNT = 12;
/**
* Cortex M class
*/
export class CortexM extends ADI implements Processor {
private enableDebug() {
return this.writeMem32(DebugRegister.DHCSR, DhcsrMask.DBGKEY | DhcsrMask.C_DEBUGEN);
}
protected readCoreRegisterCommand(register: number): DAPOperation[] {
return this.writeMem32Command(DebugRegister.DCRSR, register)
.concat(this.readMem32Command(DebugRegister.DHCSR))
.concat(this.readMem32Command(DebugRegister.DCRDR));
}
protected writeCoreRegisterCommand(register: number, value: number): DAPOperation[] {
return this.writeMem32Command(DebugRegister.DCRDR, value)
.concat(this.writeMem32Command(DebugRegister.DCRSR, register | DcrsrMask.REGWnR));
}
/**
* Get the state of the processor core
* @returns Promise of CoreState
*/
public async getState(): Promise<CoreState> {
const dhcsr = await this.readMem32(DebugRegister.DHCSR);
let state: CoreState;
if (dhcsr & DhcsrMask.S_LOCKUP) state = CoreState.LOCKUP;
else if (dhcsr & DhcsrMask.S_SLEEP) state = CoreState.SLEEPING;
else if (dhcsr & DhcsrMask.S_HALT) state = CoreState.DEBUG;
else state = CoreState.RUNNING;
if (dhcsr & DhcsrMask.S_RESET_ST) {
// The core has been reset, check if an instruction has run
const newDhcsr = await this.readMem32(DebugRegister.DHCSR);
if (newDhcsr & DhcsrMask.S_RESET_ST && !(newDhcsr & DhcsrMask.S_RETIRE_ST)) {
return CoreState.RESET;
} else {
return state;
}
} else {
return state;
}
}
/**
* Whether the target is halted
* @returns Promise of halted state
*/
public async isHalted(): Promise<boolean> {
const dhcsr = await this.readMem32(DebugRegister.DHCSR);
return !!(dhcsr & DhcsrMask.S_HALT);
}
/**
* Halt the target
* @param wait Wait until halted before returning
* @param timeout Milliseconds to wait before aborting wait
* @returns Promise
*/
public async halt(wait: boolean = true, timeout: number = 0): Promise<void> {
const halted = await this.isHalted();
if (halted) {
return;
}
await this.writeMem32(DebugRegister.DHCSR, DhcsrMask.DBGKEY | DhcsrMask.C_DEBUGEN | DhcsrMask.C_HALT);
if (!wait) {
return;
}
return this.waitDelay(() => this.isHalted(), timeout);
}
/**
* Resume a target
* @param wait Wait until resumed before returning
* @param timeout Milliseconds to wait before aborting wait
* @returns Promise
*/
public async resume(wait: boolean = true, timeout: number = 0) {
const halted = await this.isHalted();
if (!halted) {
return;
}
await this.writeMem32(DebugRegister.DFSR, DfsrMask.DWTTRAP | DfsrMask.BKPT | DfsrMask.HALTED);
await this.enableDebug();
if (!wait) {
return;
}
return this.waitDelay(async () => {
const result = await this.isHalted();
return !result;
}, timeout);
}
/**
* Read from a core register
* @param register The register to read
* @returns Promise of value
*/
public async readCoreRegister(register: CoreRegister): Promise<number> {
const results = await this.transferSequence([
this.writeMem32Command(DebugRegister.DCRSR, register),
this.readMem32Command(DebugRegister.DHCSR)
]);
const dhcsr = results[0];
if (!(dhcsr & DhcsrMask.S_REGRDY)) {
throw new Error('Register not ready');
}
return this.readMem32(DebugRegister.DCRDR);
}
/**
* Read an array of core registers
* @param registers The registers to read
* @returns Promise of register values in an array
*/
public async readCoreRegisters(registers: CoreRegister[]): Promise<number[]> {
const results: number[] = [];
for (const register of registers) {
const result = await this.readCoreRegister(register);
results.push(result);
}
return results;
}
/**
* Write to a core register
* @param register The register to write to
* @param value The value to write
* @returns Promise
*/
public async writeCoreRegister(register: CoreRegister, value: number): Promise<void> {
const results = await this.transferSequence([
this.writeMem32Command(DebugRegister.DCRDR, value),
this.writeMem32Command(DebugRegister.DCRSR, register | DcrsrMask.REGWnR),
this.readMem32Command(DebugRegister.DHCSR)
]);
const dhcsr = results[0];
if (!(dhcsr & DhcsrMask.S_REGRDY)) {
throw new Error('Register not ready');
}
}
/**
* Exucute code at a specified memory address
* @param address The address to put the code
* @param code The code to use
* @param stackPointer The stack pointer to use
* @param programCounter The program counter to use
* @param linkRegister The link register to use (defaults to address + 1)
* @param registers Values to add to the general purpose registers, R0, R1, R2, etc.
*/
public async execute(address: number, code: Uint32Array, stackPointer: number, programCounter: number, linkRegister: number = address + 1, ...registers: number[]): Promise<void> {
// Ensure a breakpoint exists at the end of the code
if (code[code.length - 1] !== BKPT_INSTRUCTION) {
const newCode = new Uint32Array(code.length + 1);
newCode.set(code);
newCode.set([BKPT_INSTRUCTION], code.length - 1);
code = newCode;
}
// Create sequence of core register writes
const sequence = [
this.writeCoreRegisterCommand(CoreRegister.SP, stackPointer),
this.writeCoreRegisterCommand(CoreRegister.PC, programCounter),
this.writeCoreRegisterCommand(CoreRegister.LR, linkRegister)
];
// Add in register values R0, R1, R2, etc.
for (let i = 0; i < Math.min(registers.length, GENERAL_REGISTER_COUNT); i++) {
sequence.push(this.writeCoreRegisterCommand(i, registers[i]));
}
// Add xPSR.
sequence.push(this.writeCoreRegisterCommand(CoreRegister.PSR, 0x01000000));
await this.halt(); // Halt the target
await this.transferSequence(sequence); // Write the registers
await this.writeBlock(address, code); // Write the code to the address
await this.resume(false); // Resume the target, without waiting
await this.waitDelay(() => this.isHalted(), EXECUTE_TIMEOUT); // Wait for the target to halt on the breakpoint
}
/**
* soft reset the target
* @param None
* @returns Promise
*/
public async softReset(): Promise<void> {
await this.writeMem32(DebugRegister.DEMCR, 0);
return this.writeMem32(NvicRegister.AIRCR, AircrMask.VECTKEY | AircrMask.SYSRESETREQ);
}
/**
* set the target to reset state
* @param hardwareReset use hardware reset pin or software reset
* @param localReset true: Requests a local CPU reset using VECTRESET, false: Requests a reset by an external system resource using SYSRESETREQ
* @param timeout Milliseconds to wait before aborting wait
* @returns Promise
*/
public async setTargetResetState(hardwareReset: boolean = true, localReset: boolean = false, timeout: number = 1000): Promise<void> {
// Enable Reset Vector Catch
await this.halt();
await this.writeMem32(DebugRegister.DEMCR, DemcrMask.CORERESET);
// Clear S_RESET_ST
await this.readMem32(DebugRegister.DHCSR);
if (hardwareReset === true) {
await this.reset();
await this.writeMem32(DebugRegister.DEMCR, 0);
return;
}
const value = localReset ? AircrMask.VECTRESET : AircrMask.SYSRESETREQ;
await this.writeMem32(NvicRegister.AIRCR, AircrMask.VECTKEY | value);
const waitReset = async (): Promise<boolean> => {
const ret = await this.readMem32(DebugRegister.DHCSR);
return !!(ret & DhcsrMask.S_RESET_ST); // Wait for S_RESET_ST bit set
};
await this.waitDelay(waitReset, timeout);
await this.writeMem32(DebugRegister.DEMCR, 0);
}
}