GitHub - AbdulAhad36/RISC-V-32: RTL design of pipelined RISC-V 32 and verified using verilog custom testbench

contains components of RISC_V 32 bit processor

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
EL-421 OEL REPORT(ahad,ibrahim,fauzan).pdf		EL-421 OEL REPORT(ahad,ibrahim,fauzan).pdf
IO_device.v		IO_device.v
LICENSE		LICENSE
OEL.pdf		OEL.pdf
README.md		README.md
RISC-V pipeline.pdf		RISC-V pipeline.pdf
alu_decoder.v		alu_decoder.v
control_registers.v		control_registers.v
control_unit.v		control_unit.v
control_unit_tb.v		control_unit_tb.v
hazard_unit.v		hazard_unit.v
instruction_fetch.v		instruction_fetch.v
main_decoder.v		main_decoder.v
memory_mapped_IO.v		memory_mapped_IO.v
mux4_1.v		mux4_1.v
pipelined_riscv.v		pipelined_riscv.v
risc_v.v		risc_v.v
riscv_mmio_uart.v		riscv_mmio_uart.v
tb_control_unit.v		tb_control_unit.v
test_bench.v		test_bench.v

Provide feedback