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nec850.cpp
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nec850.cpp
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#include "nec850.h"
#include "binaryninjaapi.h"
#include <vector>
#include <inttypes.h>
#include <stdio.h>
#include <string.h>
#include "disass.h"
#include "binaryninjaapi.h"
#include "binaryninjacore.h"
#include "lowlevelilinstruction.h"
using namespace BinaryNinja;
using namespace std;
static const char *reg_name[] = {
"r0",
"r1",
"r2",
"sp",
"gp",
"tp",
"r6",
"r7",
"r8",
"r9",
"r10",
"r11",
"r12",
"r13",
"r14",
"r15",
"r16",
"r17",
"r18",
"r19",
"r20",
"r21",
"r22",
"r23",
"r24",
"r25",
"r26",
"r27",
"r28",
"r29",
"ep",
"lp",
"pc"};
static const char *cccc_name[] = {
"v",
"c/l",
"z",
"nh",
"s/n",
"t",
"lt",
"le",
"nv",
"nc/nl",
"nz",
"h",
"ns/p",
"INVALID",
"ge",
"gt"};
static const char *cond_name[] = {
"f",
"un",
"eq",
"ueq",
"olt",
"ult",
"ole",
"ule",
"sf",
"ngle",
"seq",
"ngl",
"lt",
"nge",
"le",
"ngt"};
static const char *reg_list_names[] = {
"r24",
"r25",
"r26",
"r27",
"r20",
"r21",
"r22",
"r23",
"r28",
"r29",
"lp",
"ep",
};
static const int reg_list_regs[] = {
NEC_REG_R24,
NEC_REG_R25,
NEC_REG_R26,
NEC_REG_R27,
NEC_REG_R20,
NEC_REG_R21,
NEC_REG_R22,
NEC_REG_R23,
NEC_REG_R28,
NEC_REG_R29,
NEC_REG_LP,
NEC_REG_EP
};
class NEC850 : public Architecture
{
private:
BNEndianness endian;
/* this can maybe be moved to the API later */
BNRegisterInfo RegisterInfo(uint32_t fullWidthReg, size_t offset, size_t size, bool zeroExtend = false)
{
BNRegisterInfo result;
result.fullWidthRegister = fullWidthReg;
result.offset = offset;
result.size = size;
result.extend = zeroExtend ? ZeroExtendToFullWidth : NoExtend;
return result;
}
public:
/* initialization list */
NEC850(const char *name) : Architecture(name)
{
}
/*************************************************************************/
std::string GetSysregName(int sysreg_id)
{
switch (sysreg_id)
{
case NEC_SYSREG_EIPC:
return "eipc";
case NEC_SYSREG_EIPSW:
return "eipsw";
case NEC_SYSREG_FEPC:
return "fepc";
case NEC_SYSREG_FEPSW:
return "fepsw";
case NEC_SYSREG_PSW:
return "psw";
case NEC_SYSREG_FPSR:
return "fpsr";
case NEC_SYSREG_FPEPC:
return "fpepc";
case NEC_SYSREG_FPST:
return "fpst";
case NEC_SYSREG_FPCC:
return "fpcc";
case NEC_SYSREG_FPCFG:
return "fpcfg";
case NEC_SYSREG_FPEC:
return "fpec";
case NEC_SYSREG_EIIC:
return "eiic";
case NEC_SYSREG_FEIC:
return "feic";
case NEC_SYSREG_CTPC:
return "ctpc";
case NEC_SYSREG_CTPSW:
return "ctpsw";
case NEC_SYSREG_CTBP:
return "ctbp";
case NEC_SYSREG_EIWR:
return "eiwr";
case NEC_SYSREG_FEWR:
return "fewr";
case NEC_SYSREG_BSEL:
return "bsel";
case NEC_SYSREG_MCFG0:
return "mcfg0";
case NEC_SYSREG_RBASE:
return "rbase";
case NEC_SYSREG_EBASE:
return "ebase";
case NEC_SYSREG_INTBP:
return "intbp";
case NEC_SYSREG_MCTL:
return "mctl";
case NEC_SYSREG_PID:
return "pid";
case NEC_SYSREG_SCCFG:
return "sccfg";
case NEC_SYSREG_SCBP:
return "scbp";
case NEC_SYSREG_HTCFG0:
return "htcfg0";
case NEC_SYSREG_MEA:
return "mea";
case NEC_SYSREG_ASID:
return "asid";
case NEC_SYSREG_MEI:
return "mei";
default:
return "INVALID";
}
}
virtual BNEndianness GetEndianness() const override
{
// MYLOG("%s()\n", __func__);
return LittleEndian;
}
virtual size_t GetAddressSize() const override
{
// MYLOG("%s()\n", __func__);
return 4;
}
virtual size_t GetDefaultIntegerSize() const override
{
return 4;
}
virtual size_t GetInstructionAlignment() const override
{
return 2;
}
virtual size_t GetMaxInstructionLength() const override
{
return 8;
}
virtual vector<uint32_t> GetAllFlags() override
{
return vector<uint32_t>{
FLAG_SAT,
FLAG_CY,
FLAG_OV,
FLAG_S,
FLAG_Z};
}
virtual string GetFlagName(uint32_t flag) override
{
switch (flag)
{
case FLAG_SAT:
return "sat";
case FLAG_CY:
return "cy";
case FLAG_OV:
return "ov";
case FLAG_S:
return "s";
case FLAG_Z:
return "z";
default:
return "ERR_FLAG_NAME";
}
}
virtual vector<uint32_t> GetAllFlagWriteTypes() override
{
return vector<uint32_t>{
FLAG_WRITE_NONE,
FLAG_WRITE_ALL,
FLAG_WRITE_OVSZ,
FLAG_WRITE_Z,
FLAG_WRITE_SZ,
FLAG_WRITE_CYSZ};
}
virtual string GetFlagWriteTypeName(uint32_t writeType) override
{
switch (writeType)
{
case FLAG_WRITE_CYSZ:
return "cysz";
case FLAG_WRITE_SZ:
return "sz";
case FLAG_WRITE_OVSZ:
return "ovsz";
case FLAG_WRITE_CYOVSZ:
return "cyovsz";
case FLAG_WRITE_Z:
return "z";
case FLAG_WRITE_ALL:
return "*";
default:
return "none";
}
}
virtual vector<uint32_t> GetFlagsWrittenByFlagWriteType(uint32_t writeType) override
{
switch (writeType)
{
case FLAG_WRITE_CYSZ:
return vector<uint32_t>{
FLAG_CY, FLAG_Z, FLAG_S};
case FLAG_WRITE_SZ:
return vector<uint32_t>{
FLAG_Z, FLAG_S};
case FLAG_WRITE_OVSZ:
return vector<uint32_t>{
FLAG_Z, FLAG_S, FLAG_OV};
case FLAG_WRITE_CYOVSZ:
return vector<uint32_t>{
FLAG_Z, FLAG_S, FLAG_OV, FLAG_CY};
case FLAG_WRITE_ALL:
return vector<uint32_t>{
FLAG_CY, FLAG_Z, FLAG_OV, FLAG_S};
case FLAG_WRITE_Z:
return vector<uint32_t>{
FLAG_Z};
default:
return vector<uint32_t>();
}
}
virtual BNFlagRole GetFlagRole(uint32_t flag, uint32_t semClass) override
{
bool signedClass = true;
switch (flag)
{
case FLAG_SAT:
return SpecialFlagRole;
case FLAG_CY:
return CarryFlagRole;
case FLAG_Z:
return ZeroFlagRole;
case FLAG_OV:
return OverflowFlagRole;
case FLAG_S:
return NegativeSignFlagRole;
default:
return SpecialFlagRole;
}
}
virtual vector<uint32_t> GetFlagsRequiredForFlagCondition(BNLowLevelILFlagCondition cond, uint32_t) override
{
switch (cond)
{
case LLFC_E: /* equal */
case LLFC_NE: /* not equal */
return vector<uint32_t>{FLAG_Z};
case LLFC_ULT: /* (unsigned) less than == LT */
case LLFC_UGE: /* (unsigned) greater-or-equal == !LT */
return vector<uint32_t>{FLAG_CY};
case LLFC_UGT: /* (unsigned) greater-than == GT */
case LLFC_ULE: /* (unsigned) less-or-equal == !GT */
return vector<uint32_t>{FLAG_CY, FLAG_Z};
case LLFC_SLT: /* (signed) less than == LT */
case LLFC_SGE: /* (signed) greater-or-equal == !LT */
return vector<uint32_t>{FLAG_S, FLAG_OV};
case LLFC_SGT: /* (signed) greater-than == GT */
case LLFC_SLE: /* (signed) lesser-or-equal == !GT */
return vector<uint32_t>{FLAG_S, FLAG_OV, FLAG_Z};
case LLFC_NEG:
case LLFC_POS:
return vector<uint32_t>{FLAG_S};
case LLFC_O:
case LLFC_NO:
return vector<uint32_t>{
FLAG_OV};
default:
return vector<uint32_t>();
}
}
virtual vector<uint32_t> GetFullWidthRegisters() override
{
return vector<uint32_t>{
NEC_REG_R0, NEC_REG_R1, NEC_REG_R2, NEC_REG_SP, NEC_REG_R4, NEC_REG_R5, NEC_REG_R6, NEC_REG_R7,
NEC_REG_R8, NEC_REG_R9, NEC_REG_R10, NEC_REG_R11, NEC_REG_R12, NEC_REG_R13, NEC_REG_R14, NEC_REG_R15,
NEC_REG_R16, NEC_REG_R17, NEC_REG_R18, NEC_REG_R19, NEC_REG_R20, NEC_REG_R21, NEC_REG_R22, NEC_REG_R23,
NEC_REG_R24, NEC_REG_R25, NEC_REG_R26, NEC_REG_R27, NEC_REG_R28, NEC_REG_R29, NEC_REG_EP, NEC_REG_LP, NEC_REG_PC};
}
virtual vector<uint32_t> GetAllRegisters() override
{
vector<uint32_t> result = {
NEC_REG_R0, NEC_REG_R1, NEC_REG_R2, NEC_REG_SP, NEC_REG_R4, NEC_REG_R5, NEC_REG_R6, NEC_REG_R7,
NEC_REG_R8, NEC_REG_R9, NEC_REG_R10, NEC_REG_R11, NEC_REG_R12, NEC_REG_R13, NEC_REG_R14, NEC_REG_R15,
NEC_REG_R16, NEC_REG_R17, NEC_REG_R18, NEC_REG_R19, NEC_REG_R20, NEC_REG_R21, NEC_REG_R22, NEC_REG_R23,
NEC_REG_R24, NEC_REG_R25, NEC_REG_R26, NEC_REG_R27, NEC_REG_R28, NEC_REG_R29, NEC_REG_EP, NEC_REG_LP, NEC_REG_PC,
// system registers
NEC_SYSREG_EIPC,
NEC_SYSREG_EIPSW,
NEC_SYSREG_FEPC,
NEC_SYSREG_FEPSW,
NEC_SYSREG_PSW,
NEC_SYSREG_FPSR,
NEC_SYSREG_FPEPC,
NEC_SYSREG_FPST,
NEC_SYSREG_FPCC,
NEC_SYSREG_FPCFG,
NEC_SYSREG_FPEC,
NEC_SYSREG_EIIC,
NEC_SYSREG_FEIC,
NEC_SYSREG_CTPC,
NEC_SYSREG_CTPSW,
NEC_SYSREG_CTBP,
NEC_SYSREG_EIWR,
NEC_SYSREG_FEWR,
NEC_SYSREG_BSEL,
NEC_SYSREG_MCFG0,
NEC_SYSREG_RBASE,
NEC_SYSREG_EBASE,
NEC_SYSREG_INTBP,
NEC_SYSREG_MCTL,
NEC_SYSREG_PID,
NEC_SYSREG_SCCFG,
NEC_SYSREG_SCBP,
NEC_SYSREG_HTCFG0,
NEC_SYSREG_MEA,
NEC_SYSREG_ASID,
NEC_SYSREG_MEI};
return result;
}
virtual vector<uint32_t> GetSystemRegisters() override
{
vector<uint32_t> result = {
NEC_SYSREG_EIPC,
NEC_SYSREG_EIPSW,
NEC_SYSREG_FEPC,
NEC_SYSREG_FEPSW,
NEC_SYSREG_PSW,
NEC_SYSREG_FPSR,
NEC_SYSREG_FPEPC,
NEC_SYSREG_FPST,
NEC_SYSREG_FPCC,
NEC_SYSREG_FPCFG,
NEC_SYSREG_FPEC,
NEC_SYSREG_EIIC,
NEC_SYSREG_FEIC,
NEC_SYSREG_CTPC,
NEC_SYSREG_CTPSW,
NEC_SYSREG_CTBP,
NEC_SYSREG_EIWR,
NEC_SYSREG_FEWR,
NEC_SYSREG_BSEL,
NEC_SYSREG_MCFG0,
NEC_SYSREG_RBASE,
NEC_SYSREG_EBASE,
NEC_SYSREG_INTBP,
NEC_SYSREG_MCTL,
NEC_SYSREG_PID,
NEC_SYSREG_SCCFG,
NEC_SYSREG_SCBP,
NEC_SYSREG_HTCFG0,
NEC_SYSREG_MEA,
NEC_SYSREG_ASID,
NEC_SYSREG_MEI
};
return result;
}
virtual std::vector<uint32_t> GetGlobalRegisters() override
{
return vector<uint32_t>{NEC_REG_PC};
}
virtual string GetRegisterName(uint32_t regId) override
{
const char *result;
if (regId >= NEC_REG_R0 && regId <= NEC_REG_PC)
result = reg_name[regId];
else if (regId >= NEC_SYSREG_EIPC && regId <= NEC_SYSREG_MEI)
return GetSysregName(regId);
else
result = "";
return result;
}
ExprId get_reg(LowLevelILFunction &il, int reg_id, int size) {
if (reg_id == 0)
return il.Const(size, 0);
else
return il.Register(size, reg_id);
}
virtual BNRegisterInfo GetRegisterInfo(uint32_t regId) override
{
switch (regId)
{
// BNRegisterInfo RegisterInfo(uint32_t fullWidthReg, size_t offset,
// size_t size, bool zeroExtend = false)
case NEC_REG_R0:
return RegisterInfo(NEC_REG_R0, 0, 4);
case NEC_REG_R1:
return RegisterInfo(NEC_REG_R1, 0, 4);
case NEC_REG_R2:
return RegisterInfo(NEC_REG_R2, 0, 4);
case NEC_REG_SP:
return RegisterInfo(NEC_REG_SP, 0, 4);
case NEC_REG_R4:
return RegisterInfo(NEC_REG_R4, 0, 4);
case NEC_REG_R5:
return RegisterInfo(NEC_REG_R5, 0, 4);
case NEC_REG_R6:
return RegisterInfo(NEC_REG_R6, 0, 4);
case NEC_REG_R7:
return RegisterInfo(NEC_REG_R7, 0, 4);
case NEC_REG_R8:
return RegisterInfo(NEC_REG_R8, 0, 4);
case NEC_REG_R9:
return RegisterInfo(NEC_REG_R9, 0, 4);
case NEC_REG_R10:
return RegisterInfo(NEC_REG_R10, 0, 4);
case NEC_REG_R11:
return RegisterInfo(NEC_REG_R11, 0, 4);
case NEC_REG_R12:
return RegisterInfo(NEC_REG_R12, 0, 4);
case NEC_REG_R13:
return RegisterInfo(NEC_REG_R13, 0, 4);
case NEC_REG_R14:
return RegisterInfo(NEC_REG_R14, 0, 4);
case NEC_REG_R15:
return RegisterInfo(NEC_REG_R15, 0, 4);
case NEC_REG_R16:
return RegisterInfo(NEC_REG_R16, 0, 4);
case NEC_REG_R17:
return RegisterInfo(NEC_REG_R17, 0, 4);
case NEC_REG_R18:
return RegisterInfo(NEC_REG_R18, 0, 4);
case NEC_REG_R19:
return RegisterInfo(NEC_REG_R19, 0, 4);
case NEC_REG_R20:
return RegisterInfo(NEC_REG_R20, 0, 4);
case NEC_REG_R21:
return RegisterInfo(NEC_REG_R21, 0, 4);
case NEC_REG_R22:
return RegisterInfo(NEC_REG_R22, 0, 4);
case NEC_REG_R23:
return RegisterInfo(NEC_REG_R23, 0, 4);
case NEC_REG_R24:
return RegisterInfo(NEC_REG_R24, 0, 4);
case NEC_REG_R25:
return RegisterInfo(NEC_REG_R25, 0, 4);
case NEC_REG_R26:
return RegisterInfo(NEC_REG_R26, 0, 4);
case NEC_REG_R27:
return RegisterInfo(NEC_REG_R27, 0, 4);
case NEC_REG_R28:
return RegisterInfo(NEC_REG_R28, 0, 4);
case NEC_REG_EP:
return RegisterInfo(NEC_REG_EP, 0, 4);
case NEC_REG_LP:
return RegisterInfo(NEC_REG_LP, 0, 4);
case NEC_REG_PC:
return RegisterInfo(NEC_REG_PC, 0, 4);
case NEC_SYSREG_EIPC:
return RegisterInfo(NEC_SYSREG_EIPC, 0, 4);
case NEC_SYSREG_EIPSW:
return RegisterInfo(NEC_SYSREG_EIPSW, 0, 4);
case NEC_SYSREG_FEPC:
return RegisterInfo(NEC_SYSREG_FEPC, 0, 4);
case NEC_SYSREG_FEPSW:
return RegisterInfo(NEC_SYSREG_FEPSW, 0, 4);
case NEC_SYSREG_PSW:
return RegisterInfo(NEC_SYSREG_PSW, 0, 4);
case NEC_SYSREG_FPSR:
return RegisterInfo(NEC_SYSREG_FPSR, 0, 4);
case NEC_SYSREG_FPEPC:
return RegisterInfo(NEC_SYSREG_FPEPC, 0, 4);
case NEC_SYSREG_FPST:
return RegisterInfo(NEC_SYSREG_FPST, 0, 4);
case NEC_SYSREG_FPCC:
return RegisterInfo(NEC_SYSREG_FPCC, 0, 4);
case NEC_SYSREG_FPCFG:
return RegisterInfo(NEC_SYSREG_FPCFG, 0, 4);
case NEC_SYSREG_FPEC:
return RegisterInfo(NEC_SYSREG_FPEC, 0, 4);
case NEC_SYSREG_EIIC:
return RegisterInfo(NEC_SYSREG_EIIC, 0, 4);
case NEC_SYSREG_FEIC:
return RegisterInfo(NEC_SYSREG_FEIC, 0, 4);
case NEC_SYSREG_CTPC:
return RegisterInfo(NEC_SYSREG_CTPC, 0, 4);
case NEC_SYSREG_CTPSW:
return RegisterInfo(NEC_SYSREG_CTPSW, 0, 4);
case NEC_SYSREG_CTBP:
return RegisterInfo(NEC_SYSREG_CTBP, 0, 4);
case NEC_SYSREG_EIWR:
return RegisterInfo(NEC_SYSREG_EIWR, 0, 4);
case NEC_SYSREG_FEWR:
return RegisterInfo(NEC_SYSREG_FEWR, 0, 4);
case NEC_SYSREG_BSEL:
return RegisterInfo(NEC_SYSREG_BSEL, 0, 4);
case NEC_SYSREG_MCFG0:
return RegisterInfo(NEC_SYSREG_MCFG0, 0, 4);
case NEC_SYSREG_RBASE:
return RegisterInfo(NEC_SYSREG_RBASE, 0, 4);
case NEC_SYSREG_EBASE:
return RegisterInfo(NEC_SYSREG_EBASE, 0, 4);
case NEC_SYSREG_INTBP:
return RegisterInfo(NEC_SYSREG_INTBP, 0, 4);
case NEC_SYSREG_MCTL:
return RegisterInfo(NEC_SYSREG_MCTL, 0, 4);
case NEC_SYSREG_PID:
return RegisterInfo(NEC_SYSREG_PID, 0, 4);
case NEC_SYSREG_SCCFG:
return RegisterInfo(NEC_SYSREG_SCCFG, 0, 4);
case NEC_SYSREG_SCBP:
return RegisterInfo(NEC_SYSREG_SCBP, 0, 4);
case NEC_SYSREG_HTCFG0:
return RegisterInfo(NEC_SYSREG_HTCFG0, 0, 4);
case NEC_SYSREG_MEA:
return RegisterInfo(NEC_SYSREG_MEA, 0, 4);
case NEC_SYSREG_ASID:
return RegisterInfo(NEC_SYSREG_ASID, 0, 4);
case NEC_SYSREG_MEI:
return RegisterInfo(NEC_SYSREG_MEI, 0, 4);
default:
// LogError("%s(%d == \"%s\") invalid argument", __func__,
// regId, powerpc_reg_to_str(regId));
return RegisterInfo(0, 0, 0);
}
}
virtual uint32_t GetStackPointerRegister() override
{
return NEC_REG_SP;
}
virtual uint32_t GetLinkRegister() override
{
return NEC_REG_LP;
}
virtual std::string GetIntrinsicName (uint32_t intrinsic) override {
switch (intrinsic) {
case SCH1L_INTRINSIC:
return "_CountLeadingZeros";
case SCH1R_INTRINSIC:
return "_CountTrailingZeros";
case SCH0L_INTRINSIC:
return "_CountLeadingOnes";
case SCH0R_INTRINSIC:
return "_CountTrailingOnes";
case SYNC_MEMORY_ACCESS:
return "_SynchornizeMemoryAccess";
case SYNC_PIPELINE:
return "_SynchornizePipeline";
case SYNC_INSN_FETCHER:
return "_SynchornizeInstructionFetcher";
case SYNC_EXCEPTIONS:
return "_SynchornizeExceptions";
case CLL_INTRINSIC:
return "_ClearAtomicManipulationLink";
case SNOOZE_INTRINSIC:
return "_ClearAtomicManipulationLink";
case DI_INTRINSIC:
return "_DisableEILevelMaskableInterrupt";
case EI_INTRINSIC:
return "_EnableEILevelMaskableException";
case HALT_INTRINSIC:
return "_HaltCPU";
case RIE_INTRINSIC:
return "_ReservedInstructionException";
default:
return "";
}
}
virtual std::vector<uint32_t> GetAllIntrinsics() override {
return vector<uint32_t> {
SCH1L_INTRINSIC,
SCH1R_INTRINSIC,
SCH0L_INTRINSIC,
SCH0R_INTRINSIC,
SYNC_MEMORY_ACCESS,
SYNC_PIPELINE,
SYNC_INSN_FETCHER,
SYNC_EXCEPTIONS,
CLL_INTRINSIC,
SNOOZE_INTRINSIC,
DI_INTRINSIC,
EI_INTRINSIC,
HALT_INTRINSIC,
RIE_INTRINSIC
};
}
virtual std::vector<NameAndType> GetIntrinsicInputs (uint32_t intrinsic) override {
switch (intrinsic)
{
case SCH1L_INTRINSIC:
return {
NameAndType("WORD", Type::IntegerType(4, false))
};
case SCH1R_INTRINSIC:
return {
NameAndType("WORD", Type::IntegerType(4, false))
};
case SCH0L_INTRINSIC:
return {
NameAndType("WORD", Type::IntegerType(4, false))
};
case SCH0R_INTRINSIC:
return {
NameAndType("WORD", Type::IntegerType(4, false))
};
case SYNC_MEMORY_ACCESS:
return { };
case SYNC_PIPELINE:
return { };
case SYNC_INSN_FETCHER:
return { };
case SYNC_EXCEPTIONS:
return { };
case CLL_INTRINSIC:
return { };
case SNOOZE_INTRINSIC:
return { };
case DI_INTRINSIC:
return { };
case EI_INTRINSIC:
return { };
case HALT_INTRINSIC:
return { };
case RIE_INTRINSIC:
return { };
default:
return vector<NameAndType>();
}
}
virtual std::vector<Confidence<Ref<Type>>> GetIntrinsicOutputs (uint32_t intrinsic) override {
switch (intrinsic)
{
case SCH1L_INTRINSIC:
return { Type::IntegerType(4, false) };
case SCH1R_INTRINSIC:
return { Type::IntegerType(4, false) };
case SCH0L_INTRINSIC:
return { Type::IntegerType(4, false) };
case SCH0R_INTRINSIC:
return { Type::IntegerType(4, false) };
case SYNC_MEMORY_ACCESS:
return { };
case SYNC_PIPELINE:
return { };
case SYNC_INSN_FETCHER:
return { };
case SYNC_EXCEPTIONS:
return { };
case CLL_INTRINSIC:
return { };
case SNOOZE_INTRINSIC:
return { };
case DI_INTRINSIC:
return { };
case EI_INTRINSIC:
return { };
case HALT_INTRINSIC:
return { };
case RIE_INTRINSIC:
return { };
default:
return vector<Confidence<Ref<Type>>>();
}
}
virtual bool GetInstructionLowLevelIL(const uint8_t *data, uint64_t addr, size_t &len, LowLevelILFunction &il) override
{
insn_t *insn;
if ((insn = disassemble(data)))
{
len = insn->size;
BNLowLevelILLabel *true_label = NULL;
BNLowLevelILLabel *false_label = NULL;
LowLevelILLabel true_tag;
LowLevelILLabel false_tag;
LowLevelILLabel end_tag;
ExprId condition;
switch (insn->insn_id)
{
case N850_ABSFS:
{
il.AddInstruction(
il.SetRegister(
4,
insn->fields[1].value,
il.FloatAbs(
4,
this->get_reg(il,insn->fields[0].value,4)
)
)
);
}
break;
case N850_ADD:
{
il.AddInstruction(
il.SetRegister(
4,
insn->fields[1].value,
il.Add(
4,
this->get_reg(il,insn->fields[1].value,4),
this->get_reg(il,insn->fields[0].value,4),
FLAG_WRITE_CYOVSZ
)
)
);
}
break;
case N850_ADD_IMM:
{
il.AddInstruction(
il.SetRegister(
4,
insn->fields[1].value,
il.Add(
4,
this->get_reg(il,insn->fields[1].value,4),
il.SignExtend(
4,
il.Const(
1,
insn->fields[0].value
)
),
FLAG_WRITE_CYOVSZ
)
)
);
}
break;
case N850_ADDFS:
{
il.AddInstruction(
il.SetRegister(
4,
insn->fields[2].value,
il.FloatAdd(
4,
this->get_reg(il,insn->fields[1].value,4),
this->get_reg(il,insn->fields[0].value,4)
)
)
);
}
break;
case N850_ADF:
{
if (insn->fields[0].value == 5) {
il.AddInstruction(
il.SetRegister(
4,
insn->fields[3].value,
il.Add(
4,
il.Add(
4,
this->get_reg(il,insn->fields[2].value,4),
this->get_reg(il,insn->fields[1].value,4)
),
il.Const(
4,
1
),
FLAG_WRITE_CYOVSZ
)
)
);
} else {
switch (insn->fields[0].value)
{
case 2:
condition = il.FlagCondition(LLFC_E);
break;
case 10:
condition = il.FlagCondition(LLFC_NE);
break;
case 11:
condition = il.FlagCondition(LLFC_UGT);
break;
case 3:
condition = il.FlagCondition(LLFC_ULE);
break;
case 0:
condition = il.FlagCondition(LLFC_O);
break;
case 8:
condition = il.FlagCondition(LLFC_NO);
break;
case 1:
condition = il.FlagCondition(LLFC_ULT);
break;
case 9:
condition = il.FlagCondition(LLFC_UGE);
break;
case 6:
condition = il.FlagCondition(LLFC_SLT);
break;
case 14:
condition = il.FlagCondition(LLFC_SGE);
break;
case 7:
condition = il.FlagCondition(LLFC_SLE);
break;
case 15:
condition = il.FlagCondition(LLFC_SGT);
break;
case 4:
condition = il.FlagCondition(LLFC_NEG);
break;
case 12:
condition = il.FlagCondition(LLFC_POS);
break;
default:
break;
}
il.AddInstruction(il.If(condition,true_tag,false_tag));
il.MarkLabel(true_tag);
il.AddInstruction(
il.SetRegister(
4,
insn->fields[3].value,
il.Add(
4,
il.Add(
4,
this->get_reg(il,insn->fields[2].value,4),
this->get_reg(il,insn->fields[1].value,4)
),
il.Const(
4,
1
),
FLAG_WRITE_CYOVSZ
)
)
);
il.AddInstruction(il.Goto(end_tag));
il.MarkLabel(false_tag);
il.AddInstruction(
il.SetRegister(
4,
insn->fields[3].value,
il.Add(
4,
this->get_reg(il,insn->fields[2].value,4),
this->get_reg(il,insn->fields[1].value,4),
FLAG_WRITE_CYOVSZ
)
)
);
il.MarkLabel(end_tag);
}
}
break;
case N850_ADDI:
{
il.AddInstruction(
il.SetRegister(
4,
insn->fields[2].value,
il.Add(
4,
this->get_reg(il,insn->fields[1].value,4),
il.SignExtend(
4,
il.Const(
2,
insn->fields[0].value