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stm32l476xx_constants.s
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;******************** (C) Yifeng ZHU *******************************************
; @file stm32l476xx_constants.s
; @author Yifeng Zhu
; @date May-17-2015
; @note
; This code is for the book "Embedded Systems with ARM Cortex-M
; Microcontrollers in Assembly Language and C, Yifeng Zhu,
; ISBN-13: 978-0982692639, ISBN-10: 0982692633
; @attension
; This code is provided for education purpose. The author shall not be
; held liable for any direct, indirect or consequential damages, for any
; reason whatever. More information can be found from book website:
; http:;www.eece.maine.edu/~zhu/book
;*******************************************************************************
; This following is added to remove the compiler warning.
AREA __DEFINES_STM32L4_xx_DUMMY, CODE, READONLY
; Configuration of the Cortex-M4 Processor and Core Peripherals
__CM4_REV EQU 0x0001 ; Cortex-M4 revision r0p1
__MPU_PRESENT EQU 1 ; STM32L4XX provides an MPU
__NVIC_PRIO_BITS EQU 4 ; STM32L4XX uses 4 Bits for the Priority Levels
__Vendor_SysTickConfig EQU 0 ; Set to 1 if different SysTick Config is used
__FPU_PRESENT EQU 1 ; FPU present
; STM32L4XX Interrupt Number Definition, according to the selected device
; ****** Cortex-M4 Processor Exceptions Numbers ***************************************************************
NonMaskableInt_IRQn EQU -14 ; 2 Non Maskable Interrupt
HardFault_IRQn EQU -13 ; 4 Cortex-M4 Memory Management Interrupt
MemoryManagement_IRQn EQU -12 ; 4 Cortex-M4 Memory Management Interrupt
BusFault_IRQn EQU -11 ; 5 Cortex-M4 Bus Fault Interrupt
UsageFault_IRQn EQU -10 ; 6 Cortex-M4 Usage Fault Interrupt
SVCall_IRQn EQU -5 ; 11 Cortex-M4 SV Call Interrupt
DebugMonitor_IRQn EQU -4 ; 12 Cortex-M4 Debug Monitor Interrupt
PendSV_IRQn EQU -2 ; 14 Cortex-M4 Pend SV Interrupt
SysTick_IRQn EQU -1 ; 15 Cortex-M4 System Tick Interrupt
; ****** STM32 specific Interrupt Numbers *********************************************************************
WWDG_IRQn EQU 0 ; Window WatchDog Interrupt
PVD_PVM_IRQn EQU 1 ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts
TAMP_STAMP_IRQn EQU 2 ; Tamper and TimeStamp interrupts through the EXTI line
RTC_WKUP_IRQn EQU 3 ; RTC Wakeup interrupt through the EXTI line
FLASH_IRQn EQU 4 ; FLASH global Interrupt
RCC_IRQn EQU 5 ; RCC global Interrupt
EXTI0_IRQn EQU 6 ; EXTI Line0 Interrupt
EXTI1_IRQn EQU 7 ; EXTI Line1 Interrupt
EXTI2_IRQn EQU 8 ; EXTI Line2 Interrupt
EXTI3_IRQn EQU 9 ; EXTI Line3 Interrupt
EXTI4_IRQn EQU 10 ; EXTI Line4 Interrupt
DMA1_Channel1_IRQn EQU 11 ; DMA1 Channel 1 global Interrupt
DMA1_Channel2_IRQn EQU 12 ; DMA1 Channel 2 global Interrupt
DMA1_Channel3_IRQn EQU 13 ; DMA1 Channel 3 global Interrupt
DMA1_Channel4_IRQn EQU 14 ; DMA1 Channel 4 global Interrupt
DMA1_Channel5_IRQn EQU 15 ; DMA1 Channel 5 global Interrupt
DMA1_Channel6_IRQn EQU 16 ; DMA1 Channel 6 global Interrupt
DMA1_Channel7_IRQn EQU 17 ; DMA1 Channel 7 global Interrupt
ADC1_2_IRQn EQU 18 ; ADC1, ADC2 SAR global Interrupts
CAN1_TX_IRQn EQU 19 ; CAN1 TX Interrupt
CAN1_RX0_IRQn EQU 20 ; CAN1 RX0 Interrupt
CAN1_RX1_IRQn EQU 21 ; CAN1 RX1 Interrupt
CAN1_SCE_IRQn EQU 22 ; CAN1 SCE Interrupt
EXTI9_5_IRQn EQU 23 ; External Line[9:5] Interrupts
TIM1_BRK_TIM15_IRQn EQU 24 ; TIM1 Break interrupt and TIM15 global interrupt
TIM1_UP_TIM16_IRQn EQU 25 ; TIM1 Update Interrupt and TIM16 global interrupt
TIM1_TRG_COM_TIM17_IRQn EQU 26 ; TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt
TIM1_CC_IRQn EQU 27 ; TIM1 Capture Compare Interrupt
TIM2_IRQn EQU 28 ; TIM2 global Interrupt
TIM3_IRQn EQU 29 ; TIM3 global Interrupt
TIM4_IRQn EQU 30 ; TIM4 global Interrupt
I2C1_EV_IRQn EQU 31 ; I2C1 Event Interrupt
I2C1_ER_IRQn EQU 32 ; I2C1 Error Interrupt
I2C2_EV_IRQn EQU 33 ; I2C2 Event Interrupt
I2C2_ER_IRQn EQU 34 ; I2C2 Error Interrupt
SPI1_IRQn EQU 35 ; SPI1 global Interrupt
SPI2_IRQn EQU 36 ; SPI2 global Interrupt
USART1_IRQn EQU 37 ; USART1 global Interrupt
USART2_IRQn EQU 38 ; USART2 global Interrupt
USART3_IRQn EQU 39 ; USART3 global Interrupt
EXTI15_10_IRQn EQU 40 ; External Line[15:10] Interrupts
RTC_Alarm_IRQn EQU 41 ; RTC Alarm (A and B) through EXTI Line Interrupt
DFSDM3_IRQn EQU 42 ; SD Filter 3 global Interrupt
TIM8_BRK_IRQn EQU 43 ; TIM8 Break Interrupt
TIM8_UP_IRQn EQU 44 ; TIM8 Update Interrupt
TIM8_TRG_COM_IRQn EQU 45 ; TIM8 Trigger and Commutation Interrupt
TIM8_CC_IRQn EQU 46 ; TIM8 Capture Compare Interrupt
ADC3_IRQn EQU 47 ; ADC3 global Interrupt
FMC_IRQn EQU 48 ; FMC global Interrupt
SDMMC1_IRQn EQU 49 ; SDMMC1 global Interrupt
TIM5_IRQn EQU 50 ; TIM5 global Interrupt
SPI3_IRQn EQU 51 ; SPI3 global Interrupt
UART4_IRQn EQU 52 ; UART4 global Interrupt
UART5_IRQn EQU 53 ; UART5 global Interrupt
TIM6_DAC_IRQn EQU 54 ; TIM6 global and DAC1&2 underrun error interrupts
TIM7_IRQn EQU 55 ; TIM7 global interrupt
DMA2_Channel1_IRQn EQU 56 ; DMA2 Channel 1 global Interrupt
DMA2_Channel2_IRQn EQU 57 ; DMA2 Channel 2 global Interrupt
DMA2_Channel3_IRQn EQU 58 ; DMA2 Channel 3 global Interrupt
DMA2_Channel4_IRQn EQU 59 ; DMA2 Channel 4 global Interrupt
DMA2_Channel5_IRQn EQU 60 ; DMA2 Channel 5 global Interrupt
DFSDM0_IRQn EQU 61 ; SD Filter 0 global Interrupt
DFSDM1_IRQn EQU 62 ; SD Filter 1 global Interrupt
DFSDM2_IRQn EQU 63 ; SD Filter 2 global Interrupt
COMP_IRQn EQU 64 ; COMP1 and COMP2 Interrupts
LPTIM1_IRQn EQU 65 ; LP TIM1 interrupt
LPTIM2_IRQn EQU 66 ; LP TIM2 interrupt
OTG_FS_IRQn EQU 67 ; USB OTG FS global Interrupt
DMA2_Channel6_IRQn EQU 68 ; DMA2 Channel 6 global interrupt
DMA2_Channel7_IRQn EQU 69 ; DMA2 Channel 7 global interrupt
LPUART1_IRQn EQU 70 ; LP UART1 interrupt
QUADSPI_IRQn EQU 71 ; Quad SPI global interrupt
I2C3_EV_IRQn EQU 72 ; I2C3 event interrupt
I2C3_ER_IRQn EQU 73 ; I2C3 error interrupt
SAI1_IRQn EQU 74 ; Serial Audio Interface 1 global interrupt
SAI2_IRQn EQU 75 ; Serial Audio Interface 2 global interrupt
SWPMI1_IRQn EQU 76 ; Serial Wire Interface 1 global interrupt
TSC_IRQn EQU 77 ; Touch Sense Controller global interrupt
LCD_IRQn EQU 78 ; LCD global interrupt
RNG_IRQn EQU 80 ; RNG global interrupt
FPU_IRQn EQU 81 ; FPU global interrupt
; Analog to Digital Converter
ADC_ISR EQU 0x00 ; ADC Interrupt and Status Register, Address offset: 0x00
ADC_IER EQU 0x04 ; ADC Interrupt Enable Register, Address offset: 0x04
ADC_CR EQU 0x08 ; ADC control register, Address offset: 0x08
ADC_CFGR EQU 0x0C ; ADC Configuration register, Address offset: 0x0C
ADC_CFGR2 EQU 0x10 ; ADC Configuration register 2, Address offset: 0x10
ADC_SMPR1 EQU 0x14 ; ADC sample time register 1, Address offset: 0x14
ADC_SMPR2 EQU 0x18 ; ADC sample time register 2, Address offset: 0x18
ADC_RESERVED1 EQU 0x1C ; Reserved, 0x01C
ADC_TR1 EQU 0x20 ; ADC watchdog threshold register 1, Address offset: 0x20
ADC_TR2 EQU 0x24 ; ADC watchdog threshold register 2, Address offset: 0x24
ADC_TR3 EQU 0x28 ; ADC watchdog threshold register 3, Address offset: 0x28
ADC_RESERVED2 EQU 0x2C ; Reserved, 0x02C
ADC_SQR1 EQU 0x30 ; ADC regular sequence register 1, Address offset: 0x30
ADC_SQR2 EQU 0x34 ; ADC regular sequence register 2, Address offset: 0x34
ADC_SQR3 EQU 0x38 ; ADC regular sequence register 3, Address offset: 0x38
ADC_SQR4 EQU 0x3C ; ADC regular sequence register 4, Address offset: 0x3C
ADC_DR EQU 0x40 ; ADC regular data register, Address offset: 0x40
ADC_RESERVED3 EQU 0x44 ; Reserved, 0x044
ADC_RESERVED4 EQU 0x48 ; Reserved, 0x048
ADC_JSQR EQU 0x4C ; ADC injected sequence register, Address offset: 0x4C
ADC_RESERVED5 EQU 0x50 ; Reserved, 0x050 - 0x05C
ADC_OFR1 EQU 0x60 ; ADC offset register 1, Address offset: 0x60
ADC_OFR2 EQU 0x64 ; ADC offset register 2, Address offset: 0x64
ADC_OFR3 EQU 0x68 ; ADC offset register 3, Address offset: 0x68
ADC_OFR4 EQU 0x6C ; ADC offset register 4, Address offset: 0x6C
ADC_RESERVED6 EQU 0x70 ; Reserved, 0x070 - 0x07C
ADC_JDR1 EQU 0x80 ; ADC injected data register 1, Address offset: 0x80
ADC_JDR2 EQU 0x84 ; ADC injected data register 2, Address offset: 0x84
ADC_JDR3 EQU 0x88 ; ADC injected data register 3, Address offset: 0x88
ADC_JDR4 EQU 0x8C ; ADC injected data register 4, Address offset: 0x8C
ADC_RESERVED7 EQU 0x90 ; Reserved, 0x090 - 0x09C
ADC_AWD2CR EQU 0xA0 ; ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0
ADC_AWD3CR EQU 0xA4 ; ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4
ADC_RESERVED8 EQU 0xA8 ; Reserved, 0x0A8
ADC_RESERVED9 EQU 0xAC ; Reserved, 0x0AC
ADC_DIFSEL EQU 0xB0 ; ADC Differential Mode Selection Register, Address offset: 0xB0
ADC_CALFACT EQU 0xB4 ; ADC Calibration Factors, Address offset: 0xB4
ADC_CSR EQU 0x300 ; ADC Common status register, Address offset: ADC1 base address + 0x300
ADC_RESERVED EQU 0x304 ; Reserved, ADC1 base address + 0x304
ADC_CCR EQU 0x308 ; ADC common control register, Address offset: ADC1 base address + 0x308
ADC_CDR EQU 0x30C ; ADC common regular data register for dual Address offset: ADC1 base address + 0x30C
; Controller Area Network TxMailBox
CAN_TxMailBox_TIR EQU 0x00 ; CAN TX mailbox identifier register
CAN_TxMailBox_TDTR EQU 0x04 ; CAN mailbox data length control and time stamp register
CAN_TxMailBox_TDLR EQU 0x08 ; CAN mailbox data low register
CAN_TxMailBox_TDHR EQU 0x0C ; CAN mailbox data high register
; Controller Area Network FIFOMailBox
CAN_FIFOMailBox_RIR EQU 0x00 ; CAN receive FIFO mailbox identifier register
CAN_FIFOMailBox_RDTR EQU 0x04 ; CAN receive FIFO mailbox data length control and time stamp register
CAN_FIFOMailBox_RDLR EQU 0x08 ; CAN receive FIFO mailbox data low register
CAN_FIFOMailBox_RDHR EQU 0x0C ; CAN receive FIFO mailbox data high register
; Controller Area Network FilterRegister
CAN_FilterRegister_FR1 EQU 0x00 ; CAN Filter bank register 1
CAN_FilterRegister_FR2 EQU 0x04 ; CAN Filter bank register 1
; Controller Area Network
CAN_MCR EQU 0x00 ; CAN master control register, Address offset: 0x00
CAN_MSR EQU 0x04 ; CAN master status register, Address offset: 0x04
CAN_TSR EQU 0x08 ; CAN transmit status register, Address offset: 0x08
CAN_RF0R EQU 0x0C ; CAN receive FIFO 0 register, Address offset: 0x0C
CAN_RF1R EQU 0x10 ; CAN receive FIFO 1 register, Address offset: 0x10
CAN_IER EQU 0x14 ; CAN interrupt enable register, Address offset: 0x14
CAN_ESR EQU 0x18 ; CAN error status register, Address offset: 0x18
CAN_BTR EQU 0x1C ; CAN bit timing register, Address offset: 0x1C
CAN_RESERVED0 EQU 0x20 ; Reserved, 0x020 - 0x17F
CAN_TxMailBox0 EQU 0x180 ; CAN Tx MailBox, Address offset: 0x180 - 0x1AC
CAN_TxMailBox1 EQU 0x190 ; CAN Tx MailBox, Address offset: 0x180 - 0x1AC
CAN_TxMailBox2 EQU 0x1A0 ; CAN Tx MailBox, Address offset: 0x180 - 0x1AC
CAN_FIFOMailBox0 EQU 0x1B0 ; CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC
CAN_FIFOMailBox1 EQU 0x1C0 ; CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC
CAN_RESERVED1 EQU 0x1D0 ; Reserved, 0x1D0 - 0x1FF
CAN_FMR EQU 0x200 ; CAN filter master register, Address offset: 0x200
CAN_FM1R EQU 0x204 ; CAN filter mode register, Address offset: 0x204
CAN_RESERVED2 EQU 0x208 ; Reserved, 0x208
CAN_FS1R EQU 0x20C ; CAN filter scale register, Address offset: 0x20C
CAN_RESERVED3 EQU 0x210 ; Reserved, 0x210
CAN_FFA1R EQU 0x214 ; CAN filter FIFO assignment register, Address offset: 0x214
CAN_RESERVED4 EQU 0x218 ; Reserved, 0x218
CAN_FA1R EQU 0x21C ; CAN filter activation register, Address offset: 0x21C
CAN_RESERVED5 EQU 0x220 ; Reserved, 0x220-0x23F
CAN_FilterRegister EQU 0x240 ; CAN Filter Register, Address offset: 0x240-0x31C
; Comparator
COMP_CSR EQU 0x00 ; COMP comparator control and status register, Address offset: 0x00
; CRC calculation unit
CRC_DR EQU 0x00 ; CRC Data register, Address offset: 0x00
CRC_IDR EQU 0x04 ; CRC Independent data register, Address offset: 0x04
CRC_RESERVED0 EQU 0x05 ; Reserved, 0x05
CRC_RESERVED1 EQU 0x06 ; Reserved, 0x06
CRC_CR EQU 0x08 ; CRC Control register, Address offset: 0x08
CRC_RESERVED2 EQU 0x0C ; Reserved, 0x0C
CRC_INIT EQU 0x10 ; Initial CRC value register, Address offset: 0x10
CRC_POL EQU 0x14 ; CRC polynomial register, Address offset: 0x14
; Digital to Analog Converter
DAC_CR EQU 0x00 ; DAC control register, Address offset: 0x00
DAC_SWTRIGR EQU 0x04 ; DAC software trigger register, Address offset: 0x04
DAC_DHR12R1 EQU 0x08 ; DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08
DAC_DHR12L1 EQU 0x0C ; DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C
DAC_DHR8R1 EQU 0x10 ; DAC channel1 8-bit right aligned data holding register, Address offset: 0x10
DAC_DHR12R2 EQU 0x14 ; DAC channel2 12-bit right aligned data holding register, Address offset: 0x14
DAC_DHR12L2 EQU 0x18 ; DAC channel2 12-bit left aligned data holding register, Address offset: 0x18
DAC_DHR8R2 EQU 0x1C ; DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C
DAC_DHR12RD EQU 0x20 ; Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20
DAC_DHR12LD EQU 0x24 ; DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24
DAC_DHR8RD EQU 0x28 ; DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28
DAC_DOR1 EQU 0x2C ; DAC channel1 data output register, Address offset: 0x2C
DAC_DOR2 EQU 0x30 ; DAC channel2 data output register, Address offset: 0x30
DAC_SR EQU 0x34 ; DAC status register, Address offset: 0x34
DAC_CCR EQU 0x38 ; DAC calibration control register, Address offset: 0x38
DAC_MCR EQU 0x3C ; DAC mode control register, Address offset: 0x3C
DAC_SHSR1 EQU 0x40 ; DAC Sample and Hold sample time register 1, Address offset: 0x40
DAC_SHSR2 EQU 0x44 ; DAC Sample and Hold sample time register 2, Address offset: 0x44
DAC_SHHR EQU 0x48 ; DAC Sample and Hold hold time register, Address offset: 0x48
DAC_SHRR EQU 0x4C ; DAC Sample and Hold refresh time register, Address offset: 0x4C
; DFSDM module registers
DFSDM_Filter_CR1 EQU 0x100 ; DFSDM control register1, Address offset: 0x100
DFSDM_Filter_CR2 EQU 0x104 ; DFSDM control register2, Address offset: 0x104
DFSDM_Filter_ISR EQU 0x108 ; DFSDM interrupt and status register, Address offset: 0x108
DFSDM_Filter_ICR EQU 0x10C ; DFSDM interrupt flag clear register, Address offset: 0x10C
DFSDM_Filter_JCHGR EQU 0x110 ; DFSDM injected channel group selection register, Address offset: 0x110
DFSDM_Filter_FCR EQU 0x114 ; DFSDM filter control register, Address offset: 0x114
DFSDM_Filter_JDATAR EQU 0x118 ; DFSDM data register for injected group, Address offset: 0x118
DFSDM_Filter_RDATAR EQU 0x11C ; DFSDM data register for regular group, Address offset: 0x11C
DFSDM_Filter_AWHTR EQU 0x120 ; DFSDM analog watchdog high threshold register, Address offset: 0x120
DFSDM_Filter_AWLTR EQU 0x124 ; DFSDM analog watchdog low threshold register, Address offset: 0x124
DFSDM_Filter_AWSR EQU 0x128 ; DFSDM analog watchdog status register Address offset: 0x128
DFSDM_Filter_AWCFR EQU 0x12C ; DFSDM analog watchdog clear flag register Address offset: 0x12C
DFSDM_Filter_EXMAX EQU 0x130 ; DFSDM extreme detector maximum register, Address offset: 0x130
DFSDM_Filter_EXMIN EQU 0x134 ; DFSDM extreme detector minimum register Address offset: 0x134
DFSDM_Filter_CNVTIMR EQU 0x138 ; DFSDM conversion timer, Address offset: 0x138
; DFSDM channel configuration registers
DFSDM_Channel_CHCFGR1 EQU 0x00 ; DFSDM channel configuration register1, Address offset: 0x00
DFSDM_Channel_CHCFGR2 EQU 0x04 ; DFSDM channel configuration register2, Address offset: 0x04
DFSDM_Channel_AWSCDR EQU 0x08 ; DFSDM channel analog watchdog and short circuit detector register, Address offset: 0x08
DFSDM_Channel_CHWDATAR EQU 0x0C ; DFSDM channel watchdog filter data register, Address offset: 0x0C
DFSDM_Channel_CHDATINR EQU 0x10 ; DFSDM channel data input register, Address offset: 0x10
; Debug MCU
DBGMCU_IDCODE EQU 0x00 ; MCU device ID code, Address offset: 0x00
DBGMCU_CR EQU 0x04 ; Debug MCU configuration register, Address offset: 0x04
DBGMCU_APB1FZR1 EQU 0x08 ; Debug MCU APB1 freeze register 1, Address offset: 0x08
DBGMCU_APB1FZR2 EQU 0x0C ; Debug MCU APB1 freeze register 2, Address offset: 0x0C
DBGMCU_APB2FZ EQU 0x10 ; Debug MCU APB2 freeze register, Address offset: 0x10
; DMA Controller
DMA_Channel_CCR EQU 0x00 ; DMA channel x configuration register
DMA_Channel_CNDTR EQU 0x04 ; DMA channel x number of data register
DMA_Channel_CPAR EQU 0x08 ; DMA channel x peripheral address register
DMA_Channel_CMAR EQU 0x0C ; DMA channel x memory address register
DMA_ISR EQU 0x00 ; DMA interrupt status register, Address offset: 0x00
DMA_IFCR EQU 0x04 ; DMA interrupt flag clear register, Address offset: 0x04
DMA_Request_CSELR EQU 0x00 ; DMA option register, Address offset: 0x00
; External Interrupt/Event Controller
EXTI_IMR1 EQU 0x00 ; EXTI Interrupt mask register 1, Address offset: 0x00
EXTI_EMR1 EQU 0x04 ; EXTI Event mask register 1, Address offset: 0x04
EXTI_RTSR1 EQU 0x08 ; EXTI Rising trigger selection register 1, Address offset: 0x08
EXTI_FTSR1 EQU 0x0C ; EXTI Falling trigger selection register 1, Address offset: 0x0C
EXTI_SWIER1 EQU 0x10 ; EXTI Software interrupt event register 1, Address offset: 0x10
EXTI_PR1 EQU 0x14 ; EXTI Pending register 1, Address offset: 0x14
EXTI_RESERVED1 EQU 0x18 ; Reserved, 0x18
EXTI_RESERVED2 EQU 0x1C ; Reserved, 0x1C
EXTI_IMR2 EQU 0x20 ; EXTI Interrupt mask register 2, Address offset: 0x20
EXTI_EMR2 EQU 0x24 ; EXTI Event mask register 2, Address offset: 0x24
EXTI_RTSR2 EQU 0x28 ; EXTI Rising trigger selection register 2, Address offset: 0x28
EXTI_FTSR2 EQU 0x2C ; EXTI Falling trigger selection register 2, Address offset: 0x2C
EXTI_SWIER2 EQU 0x30 ; EXTI Software interrupt event register 2, Address offset: 0x30
EXTI_PR2 EQU 0x34 ; EXTI Pending register 2, Address offset: 0x34
; Firewall
FIREWALL_CSSA EQU 0x00 ; Code Segment Start Address register, Address offset: 0x00
FIREWALL_CSL EQU 0x04 ; Code Segment Length register, Address offset: 0x04
FIREWALL_NVDSSA EQU 0x08 ; NON volatile data Segment Start Address register, Address offset: 0x08
FIREWALL_NVDSL EQU 0x0C ; NON volatile data Segment Length register, Address offset: 0x0C
FIREWALL_VDSSA EQU 0x10 ; Volatile data Segment Start Address register, Address offset: 0x10
FIREWALL_VDSL EQU 0x14 ; Volatile data Segment Length register, Address offset: 0x14
FIREWALL_RESERVED1 EQU 0x18 ; Reserved1, Address offset: 0x18
FIREWALL_RESERVED2 EQU 0x1C ; Reserved2, Address offset: 0x1C
FIREWALL_CR EQU 0x20 ; Configuration register, Address offset: 0x20
; FLASH Registers
FLASH_ACR EQU 0x00 ; FLASH access control register, Address offset: 0x00
FLASH_PDKEYR EQU 0x04 ; FLASH power down key register, Address offset: 0x04
FLASH_KEYR EQU 0x08 ; FLASH key register, Address offset: 0x08
FLASH_OPTKEYR EQU 0x0C ; FLASH option key register, Address offset: 0x0C
FLASH_SR EQU 0x10 ; FLASH status register, Address offset: 0x10
FLASH_CR EQU 0x14 ; FLASH control register, Address offset: 0x14
FLASH_ECCR EQU 0x18 ; FLASH ECC register, Address offset: 0x18
FLASH_RESERVED1 EQU 0x1C ; Reserved1, Address offset: 0x1C
FLASH_OPTR EQU 0x20 ; FLASH option register, Address offset: 0x20
FLASH_PCROP1SR EQU 0x24 ; FLASH bank1 PCROP start address register, Address offset: 0x24
FLASH_PCROP1ER EQU 0x28 ; FLASH bank1 PCROP end address register, Address offset: 0x28
FLASH_WRP1AR EQU 0x2C ; FLASH bank1 WRP area A address register, Address offset: 0x2C
FLASH_WRP1BR EQU 0x30 ; FLASH bank1 WRP area B address register, Address offset: 0x30
FLASH_RESERVED2 EQU 0x34 ; Reserved2, Address offset: 0x34
FLASH_PCROP2SR EQU 0x44 ; FLASH bank2 PCROP start address register, Address offset: 0x44
FLASH_PCROP2ER EQU 0x48 ; FLASH bank2 PCROP end address register, Address offset: 0x48
FLASH_WRP2AR EQU 0x4C ; FLASH bank2 WRP area A address register, Address offset: 0x4C
FLASH_WRP2BR EQU 0x50 ; FLASH bank2 WRP area B address register, Address offset: 0x50
; Flexible Memory Controller
FMC_Bank1_BTCR0 EQU 0x00 ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
FMC_Bank1_BTCR1 EQU 0x04 ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
FMC_Bank1_BTCR2 EQU 0x08 ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
FMC_Bank1_BTCR3 EQU 0x0C ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
FMC_Bank1_BTCR4 EQU 0x10 ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
FMC_Bank1_BTCR5 EQU 0x14 ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
FMC_Bank1_BTCR6 EQU 0x18 ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
FMC_Bank1_BTCR7 EQU 0x1C ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C
; Flexible Memory Controller Bank1E
FMC_Bank1E_BWTR0 EQU 0x104 ; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
FMC_Bank1E_BWTR1 EQU 0x108 ; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
FMC_Bank1E_BWTR2 EQU 0x10C ; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
FMC_Bank1E_BWTR3 EQU 0x110 ; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
FMC_Bank1E_BWTR4 EQU 0x114 ; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
FMC_Bank1E_BWTR5 EQU 0x118 ; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
FMC_Bank1E_BWTR6 EQU 0x11C ; NOR/PSRAM write timing registers, Address offset: 0x104-0x11C
; Flexible Memory Controller Bank3
FMC_Bank3_PCR EQU 0x80 ; NAND Flash control register, Address offset: 0x80
FMC_Bank3_SR EQU 0x84 ; NAND Flash FIFO status and interrupt register, Address offset: 0x84
FMC_Bank3_PMEM EQU 0x88 ; NAND Flash Common memory space timing register, Address offset: 0x88
FMC_Bank3_PATT EQU 0x8C ; NAND Flash Attribute memory space timing register, Address offset: 0x8C
FMC_Bank3_RESERVED0 EQU 0x90 ; Reserved, 0x90
FMC_Bank3_ECCR EQU 0x94 ; NAND Flash ECC result registers, Address offset: 0x94
; General Purpose I/O
GPIO_MODER EQU 0x00 ; GPIO port mode register, Address offset: 0x00
GPIO_OTYPER EQU 0x04 ; GPIO port output type register, Address offset: 0x04
GPIO_OSPEEDR EQU 0x08 ; GPIO port output speed register, Address offset: 0x08
GPIO_PUPDR EQU 0x0C ; GPIO port pull-up/pull-down register, Address offset: 0x0C
GPIO_IDR EQU 0x10 ; GPIO port input data register, Address offset: 0x10
GPIO_ODR EQU 0x14 ; GPIO port output data register, Address offset: 0x14
GPIO_BSRR EQU 0x18 ; GPIO port bit set/reset register, Address offset: 0x18
GPIO_LCKR EQU 0x1C ; GPIO port configuration lock register, Address offset: 0x1C
GPIO_AFR0 EQU 0x20 ; GPIO alternate function registers, Address offset: 0x20-0x24
GPIO_AFR1 EQU 0x24 ; GPIO alternate function registers, Address offset: 0x20-0x24
GPIO_BRR EQU 0x28 ; GPIO Bit Reset register, Address offset: 0x28
GPIO_ASCR EQU 0x2C ; GPIO analog switch control register, Address offset: 0x2C
; Inter-integrated Circuit Interface
I2C_CR1 EQU 0x00 ; I2C Control register 1, Address offset: 0x00
I2C_CR2 EQU 0x04 ; I2C Control register 2, Address offset: 0x04
I2C_OAR1 EQU 0x08 ; I2C Own address 1 register, Address offset: 0x08
I2C_OAR2 EQU 0x0C ; I2C Own address 2 register, Address offset: 0x0C
I2C_TIMINGR EQU 0x10 ; I2C Timing register, Address offset: 0x10
I2C_TIMEOUTR EQU 0x14 ; I2C Timeout register, Address offset: 0x14
I2C_ISR EQU 0x18 ; I2C Interrupt and status register, Address offset: 0x18
I2C_ICR EQU 0x1C ; I2C Interrupt clear register, Address offset: 0x1C
I2C_PECR EQU 0x20 ; I2C PEC register, Address offset: 0x20
I2C_RXDR EQU 0x24 ; I2C Receive data register, Address offset: 0x24
I2C_TXDR EQU 0x28 ; I2C Transmit data register, Address offset: 0x28
; Independent WATCHDOG
IWDG_KR EQU 0x00 ; IWDG Key register, Address offset: 0x00
IWDG_PR EQU 0x04 ; IWDG Prescaler register, Address offset: 0x04
IWDG_RLR EQU 0x08 ; IWDG Reload register, Address offset: 0x08
IWDG_SR EQU 0x0C ; IWDG Status register, Address offset: 0x0C
IWDG_WINR EQU 0x10 ; IWDG Window register, Address offset: 0x10
; LCD
LCD_FCR EQU 0x04 ; LCD frame control register, Address offset: 0x04
LCD_SR EQU 0x08 ; LCD status register, Address offset: 0x08
LCD_CLR EQU 0x0C ; LCD clear register, Address offset: 0x0C
LCD_RESERVED EQU 0x10 ; Reserved, Address offset: 0x10
LCD_RAM0 EQU 0x14 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM1 EQU 0x18 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM2 EQU 0x1C ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM3 EQU 0x20 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM4 EQU 0x24 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM5 EQU 0x28 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM6 EQU 0x2C ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM7 EQU 0x30 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM8 EQU 0x34 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM9 EQU 0x38 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM10 EQU 0x3C ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM11 EQU 0x40 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM12 EQU 0x44 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM13 EQU 0x48 ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM14 EQU 0x4C ; LCD display memory, Address offset: 0x14-0x50
LCD_RAM15 EQU 0x50 ; LCD display memory, Address offset: 0x14-0x50
; LPTIMER
LPTIM_ISR EQU 0x00 ; LPTIM Interrupt and Status register, Address offset: 0x00
LPTIM_ICR EQU 0x04 ; LPTIM Interrupt Clear register, Address offset: 0x04
LPTIM_IER EQU 0x08 ; LPTIM Interrupt Enable register, Address offset: 0x08
LPTIM_CFGR EQU 0x0C ; LPTIM Configuration register, Address offset: 0x0C
LPTIM_CR EQU 0x10 ; LPTIM Control register, Address offset: 0x10
LPTIM_CMP EQU 0x14 ; LPTIM Compare register, Address offset: 0x14
LPTIM_ARR EQU 0x18 ; LPTIM Autoreload register, Address offset: 0x18
LPTIM_CNT EQU 0x1C ; LPTIM Counter register, Address offset: 0x1C
LPTIM_OR EQU 0x20 ; LPTIM Option register, Address offset: 0x20
; Operational Amplifier (OPAMP)
OPAMP_CSR EQU 0x00 ; OPAMP control/status register, Address offset: 0x00
OPAMP_OTR EQU 0x04 ; OPAMP offset trimming register for normal mode, Address offset: 0x04
OPAMP_LPOTR EQU 0x08 ; OPAMP offset trimming register for low power mode, Address offset: 0x08
; Power Control
PWR_CR1 EQU 0x00 ; PWR power control register 1, Address offset: 0x00
PWR_CR2 EQU 0x04 ; PWR power control register 2, Address offset: 0x04
PWR_CR3 EQU 0x08 ; PWR power control register 3, Address offset: 0x08
PWR_CR4 EQU 0x0C ; PWR power control register 4, Address offset: 0x0C
PWR_SR1 EQU 0x10 ; PWR power status register 1, Address offset: 0x10
PWR_SR2 EQU 0x14 ; PWR power status register 2, Address offset: 0x14
PWR_SCR EQU 0x18 ; PWR power status reset register, Address offset: 0x18
PWR_RESERVED EQU 0x1C; Reserved, Address offset: 0x1C
PWR_PUCRA EQU 0x20 ; Pull_up control register of portA, Address offset: 0x20
PWR_PDCRA EQU 0x24 ; Pull_Down control register of portA, Address offset: 0x24
PWR_PUCRB EQU 0x28 ; Pull_up control register of portB, Address offset: 0x28
PWR_PDCRB EQU 0x2C ; Pull_Down control register of portB, Address offset: 0x2C
PWR_PUCRC EQU 0x30 ; Pull_up control register of portC, Address offset: 0x30
PWR_PDCRC EQU 0x34 ; Pull_Down control register of portC, Address offset: 0x34
PWR_PUCRD EQU 0x38 ; Pull_up control register of portD, Address offset: 0x38
PWR_PDCRD EQU 0x3C ; Pull_Down control register of portD, Address offset: 0x3C
PWR_PUCRE EQU 0x40 ; Pull_up control register of portE, Address offset: 0x40
PWR_PDCRE EQU 0x44 ; Pull_Down control register of portE, Address offset: 0x44
PWR_PUCRF EQU 0x48 ; Pull_up control register of portF, Address offset: 0x48
PWR_PDCRF EQU 0x4C ; Pull_Down control register of portF, Address offset: 0x4C
PWR_PUCRG EQU 0x50 ; Pull_up control register of portG, Address offset: 0x50
PWR_PDCRG EQU 0x54 ; Pull_Down control register of portG, Address offset: 0x54
PWR_PUCRH EQU 0x58 ; Pull_up control register of portH, Address offset: 0x58
PWR_PDCRH EQU 0x5C ; Pull_Down control register of portH, Address offset: 0x5C
; QUAD Serial Peripheral Interface
QUADSPI_CR EQU 0x00 ; QUADSPI Control register, Address offset: 0x00
QUADSPI_DCR EQU 0x04 ; QUADSPI Device Configuration register, Address offset: 0x04
QUADSPI_SR EQU 0x08 ; QUADSPI Status register, Address offset: 0x08
QUADSPI_FCR EQU 0x0C ; QUADSPI Flag Clear register, Address offset: 0x0C
QUADSPI_DLR EQU 0x10 ; QUADSPI Data Length register, Address offset: 0x10
QUADSPI_CCR EQU 0x14 ; QUADSPI Communication Configuration register, Address offset: 0x14
QUADSPI_AR EQU 0x18 ; QUADSPI Address register, Address offset: 0x18
QUADSPI_ABR EQU 0x1C ; QUADSPI Alternate Bytes register, Address offset: 0x1C
QUADSPI_DR EQU 0x20 ; QUADSPI Data register, Address offset: 0x20
QUADSPI_PSMKR EQU 0x24 ; QUADSPI Polling Status Mask register, Address offset: 0x24
QUADSPI_PSMAR EQU 0x28 ; QUADSPI Polling Status Match register, Address offset: 0x28
QUADSPI_PIR EQU 0x2C ; QUADSPI Polling Interval register, Address offset: 0x2C
QUADSPI_LPTR EQU 0x30 ; QUADSPI Low Power Timeout register, Address offset: 0x30
; Reset and Clock Control
RCC_CR EQU 0x00 ; RCC clock control register, Address offset: 0x00
RCC_ICSCR EQU 0x04 ; RCC Internal Clock Sources Calibration Register, Address offset: 0x04
RCC_CFGR EQU 0x08 ; RCC clock configuration register, Address offset: 0x08
RCC_PLLCFGR EQU 0x0C ; RCC System PLL configuration register, Address offset: 0x0C
RCC_PLLSAI1CFGR EQU 0x10 ; RCC PLL SAI1 Configuration Register, Address offset: 0x10
RCC_PLLSAI2CFGR EQU 0x14 ; RCC PLL SAI2 Configuration Register, Address offset: 0x14
RCC_CIER EQU 0x18 ; RCC Clock Interrupt Enable Register, Address offset: 0x18
RCC_CIFR EQU 0x1C ; RCC Clock Interrupt Flag Register, Address offset: 0x1C
RCC_CICR EQU 0x20 ; RCC Clock Interrupt Clear Register, Address offset: 0x20
RCC_RESERVED0 EQU 0x24 ; Reserved, Address offset: 0x24
RCC_AHB1RSTR EQU 0x28 ; RCC AHB1 peripheral reset register, Address offset: 0x28
RCC_AHB2RSTR EQU 0x2C ; RCC AHB2 peripheral reset register, Address offset: 0x2C
RCC_AHB3RSTR EQU 0x30 ; RCC AHB3 peripheral reset register, Address offset: 0x30
RCC_RESERVED1 EQU 0x34 ; Reserved, Address offset: 0x34
RCC_APB1RSTR1 EQU 0x38 ; RCC APB1 macrocells resets Low Word, Address offset: 0x38
RCC_APB1RSTR2 EQU 0x3C ; RCC APB1 macrocells resets High Word, Address offset: 0x3C
RCC_APB2RSTR EQU 0x40 ; RCC APB2 macrocells resets, Address offset: 0x40
RCC_RESERVED2 EQU 0x44 ; Reserved, Address offset: 0x44
RCC_AHB1ENR EQU 0x48 ; RCC AHB1 peripheral clock enable register, Address offset: 0x48
RCC_AHB2ENR EQU 0x4C ; RCC AHB2 peripheral clock enable register, Address offset: 0x4C
RCC_AHB3ENR EQU 0x50 ; RCC AHB3 peripheral clock enable register, Address offset: 0x50
RCC_RESERVED3 EQU 0x54 ; Reserved, Address offset: 0x54
RCC_APB1ENR1 EQU 0x58 ; RCC APB1 macrocells clock enables Low Word, Address offset: 0x58
RCC_APB1ENR2 EQU 0x5C ; RCC APB1 macrocells clock enables High Word, Address offset: 0x5C
RCC_APB2ENR EQU 0x60 ; RCC APB2 macrocells clock enabled, Address offset: 0x60
RCC_RESERVED4 EQU 0x64 ; Reserved, Address offset: 0x64
RCC_AHB1SMENR EQU 0x60 ; RCC AHB1 macrocells clocks enables in sleep mode, Address offset: 0x60
RCC_AHB2SMENR EQU 0x64 ; RCC AHB2 macrocells clock enables in sleep mode, Address offset: 0x64
RCC_AHB3SMENR EQU 0x70 ; RCC AHB3 macrocells clock enables in sleep mode, Address offset: 0x70
RCC_RESERVED5 EQU 0x74 ; Reserved, Address offset: 0x74
RCC_APB1SMENR1 EQU 0x78 ; RCC APB1 macrocells clock enables in sleep mode Low Word, Address offset: 0x78
RCC_APB1SMENR2 EQU 0x7C ; RCC APB1 macrocells clock enables in sleep mode High Word, Address offset: 0x7C
RCC_APB2SMENR EQU 0x80 ; RCC APB2 macrocells clock enabled in sleep mode, Address offset: 0x80
RCC_RESERVED6 EQU 0x84 ; Reserved, Address offset: 0x84
RCC_CCIPR EQU 0x88 ; RCC IPs Clocks Configuration Register, Address offset: 0x88
RCC_RESERVED7 EQU 0x8C ; Reserved, Address offset: 0x8C
RCC_BDCR EQU 0x90 ; RCC Vswitch Backup Domain Control Register, Address offset: 0x90
RCC_CSR EQU 0x94 ; RCC clock control & status register, Address offset: 0x94
; Real-Time Clock
RTC_TR EQU 0x00 ; RTC time register, Address offset: 0x00
RTC_DR EQU 0x04 ; RTC date register, Address offset: 0x04
RTC_CR EQU 0x08 ; RTC control register, Address offset: 0x08
RTC_ISR EQU 0x0C ; RTC initialization and status register, Address offset: 0x0C
RTC_PRER EQU 0x10 ; RTC prescaler register, Address offset: 0x10
RTC_WUTR EQU 0x14 ; RTC wakeup timer register, Address offset: 0x14
RTC_Reserved EQU 0x18 ; Reserved
RTC_ALRMAR EQU 0x1C ; RTC alarm A register, Address offset: 0x1C
RTC_ALRMBR EQU 0x20 ; RTC alarm B register, Address offset: 0x20
RTC_WPR EQU 0x24 ; RTC write protection register, Address offset: 0x24
RTC_SSR EQU 0x28 ; RTC sub second register, Address offset: 0x28
RTC_SHIFTR EQU 0x2C ; RTC shift control register, Address offset: 0x2C
RTC_TSTR EQU 0x30 ; RTC time stamp time register, Address offset: 0x30
RTC_TSDR EQU 0x34 ; RTC time stamp date register, Address offset: 0x34
RTC_TSSSR EQU 0x38 ; RTC time-stamp sub second register, Address offset: 0x38
RTC_CALR EQU 0x3C ; RTC calibration register, Address offset: 0x3C
RTC_TAMPCR EQU 0x40 ; RTC tamper configuration register, Address offset: 0x40
RTC_ALRMASSR EQU 0x44 ; RTC alarm A sub second register, Address offset: 0x44
RTC_ALRMBSSR EQU 0x48 ; RTC alarm B sub second register, Address offset: 0x48
RTC_OR EQU 0x4C ; RTC option register, Address offset: 0x4C
RTC_BKP0R EQU 0x50 ; RTC backup register 0, Address offset: 0x50
RTC_BKP1R EQU 0x54 ; RTC backup register 1, Address offset: 0x54
RTC_BKP2R EQU 0x58 ; RTC backup register 2, Address offset: 0x58
RTC_BKP3R EQU 0x5C ; RTC backup register 3, Address offset: 0x5C
RTC_BKP4R EQU 0x60 ; RTC backup register 4, Address offset: 0x60
RTC_BKP5R EQU 0x64 ; RTC backup register 5, Address offset: 0x64
RTC_BKP6R EQU 0x68 ; RTC backup register 6, Address offset: 0x68
RTC_BKP7R EQU 0x6C ; RTC backup register 7, Address offset: 0x6C
RTC_BKP8R EQU 0x70 ; RTC backup register 8, Address offset: 0x70
RTC_BKP9R EQU 0x74 ; RTC backup register 9, Address offset: 0x74
RTC_BKP10R EQU 0x78 ; RTC backup register 10, Address offset: 0x78
RTC_BKP11R EQU 0x7C ; RTC backup register 11, Address offset: 0x7C
RTC_BKP12R EQU 0x80 ; RTC backup register 12, Address offset: 0x80
RTC_BKP13R EQU 0x84 ; RTC backup register 13, Address offset: 0x84
RTC_BKP14R EQU 0x88 ; RTC backup register 14, Address offset: 0x88
RTC_BKP15R EQU 0x8C ; RTC backup register 15, Address offset: 0x8C
RTC_BKP16R EQU 0x90 ; RTC backup register 16, Address offset: 0x90
RTC_BKP17R EQU 0x94 ; RTC backup register 17, Address offset: 0x94
RTC_BKP18R EQU 0x98 ; RTC backup register 18, Address offset: 0x98
RTC_BKP19R EQU 0x9C ; RTC backup register 19, Address offset: 0x9C
RTC_BKP20R EQU 0xA0 ; RTC backup register 20, Address offset: 0xA0
RTC_BKP21R EQU 0xA4 ; RTC backup register 21, Address offset: 0xA4
RTC_BKP22R EQU 0xA8 ; RTC backup register 22, Address offset: 0xA8
RTC_BKP23R EQU 0xAC ; RTC backup register 23, Address offset: 0xAC
RTC_BKP24R EQU 0xB0 ; RTC backup register 24, Address offset: 0xB0
RTC_BKP25R EQU 0xB4 ; RTC backup register 25, Address offset: 0xB4
RTC_BKP26R EQU 0xB0 ; RTC backup register 26, Address offset: 0xB8
RTC_BKP27R EQU 0xB0 ; RTC backup register 27, Address offset: 0xBC
RTC_BKP28R EQU 0xC0 ; RTC backup register 28, Address offset: 0xC0
RTC_BKP29R EQU 0xC0 ; RTC backup register 29, Address offset: 0xC4
RTC_BKP30R EQU 0xC0 ; RTC backup register 30, Address offset: 0xC8
RTC_BKP31R EQU 0xC0 ; RTC backup register 31, Address offset: 0xCC
; Serial Audio Interface
SAI_GCR EQU 0x00 ; SAI global configuration register, Address offset: 0x00
SAI_Block_CR1 EQU 0x04 ; SAI block x configuration register 1, Address offset: 0x04
SAI_Block_CR2 EQU 0x08 ; SAI block x configuration register 2, Address offset: 0x08
SAI_Block_FRCR EQU 0x0C ; SAI block x frame configuration register, Address offset: 0x0C
SAI_Block_SLOTR EQU 0x10 ; SAI block x slot register, Address offset: 0x10
SAI_Block_IMR EQU 0x14 ; SAI block x interrupt mask register, Address offset: 0x14
SAI_Block_SR EQU 0x18 ; SAI block x status register, Address offset: 0x18
SAI_Block_CLRFR EQU 0x1C ; SAI block x clear flag register, Address offset: 0x1C
SAI_Block_DR EQU 0x20 ; SAI block x data register, Address offset: 0x20
; Secure digital input/output Interface
SDMMC_POWER EQU 0x00 ; SDMMC power control register, Address offset: 0x00
SDMMC_CLKCR EQU 0x04 ; SDMMC clock control register, Address offset: 0x04
SDMMC_ARG EQU 0x08 ; SDMMC argument register, Address offset: 0x08
SDMMC_CMD EQU 0x0C ; SDMMC command register, Address offset: 0x0C
SDMMC_RESPCMD EQU 0x10 ; SDMMC command response register, Address offset: 0x10
SDMMC_RESP1 EQU 0x14 ; SDMMC response 1 register, Address offset: 0x14
SDMMC_RESP2 EQU 0x18 ; SDMMC response 2 register, Address offset: 0x18
SDMMC_RESP3 EQU 0x1C ; SDMMC response 3 register, Address offset: 0x1C
SDMMC_RESP4 EQU 0x20 ; SDMMC response 4 register, Address offset: 0x20
SDMMC_DTIMER EQU 0x24 ; SDMMC data timer register, Address offset: 0x24
SDMMC_DLEN EQU 0x28 ; SDMMC data length register, Address offset: 0x28
SDMMC_DCTRL EQU 0x2C ; SDMMC data control register, Address offset: 0x2C
SDMMC_DCOUNT EQU 0x30 ; SDMMC data counter register, Address offset: 0x30
SDMMC_STA EQU 0x34 ; SDMMC status register, Address offset: 0x34
SDMMC_ICR EQU 0x38 ; SDMMC interrupt clear register, Address offset: 0x38
SDMMC_MASK EQU 0x3C ; SDMMC mask register, Address offset: 0x3C
SDMMC_RESERVED0 EQU 0x40 ; Reserved, 0x40-0x44
SDMMC_FIFOCNT EQU 0x48 ; SDMMC FIFO counter register, Address offset: 0x48
SDMMC_RESERVED1 EQU 0x4C ; Reserved, 0x4C-0x7C
SDMMC_FIFO EQU 0x80 ; SDMMC data FIFO register, Address offset: 0x80
; Serial Peripheral Interface
SPI_CR1 EQU 0x00 ; SPI Control register 1, Address offset: 0x00
SPI_CR2 EQU 0x04 ; SPI Control register 2, Address offset: 0x04
SPI_SR EQU 0x08 ; SPI Status register, Address offset: 0x08
SPI_DR EQU 0x0C ; SPI data register, Address offset: 0x0C
SPI_CRCPR EQU 0x10 ; SPI CRC polynomial register, Address offset: 0x10
SPI_RXCRCR EQU 0x14 ; SPI Rx CRC register, Address offset: 0x14
SPI_TXCRCR EQU 0x18 ; SPI Tx CRC register, Address offset: 0x18
SPI_RESERVED1 EQU 0x1C ; Reserved, Address offset: 0x1C
SPI_RESERVED2 EQU 0x20 ; Reserved, Address offset: 0x20
; Single Wire Protocol Master Interface SPWMI
SWPMI_CR EQU 0x00 ; SWPMI Configuration/Control register, Address offset: 0x00
SWPMI_BRR EQU 0x04 ; SWPMI bitrate register, Address offset: 0x04
SWPMI_RESERVED1 EQU 0x08 ; Reserved, 0x08
SWPMI_ISR EQU 0x0C ; SWPMI Interrupt and Status register, Address offset: 0x0C
SWPMI_ICR EQU 0x10 ; SWPMI Interrupt Flag Clear register, Address offset: 0x10
SWPMI_IER EQU 0x14 ; SWPMI Interrupt Enable register, Address offset: 0x14
SWPMI_RFL EQU 0x18 ; SWPMI Receive Frame Length register, Address offset: 0x18
SWPMI_TDR EQU 0x1C ; SWPMI Transmit data register, Address offset: 0x1C
SWPMI_RDR EQU 0x20 ; SWPMI Receive data register, Address offset: 0x20
SWPMI_OR EQU 0x24 ; SWPMI Option register, Address offset: 0x24
; System configuration controller
SYSCFG_MEMRMP EQU 0x00 ; SYSCFG memory remap register, Address offset: 0x00
SYSCFG_CFGR1 EQU 0x04 ; SYSCFG configuration register 1, Address offset: 0x04
SYSCFG_EXTICR0 EQU 0x08 ; SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14
SYSCFG_EXTICR1 EQU 0x0C ; SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14
SYSCFG_EXTICR2 EQU 0x10 ; SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14
SYSCFG_EXTICR3 EQU 0x14 ; SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14
SYSCFG_SCSR EQU 0x18 ; SYSCFG SRAM2 control and status register, Address offset: 0x18
SYSCFG_CFGR2 EQU 0x1C ; SYSCFG configuration register 2, Address offset: 0x1C
SYSCFG_SWPR EQU 0x20 ; SYSCFG SRAM2 write protection register, Address offset: 0x20
SYSCFG_SKR EQU 0x24 ; SYSCFG SRAM2 key register, Address offset: 0x24
; TIM
TIM_CR1 EQU 0x00 ; TIM control register 1, Address offset: 0x00
TIM_CR2 EQU 0x04 ; TIM control register 2, Address offset: 0x04
TIM_SMCR EQU 0x08 ; TIM slave mode control register, Address offset: 0x08
TIM_DIER EQU 0x0C ; TIM DMA/interrupt enable register, Address offset: 0x0C
TIM_SR EQU 0x10 ; TIM status register, Address offset: 0x10
TIM_EGR EQU 0x14 ; TIM event generation register, Address offset: 0x14
TIM_CCMR1 EQU 0x18 ; TIM capture/compare mode register 1, Address offset: 0x18
TIM_CCMR2 EQU 0x1C ; TIM capture/compare mode register 2, Address offset: 0x1C
TIM_CCER EQU 0x20 ; TIM capture/compare enable register, Address offset: 0x20
TIM_CNT EQU 0x24 ; TIM counter register, Address offset: 0x24
TIM_PSC EQU 0x28 ; TIM prescaler, Address offset: 0x28
TIM_ARR EQU 0x2C ; TIM auto-reload register, Address offset: 0x2C
TIM_RCR EQU 0x30 ; TIM repetition counter register, Address offset: 0x30
TIM_CCR1 EQU 0x34 ; TIM capture/compare register 1, Address offset: 0x34
TIM_CCR2 EQU 0x38 ; TIM capture/compare register 2, Address offset: 0x38
TIM_CCR3 EQU 0x3C ; TIM capture/compare register 3, Address offset: 0x3C
TIM_CCR4 EQU 0x40 ; TIM capture/compare register 4, Address offset: 0x40
TIM_BDTR EQU 0x44 ; TIM break and dead-time register, Address offset: 0x44
TIM_DCR EQU 0x48 ; TIM DMA control register, Address offset: 0x48
TIM_DMAR EQU 0x4C ; TIM DMA address for full transfer, Address offset: 0x4C
TIM_OR1 EQU 0x50 ; TIM option register 1, Address offset: 0x50
TIM_CCMR3 EQU 0x54 ; TIM capture/compare mode register 3, Address offset: 0x54
TIM_CCR5 EQU 0x58 ; TIM capture/compare register5, Address offset: 0x58
TIM_CCR6 EQU 0x5C ; TIM capture/compare register6, Address offset: 0x5C
TIM_OR2 EQU 0x60 ; TIM option register 2, Address offset: 0x60
TIM_OR3 EQU 0x64 ; TIM option register 3, Address offset: 0x64
; Touch Sensing Controller (TSC)
TSC_CR EQU 0x00 ; TSC control register, Address offset: 0x00
TSC_IER EQU 0x04 ; TSC interrupt enable register, Address offset: 0x04
TSC_ICR EQU 0x08 ; TSC interrupt clear register, Address offset: 0x08
TSC_ISR EQU 0x0C ; TSC interrupt status register, Address offset: 0x0C
TSC_IOHCR EQU 0x10 ; TSC I/O hysteresis control register, Address offset: 0x10
TSC_RESERVED1 EQU 0x14 ; Reserved, Address offset: 0x14
TSC_IOASCR EQU 0x18 ; TSC I/O analog switch control register, Address offset: 0x18
TSC_RESERVED2 EQU 0x1C ; Reserved, Address offset: 0x1C
TSC_IOSCR EQU 0x20 ; TSC I/O sampling control register, Address offset: 0x20
TSC_RESERVED3 EQU 0x24 ; Reserved, Address offset: 0x24
TSC_IOCCR EQU 0x28 ; TSC I/O channel control register, Address offset: 0x28
TSC_RESERVED4 EQU 0x2C ; Reserved, Address offset: 0x2C
TSC_IOGCSR EQU 0x30 ; TSC I/O group control status register, Address offset: 0x30
TSC_IOGXCR0 EQU 0x34 ; TSC I/O group x counter register, Address offset: 0x34-50
TSC_IOGXCR1 EQU 0x38 ; TSC I/O group x counter register, Address offset: 0x34-50
TSC_IOGXCR2 EQU 0x3C ; TSC I/O group x counter register, Address offset: 0x34-50
TSC_IOGXCR3 EQU 0x40 ; TSC I/O group x counter register, Address offset: 0x34-50
TSC_IOGXCR4 EQU 0x44 ; TSC I/O group x counter register, Address offset: 0x34-50
TSC_IOGXCR5 EQU 0x48 ; TSC I/O group x counter register, Address offset: 0x34-50
TSC_IOGXCR6 EQU 0x4C ; TSC I/O group x counter register, Address offset: 0x34-50
TSC_IOGXCR7 EQU 0x50 ; TSC I/O group x counter register, Address offset: 0x34-50
; Universal Synchronous Asynchronous Receiver Transmitter
USART_CR1 EQU 0x00 ; USART Control register 1, Address offset: 0x00
USART_CR2 EQU 0x04 ; USART Control register 2, Address offset: 0x04
USART_CR3 EQU 0x08 ; USART Control register 3, Address offset: 0x08
USART_BRR EQU 0x0C ; USART Baud rate register, Address offset: 0x0C
USART_GTPR EQU 0x10 ; USART Guard time and prescaler register, Address offset: 0x10
USART_RESERVED2 EQU 0x12 ; Reserved, 0x12
USART_RTOR EQU 0x14 ; USART Receiver Time Out register, Address offset: 0x14
USART_RQR EQU 0x18 ; USART Request register, Address offset: 0x18
USART_RESERVED3 EQU 0x1A ; Reserved, 0x1A
USART_ISR EQU 0x1C ; USART Interrupt and status register, Address offset: 0x1C
USART_ICR EQU 0x20 ; USART Interrupt flag Clear register, Address offset: 0x20
USART_RDR EQU 0x24 ; USART Receive Data register, Address offset: 0x24
USART_RESERVED4 EQU 0x26 ; Reserved, 0x26
USART_TDR EQU 0x28 ; USART Transmit Data register, Address offset: 0x28
USART_RESERVED5 EQU 0x2A ; Reserved, 0x2A
; VREFBUF
VREFBUF_CSR EQU 0x00 ; VREFBUF control and status register, Address offset: 0x00
VREFBUF_CCR EQU 0x04 ; VREFBUF calibration and control register, Address offset: 0x04
; Window WATCHDOG
WWDG_CR EQU 0x00 ; WWDG Control register, Address offset: 0x00
WWDG_CFR EQU 0x04 ; WWDG Configuration register, Address offset: 0x04
WWDG_SR EQU 0x08 ; WWDG Status register, Address offset: 0x08
; RNG
NRG_CR EQU 0x00 ; RNG control register, Address offset: 0x00
NRG_SR EQU 0x04 ; RNG status register, Address offset: 0x04
NRG_DR EQU 0x08 ; RNG data register, Address offset: 0x08
; USB_OTG_Core_register
USB_OTG_Global_GOTGCTL EQU 0x00 ; USB_OTG Control and Status Register 000h
USB_OTG_Global_GOTGINT EQU 0x04 ; USB_OTG Interrupt Register 004h
USB_OTG_Global_GAHBCFG EQU 0x08 ; Core AHB Configuration Register 008h
USB_OTG_Global_GUSBCFG EQU 0x0C ; Core USB Configuration Register 00Ch
USB_OTG_Global_GRSTCTL EQU 0x10 ; Core Reset Register 010h
USB_OTG_Global_GINTSTS EQU 0x14 ; Core Interrupt Register 014h
USB_OTG_Global_GINTMSK EQU 0x18 ; Core Interrupt Mask Register 018h
USB_OTG_Global_GRXSTSR EQU 0x1C ; Receive Sts Q Read Register 01Ch
USB_OTG_Global_GRXSTSP EQU 0x20 ; Receive Sts Q Read & POP Register 020h
USB_OTG_Global_GRXFSIZ EQU 0x24 ; Receive FIFO Size Register 024h
USB_OTG_Global_DIEPTXF0_HNPTXFSIZ EQU 0x28 ; EP0 / Non Periodic Tx FIFO Size Register 028h
USB_OTG_Global_HNPTXSTS EQU 0x0C ; Non Periodic Tx FIFO/Queue Sts reg 02Ch
USB_OTG_Global_Reserved30 EQU 0x30 ; Reserved 030h
USB_OTG_Global_GCCFG EQU 0x38 ; General Purpose IO Register 038h
USB_OTG_Global_CID EQU 0x3C ; User ID Register 03Ch
USB_OTG_Global_Reserved5 EQU 0x40 ; Reserved 040h-048h
USB_OTG_Global_GHWCFG3 EQU 0x4C ; User HW config3 04Ch
USB_OTG_Global_Reserved6 EQU 0x50 ; Reserved 050h
USB_OTG_Global_GLPMCFG EQU 0x54 ; LPM Register 054h
USB_OTG_Global_GPWRDN EQU 0x58 ; Power Down Register 058h
USB_OTG_Global_GDFIFOCFG EQU 0x5C ; DFIFO Software Config Register 05Ch
USB_OTG_Global_GADPCTL EQU 0x60 ; ADP Timer, Control and Status Register 60Ch
USB_OTG_Global_Reserved43 EQU 0x64 ; Reserved 058h-0FFh
USB_OTG_Global_HPTXFSIZ EQU 0x100 ; Host Periodic Tx FIFO Size Reg 100h
USB_OTG_Global_DIEPTXF0 EQU 0x104 ; dev Periodic Transmit FIFO
; USB_OTG_device_Registers
USB_OTG_Device_DCFG EQU 0x800 ; dev Configuration Register 800h
USB_OTG_Device_DCTL EQU 0x804 ; dev Control Register 804h
USB_OTG_Device_DSTS EQU 0x808 ; dev Status Register (RO) 808h
USB_OTG_Device_Reserved0C EQU 0x80C ; Reserved 80Ch
USB_OTG_Device_DIEPMSK EQU 0x810 ; dev IN Endpoint Mask 810h
USB_OTG_Device_DOEPMSK EQU 0x814 ; dev OUT Endpoint Mask 814h
USB_OTG_Device_DAINT EQU 0x818 ; dev All Endpoints Itr Reg 818h
USB_OTG_Device_DAINTMSK EQU 0x81C ; dev All Endpoints Itr Mask 81Ch
USB_OTG_Device_Reserved20 EQU 0x820 ; Reserved 820h
USB_OTG_Device_Reserved9 EQU 0x824 ; Reserved 824h
USB_OTG_Device_DVBUSDIS EQU 0x828 ; dev VBUS discharge Register 828h
USB_OTG_Device_DVBUSPULSE EQU 0x82C ; dev VBUS Pulse Register 82Ch
USB_OTG_Device_DTHRCTL EQU 0x830 ; dev thr 830h
USB_OTG_Device_DIEPEMPMSK EQU 0x834 ; dev empty msk 834h
USB_OTG_Device_DEACHINT EQU 0x838 ; dedicated EP interrupt 838h
USB_OTG_Device_DEACHMSK EQU 0x83C ; dedicated EP msk 83Ch
USB_OTG_Device_Reserved40 EQU 0x840 ; dedicated EP mask 840h
USB_OTG_Device_DINEP1MSK EQU 0x844 ; dedicated EP mask 844h
USB_OTG_Device_Reserved44 EQU 0x848 ; Reserved 844-87Ch
USB_OTG_Device_DOUTEP1MSK EQU 0x884 ; dedicated EP msk 884h
; USB_OTG_IN_Endpoint-Specific_Register
USB_OTG_INEndpoint_DIEPCTL EQU 0x900 ; dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h
USB_OTG_INEndpoint_Reserved04 EQU 0x904 ; Reserved 900h + (ep_num * 20h) + 04h
USB_OTG_INEndpoint_DIEPINT EQU 0x908 ; dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h
USB_OTG_INEndpoint_Reserved0C EQU 0x90C ; Reserved 900h + (ep_num * 20h) + 0Ch
USB_OTG_INEndpoint_DIEPTSIZ EQU 0x910 ; IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h
USB_OTG_INEndpoint_DIEPDMA EQU 0x914 ; IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h
USB_OTG_INEndpoint_DTXFSTS EQU 0x918 ; IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h
USB_OTG_INEndpoint_Reserved18 EQU 0x91C ; Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch
; USB_OTG_OUT_Endpoint-Specific_Registers
SB_OTG_OUTEndpoint_DOEPCTL EQU 0xB00 ; dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h
SB_OTG_OUTEndpoint_Reserved04 EQU 0xB04 ; Reserved B00h + (ep_num * 20h) + 04h
SB_OTG_OUTEndpoint_DOEPINT EQU 0xB08 ; dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h
SB_OTG_OUTEndpoint_Reserved0C EQU 0xB0C ; Reserved B00h + (ep_num * 20h) + 0Ch
SB_OTG_OUTEndpoint_DOEPTSIZ EQU 0xB10 ; dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h
SB_OTG_OUTEndpoint_DOEPDMA EQU 0xB14 ; dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h
SB_OTG_OUTEndpoint_Reserved18 EQU 0xB18 ; Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch
; USB_OTG_Host_Mode_Register_Structures
USB_OTG_Host_HCFG EQU 0x400 ; Host Configuration Register 400h
USB_OTG_Host_HFIR EQU 0x404 ; Host Frame Interval Register 404h
USB_OTG_Host_HFNUM EQU 0x408 ; Host Frame Nbr/Frame Remaining 408h
USB_OTG_Host_Reserved40C EQU 0x40C ; Reserved 40Ch
USB_OTG_Host_HPTXSTS EQU 0x410 ; Host Periodic Tx FIFO/ Queue Status 410h
USB_OTG_Host_HAINT EQU 0x414 ; Host All Channels Interrupt Register 414h
USB_OTG_Host_HAINTMSK EQU 0x418 ; Host All Channels Interrupt Mask 418h
; USB_OTG_Host_Channel_Specific_Registers
USB_OTG_HostChannel_HCCHAR EQU 0x00
USB_OTG_HostChannel_HCSPLT EQU 0x04
USB_OTG_HostChannel_HCINT EQU 0x08
USB_OTG_HostChannel_HCINTMSK EQU 0x0C
USB_OTG_HostChannel_HCTSIZ EQU 0x10
USB_OTG_HostChannel_HCDMA EQU 0x14
USB_OTG_HostChannel_Reserved EQU 0x18
; Peripheral_memory_map
FLASH_BASE EQU (0x08000000) ; FLASH(up to 1 MB) base address
SRAM1_BASE EQU (0x20000000) ; SRAM1(96 KB) base address
PERIPH_BASE EQU (0x40000000) ; Peripheral base address
FMC_BASE EQU (0x60000000) ; FMC base address
SRAM2_BASE EQU (0x10000000) ; SRAM2(32 KB) base address
FMC_R_BASE EQU (0xA0000000) ; FMC control registers base address
QSPI_R_BASE EQU (0xA0001000) ; QUADSPI control registers base address
SRAM1_BB_BASE EQU (0x22000000) ; SRAM1(96 KB) base address in the bit-band region
PERIPH_BB_BASE EQU (0x42000000) ; Peripheral base address in the bit-band region
SRAM2_BB_BASE EQU (0x12000000) ; SRAM2(32 KB) base address in the bit-band region
; Legacy defines
SRAM_BASE EQU SRAM1_BASE
SRAM_BB_BASE EQU SRAM1_BB_BASE
SRAM1_SIZE_MAX EQU (0x00018000) ; maximum SRAM1 size (up to 96 KBytes)
SRAM2_SIZE EQU (0x00008000) ; SRAM2 size (32 KBytes)
; Peripheral memory map
APB1PERIPH_BASE EQU PERIPH_BASE
APB2PERIPH_BASE EQU (PERIPH_BASE + 0x00010000)
AHB1PERIPH_BASE EQU (PERIPH_BASE + 0x00020000)
AHB2PERIPH_BASE EQU (PERIPH_BASE + 0x08000000)
FMC_BANK1 EQU FMC_BASE
FMC_BANK1_1 EQU FMC_BANK1
FMC_BANK1_2 EQU (FMC_BANK1 + 0x04000000)
FMC_BANK1_3 EQU (FMC_BANK1 + 0x08000000)
FMC_BANK1_4 EQU (FMC_BANK1 + 0x0C000000)
FMC_BANK3 EQU (FMC_BASE + 0x20000000)
; APB1 peripherals
TIM2_BASE EQU (APB1PERIPH_BASE + 0x0000)
TIM3_BASE EQU (APB1PERIPH_BASE + 0x0400)
TIM4_BASE EQU (APB1PERIPH_BASE + 0x0800)
TIM5_BASE EQU (APB1PERIPH_BASE + 0x0C00)
TIM6_BASE EQU (APB1PERIPH_BASE + 0x1000)
TIM7_BASE EQU (APB1PERIPH_BASE + 0x1400)
LCD_BASE EQU (APB1PERIPH_BASE + 0x2400)
RTC_BASE EQU (APB1PERIPH_BASE + 0x2800)
WWDG_BASE EQU (APB1PERIPH_BASE + 0x2C00)
IWDG_BASE EQU (APB1PERIPH_BASE + 0x3000)
SPI2_BASE EQU (APB1PERIPH_BASE + 0x3800)
SPI3_BASE EQU (APB1PERIPH_BASE + 0x3C00)
USART2_BASE EQU (APB1PERIPH_BASE + 0x4400)
USART3_BASE EQU (APB1PERIPH_BASE + 0x4800)
UART4_BASE EQU (APB1PERIPH_BASE + 0x4C00)
UART5_BASE EQU (APB1PERIPH_BASE + 0x5000)
I2C1_BASE EQU (APB1PERIPH_BASE + 0x5400)
I2C2_BASE EQU (APB1PERIPH_BASE + 0x5800)
I2C3_BASE EQU (APB1PERIPH_BASE + 0x5C00)
CAN1_BASE EQU (APB1PERIPH_BASE + 0x6400)
LPTIM1_BASE EQU (APB1PERIPH_BASE + 0x7C00)
PWR_BASE EQU (APB1PERIPH_BASE + 0x7000)
DAC_BASE EQU (APB1PERIPH_BASE + 0x7400)
DAC1_BASE EQU (APB1PERIPH_BASE + 0x7400)
OPAMP_BASE EQU (APB1PERIPH_BASE + 0x7800)
OPAMP1_BASE EQU (APB1PERIPH_BASE + 0x7800)
OPAMP2_BASE EQU (APB1PERIPH_BASE + 0x7810)
LPUART1_BASE EQU (APB1PERIPH_BASE + 0x8000)
SWPMI1_BASE EQU (APB1PERIPH_BASE + 0x8800)
LPTIM2_BASE EQU (APB1PERIPH_BASE + 0x9400)
; APB2 peripherals
SYSCFG_BASE EQU (APB2PERIPH_BASE + 0x0000)
VREFBUF_BASE EQU (APB2PERIPH_BASE + 0x0030)
COMP1_BASE EQU (APB2PERIPH_BASE + 0x0200)
COMP2_BASE EQU (APB2PERIPH_BASE + 0x0204)
EXTI_BASE EQU (APB2PERIPH_BASE + 0x0400)
FIREWALL_BASE EQU (APB2PERIPH_BASE + 0x1C00)
SDMMC1_BASE EQU (APB2PERIPH_BASE + 0x2800)
TIM1_BASE EQU (APB2PERIPH_BASE + 0x2C00)
SPI1_BASE EQU (APB2PERIPH_BASE + 0x3000)
TIM8_BASE EQU (APB2PERIPH_BASE + 0x3400)
USART1_BASE EQU (APB2PERIPH_BASE + 0x3800)
TIM15_BASE EQU (APB2PERIPH_BASE + 0x4000)
TIM16_BASE EQU (APB2PERIPH_BASE + 0x4400)
TIM17_BASE EQU (APB2PERIPH_BASE + 0x4800)
SAI1_BASE EQU (APB2PERIPH_BASE + 0x5400)
SAI1_Block_A_BASE EQU (SAI1_BASE + 0x004)
SAI1_Block_B_BASE EQU (SAI1_BASE + 0x024)
SAI2_BASE EQU (APB2PERIPH_BASE + 0x5800)
SAI2_Block_A_BASE EQU (SAI2_BASE + 0x004)
SAI2_Block_B_BASE EQU (SAI2_BASE + 0x024)
DFSDM_BASE EQU (APB2PERIPH_BASE + 0x6000)
DFSDM_Channel0_BASE EQU (DFSDM_BASE + 0x00)
DFSDM_Channel1_BASE EQU (DFSDM_BASE + 0x20)
DFSDM_Channel2_BASE EQU (DFSDM_BASE + 0x40)
DFSDM_Channel3_BASE EQU (DFSDM_BASE + 0x60)
DFSDM_Channel4_BASE EQU (DFSDM_BASE + 0x80)
DFSDM_Channel5_BASE EQU (DFSDM_BASE + 0xA0)
DFSDM_Channel6_BASE EQU (DFSDM_BASE + 0xC0)
DFSDM_Channel7_BASE EQU (DFSDM_BASE + 0xE0)
DFSDM_Filter0_BASE EQU (DFSDM_BASE + 0x100)
DFSDM_Filter1_BASE EQU (DFSDM_BASE + 0x180)
DFSDM_Filter2_BASE EQU (DFSDM_BASE + 0x200)
DFSDM_Filter3_BASE EQU (DFSDM_BASE + 0x280)
; AHB1 peripherals
DMA1_BASE EQU (AHB1PERIPH_BASE)
DMA2_BASE EQU (AHB1PERIPH_BASE + 0x0400)
RCC_BASE EQU (AHB1PERIPH_BASE + 0x1000)
FLASH_R_BASE EQU (AHB1PERIPH_BASE + 0x2000)
CRC_BASE EQU (AHB1PERIPH_BASE + 0x3000)
TSC_BASE EQU (AHB1PERIPH_BASE + 0x4000)
DMA1_Channel1_BASE EQU (DMA1_BASE + 0x0008)
DMA1_Channel2_BASE EQU (DMA1_BASE + 0x001C)
DMA1_Channel3_BASE EQU (DMA1_BASE + 0x0030)
DMA1_Channel4_BASE EQU (DMA1_BASE + 0x0044)
DMA1_Channel5_BASE EQU (DMA1_BASE + 0x0058)
DMA1_Channel6_BASE EQU (DMA1_BASE + 0x006C)
DMA1_Channel7_BASE EQU (DMA1_BASE + 0x0080)
DMA1_CSELR_BASE EQU (DMA1_BASE + 0x00A8)
DMA2_Channel1_BASE EQU (DMA2_BASE + 0x0008)
DMA2_Channel2_BASE EQU (DMA2_BASE + 0x001C)
DMA2_Channel3_BASE EQU (DMA2_BASE + 0x0030)
DMA2_Channel4_BASE EQU (DMA2_BASE + 0x0044)
DMA2_Channel5_BASE EQU (DMA2_BASE + 0x0058)
DMA2_Channel6_BASE EQU (DMA2_BASE + 0x006C)
DMA2_Channel7_BASE EQU (DMA2_BASE + 0x0080)
DMA2_CSELR_BASE EQU (DMA2_BASE + 0x00A8)
; AHB2 peripherals
GPIOA_BASE EQU (AHB2PERIPH_BASE + 0x0000)
GPIOB_BASE EQU (AHB2PERIPH_BASE + 0x0400)
GPIOC_BASE EQU (AHB2PERIPH_BASE + 0x0800)
GPIOD_BASE EQU (AHB2PERIPH_BASE + 0x0C00)
GPIOE_BASE EQU (AHB2PERIPH_BASE + 0x1000)
GPIOF_BASE EQU (AHB2PERIPH_BASE + 0x1400)
GPIOG_BASE EQU (AHB2PERIPH_BASE + 0x1800)
GPIOH_BASE EQU (AHB2PERIPH_BASE + 0x1C00)
USBOTG_BASE EQU (AHB2PERIPH_BASE + 0x08000000)
ADC1_BASE EQU (AHB2PERIPH_BASE + 0x08040000)
ADC2_BASE EQU (AHB2PERIPH_BASE + 0x08040100)
ADC3_BASE EQU (AHB2PERIPH_BASE + 0x08040200)
ADC123_COMMON_BASE EQU (AHB2PERIPH_BASE + 0x08040300)
RNG_BASE EQU (AHB2PERIPH_BASE + 0x08060800)
; FMC Banks registers base address
FMC_Bank1_R_BASE EQU (FMC_R_BASE + 0x0000)
FMC_Bank1E_R_BASE EQU (FMC_R_BASE + 0x0104)
FMC_Bank2_R_BASE EQU (FMC_R_BASE + 0x0060)
FMC_Bank3_R_BASE EQU (FMC_R_BASE + 0x0080)
FMC_Bank4_R_BASE EQU (FMC_R_BASE + 0x00A0)
; Debug MCU registers base address
DBGMCU_BASE EQU (0xE0042000)
; USB registers base address
USB_OTG_FS_PERIPH_BASE EQU (0x50000000)
USB_OTG_GLOBAL_BASE EQU (0x000)
USB_OTG_DEVICE_BASE EQU (0x800)
USB_OTG_IN_ENDPOINT_BASE EQU (0x900)
USB_OTG_OUT_ENDPOINT_BASE EQU (0xB00)
USB_OTG_EP_REG_SIZE EQU (0x20)
USB_OTG_HOST_BASE EQU (0x400)
USB_OTG_HOST_PORT_BASE EQU (0x440)
USB_OTG_HOST_CHANNEL_BASE EQU (0x500)