jesd204b glossary

JESD204B Glossary

Control characters

Character	Code	Description
/R/	K28.0	Initial lane alignment sequence multi-frame start.
/A/	K28.3	Lane alignment
/Q/	K28.4	Initial lane alignment sequence configuration marker.
/K/	K28.5	Code group synchronization.
/F/	K28.7	Frame synchronization.

Abbreviations

Abbreviation	Meaning
CGS	Code Group Synchronization
ILAS	Initial Lane Alignment Sequence
LMFC	Local Multi Frame Clock
MCDA	Multiple Converter Device Alignment
NMCDA	No Multiple Converter Device Alignment
RBD	RX Buffer Delay

Clocks

Clock Type	Description
character clock	Clock with which 8b10b characters and octets are generated.
conversion clock	Clock used by a converter device to perform the A2D or D2A conversion.
device clock	Master clock supplied to the JESD204B device from which all other clock signals must be derived.
frame clock	Clock rate at which samples are generated/processed. Has the same rate as the conversion clock, except for interpolating DACs or decimating DACs, where it is slower by the interpolation/decimation factor.
line clock	Clock for the high-speed serial interface.
local clock	A clock generated inside a JESD204B device.
SYSREF clock	Slow clock used for cross-device synchronization purposes.

All clocks inside a JESD204B system must have a integer relationship.