AD469x Platform FPGA Architecture cpack Module

The ad469x_cpack module receives the 16 channels of 16-bit adc_data along with adc_valid signals and packs them into a single 256bit bus.

The packing is dependent on which channels are enabled. The enables are driven from memory-mapped registers in the axi_ad469x_adc axi_adc_core module.

Below, are examples of packing ADC data.

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