NDK: [MAINTENANCE] Update NDK CORE and OFM submodule

CESNET · Feb 7, 2024 · 03d8b9c · 03d8b9c
1 parent 27e3f5d
commit 03d8b9c
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/ndk/core b/ndk/core
diff --git a/ndk/ofm b/ndk/ofm
+2 −0		intel/Modules.tcl
+1 −1		intel/doc/mi.rst
+7 −1		intel/src/DevTree.tcl
+17 −0		intel/src/comp/jtag_op_ctrl/Modules.tcl
+35 −0		intel/src/comp/jtag_op_ctrl/jtag_op_ctrl_arch.vhd
+19 −0		intel/src/comp/jtag_op_ctrl/jtag_op_ctrl_empty.vhd
+58 −0		intel/src/comp/jtag_op_ctrl/jtag_op_ctrl_ent.vhd
+157 −331		intel/src/comp/network_mod/comp/network_mod_core/network_mod_core_etile.vhd
+14 −2		intel/src/comp/network_mod/comp/network_mod_logic/network_mod_logic.vhd
+3 −1		intel/src/comp/network_mod/uvm/Modules.tcl
+6 −5		intel/src/comp/network_mod/uvm/signals_sig.fdo
+12 −9		intel/src/comp/network_mod/uvm/tbench/env/env.sv
+1 −0		intel/src/comp/network_mod/uvm/tbench/env/model.sv
+4 −0		intel/src/comp/network_mod/uvm/tbench/env/pkg.sv
+314 −0		intel/src/comp/network_mod/uvm/tbench/env/reg_sequence.sv
+29 −0		intel/src/comp/network_mod/uvm/tbench/env/registers.sv
+119 −0		intel/src/comp/network_mod/uvm/tbench/env/regmodel.sv
+77 −35		intel/src/comp/network_mod/uvm/tbench/env/sequence.sv
+13 −1		intel/src/comp/network_mod/uvm/tbench/env/sequencer.sv
+2 −10		intel/src/comp/network_mod/uvm/top_level.fdo
+24 −0		intel/src/fpga_common.vhd
+2 −2		intel/src/mi_addr_space_pkg.vhd
+11 −0		comp/debug/jtag_op_client/DevTree.tcl
+16 −0		comp/debug/jtag_op_client/Modules.tcl
+199 −0		comp/debug/jtag_op_client/jtag_op_client.vhd
+2,696 −0		comp/debug/jtag_op_client/jtag_op_ip.ip
+87 −0		comp/debug/jtag_op_client/readme.rst
+91 −0		comp/debug/jtag_op_client/sw/jtag_op_mgmt.py
+18 −0		comp/debug/jtag_op_client/synth/Makefile
+8 −7		comp/mfb_tools/flow/enabler/enabler.vhd
+7 −3		comp/nic/mac_lite/rx_mac_lite/rx_mac_lite.vhd
+9 −0		comp/nic/mac_lite/rx_mac_lite/uvm/Modules.tcl
+170 −0		comp/nic/mac_lite/rx_mac_lite/uvm/base.sv
+21 −0		comp/nic/mac_lite/rx_mac_lite/uvm/pkg.sv
+236 −0		comp/nic/mac_lite/rx_mac_lite/uvm/registers.sv
+160 −0		comp/nic/mac_lite/rx_mac_lite/uvm/regmodel.sv
+258 −0		comp/nic/mac_lite/rx_mac_lite/uvm/rfc.sv
+9 −0		comp/nic/mac_lite/tx_mac_lite/uvm/Modules.tcl
+19 −0		comp/nic/mac_lite/tx_mac_lite/uvm/pkg.sv
+96 −0		comp/nic/mac_lite/tx_mac_lite/uvm/registers.sv
+117 −0		comp/nic/mac_lite/tx_mac_lite/uvm/regmodel.sv
+1 −0		comp/uvm/common/pkg.sv
+56 −0		comp/uvm/common/sync.sv
+1 −1		comp/uvm/logic_vector_array_avst/sequence.sv
+70 −10		comp/uvm/mi/reg2bus_convert.sv
+3 −0		comp/uvm/probe/cbs.sv
+19 −5		comp/uvm/reset/sequence.sv
+1 −0		doc/source/debug.rst