diff --git a/comp/base/logic/squarer/Modules.tcl b/comp/base/logic/squarer/Modules.tcl deleted file mode 100644 index d381604b3..000000000 --- a/comp/base/logic/squarer/Modules.tcl +++ /dev/null @@ -1,17 +0,0 @@ -# Modules.tcl: Local include Modules tcl script -# Copyright (C) 2009 CESNET -# Author: Ondrej Lengal -# -# SPDX-License-Identifier: BSD-3-Clause - -# files with separate entity definition -set MOD "$MOD $ENTITY_BASE/squarer_ent.vhd" - -if { $ARCHGRP == "FULL" } { - - # files with both entity declaration and architecture definition - set MOD "$MOD $ENTITY_BASE/sqr_dop2_lat1.vhd" - - # files with separate architecture definition - set MOD "$MOD $ENTITY_BASE/squarer.vhd" -} diff --git a/comp/base/logic/squarer/sim/signals.fdo b/comp/base/logic/squarer/sim/signals.fdo deleted file mode 100644 index 1c56daa0f..000000000 --- a/comp/base/logic/squarer/sim/signals.fdo +++ /dev/null @@ -1,16 +0,0 @@ -# signals.fdo : Include file with signals -# Copyright (C) 2009 CESNET -# Author: Ondrej Lengal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -proc blk_squarer_ifc { BASE } { - - add_wave "-noupdate -label clk -color yellow " $BASE/CLK - - add_wave "-noupdate -unsigned -label data " $BASE/DATA - add_wave "-noupdate -unsigned -label result " $BASE/RESULT - -} diff --git a/comp/base/logic/squarer/sim/squarer.fdo b/comp/base/logic/squarer/sim/squarer.fdo deleted file mode 100644 index 6ee37a581..000000000 --- a/comp/base/logic/squarer/sim/squarer.fdo +++ /dev/null @@ -1,24 +0,0 @@ -# squarer.fdo: Squarer simulation file -# Copyright (C) 2009 CESNET -# Author: Ondrej Lengal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -set FIRMWARE_BASE "../../../../.." -set COMP_BASE "$FIRMWARE_BASE/comp" -set SQUARER_BASE "$OFM_PATH/comp/base/logic/squarer" - -set SIG_FILE "$SQUARER_BASE/sim/squarer_sig.fdo" -set SIGNALS_FILE "$SQUARER_BASE/sim/signals.fdo" -set TB_FILE "$SQUARER_BASE/sim/squarer_tb.vhd" - - -set COMPONENTS [list \ - [ list "SQUARER" $SQUARER_BASE "FULL"] \ - ] - -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -nb_sim_run 1000ms diff --git a/comp/base/logic/squarer/sim/squarer_sig.fdo b/comp/base/logic/squarer/sim/squarer_sig.fdo deleted file mode 100644 index 3e493e80c..000000000 --- a/comp/base/logic/squarer/sim/squarer_sig.fdo +++ /dev/null @@ -1,23 +0,0 @@ -# squarer.fdo : Include file with signals -# Copyright (C) 2009 CESNET -# Author: Ondrej Lengal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths - -source $SIGNALS_FILE - -set TB_PATH "/testbench" -set SQUARER_PATH "$TB_PATH/uut" - -add_wave "-noupdate -label clk -color yellow " $TB_PATH/clk - -add wave -divider "*****************************" -add wave -divider " Squarer " -add wave -divider "*****************************" -blk_squarer_ifc "$SQUARER_PATH" - diff --git a/comp/base/logic/squarer/sim/squarer_tb.vhd b/comp/base/logic/squarer/sim/squarer_tb.vhd deleted file mode 100644 index df46a1f00..000000000 --- a/comp/base/logic/squarer/sim/squarer_tb.vhd +++ /dev/null @@ -1,151 +0,0 @@ --- squarer_tb.vhd: Testbench for Squarer --- Copyright (C) 2009 CESNET --- Author: Ondrej Lengal --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity testbench is -end entity testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture behavioral of testbench is - - -- ------------------------------------------------------------------------- - -- Constants - -- ------------------------------------------------------------------------- - - constant OPERAND_WIDTH : integer := 34; - constant RESULT_WIDTH : integer := 68; - constant DEGREE_OF_PARALLELISM : integer := 2; - constant LATENCY : integer := 1; - - -- Other constants - constant clkper : time := 10 ns; - constant reset_time : time := 100 ns; - - -- ------------------------------------------------------------------------- - -- Signals - -- ------------------------------------------------------------------------- - - -- common interface - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - - -- data inputs - signal data : std_logic_vector(OPERAND_WIDTH-1 downto 0) := (others => '0'); - signal reg_data : std_logic_vector(OPERAND_WIDTH-1 downto 0) := (others => '0'); - - -- data output - signal result : std_logic_vector(RESULT_WIDTH-1 downto 0) := (others => '0'); - - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- -begin - - -- ------------------------------------------------------------------------- - -- Squarer - -- ------------------------------------------------------------------------- - uut: entity work.SQUARER - generic map - ( - -- widths of operand - OPERAND_WIDTH => OPERAND_WIDTH, - -- width of result - RESULT_WIDTH => RESULT_WIDTH, - -- degree of parallelism, i.e. into how many parts will the input be split - DEGREE_OF_PARALLELISM => DEGREE_OF_PARALLELISM, - -- latency in clock cycles - LATENCY => LATENCY - ) - port map - ( - -- common interface - CLK => clk, - - -- the operand - -- NOTE: squarer works by default as signed. For this reason, you need - -- to set the MSB to something you don't need (it doesn't matter - -- whether to '0' or '1' because square operation makes the result - -- positive either way - DATA => data, - - -- result (is valid LATENCY clock cycles after operands are set) - RESULT => result - ); - - - -- clock generator --------------------------------------------------------- - clk_gen : process - begin - clk <= '1'; - wait for clkper/2; - clk <= '0'; - wait for clkper/2; - end process; - - -- reset generator -------------------------------------------------------- - reset_gen : process - begin - reset <= '1'; - wait for reset_time; - reset <= '0'; - wait; - end process; - - -- counter of input data - cnt_data_p: process (clk) - begin - if (rising_edge(clk)) then - if (reset = '1') then - data <= (others => '0'); - else - data <= data + 100000; - end if; - end if; - end process; - - -- register for saving data - reg_data_p: process (clk) - begin - if (rising_edge(clk)) then - reg_data <= data; - end if; - end process; - - cmp_valid_sqr_p: process (clk) - begin - assert ((reset = '1') OR (result = (reg_data * reg_data))) - report "Verification failure!" - severity failure; - end process; - - - --- ---------------------------------------------------------------------------- --- Main testbench process --- ---------------------------------------------------------------------------- -tb : process -begin - - wait; -end process; - -end architecture; diff --git a/comp/base/logic/squarer/sqr_dop2_lat1.vhd b/comp/base/logic/squarer/sqr_dop2_lat1.vhd deleted file mode 100644 index 7b3e676e8..000000000 --- a/comp/base/logic/squarer/sqr_dop2_lat1.vhd +++ /dev/null @@ -1,229 +0,0 @@ --- sqr_dop2_lat1.vhd: Squarer with 2 parts and latency of 1 clock cycles --- Copyright (C) 2009 CESNET --- Author(s): Ondrej Lengal --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - ---library unisim; ---use unisim.vcomponents.all; - --- ========================================================================== --- ENTITY DECLARATION --- ========================================================================== -entity SQR_DOP2_LAT1 is - generic - ( - -- widths of operands - OPERAND_WIDTH : integer := 34; - -- width of result - RESULT_WIDTH : integer := 68 - ); - port - ( - -- common interface - CLK : in std_logic; - - -- operand - DATA : in std_logic_vector(OPERAND_WIDTH-1 downto 0); - - -- result (is valid 2 clock cycles after operands are set) - RESULT : out std_logic_vector(RESULT_WIDTH-1 downto 0) - ); -end entity; - - --- ========================================================================== --- ARCHITECTURE DESCRIPTION --- ========================================================================== -architecture arch of SQR_DOP2_LAT1 is - --- ========================================================================== --- TYPES --- ========================================================================== - - -- attribute not to merge logic blocks, should prevent pushing registers - -- into DSP block - attribute keep : string; - - -- attribute for the use of DSP48 for adders - attribute use_dsp48 : string; - --- ========================================================================== --- CONSTANTS --- ========================================================================== - - -- constants for ranges - constant IN_RNG : integer := OPERAND_WIDTH / 2; - constant RES_RNG : integer := 2 * IN_RNG; - constant RES_HALF_RNG : integer := RES_RNG / 2; - - -- assignment of bit numbers for input - constant IN_LOWER_LSB : integer := 0; - constant IN_LOWER_MSB : integer := IN_LOWER_LSB + IN_RNG - 1; - constant IN_HIGHER_LSB : integer := IN_LOWER_MSB + 1; - constant IN_HIGHER_MSB : integer := IN_HIGHER_LSB + IN_RNG - 1; - - -- assignment of bit numbers for result - constant RES_LOWER_LSB : integer := 0; - constant RES_LOWER_MSB : integer := RES_LOWER_LSB + RES_RNG - 1; - constant RES_HIGHER_LSB : integer := RES_LOWER_MSB + 1; - constant RES_HIGHER_MSB : integer := RES_HIGHER_LSB + RES_RNG - 1; - constant RES_HILO_LSB : integer := IN_RNG; - constant RES_HILO_MSB : integer := RES_HILO_LSB + RES_RNG - 1; - - --- ========================================================================== --- SIGNALS --- ========================================================================== - - -- split input operands - signal data_lo : std_logic_vector(IN_RNG-1 downto 0); - signal data_hi : std_logic_vector(IN_RNG-1 downto 0); - - -- multiplication partial results - signal mult_hihi : std_logic_vector(RES_RNG-1 downto 0); - signal mult_hilo : std_logic_vector(RES_RNG-1 downto 0); - signal mult_lolo : std_logic_vector(RES_RNG-1 downto 0); - - -- registers for saving multipliers result - signal reg_mult_hihi : std_logic_vector(RES_RNG-1 downto 0); - signal reg_mult_hilo : std_logic_vector(RES_RNG-1 downto 0); - signal reg_mult_lolo : std_logic_vector(RES_RNG-1 downto 0); - - -- adder - signal sum_lo_in0 : std_logic_vector(RES_HALF_RNG-1 downto 0); - signal sum_lo_in1 : std_logic_vector(RES_HALF_RNG-1 downto 0); - signal sum_lo : std_logic_vector(RES_HALF_RNG-1 downto 0); - - signal sum_hi_cin : std_logic; - signal sum_hi_in0 : std_logic_vector(RES_HALF_RNG+1 downto 0); - signal sum_hi_in1 : std_logic_vector(RES_HALF_RNG+1 downto 0); - signal sum_hi : std_logic_vector(RES_HALF_RNG+1 downto 0); - - signal highest : std_logic_vector(RES_HALF_RNG-2 downto 0); - - signal sum_all : std_logic_vector(RESULT_WIDTH-1 downto 0); - - -- implement adders in DSPs - -- NOTE: I commented it out because XST is stupid and if you wanted to - -- store the result into a register, it moved the register into the - -- DSP no matter that you had a computation behind that register, - -- therefore the critical path was lengthened - --attribute use_dsp48 of sum_lo : signal is "yes"; - --attribute use_dsp48 of sum_hi : signal is "yes"; - --attribute use_dsp48 of highest: signal is "yes"; - - -- do not merge registers that may be on inputs/outputs into DSP blocks - attribute keep of DATA : signal is "true"; - attribute keep of RESULT : signal is "true"; - -begin - - -- -------------------------------------------------------------------------- - -- Description - -- -------------------------------------------------------------------------- - -- - -- The squarer splits the operands into two parts and multiplies them - -- separately while exploiting the formula, e.g. for OPERAND_WIDTH = 24: - -- - -- (a*2^12 + b)^2 = a^2 * 2^24 + b^2 + 2^13 * a * b - -- - -- where: - -- a = x(23:12) - -- b = x(11:0) - -- - - - -- -------------------------------------------------------------------------- - -- Assertions - -- -------------------------------------------------------------------------- - - assert (OPERAND_WIDTH mod 2 = 0) - report "Only even width of operand supported!" - severity failure; - - - -- -------------------------------------------------------------------------- - -- Inputs - -- -------------------------------------------------------------------------- - - data_lo <= DATA(IN_LOWER_MSB downto IN_LOWER_LSB); - data_hi <= DATA(IN_HIGHER_MSB downto IN_HIGHER_LSB); - - - -- -------------------------------------------------------------------------- - -- Multiplication - -- -------------------------------------------------------------------------- - - -- partial multiplications - mult_hihi <= data_hi * data_hi; - mult_hilo <= data_hi * data_lo; - mult_lolo <= data_lo * data_lo; - - - -- -------------------------------------------------------------------------- - -- Pipelining registers - -- -------------------------------------------------------------------------- - - reg_mult_hihi_p: process (CLK) - begin - if (rising_edge(CLK)) then - reg_mult_hihi <= mult_hihi; - end if; - end process; - - reg_mult_hilo_p: process (CLK) - begin - if (rising_edge(CLK)) then - reg_mult_hilo <= mult_hilo; - end if; - end process; - - reg_mult_lolo_p: process (CLK) - begin - if (rising_edge(CLK)) then - reg_mult_lolo <= mult_lolo; - end if; - end process; - - - -- -------------------------------------------------------------------------- - -- Addition - -- -------------------------------------------------------------------------- - - -- addition of lower part of the result - sum_lo_in0 <= '0' & reg_mult_hilo(RES_HALF_RNG-2 downto 0); - sum_lo_in1 <= '0' & reg_mult_lolo(RES_RNG-1 downto RES_HALF_RNG+1); - sum_lo <= sum_lo_in0 + sum_lo_in1; - - -- addition of higher part of the result - sum_hi_cin <= sum_lo(RES_HALF_RNG-1); - sum_hi_in0 <= '0' & reg_mult_hihi(RES_HALF_RNG downto 0); - sum_hi_in1 <= '0' & reg_mult_hilo(RES_RNG-1 downto RES_HALF_RNG-1); - sum_hi <= sum_hi_in0 + sum_hi_in1 + sum_hi_cin; - - -- adding to the highest part - highest <= reg_mult_hihi(RES_RNG-1 downto RES_HALF_RNG+1) - + sum_hi(RES_HALF_RNG+1); - - -- composing the whole sum into a single vector - sum_all <= highest - & sum_hi(RES_HALF_RNG downto 0) - & sum_lo(RES_HALF_RNG-2 downto 0) - & reg_mult_lolo(RES_HALF_RNG downto 0); - - -- -------------------------------------------------------------------------- - -- Output - -- -------------------------------------------------------------------------- - - RESULT <= sum_all; - -end architecture; diff --git a/comp/base/logic/squarer/squarer.vhd b/comp/base/logic/squarer/squarer.vhd deleted file mode 100644 index 6a480c26e..000000000 --- a/comp/base/logic/squarer/squarer.vhd +++ /dev/null @@ -1,47 +0,0 @@ --- squarer.vhd: Squarer wrapper --- Copyright (C) 2009 CESNET --- Author(s): Ondrej Lengal --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library ieee; -use ieee.std_logic_1164.all; - --- ========================================================================== --- ARCHITECTURE DESCRIPTION --- ========================================================================== -architecture arch of SQUARER is -begin - - -- when you add a new setting, add it at the end of OR in this assert - assert (((DEGREE_OF_PARALLELISM = 2) AND (LATENCY = 1)) OR false) - report "Unsupported settings of DEGREE_OF_PARALLELISM and LATENCY!" - severity failure; - - gen_sqr_dop2_lat1: if ((DEGREE_OF_PARALLELISM = 2) AND (LATENCY = 1)) generate - - sqr: entity work.SQR_DOP2_LAT1 - generic map - ( - -- widths of operands - OPERAND_WIDTH => OPERAND_WIDTH, - -- width of result - RESULT_WIDTH => RESULT_WIDTH - ) - port map - ( - -- common interface - CLK => CLK, - - -- operand - DATA => DATA, - - -- result (is valid 2 clock cycles after operands are set) - RESULT => RESULT - ); - end generate; - -end architecture; diff --git a/comp/base/logic/squarer/squarer_ent.vhd b/comp/base/logic/squarer/squarer_ent.vhd deleted file mode 100644 index 1e0a13b18..000000000 --- a/comp/base/logic/squarer/squarer_ent.vhd +++ /dev/null @@ -1,39 +0,0 @@ --- squarer_ent.vhd: Squarer entity declaration --- Copyright (C) 2009 CESNET --- Author(s): Ondrej Lengal --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library ieee; -use ieee.std_logic_1164.all; - --- ========================================================================== --- ENTITY DECLARATION --- ========================================================================== -entity SQUARER is - generic - ( - -- widths of operand - OPERAND_WIDTH : integer := 20; - -- width of result - RESULT_WIDTH : integer := 40; - -- degree of parallelism, i.e. into how many parts will the input be split - DEGREE_OF_PARALLELISM : integer := 2; - -- latency in clock cycles - LATENCY : integer := 1 - ); - port - ( - -- common interface - CLK : in std_logic; - - -- the operand - DATA : in std_logic_vector(OPERAND_WIDTH-1 downto 0); - - -- result (is valid LATENCY clock cycles after operands are set) - RESULT : out std_logic_vector(RESULT_WIDTH-1 downto 0) - ); -end entity; diff --git a/comp/base/logic/squarer/synth/Makefile b/comp/base/logic/squarer/synth/Makefile deleted file mode 100644 index 6e3e79f24..000000000 --- a/comp/base/logic/squarer/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=squarer - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/base/mem/cam/Modules.tcl b/comp/base/mem/cam/Modules.tcl deleted file mode 100644 index 758ca518a..000000000 --- a/comp/base/mem/cam/Modules.tcl +++ /dev/null @@ -1,27 +0,0 @@ -# Modules.tcl: Local include Modules tcl script -# Copyright (C) 2007 CESNET -# Author: Martin Kosek -# -# SPDX-License-Identifier: BSD-3-Clause - -set CARRY_BASE "$OFM_PATH/comp/base/logic/carry_chain" -set DEC_MODULE "$OFM_PATH/comp/base/logic/dec1fn/dec1fn_enable.vhd" - -set MOD "$MOD $DEC_MODULE" -set PKG_BASE "$OFM_PATH/comp/base/pkg" -set COMPONENTS [list \ - [ list "PKG" $PKG_BASE "MATH"] \ - [ list "CARRY" $CARRY_BASE "FULL"] \ -] - -if { $ARCHGRP == "LIGHT" } { - #lightweight version of CAM made of registers - set MOD "$MOD $ENTITY_BASE/cam_light_2port.vhd" - set MOD "$MOD $ENTITY_BASE/cam_light.vhd" -} else { - set MOD "$MOD $ENTITY_BASE/cam_fill_element.vhd" - set MOD "$MOD $ENTITY_BASE/cam_filling_part.vhd" - set MOD "$MOD $ENTITY_BASE/cam_row.vhd" - set MOD "$MOD $ENTITY_BASE/cam_data_array.vhd" - set MOD "$MOD $ENTITY_BASE/cam.vhd" -} diff --git a/comp/base/mem/cam/README b/comp/base/mem/cam/README deleted file mode 100644 index 4d209c7ee..000000000 --- a/comp/base/mem/cam/README +++ /dev/null @@ -1,6 +0,0 @@ -Ternary Content Associative Memory (TCAM) -========================================= - -For most scenarios, use the CAM entity in VHDL, and "CAM" entity name and "CAM" archgrp in Modules.tcl - -Documentation: https://homeproj.cesnet.cz/projects/fwbase/wiki/CAM diff --git a/comp/base/mem/cam/cam.vhd b/comp/base/mem/cam/cam.vhd deleted file mode 100644 index c30277cfe..000000000 --- a/comp/base/mem/cam/cam.vhd +++ /dev/null @@ -1,192 +0,0 @@ --- --- cam.vhd: Top level of CAM component --- Copyright (C) 2006 CESNET --- Author(s): Martin kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity CAM is - generic ( - -- Data row width (bits, should be a multiple of ELEM_WIDTH) - CAM_ROW_WIDTH : integer := 128; - -- Number of data rows (depth of the CAM) - CAM_ROW_COUNT : integer := 32; - -- Width of address bus - -- set to log2(CAM_ROW_COUNT) - CAM_ADDR_WIDTH : integer := 5; - -- Width of internal storage element - -- 4 for VirtexII SRL16E (legacy, but works also for V5,6,7) - -- 5 for Virtex5,6,7 SRLC32E - -- 6 for Virtex5,6,7 RAM64x1S (stores 6 bits/LUT, most effective) - ELEM_WIDTH : integer := 4; - -- Width of "bank" addres within each storage element. - -- Saves resources, but slows down the search. - -- Search time is 2^SEQUENCED_SEARCH. - -- Write time is 2^(ELEM_WIDTH-SEQUENCED_SEARCH). - -- !!! Only with ELEM_WIDTH = 6 !!! - SEQUENCED_SEARCH : integer := 0; - -- If true, writing a masked bit (mask=0) has two different meanings: - -- If data bit is 0, then it is don't care - -- But if data bit is 1, then it is UNMATCHABLE! - USE_UNMATCHABLE : boolean := false; - -- Forced usage of carry chains in match aggregation - -- NOTE: DO NOT USE! Vivado (2016.3 and older) cannot aggregate carry chains into slices effectively! - USE_CARRY_CHAINS : boolean := false; - -- Enable registers for better timing inside matching logic. - -- Do not use together with carry chains! - MATCH_REG : boolean := false - ); - port ( - -- common interface - CLK : in std_logic; - RESET : in std_logic; - - -- insert interface - ADDR : in std_logic_vector((CAM_ADDR_WIDTH - 1) downto 0); - MASK_IN : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - WRITE_EN : in std_logic; - - -- insert/search interface - DATA_IN : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - - -- search interface - MATCH_EN : in std_logic; - MATCH_RDY : out std_logic; -- Accept new MATCH_EN - -- Const 1 for SEQUENCED_SEARCH = 0 - MATCH_RST : in std_logic; - MATCH_BUS : out std_logic_vector((CAM_ROW_COUNT - 1) downto 0); - MATCH_BUS_VLD : out std_logic - ); -end entity CAM; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture cam_arch of CAM is - - --- ------------------ Signals declaration ------------------------------------- - signal reg_addr : std_logic_vector((CAM_ADDR_WIDTH - 1) downto 0); - signal reg_addr_we : std_logic; - signal reg_data_in : std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - signal reg_data_in_we : std_logic; - signal reg_mask_in : std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - signal reg_mask_in_we : std_logic; - signal reg_match_en : std_logic; - signal reg_match_rst : std_logic; - - signal sig_match_rdy : std_logic; - - attribute keep : string; - attribute keep of reg_data_in_we : signal is "true"; - attribute keep of reg_mask_in_we : signal is "true"; - -begin - - assert (CAM_ROW_WIDTH mod ELEM_WIDTH) = 0 - report "CAM_ROW_WIDTH must be multiple of ELEM_WIDTH!" - severity error; - - assert (ELEM_WIDTH = 6 or SEQUENCED_SEARCH = 0) - report "SEQUENCED_SEARCH can be used only with ELEM_WIDTH=6!" - severity error; - - MATCH_RDY <= sig_match_rdy; - - reg_addr_we <= WRITE_EN; - reg_data_in_we <= WRITE_EN or MATCH_EN; - reg_mask_in_we <= WRITE_EN or MATCH_EN; - --- -------- Generating and maping cam_data_array ------------------------------ - DATA_ARRAY: entity work.cam_data_array - generic map ( - CAM_ROW_WIDTH => CAM_ROW_WIDTH, - CAM_ROW_COUNT => CAM_ROW_COUNT, - CAM_ADDR_WIDTH => CAM_ADDR_WIDTH, - ELEM_WIDTH => ELEM_WIDTH, - SEQUENCED_SEARCH => SEQUENCED_SEARCH, - USE_UNMATCHABLE => USE_UNMATCHABLE, - USE_CARRY_CHAINS => USE_CARRY_CHAINS, - MATCH_REG => MATCH_REG - ) - port map ( - ADDR => reg_addr, - DATA_IN => reg_data_in, - MASK_IN => reg_mask_in, - WRITE_ENABLE => WRITE_EN, - MATCH_ENABLE => reg_match_en, - MATCH_RDY => sig_match_rdy, - MATCH_RST => reg_match_rst, - RESET => RESET, - CLK => CLK, - MATCH_BUS => MATCH_BUS, - MATCH_VLD => MATCH_BUS_VLD - ); - - --- register reg_addr ---------------------------------------------------------- -reg_addrp: process(CLK) -begin - if (CLK'event AND CLK = '1') then - if (reg_addr_we = '1') then - reg_addr <= ADDR; - end if; - end if; -end process; - --- register reg_data_in ------------------------------------------------------- -reg_data_inp: process(CLK) -begin - if (CLK'event AND CLK = '1') then - if (reg_data_in_we = '1') then - reg_data_in <= DATA_IN; - end if; - end if; -end process; - --- register reg_mask_in ------------------------------------------------------- -reg_mask_inp: process(CLK) -begin - if (CLK'event AND CLK = '1') then - if (reg_mask_in_we = '1') then - reg_mask_in <= MASK_IN; - end if; - end if; -end process; - --- register reg_match_enable -------------------------------------------------- -reg_match_enablep: process(CLK) -begin - if (CLK'event AND CLK = '1') then - if (RESET = '1') then - reg_match_en <= '0'; - elsif sig_match_rdy = '1' then - reg_match_en <= MATCH_EN; - end if; - end if; -end process; - -reg_match_resetp: process(CLK) -begin - if (CLK'event AND CLK = '1') then - if sig_match_rdy = '1' then - reg_match_rst <= MATCH_RST; - end if; - end if; -end process; - -end architecture cam_arch; diff --git a/comp/base/mem/cam/cam_data_array.vhd b/comp/base/mem/cam/cam_data_array.vhd deleted file mode 100644 index f1aef029e..000000000 --- a/comp/base/mem/cam/cam_data_array.vhd +++ /dev/null @@ -1,323 +0,0 @@ --- --- cam_data_array.vhd: Array of memory elements + filling part --- Copyright (C) 2005 CESNET --- Author(s): Martin kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- ---$Id$ --- --- TODO: --- --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity cam_data_array is - generic ( - -- Data row width (bits, should be a multiple of ELEM_WIDTH) - CAM_ROW_WIDTH : integer; - -- Number of data rows (depth of the CAM) - CAM_ROW_COUNT : integer; - -- Width of address bus - -- should be greater or equal to log2(CAM_ROW_COUNT) - CAM_ADDR_WIDTH : integer; - -- Width of internal element - -- 4 for VirtexII SRL16E (legacy, but works also for V5,6,7) - -- 5 for Virtex5,6,7 SRLC32E - -- 6 for Virtex5,6,7 RAM64x1S (stores 6 bits/LUT, most effective) - ELEM_WIDTH : integer := 4; - -- Width of "bank" addres within each storage element. - -- Saves resources, but slows down the search. - -- Search time is 2^SEQUENCED_SEARCH. - -- Write time is 2^(ELEM_WIDTH-SEQUENCED_SEARCH). - SEQUENCED_SEARCH : integer := 0; - -- If true, writing a masked bit (mask=0) has two different meanings: - -- If the bit is 0, then it is don't care - -- But if the bit is 1, then it is UNMATCHABLE! - USE_UNMATCHABLE : boolean := false; - -- Forced usage of carry chains in match aggregation - USE_CARRY_CHAINS : boolean := false; - -- Enable registers for better timing inside matching logic. - -- Do not use together with carry chains! - MATCH_REG : boolean := false - ); - port ( - ADDR : in std_logic_vector((CAM_ADDR_WIDTH - 1) downto 0); - DATA_IN : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - MASK_IN : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - WRITE_ENABLE : in std_logic; - - MATCH_ENABLE : in std_logic; - MATCH_RDY : out std_logic; - MATCH_RST : in std_logic; - RESET : in std_logic; - CLK : in std_logic; - MATCH_BUS : out std_logic_vector((CAM_ROW_COUNT - 1) downto 0); - MATCH_VLD : out std_logic - ); -end entity cam_data_array; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture cam_data_array_arch of cam_data_array is - - -- SEQUENCED_SEARCH needs less rows - constant CAM_ROW_COUNT_SEQ : integer := CAM_ROW_COUNT/(2**SEQUENCED_SEARCH); - - -- Number of bits matched in one element - constant MATCH_PER_ELEM : integer := ELEM_WIDTH - SEQUENCED_SEARCH; - - -- Number of elements to match the whole word - constant ELEM_COUNT : integer := div_roundup(CAM_ROW_WIDTH, MATCH_PER_ELEM); - - -- SEQUENCED_SEARCH needs wider words - constant CAM_ROW_WIDTH_SEQ : integer := ELEM_COUNT * ELEM_WIDTH; - - --- ------------------ Signals declaration ------------------------------------- - signal write_enable_bus : std_logic_vector((CAM_ROW_COUNT_SEQ - 1) downto 0); - signal data_fill_bus : std_logic_vector(ELEM_COUNT - 1 downto 0); - signal match_out : std_logic_vector((CAM_ROW_COUNT_SEQ - 1) downto 0); - - signal write_addr : std_logic_vector(ELEM_WIDTH-1 downto 0); - signal write_addr_mult : std_logic_vector(CAM_ROW_WIDTH_SEQ-1 downto 0); - signal write_enable_out : std_logic; - signal data_in_mx : std_logic_vector(CAM_ROW_WIDTH_SEQ-1 downto 0); - - signal data_in_seq : std_logic_vector(CAM_ROW_WIDTH_SEQ-1 downto 0); - signal cnt_search : std_logic_vector(max(1,SEQUENCED_SEARCH)-1 downto 0); - signal cnt_search_dly : std_logic_vector(max(1,SEQUENCED_SEARCH)-1 downto 0); - signal cnt_search_dly2 : std_logic_vector(max(1,SEQUENCED_SEARCH)-1 downto 0); - signal max_search : std_logic_vector(max(1,SEQUENCED_SEARCH)-1 downto 0); - signal min_search : std_logic_vector(max(1,SEQUENCED_SEARCH)-1 downto 0); - signal sig_match_rdy : std_logic; - - -- Store all but the last bank - -- Signal width is for the whole result for easier indexing - signal reg_match_out : std_logic_vector(CAM_ROW_COUNT-1 downto 0); - - signal sig_match_out : std_logic_vector(CAM_ROW_COUNT - 1 downto 0); - signal reg_match_vld : std_logic; - signal reg_match_enable : std_logic; - signal rows_match_enable: std_logic; - - -- Extend DATA_IN signal to the required width - signal data_in_ext - : std_logic_vector(ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto 0); -begin - --- -------- Generating and maping cam_filling_part ---------------------------- - FILLING_PART: entity work.cam_filling_part - generic map ( - CAM_ROW_WIDTH => CAM_ROW_WIDTH, - CAM_ROW_COUNT => CAM_ROW_COUNT, - CAM_ADDR_WIDTH => CAM_ADDR_WIDTH, - ELEM_WIDTH => ELEM_WIDTH, - SEQUENCED_SEARCH => SEQUENCED_SEARCH, - ELEM_COUNT => ELEM_COUNT, - USE_UNMATCHABLE => USE_UNMATCHABLE - ) - port map ( - ADDR => ADDR, - DATA_IN => DATA_IN, - MASK_IN => MASK_IN, - WRITE_ENABLE => WRITE_ENABLE, - RESET => RESET, - CLK => CLK, - ADDR_OUT => write_addr, - WRITE_ENABLE_OUT => write_enable_out, - WRITE_ENABLE_BUS => write_enable_bus, - DATA_FILL_BUS => data_fill_bus - ); - - -- Write address is the same for all elems - multiply_addr_out : for i in 0 to ELEM_COUNT - 1 generate - write_addr_mult((i+1)*ELEM_WIDTH-1 downto i*ELEM_WIDTH) <= write_addr; - end generate; - - -- When using RAM64x1S, address must be sent with each write - use_mux : if ELEM_WIDTH = 6 generate - data_in_mx_p : process(data_in_seq, write_addr_mult, write_enable_out) - begin - if write_enable_out = '0' then - data_in_mx <= data_in_seq; - else - data_in_mx <= write_addr_mult; - end if; - end process; - end generate; - - -- When using SRL16E or SRL32E, addressing is automatic by shifting - dont_use_mux : if ELEM_WIDTH /= 6 generate - data_in_mx <= data_in_seq; - end generate; - --- -------- Generating and maping cam_rows ------------------------------------ - ROW_GEN: for i in 0 to (CAM_ROW_COUNT_SEQ - 1) generate - -- generate all memory rows - ROW_INST: entity work.cam_row - generic map ( - CAM_ROW_WIDTH => CAM_ROW_WIDTH_SEQ, - ELEM_WIDTH => ELEM_WIDTH, - USE_CARRY_CHAINS => USE_CARRY_CHAINS, - MATCH_REG => MATCH_REG - ) - port map ( - DATA_FILL => data_fill_bus, - DATA_IN => data_in_mx, - WRITE_ENABLE => write_enable_bus(i), - MATCH_ENABLE => rows_match_enable, - CLK => CLK, - MATCH => match_out(i) - ); - end generate; - - match_reg_gen : if MATCH_REG generate - signal reg2 : std_logic; - begin - reg_match_p : process(CLK) - begin - if CLK'event and CLK = '1' then - if RESET = '1' then - reg2 <= '0'; - reg_match_enable <= '0'; - else - reg2 <= MATCH_ENABLE; - reg_match_enable <= reg2; - end if; - cnt_search_dly <= cnt_search; - cnt_search_dly2 <= cnt_search_dly; - end if; - end process; - end generate; - match_noreg_gen : if not MATCH_REG generate - cnt_search_dly <= cnt_search; - reg_match_p : process(CLK) - begin - if CLK'event and CLK = '1' then - if RESET = '1' then - reg_match_enable <= '0'; - else - reg_match_enable <= MATCH_ENABLE; - end if; - cnt_search_dly2 <= cnt_search_dly; - end if; - end process; - end generate; - - no_extend_gen : if ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH) = CAM_ROW_WIDTH - generate - data_in_ext <= DATA_IN; - end generate; - - -- Need to deal with unused bits of the last element - extend_gen : if ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH) /= CAM_ROW_WIDTH - generate - data_in_ext(CAM_ROW_WIDTH-1 downto 0) <= DATA_IN; - data_in_ext(ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto CAM_ROW_WIDTH) - <= (others => '0'); -- Store zeros in unused bits (masked anyway) - end generate; - - -- Code for sequenced version - gen_sequenced : if SEQUENCED_SEARCH > 0 generate - - --* Counter for searching in multiple banks - cnt_search_p : process(CLK) - begin - if CLK'event and CLK = '1' then - if RESET = '1' then - cnt_search <= (others => '0'); - else - if MATCH_ENABLE = '1' or cnt_search /= min_search then - cnt_search <= cnt_search + 1; - end if; - end if; - end if; - end process; - - max_search <= (others => '1'); - min_search <= (others => '0'); - - -- Not ready when currently matching in non-last bank. - sig_match_rdy <= '0' when MATCH_ENABLE = '1' and - cnt_search /= max_search - else '1'; - - -- Match bus also contains bank addressing - split_data_in : for i in 0 to ELEM_COUNT - 1 generate - data_in_seq((i+1)*ELEM_WIDTH-1 downto i*ELEM_WIDTH) <= - cnt_search & - data_in_ext((i+1)*MATCH_PER_ELEM-1 downto i*MATCH_PER_ELEM); - end generate; - - -- Store outputs from all but the last bank - -- (The last bank is also stored, but not used, actually) - reg_match_gen : for i in 0 to CAM_ROW_COUNT_SEQ-1 generate - reg_match_gen2: for j in 0 to 2**SEQUENCED_SEARCH-1 generate - reg_match_out_p : process(CLK) - begin - if CLK'event and CLK = '1' then - if j = conv_integer(cnt_search_dly2) then - reg_match_out((i*(2**SEQUENCED_SEARCH)) + j) <= - match_out(i); - end if; - end if; - end process; - end generate; - end generate; - - -- Map registered and direct outputs to one vector - mach_out_gen : for i in 0 to (CAM_ROW_COUNT/(2**SEQUENCED_SEARCH)) - 1 - generate - sig_match_out(((2**SEQUENCED_SEARCH)*(i+1))-1 downto - (2**SEQUENCED_SEARCH)*i) <= - match_out(i) & - reg_match_out(((2**SEQUENCED_SEARCH)*(i+1))-2 downto - (2**SEQUENCED_SEARCH)*i); - end generate; - - MATCH_BUS <= sig_match_out; - - -- Match will be ready one cycle after last search - reg_match_vld_p : process(CLK) - begin - if CLK'event and CLK = '1' then - if RESET = '1' then - reg_match_vld <= '0'; - else - if cnt_search_dly = max_search then - reg_match_vld <= '1'; - else - reg_match_vld <= '0'; - end if; - end if; - end if; - end process; - - MATCH_VLD <= reg_match_vld; - - rows_match_enable <= '1' when (MATCH_ENABLE = '1' or cnt_search /= min_search) and MATCH_RST='0' else '0'; - - end generate; - - -- Code for classical (non-sequenced) version - gen_not_sequenced : if SEQUENCED_SEARCH = 0 generate - sig_match_rdy <= '1'; - data_in_seq <= DATA_IN; - MATCH_BUS <= match_out; - MATCH_VLD <= reg_match_enable; - rows_match_enable <= MATCH_ENABLE and not MATCH_RST; - end generate; - - MATCH_RDY <= sig_match_rdy; - -end architecture cam_data_array_arch; diff --git a/comp/base/mem/cam/cam_fill_element.vhd b/comp/base/mem/cam/cam_fill_element.vhd deleted file mode 100644 index 53b21e0af..000000000 --- a/comp/base/mem/cam/cam_fill_element.vhd +++ /dev/null @@ -1,64 +0,0 @@ --- cam_fill_element.vhd: Basic filling element of CAM. --- Copyright (C) 2005 CESNET --- Author(s): Martin kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity cam_fill_element is - generic( - -- Width of internal storage element - -- 4 for VirtexII SRL16E (legacy, but works also for V5,6,7) - -- 5 for Virtex5,6,7 SRLC32E - -- 6 for Virtex5,6,7 RAM64x1S (stores 6 bits/LUT, most effective) - ELEM_WIDTH : integer := 4; - -- If true, writing a masked bit (mask=0) has two different meanings: - -- If the bit is 0, then it is don't care - -- But if the bit is 1, then it is UNMATCHABLE! - USE_UNMATCHABLE : boolean := false - ); - port( - CNT_IN : in std_logic_vector(ELEM_WIDTH-1 downto 0); - MASK_IN : in std_logic_vector(ELEM_WIDTH-1 downto 0); - DATA_IN : in std_logic_vector(ELEM_WIDTH-1 downto 0); - DATA_FILL : out std_logic - ); -end entity cam_fill_element; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture cam_fill_element_arch of cam_fill_element is - --- ------------------ Signals declaration ------------------------------------- - signal and1_out : std_logic_vector(ELEM_WIDTH-1 downto 0); - signal and2_out : std_logic_vector(ELEM_WIDTH-1 downto 0); - -begin - -NO_UNM_GEN : if USE_UNMATCHABLE = false generate - and1_out <= CNT_IN and MASK_IN; - and2_out <= DATA_IN and MASK_IN; -end generate; - -UNM_GEN : if USE_UNMATCHABLE = true generate - and1_out <= CNT_IN and MASK_IN; - and2_out <= DATA_IN; -end generate; - -DATA_FILL <= '1' when (and1_out = and2_out) else '0'; - -end architecture cam_fill_element_arch; diff --git a/comp/base/mem/cam/cam_filling_part.vhd b/comp/base/mem/cam/cam_filling_part.vhd deleted file mode 100644 index 51e713202..000000000 --- a/comp/base/mem/cam/cam_filling_part.vhd +++ /dev/null @@ -1,177 +0,0 @@ --- --- cam_filling_part.vhd: An important part of CAM responsible for filling --- memory rows --- Copyright (C) 2005 CESNET --- Author(s): Martin kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity cam_filling_part is - generic( - -- Data row width (bits, should be a multiple of ELEM_WIDTH) - CAM_ROW_WIDTH : integer; - -- Number of data rows (depth of the CAM) - CAM_ROW_COUNT : integer; - -- Width of address bus - -- should be greater or equal to log2(CAM_ROW_COUNT) - CAM_ADDR_WIDTH : integer; - -- Width of internal storage element - -- 4 for VirtexII SRL16E (legacy, but works also for V5,6,7) - -- 5 for Virtex5,6,7 SRLC32E - -- 6 for Virtex5,6,7 RAM64x1S (stores 6 bits/LUT, most effective) - ELEM_WIDTH : integer := 4; - -- Width of "bank" addres within each storage element. - -- Saves resources, but slows down the search. - -- Search time is 2^SEQUENCED_SEARCH. - -- Write time is 2^(ELEM_WIDTH-SEQUENCED_SEARCH). - SEQUENCED_SEARCH : integer := 0; - -- Helper value - ELEM_COUNT : integer; - -- If true, writing a masked bit (mask=0) has two different meanings: - -- If the bit is 0, then it is don't care - -- But if the bit is 1, then it is UNMATCHABLE! - USE_UNMATCHABLE : boolean := false - ); - port( - ADDR : in std_logic_vector((CAM_ADDR_WIDTH - 1) downto 0); - DATA_IN : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - MASK_IN : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - WRITE_ENABLE : in std_logic; - RESET : in std_logic; - CLK : in std_logic; - -- Write address (needed only for RAM64x1S) - ADDR_OUT : out std_logic_vector(ELEM_WIDTH-1 downto 0); - WRITE_ENABLE_OUT : out std_logic; - -- Write enable for each row - WRITE_ENABLE_BUS : out std_logic_vector - ((CAM_ROW_COUNT/(2**SEQUENCED_SEARCH) - 1) downto 0); - -- Write data for each element - DATA_FILL_BUS : out std_logic_vector(ELEM_COUNT - 1 downto 0) - ); -end entity cam_filling_part; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture cam_filling_part_arch of cam_filling_part is - --- ------------------ Signals declaration ------------------------------------- - signal fill_result : std_logic_vector((ELEM_COUNT - 1) downto 0); - signal dec1fn_we : std_logic; - signal counter - : std_logic_vector((ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto 0); - signal counter_ce : std_logic; - signal cnt_busy : std_logic; - signal dec1fn_out - : std_logic_vector((CAM_ROW_COUNT/(2**SEQUENCED_SEARCH)) - 1 downto 0); - signal dec1fn_reduced - : std_logic_vector((log2(CAM_ROW_COUNT)-SEQUENCED_SEARCH) - 1 downto 0); - - -- Extend MASK_IN signal to the required width - signal mask_in_ext - : std_logic_vector(ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto 0); - -- Extend DATA_IN signal to the required width - signal data_in_ext - : std_logic_vector(ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto 0); - -begin - DATA_FILL_BUS <= fill_result; - counter_ce <= WRITE_ENABLE; - WRITE_ENABLE_OUT <= dec1fn_we; - WRITE_ENABLE_BUS <= dec1fn_out; - ADDR_OUT(counter'length-1 downto 0) <= counter; - seq_addr_gen : if(SEQUENCED_SEARCH>0) generate - ADDR_OUT(ADDR_OUT'length-1 downto ADDR_OUT'length-SEQUENCED_SEARCH) <= ADDR(SEQUENCED_SEARCH-1 downto 0); - end generate; - - no_extend_gen : if ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH) = CAM_ROW_WIDTH - generate - mask_in_ext <= MASK_IN; - data_in_ext <= DATA_IN; - end generate; - - -- Need to deal with unused bits of the last element - extend_gen : if ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH) /= CAM_ROW_WIDTH - generate - mask_in_ext(CAM_ROW_WIDTH-1 downto 0) <= MASK_IN; - data_in_ext(CAM_ROW_WIDTH-1 downto 0) <= DATA_IN; - - mask_in_ext(ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto CAM_ROW_WIDTH) - <= (others => '0'); -- Store zeros in unused bits mask->always matched - data_in_ext(ELEM_COUNT*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto CAM_ROW_WIDTH) - <= (others => '0'); -- Store zeros in unused bits (masked anyway) - end generate; - --- --------- Generating and maping cam_elements ------------------------------- - FILL_ROW: for i in 0 to (ELEM_COUNT - 1) generate - -- generate all filling elements - ELEMENT_INST: entity work.cam_fill_element - generic map( - ELEM_WIDTH => ELEM_WIDTH-SEQUENCED_SEARCH, - USE_UNMATCHABLE=> USE_UNMATCHABLE - ) - port map ( - CNT_IN => counter, - MASK_IN => mask_in_ext((i+1)*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto i*(ELEM_WIDTH-SEQUENCED_SEARCH)), - DATA_IN => data_in_ext((i+1)*(ELEM_WIDTH-SEQUENCED_SEARCH)-1 downto i*(ELEM_WIDTH-SEQUENCED_SEARCH)), - DATA_FILL => fill_result(i) - ); - end generate; - - --- counter --------------------------------------------------------- - counterp: process(CLK) - begin - if (CLK'event AND CLK = '1') then - if (RESET = '1') then - counter <= (others => '1'); - dec1fn_we <= '0'; - cnt_busy <= '0'; - elsif (counter_ce = '1' AND cnt_busy /= '1') then - counter <= (others => '1'); - cnt_busy <= '1'; - dec1fn_we <= '1'; - elsif (cnt_busy = '1') then - if (counter = 0) then - cnt_busy <= '0'; - dec1fn_we <= '0'; - else - counter <= counter - 1; - end if; - end if; - end if; - end process; - --- --------- Generating and maping generic decoder ---------------------------- - DEC1FN : entity work.dec1fn_enable - generic map ( - ITEMS => CAM_ROW_COUNT / (2**SEQUENCED_SEARCH) - ) - port map ( - ADDR => dec1fn_reduced, - ENABLE => dec1fn_we, - DO => dec1fn_out - ); - --- -------- Maping decoder input (have to adjust ADDR) ------------------------ - MAP_DEC1FN_OUT: for i in 0 to (log2(CAM_ROW_COUNT)-SEQUENCED_SEARCH) - 1 - generate - dec1fn_reduced(i) <= ADDR(i+SEQUENCED_SEARCH); - end generate; - -end architecture cam_filling_part_arch; diff --git a/comp/base/mem/cam/cam_light.vhd b/comp/base/mem/cam/cam_light.vhd deleted file mode 100644 index 9cffb6416..000000000 --- a/comp/base/mem/cam/cam_light.vhd +++ /dev/null @@ -1,78 +0,0 @@ --- cam_light.vhd: Lightweight CAM --- Copyright (C) 2009 CESNET --- Author(s): Martin kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity CAM is - generic ( - -- Data row width (bits, should be a multiple of 4) - CAM_ROW_WIDTH : integer; - -- Number of data rows (depth of the CAM) - CAM_ROW_COUNT : integer - ); - port ( - -- common interface - CLK : in std_logic; - RESET : in std_logic; - - -- insert interface - ADDR : in std_logic_vector(log2(CAM_ROW_COUNT)-1 downto 0); - DATA_IN : in std_logic_vector(CAM_ROW_WIDTH-1 downto 0); - WRITE_EN : in std_logic; - CLEAR : in std_logic; - - -- search interface - MATCH_EN : in std_logic; - MATCH_BUS : out std_logic_vector(CAM_ROW_COUNT-1 downto 0); - MATCH_BUS_VLD : out std_logic; - MATCHED : out std_logic - ); -end entity CAM; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture light of CAM is -begin - CAM_I : entity work.CAM_2PORT - generic map ( - CAM_ROW_WIDTH => CAM_ROW_WIDTH, - CAM_ROW_COUNT => CAM_ROW_COUNT - ) - port map ( - -- common interface - CLK => CLK, - RESET => RESET, - -- insert interface - ADDR => ADDR, - DATA_IN => DATA_IN, - WRITE_EN => WRITE_EN, - CLEAR => CLEAR, - CLEAR_ADDR => ADDR, - - -- search interface - MATCH_DATA => DATA_IN, - MATCH_EN => MATCH_EN, - MATCH_BUS => MATCH_BUS, - MATCH_BUS_VLD => MATCH_BUS_VLD, - MATCHED => MATCHED - ); - -end architecture light; diff --git a/comp/base/mem/cam/cam_light_2port.vhd b/comp/base/mem/cam/cam_light_2port.vhd deleted file mode 100644 index efdcf97c5..000000000 --- a/comp/base/mem/cam/cam_light_2port.vhd +++ /dev/null @@ -1,181 +0,0 @@ --- cam_light_2port.vhd: 2 port (Match, Write) Lightweight CAM --- Copyright (C) 2009 CESNET --- Author(s): Martin kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- NOTICE: when clearing and writing to the same address, WRITE has higher priority --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity CAM_2PORT is - generic ( - -- Data row width (bits, should be a multiple of 4) - CAM_ROW_WIDTH : integer; - -- Number of data rows (depth of the CAM) - CAM_ROW_COUNT : integer - ); - port ( - -- common interface - CLK : in std_logic; - RESET : in std_logic; - - -- insert interface - ADDR : in std_logic_vector(log2(CAM_ROW_COUNT)-1 downto 0); - DATA_IN : in std_logic_vector(CAM_ROW_WIDTH-1 downto 0); - WRITE_EN : in std_logic; - CLEAR : in std_logic; - CLEAR_ADDR : in std_logic_vector(log2(CAM_ROW_COUNT)-1 downto 0); - - -- search interface - MATCH_DATA : in std_logic_vector(CAM_ROW_WIDTH-1 downto 0); - MATCH_EN : in std_logic; - MATCH_BUS : out std_logic_vector(CAM_ROW_COUNT-1 downto 0); - MATCH_BUS_VLD : out std_logic; - MATCHED : out std_logic - ); -end entity CAM_2PORT; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture light of CAM_2PORT is - signal reg_data : std_logic_vector(CAM_ROW_COUNT*CAM_ROW_WIDTH-1 - downto 0); - signal reg_data_we : std_logic_vector(CAM_ROW_COUNT-1 downto 0); - signal reg_valid : std_logic_vector(CAM_ROW_COUNT-1 downto 0); - signal reg_valid_s : std_logic_vector(CAM_ROW_COUNT-1 downto 0); - signal reg_valid_c : std_logic_vector(CAM_ROW_COUNT-1 downto 0); - - signal reg_match_bus : std_logic_vector(CAM_ROW_COUNT-1 downto 0); - signal reg_matched : std_logic; - signal reg_match_vld : std_logic; - signal cmp_matched : std_logic_vector(CAM_ROW_COUNT-1 downto 0); - signal sig_matched : std_logic; - -begin - reg_valid_s <= reg_data_we; - - -- mapping output ports - MATCH_BUS <= reg_match_bus; - MATCH_BUS_VLD <= reg_match_vld; - MATCHED <= reg_matched; - - -- decode address - DEC1FN_WRITE : entity work.dec1fn_enable - generic map ( - ITEMS => CAM_ROW_COUNT - ) - port map ( - ADDR => ADDR, - ENABLE => WRITE_EN, - DO => reg_data_we - ); - - -- decode address - DEC1FN_CLEAR : entity work.dec1fn_enable - generic map ( - ITEMS => CAM_ROW_COUNT - ) - port map ( - ADDR => CLEAR_ADDR, - ENABLE => CLEAR, - DO => reg_valid_c - ); - - GEN_REGS : for i in 0 to CAM_ROW_COUNT-1 generate - -- register reg_data - reg_datap: process(CLK) - begin - if (CLK'event AND CLK = '1') then - if (reg_data_we(i) = '1') then - reg_data((i+1)*CAM_ROW_WIDTH-1 downto i*CAM_ROW_WIDTH) <= DATA_IN; - end if; - end if; - end process; - end generate; - - GEN_REG_DV : for i in 0 to CAM_ROW_COUNT-1 generate - -- register reg_valid - reg_validp: process(CLK) - begin - if (CLK'event AND CLK = '1') then - if (reg_valid_s(i) = '1') then - reg_valid(i) <= '1'; - elsif (reg_valid_c(i) = '1') then - reg_valid(i) <= '0'; - end if; - end if; - end process; - end generate; - - GEN_CMPS : for i in 0 to CAM_ROW_COUNT-1 generate - cmp_matched(i) <= '1' when - ((reg_data((i+1)*CAM_ROW_WIDTH-1 downto i*CAM_ROW_WIDTH) - = MATCH_DATA) and (reg_valid(i) = '1')) - else '0'; - end generate; - - -- register reg_match_bus - reg_match_busp: process(CLK) - begin - if (CLK'event AND CLK = '1') then - if (RESET = '1') then - reg_match_bus <= (others => '0'); - elsif (MATCH_EN = '1') then - reg_match_bus <= cmp_matched; - end if; - end if; - end process; - - -- register reg_matched - reg_matchedp: process(CLK) - begin - if (CLK'event AND CLK = '1') then - if (RESET = '1') then - reg_matched <= '0'; - elsif (MATCH_EN = '1') then - reg_matched <= sig_matched; - end if; - end if; - end process; - - -- register reg_match_vld - reg_match_vldp: process(CLK) - begin - if (CLK'event AND CLK = '1') then - if (RESET = '1') then - reg_match_vld <= '0'; - else - reg_match_vld <= MATCH_EN; - end if; - end if; - end process; - - -- sig_matched signal made from ORed cmp_matched bus - sig_matchedp : process(cmp_matched) - variable or_int : std_logic; - begin - or_int := '0'; - - for k in 0 to CAM_ROW_COUNT-1 loop - or_int := or_int or cmp_matched(k); - end loop; - - sig_matched <= or_int; - end process; - - -end architecture light; diff --git a/comp/base/mem/cam/cam_row.vhd b/comp/base/mem/cam/cam_row.vhd deleted file mode 100644 index b1f739088..000000000 --- a/comp/base/mem/cam/cam_row.vhd +++ /dev/null @@ -1,166 +0,0 @@ --- --- cam_row.vhd: One memory row of CAM. --- Copyright (C) 2005 CESNET --- Author(s): Martin kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_misc.all; - -library unisim; -use unisim.vcomponents.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity cam_row is - generic( - -- Data row width (bits, should be a multiple of ELEM_WIDTH) - CAM_ROW_WIDTH : integer; - -- Width of internal storage element - -- 4 for VirtexII SRL16E (legacy, but works also for V5,6,7) - -- 5 for Virtex5,6,7 SRLC32E - -- 6 for Virtex5,6,7 RAM64x1S (stores 6 bits/LUT, most effective) - ELEM_WIDTH : integer := 4; - -- Forced usage of carry chains in match aggregation - USE_CARRY_CHAINS : boolean := false; - -- Enable registers for better timing inside matching logic. - -- Do not use together with carry chains! - MATCH_REG : boolean := false - ); - port( - DATA_FILL : in std_logic_vector(((CAM_ROW_WIDTH / ELEM_WIDTH)-1) downto 0); - DATA_IN : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - WRITE_ENABLE : in std_logic; - MATCH_ENABLE : in std_logic; - CLK : in std_logic; - MATCH : out std_logic - ); -end entity cam_row; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture cam_row_arch of cam_row is - --- ----------------- Constants declaration ------------------------------------ - -- Number of elements (cam_element) - constant ELEM_COUNT : integer := (CAM_ROW_WIDTH / ELEM_WIDTH); - - --- ------------------ Signals declaration ------------------------------------- - signal muxcy_sel, muxcy_sel_reg : std_logic_vector(ELEM_COUNT-1 downto 0); - signal reg_result : std_logic := '0'; - signal match_result : std_logic; - signal match_enable_reg : std_logic; - -begin - --- --------- Generating and maping cam_elements ------------------------------- - DATA_ROW: for i in 0 to (ELEM_COUNT - 1) generate - signal local_data_in : std_logic_vector(ELEM_WIDTH-1 downto 0); - begin - local_data_in <= DATA_IN((((i+1)*ELEM_WIDTH)-1) downto (i*ELEM_WIDTH)); - srl16e_gen : if ELEM_WIDTH = 4 generate - shift_register : SRL16E - generic map ( - INIT => X"0000" - ) port map ( - d => DATA_FILL(i), - ce => WRITE_ENABLE, - clk => CLK, - a0 => local_data_in(0), - a1 => local_data_in(1), - a2 => local_data_in(2), - a3 => local_data_in(3), - q => muxcy_sel(i) - ); - end generate; - srlc32e_gen : if ELEM_WIDTH = 5 generate - shift_register : SRLC32E - generic map ( - INIT => X"00000000" - ) port map ( - d => DATA_FILL(i), - ce => WRITE_ENABLE, - clk=> CLK, - a => local_data_in, - q => muxcy_sel(i), - q31=> open -- Cascading not used - ); - end generate; - ram64x1s_gen : if ELEM_WIDTH = 6 generate - RAM64X1S_inst : RAM64X1S - generic map ( - INIT => X"0000000000000000") - port map ( - O => muxcy_sel(i), -- 1-bit data output - A0 => local_data_in(0), -- Address[0] input bit - A1 => local_data_in(1), -- Address[1] input bit - A2 => local_data_in(2), -- Address[2] input bit - A3 => local_data_in(3), -- Address[3] input bit - A4 => local_data_in(4), -- Address[4] input bit - A5 => local_data_in(5), -- Address[5] input bit - D => DATA_FILL(i), -- 1-bit data input - WCLK => CLK, -- Write clock input - WE => WRITE_ENABLE -- Write enable input - ); - end generate; - end generate; - --- match result aggregation --------------------------------------------------- - carry_gen : if USE_CARRY_CHAINS generate - signal reg_match_bus : std_logic_vector(ELEM_COUNT-1 downto 0); - begin - match_aggregate : entity work.CARRY_CHAIN - generic map( - -- DEVICE => DEVICE, - CARRY_WIDTH => ELEM_COUNT - ) port map ( - CI => match_enable_reg, - DI => (others => '0'), - S => muxcy_sel_reg, - CO => reg_match_bus, - DO => open - ); - match_result <= reg_match_bus(ELEM_COUNT-1); - end generate; - - logic_gen : if not USE_CARRY_CHAINS generate - match_result <= match_enable_reg and and_reduce(muxcy_sel_reg); - end generate; - --- register reg_result -------------------------------------------------------- - reg_resultp: process(CLK) - begin - if (CLK'event AND CLK = '1') then - reg_result <= match_result; - end if; - end process; - MATCH <= reg_result; - - match_reg_gen : if MATCH_REG generate - reg : process(CLK) - begin - if (CLK'event AND CLK = '1') then - muxcy_sel_reg <= muxcy_sel; - match_enable_reg <= MATCH_ENABLE; - end if; - end process; - end generate; - match_noreg_gen : if not MATCH_REG generate - muxcy_sel_reg <= muxcy_sel; - match_enable_reg <= MATCH_ENABLE; - end generate; - -end architecture cam_row_arch; diff --git a/comp/base/mem/cam/sim/cam.fdo b/comp/base/mem/cam/sim/cam.fdo deleted file mode 100644 index d20ebd7e4..000000000 --- a/comp/base/mem/cam/sim/cam.fdo +++ /dev/null @@ -1,22 +0,0 @@ -# cam.fdo: CAM behavioral simulation FDO script -# Copyright (C) 2006 CESNET -# Author: Martin Kosek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -set FIRMWARE_BASE "../../../../.." -set COMP_BASE "$FIRMWARE_BASE/comp" -set CAM_BASE "$OFM_PATH/comp/base/mem/cam" - -set SIG_FILE "$CAM_BASE/sim/cam_sig.fdo" -set TB_FILE "$CAM_BASE/sim/cam_tb.vhd" - -set COMPONENTS [list \ - [ list "CAM" $CAM_BASE "CAM"] \ - ] - -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -nb_sim_run 12us diff --git a/comp/base/mem/cam/sim/cam_sig.fdo b/comp/base/mem/cam/sim/cam_sig.fdo deleted file mode 100644 index 0c1228641..000000000 --- a/comp/base/mem/cam/sim/cam_sig.fdo +++ /dev/null @@ -1,17 +0,0 @@ -# cam_sig.fdo : Include file with signals for CAM -# Copyright (C) 2006 CESNET -# Author: Martin Kosek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths -set CAM_PATH "/testbench/uut" - -source "signals.fdo" - -blk_CAM -blk_CAM_INT - diff --git a/comp/base/mem/cam/sim/cam_tb.vhd b/comp/base/mem/cam/sim/cam_tb.vhd deleted file mode 100644 index 0e10fd354..000000000 --- a/comp/base/mem/cam/sim/cam_tb.vhd +++ /dev/null @@ -1,222 +0,0 @@ --- cam_tb.vhd: Testbench for CAM --- Copyright (C) 2005 CESNET --- Author(s): Martin Kosek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity testbench is -end testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture cam_tb of testbench is - - constant CAM_ROW_WIDTH : integer := 18; - constant CAM_ROW_COUNT : integer := 16; - constant CAM_ADDR_WIDTH : integer := 8; - constant CAM_ELEM_WIDTH : integer := 6; - constant SEQUENCED_SEARCH: integer := 3; - constant USE_UNMATCHABLE : boolean := true; - - constant clk_period : time := 10 ns; - constant WAIT_BETWEEN_SEARCH:integer:= 0; - --- ------------------ Signals declaration ------------------------------------- - signal ADDR : std_logic_vector((CAM_ADDR_WIDTH - 1) downto 0); - signal DATA_IN : std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - signal MASK_IN : std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - signal WRITE_ENABLE : std_logic; - signal MATCH_ENABLE : std_logic; - signal MATCH_RDY : std_logic; - signal MATCH_RST : std_logic; - signal RESET : std_logic; - signal CLK : std_logic; - signal MATCH_BUS : std_logic_vector((CAM_ROW_COUNT - 1) downto 0); - signal MATCH_BUS_VLD : std_logic; - -begin - --- ---------- Connecting component to testbench ------------------------------ - UUT : entity work.CAM - generic map ( - CAM_ROW_WIDTH => CAM_ROW_WIDTH, - CAM_ROW_COUNT => CAM_ROW_COUNT, - CAM_ADDR_WIDTH => CAM_ADDR_WIDTH, - ELEM_WIDTH => CAM_ELEM_WIDTH, - SEQUENCED_SEARCH=>SEQUENCED_SEARCH, - USE_UNMATCHABLE=> USE_UNMATCHABLE - ) - port map ( - ADDR => ADDR, - DATA_IN => DATA_IN, - MASK_IN => MASK_IN, - WRITE_EN => WRITE_ENABLE, - MATCH_EN => MATCH_ENABLE, - MATCH_RDY => MATCH_RDY, - MATCH_RST => MATCH_RST, - RESET => RESET, - CLK => CLK, - MATCH_BUS => MATCH_BUS, - MATCH_BUS_VLD => MATCH_BUS_VLD - ); - --- ----------- Generating clock signal ---------------------------------------- - tb_clk_gen: process - begin - CLK <= '1'; - wait for clk_period/2; - CLK <= '0'; - wait for clk_period/2; - end process tb_clk_gen; - --- ----------- Probes --------------------------------------------------------- - probe : process --- ---------------------------------------------------------------- --- Procedures declaration --- ---------------------------------------------------------------- - --- ---------------------------------------------------------------- --- procedure cam_insert_word inserts one word into CAM data array in the row --- selected by address --- --- Parameters: --- p_addr: data row address --- p_data_in: inserted data --- p_mask_in: specify 'care' and 'dont't care' bits --- '1' => I care about that bit --- '0' => I don't care about that bit --- - procedure cam_insert_word( - p_addr : in std_logic_vector((CAM_ADDR_WIDTH - 1) downto 0); - p_data_in : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0); - p_mask_in : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0) - ) is - begin - wait until clk'event and clk='1'; - wait for 1 ns; - WRITE_ENABLE <= '1'; - ADDR <= p_addr; - DATA_IN <= p_data_in; - MASK_IN <= p_mask_in; - wait for clk_period; - WRITE_ENABLE <= '0'; - wait for 64*clk_period; - wait until clk'event and clk='1'; - wait for 1 ns; - end cam_insert_word; - --- ---------------------------------------------------------------- --- procedure cam_search_word searches in CAM for selected data --- --- Parameters: --- p_data_in: data that should be searched in CAM --- - procedure cam_search_word( - p_data_in : in std_logic_vector((CAM_ROW_WIDTH - 1) downto 0) - ) is - begin - wait until clk'event and clk='1'; - wait for 1 ns; - MATCH_ENABLE <= '1'; - DATA_IN <= p_data_in; - wait for clk_period; - MATCH_ENABLE <= '0'; - end cam_search_word; - - begin --- ----------- Activating RESET signal ---------------------------------------- - RESET <= '1'; - wait for 10*clk_period; - wait until CLK'event and CLK='1'; - - RESET <= '0'; - - MATCH_RST <= '0'; - WRITE_ENABLE <= '0'; - MATCH_ENABLE <= '0'; - MASK_IN <= "000000000000000000"; - ADDR <= "00000000"; - DATA_IN <= "000000000000000000"; - - wait for clk_period; - wait until CLK'event and CLK='1'; - wait for 1 ns; - --- ----------- Fill memory elements ------------------------------------------- - --- Try simple inserting (without using MASK) - cam_insert_word("00000000","000000000000000000","111111111111111111"); - cam_insert_word("00000001","000000000011111111","111111111111111111"); - cam_insert_word("00000010","000000000011110000","111111111111111111"); - cam_insert_word("00000011","000000000000001111","111111111111111111"); - cam_insert_word("00000100","000000000010101010","111111111111111111"); - cam_insert_word("00000101","000000000001010101","111111111111111111"); - cam_insert_word("00000110","000000000011001100","111111111111111111"); - cam_insert_word("00000111","000000000000110011","111111111111111111"); - cam_insert_word("00001000","000000000011000011","111111111111111111"); - cam_insert_word("00001001","000000000000111100","111111111111111111"); - cam_insert_word("00001010","000000000001000010","111111111111111111"); - cam_insert_word("00001011","000000000001100110","111111111111111111"); - --- Try advanced inserting (specifying MASK) - cam_insert_word("00001100","000000000010101010","111111111110101010"); - -- 1d1d1d1d - cam_insert_word("00001101","000000000011110000","111111111111110000"); - -- 1111dddd - cam_insert_word("00001110","000000000000001111","111111111100001111"); - -- dddd1111 - cam_insert_word("00001111","000000000000000001","111111111100000000"); - -- dddddddu (LSB is unmatchable, because data=1 and mask=0) - --- ----------- Try memory elements -------------------------------------------- - wait for 5*clk_period; - wait until clk'event and clk='1'; - wait for 1 ns; - - cam_search_word("000000000000000000"); - wait until MATCH_BUS_VLD = '1'; - wait for 0.5*clk_period; -- this wait is here only for testing purposes (so that - -- assertion will work) - assert (MATCH_BUS="0000000000000001") - report "Search #1 FAILED!!!" severity error; - - wait for WAIT_BETWEEN_SEARCH*clk_period; - cam_search_word("000000000011111111"); - wait until MATCH_BUS_VLD = '1'; - wait for 0.5*clk_period; - assert (MATCH_BUS="0111000000000010") - report "Search #2 FAILED!!!" severity error; - - wait for WAIT_BETWEEN_SEARCH*clk_period; - cam_search_word("000000000010101010"); - wait until MATCH_BUS_VLD = '1'; - wait for 0.5*clk_period; - assert (MATCH_BUS="0001000000010000") - report "Search #3 FAILED!!!" severity error; - - wait for WAIT_BETWEEN_SEARCH*clk_period; - cam_search_word("000000000001010101"); - wait until MATCH_BUS_VLD = '1'; - wait for 0.5*clk_period; - assert (MATCH_BUS="0000000000100000") - report "Search #4 FAILED!!!" severity error; - - wait; - end process probe; - -end cam_tb; diff --git a/comp/base/mem/cam/sim/signals.fdo b/comp/base/mem/cam/sim/signals.fdo deleted file mode 100644 index 293b3e485..000000000 --- a/comp/base/mem/cam/sim/signals.fdo +++ /dev/null @@ -1,45 +0,0 @@ -# signals.fdo : Include file with signals -# Copyright (C) 2006 CESNET -# Author: Martin Kosek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -proc blk_CAM { } { - global CAM_PATH - - add wave -divider "CAM" - add_wave "-label reset -color yellow" $CAM_PATH/reset - add_wave "-label clk -color yellow" $CAM_PATH/clk - add wave -divider "Control signals" - add_wave "-label write_en" $CAM_PATH/write_en - add_wave "-label match_en" $CAM_PATH/match_en - add_wave "-label match_rdy" $CAM_PATH/match_rdy - add_wave "-label match_rst" $CAM_PATH/match_rst - add wave -divider "Input data" - add_wave "-label addr" $CAM_PATH/addr - add_wave "-label data_in" $CAM_PATH/data_in - add_wave "-label mask_in" $CAM_PATH/mask_in - add wave -divider "Output data" - add_wave "-label match_bus" $CAM_PATH/match_bus - add_wave "-label match_bus_vld" $CAM_PATH/match_bus_vld -} - - -proc blk_CAM_INT { } { - global CAM_PATH - - add wave -divider "CAM internals" - add_wave "-label filling_part/addr_out" $CAM_PATH/data_array/filling_part/addr_out - add_wave "-label filling_part/write_enable_out" $CAM_PATH/data_array/filling_part/write_enable_out - add_wave "-label filling_part/write_enable_bus" $CAM_PATH/data_array/filling_part/write_enable_bus - add_wave "-label filling_part/data_fill_bus" $CAM_PATH/data_array/filling_part/data_fill_bus - add_wave "-label data_array/MATCH_ENABLE" $CAM_PATH/data_array/MATCH_ENABLE - add_wave "-label data_array/reg_match_enable" $CAM_PATH/data_array/reg_match_enable - add_wave "-label data_array/data_in_seq" $CAM_PATH/data_array/data_in_seq - add_wave "-label data_array/match_out" $CAM_PATH/data_array/match_out - add_wave "-label data_array/reg_match_out" $CAM_PATH/data_array/reg_match_out - add_wave "-label data_array/cnt_search" $CAM_PATH/data_array/cnt_search - add_wave "-label data_array/cnt_search_dly" $CAM_PATH/data_array/cnt_search_dly -} diff --git a/comp/base/mem/cam/synth/Makefile b/comp/base/mem/cam/synth/Makefile deleted file mode 100644 index f26585612..000000000 --- a/comp/base/mem/cam/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=CAM - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/base/misc/clk_gen/Modules.tcl b/comp/base/misc/clk_gen/Modules.tcl deleted file mode 100644 index 3ca50b5bb..000000000 --- a/comp/base/misc/clk_gen/Modules.tcl +++ /dev/null @@ -1,13 +0,0 @@ -# Modules.tcl: Local include Modules tcl script -# Copyright (C) 2012 CESNET -# Author: Lukas Kekely -# -# SPDX-License-Identifier: BSD-3-Clause - -# Source files for all components -if { $ARCHGRP != "VIRTEX6" } { - set MOD "$MOD $ENTITY_BASE/clk2x.vhd" - set MOD "$MOD $ENTITY_BASE/clk4x.vhd" - set MOD "$MOD $ENTITY_BASE/clk_gen.vhd" - set PACKAGES "$PACKAGES $ENTITY_BASE/clk_gen_pkg.vhd" -} diff --git a/comp/base/misc/clk_gen/clk2x.vhd b/comp/base/misc/clk_gen/clk2x.vhd deleted file mode 100644 index b1b1bf0a2..000000000 --- a/comp/base/misc/clk_gen/clk2x.vhd +++ /dev/null @@ -1,277 +0,0 @@ --- clk2x.vhd : Twice multiply clock generation --- Copyright (C) 2003 CESNET --- Author(s): Jan Korenek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO list : --- --- --- - -library IEEE; -use IEEE.std_logic_1164.all; - --- pragma translate_off -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; --- pragma translate_on - --- ------------------------------------------------------------------------ --- Entity : BUFG_CLK2X_SUBM --- ------------------------------------------------------------------------ - -entity CLK2X_MOD is - port ( - CLK_IN : in std_logic; - RST : in std_logic; - CLK1X : out std_logic; - CLK1X_PH90 : out std_logic; - CLK1X_PH180 : out std_logic; - CLK2X : out std_logic; - CLK2X_PH180 : out std_logic; - CLK2DV : out std_logic; - CLK2DV_PH90 : out std_logic; - CLK4X : out std_logic; - LOCK : out std_logic - ); -end clk2x_mod; - --- ------------------------------------------------------------------------ --- Architecture : BUFG_CLK2X_SUBM_arch --- ------------------------------------------------------------------------ - -architecture behavioral of clk2x_mod is - --- Components Declarations: -component BUFG - port ( - I : in std_logic; - O : out std_logic - ); -end component; - -component DCM - -- pragma translate_off - generic ( - DLL_FREQUENCY_MODE : string := "LOW"; - DUTY_CYCLE_CORRECTION : boolean := TRUE; - STARTUP_WAIT : boolean := FALSE; - CLKDV_DIVIDE : real := 2.0; - CLKFX_MULTIPLY : integer := 4 - ); - -- pragma translate_on - - port ( - CLKIN : in std_logic; - CLKFB : in std_logic; - DSSEN : in std_logic; - PSINCDEC : in std_logic; - PSEN : in std_logic; - PSCLK : in std_logic; - RST : in std_logic; - CLK0 : out std_logic; - CLK90 : out std_logic; - CLK180 : out std_logic; - CLK270 : out std_logic; - CLK2X : out std_logic; - CLK2X180 : out std_logic; - CLKDV : out std_logic; - CLKFX : out std_logic; - CLKFX180 : out std_logic; - LOCKED : out std_logic; - PSDONE : out std_logic; - STATUS : out std_logic_vector(7 downto 0) - ); -end component; - - --- Attributes -attribute DLL_FREQUENCY_MODE : string; -attribute DUTY_CYCLE_CORRECTION : string; -attribute STARTUP_WAIT : string; -attribute CLKDV_DIVIDE : real; -attribute CLKIN_PERIOD : real; -attribute CLKFX_MULTIPLY : integer; - -attribute DLL_FREQUENCY_MODE of U_DCM0: label is "LOW"; -attribute DUTY_CYCLE_CORRECTION of U_DCM0: label is "TRUE"; -attribute STARTUP_WAIT of U_DCM0: label is "FALSE"; -attribute CLKDV_DIVIDE of U_DCM0: label is 2.0; -attribute CLKIN_PERIOD of U_DCM0: label is 20.0; -attribute CLKFX_MULTIPLY of U_DCM0: label is 4; - -attribute DLL_FREQUENCY_MODE of U_DCM1: label is "LOW"; -attribute DUTY_CYCLE_CORRECTION of U_DCM1: label is "TRUE"; -attribute STARTUP_WAIT of U_DCM1: label is "FALSE"; -attribute CLKDV_DIVIDE of U_DCM1: label is 2.0; - - --- ----------------------------------------------------------------------- --- Signal Declarations: -constant gnd : std_logic := '0'; - -signal dcm0_clk0_buf : std_logic; -signal dcm0_clk0 : std_logic; -signal dcm0_clk90 : std_logic; -signal dcm0_clk180 : std_logic; -signal dcm0_clk2x : std_logic; -signal dcm0_clk2x180 : std_logic; -signal dcm0_clkdv : std_logic; -signal dcm0_clkdv_buf: std_logic; -signal dcm0_clk4x : std_logic; -signal dcm0_clk4x_buf: std_logic; -signal dcm0_lock : std_logic; - -signal reg1_dcm1rst : std_logic; -signal reg2_dcm1rst : std_logic; -signal reg3_dcm1rst : std_logic; -signal dcm1_clk0_buf : std_logic; -signal dcm1_clk0 : std_logic; -signal dcm1_clk90 : std_logic; -signal dcm1_clk90_buf: std_logic; -signal dcm1_lock : std_logic; - -begin - --- ---------------- DCM0 Instantion ------------------ -U_DCM0: DCM - -- pragma translate_off - generic map ( - DLL_FREQUENCY_MODE => "LOW", - DUTY_CYCLE_CORRECTION => TRUE, - STARTUP_WAIT => FALSE, - CLKDV_DIVIDE => 2.0 - ) - -- pragma translate_on - port map ( - CLKIN => CLK_IN, - CLKFB => dcm0_clk0_buf, - DSSEN => gnd, - PSINCDEC => gnd, - PSEN => gnd, - PSCLK => gnd, - RST => RST, - CLK0 => dcm0_clk0, - CLK90 => dcm0_clk90, - CLK180 => dcm0_clk180, - CLK2X => dcm0_clk2x, - CLK2X180 => dcm0_clk2x180, - CLKFX => dcm0_clk4x, - CLKDV => dcm0_clkdv, - LOCKED => dcm0_lock - ); - --- BUFG Instantiation -BUFG2X_U : BUFG - port map ( - I => dcm0_clk2x, - O => CLK2X - ); - --- BUFG Instantiation -BUFG2XPH180_U : BUFG - port map ( - I => dcm0_clk2x180, - O => CLK2X_PH180 - ); - --- BUFG Instantiation -BUFG1X_U : BUFG - port map ( - I => dcm0_clk0, - O => dcm0_clk0_buf - ); - --- BUFG Instantiation -BUFG1XPH90_U : BUFG - port map ( - I => dcm0_clk90, - O => CLK1X_PH90 - ); - --- BUFG Instantiation -BUFG1XPH180_U : BUFG - port map ( - I => dcm0_clk180, - O => CLK1X_PH180 - ); - --- BUFG Instantiation -BUFDV_IN_U : BUFG - port map ( - I => dcm0_clkdv, - O => dcm0_clkdv_buf - ); - --- BUFG Instantiation -BUFFX_IN_U : BUFG - port map ( - I => dcm0_clk4x, - O => dcm0_clk4x_buf - ); - - --- ---------------- DCM1 Instantion ------------------ --- reg_dcmrst register -process(RST, dcm0_clkdv_buf) -begin - if (RST = '1') then - reg1_dcm1rst <= '1'; - reg2_dcm1rst <= '1'; - reg3_dcm1rst <= '1'; - elsif (dcm0_clkdv_buf'event AND dcm0_clkdv_buf = '1') then - reg1_dcm1rst <= not dcm0_lock; - reg2_dcm1rst <= reg1_dcm1rst; - reg3_dcm1rst <= reg2_dcm1rst; - end if; -end process; - --- DCM Instantiation -U_DCM1: DCM - -- pragma translate_off - generic map ( - DLL_FREQUENCY_MODE => "LOW", - DUTY_CYCLE_CORRECTION => TRUE, - STARTUP_WAIT => FALSE, - CLKDV_DIVIDE => 2.0 - ) - -- pragma translate_on - port map ( - CLKIN => dcm0_clkdv_buf, - CLKFB => dcm1_clk0_buf, - DSSEN => gnd, - PSINCDEC => gnd, - PSEN => gnd, - PSCLK => gnd, - RST => reg3_dcm1rst, - CLK0 => dcm1_clk0, - CLK90=> dcm1_clk90, - LOCKED => dcm1_lock - ); - --- BUFG Instantiation -BUFDV_U : BUFG - port map ( - I => dcm1_clk0, - O => dcm1_clk0_buf - ); - --- BUFG Instantiation -BUFDV_PHU : BUFG - port map ( - I => dcm1_clk90, - O => dcm1_clk90_buf - ); - --- Interface mapping -CLK1X <= dcm0_clk0_buf; -CLK2DV <= dcm1_clk0_buf; -CLK2DV_PH90 <= dcm1_clk90_buf; -CLK4x <= dcm0_clk4x_buf; -LOCK <= dcm1_lock; - -end behavioral; - diff --git a/comp/base/misc/clk_gen/clk4x.vhd b/comp/base/misc/clk_gen/clk4x.vhd deleted file mode 100644 index a27e4180c..000000000 --- a/comp/base/misc/clk_gen/clk4x.vhd +++ /dev/null @@ -1,128 +0,0 @@ --- clk4x.vhd: Clock generation entity --- Copyright (C) 2003 CESNET --- Author(s): Jan Korenek --- --- SPDX-License-Identifier: BSD-3-Clause --- -library IEEE; -use IEEE.std_logic_1164.all; --- --- pragma translate_off -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; --- pragma translate_on - --- ----------------------------------------------------------------------- --- Entity declaration --- ----------------------------------------------------------------------- -entity clk4x_mod is -port ( - CLK_IN : in std_logic; - RST : in std_logic; - CLK4X : out std_logic; - LOCK : out std_logic -); -end clk4x_mod; - --- ----------------------------------------------------------------------- --- Architecture declaration --- ----------------------------------------------------------------------- -architecture behavioral of clk4x_mod is - --- ------------------- Component declaration ----------------------------- -component BUFG -port ( - I : in std_logic; - O : out std_logic -); -end component; - -component DCM --- pragma translate_off -generic ( - DFS_FREQUENCY_MODE : string := "LOW"; - CLKFX_DIVIDE : integer := 1; - CLKFX_MULTIPLY : integer := 4 ; - STARTUP_WAIT : boolean := FALSE -); --- pragma translate_on - -port ( - CLKIN : in std_logic; - CLKFB : in std_logic; - DSSEN : in std_logic; - PSINCDEC : in std_logic; - PSEN : in std_logic; - PSCLK : in std_logic; - RST : in std_logic; - CLK0 : out std_logic; - CLK90 : out std_logic; - CLK180 : out std_logic; - CLK270 : out std_logic; - CLK2X : out std_logic; - CLK2X180 : out std_logic; - CLKDV : out std_logic; - CLKFX : out std_logic; - CLKFX180 : out std_logic; - LOCKED : out std_logic; - PSDONE : out std_logic; - STATUS : out std_logic_vector(7 downto 0) -); -end component; - - --- Attributes -attribute DFS_FREQUENCY_MODE : string; -attribute CLKFX_DIVIDE : integer; -attribute CLKFX_MULTIPLY : integer; -attribute STARTUP_WAIT : string; - -attribute DFS_FREQUENCY_MODE of U_DCM: label is "LOW"; -attribute CLKFX_DIVIDE of U_DCM: label is 1; -attribute CLKFX_MULTIPLY of U_DCM: label is 4; -attribute STARTUP_WAIT of U_DCM: label is "FALSE"; - --- Signal Declarations: -signal gnd : std_logic; -signal clk0_w: std_logic; -signal clk1x_w: std_logic; -signal clkfx_w: std_logic; -signal clkf_w: std_logic; - --- ----------------------------------------------------------------------- -begin -gnd <= '0'; -CLK4X <= clkf_w; - --- DCM Instantiation -U_DCM: DCM -port map ( - CLKIN => CLK_IN, - CLKFB => clk1x_w, - DSSEN => gnd, - PSINCDEC => gnd, - PSEN => gnd, - PSCLK => gnd, - RST => rst, - CLK0 => clk0_w, - CLKFX => clkfx_w, - LOCKED => LOCK -); - --- BUFG Instantiation for CLKFX -U0_BUFG: BUFG -port map ( - I => clkfx_w, - O => clkf_w -); - --- BUFG Instantiation -U2_BUFG: BUFG -port map ( - I => clk0_w, - O => clk1x_w -); - -end behavioral; --- ----------------------------------------------------------------------- - diff --git a/comp/base/misc/clk_gen/clk_gen.vhd b/comp/base/misc/clk_gen/clk_gen.vhd deleted file mode 100644 index 5896d9453..000000000 --- a/comp/base/misc/clk_gen/clk_gen.vhd +++ /dev/null @@ -1,121 +0,0 @@ --- clk_gen.vhd: Clock generation entity --- Copyright (C) 2003 CESNET, Liberouter project --- Author(s): Jan Korenek korenek@liberouter.org --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - Do the behavioral and after PAR tests --- - Add to top level entity - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - - --- ---------------------------------------------------------------------- --- Entity : clk_gen --- ---------------------------------------------------------------------- -entity CLK_GEN is - Port ( - -- ======= - -- Input - -- ======= - - -- Input clock freqvency (50MHz) - CLK50_IN : in std_logic; - -- Global reset signal - RESET : in std_logic; - -- ======= - -- Output - -- ======= - - -- 25MHz output clock - CLK25 : out std_logic; - -- 25MHz output clock (90' phase shift) - CLK25_PH90 : out std_logic; - -- 50MHz output clock - CLK50_OUT : out std_logic; - -- 50MHz output clock (90' phase shift) - CLK50_PH90 : out std_logic; - -- 50MHz output clock (180' phase shift) - CLK50_PH180 : out std_logic; - -- 100MHz output clock - CLK100 : out std_logic; - -- 100MHz output clock (180' phase shift) - CLK100_PH180: out std_logic; - -- 200MHz output clock - CLK200 : out std_logic; - LOCK : out std_logic - ); -end clk_gen; - --- ---------------------------------------------------------------------- --- Architecture : behavioral --- ---------------------------------------------------------------------- -architecture full of CLK_GEN is - --- Component : Twice multiply freqvency -component clk2x_mod is - port ( - CLK_IN : in std_logic; - RST : in std_logic; - CLK1X : out std_logic; - CLK1X_PH90 : out std_logic; - CLK1X_PH180 : out std_logic; - CLK2X : out std_logic; - CLK2X_PH180 : out std_logic; - CLK2DV : out std_logic; - CLK2DV_PH90 : out std_logic; - CLK4X : out std_logic; - LOCK : out std_logic - ); -end component; - --- component clk4x_mod is --- port ( --- CLK_IN : in std_logic; --- RST : in std_logic; --- CLK4X : out std_logic; --- LOCK : out std_logic --- ); --- end component; - -signal clk50x100_lock : std_logic; -signal clk200_lock : std_logic; - --- ---------------------------------------------------------------------- -begin - --- 100MHz generation component -CLK100_U : clk2x_mod -port map ( - CLK_IN => CLK50_IN, - RST => RESET, - CLK1X => CLK50_OUT, - CLK1X_PH90 => CLK50_PH90, - CLK1X_PH180 => CLK50_PH180, - CLK2X => CLK100, - CLK2X_PH180 => CLK100_PH180, - CLK2DV => CLK25, - CLK2DV_PH90 => CLK25_PH90, - CLK4X => CLK200, - LOCK => clk50x100_lock -); - --- 200MHz generation component --- CLK200_U : clk4x_mod --- port map ( --- CLK_IN => CLK50_IN, --- RST => RESET, --- CLK4X => CLK200, --- LOCK => clk200_lock --- ); - -LOCK <= clk50x100_lock; -- and clk200_lock; - -end full; --- ---------------------------------------------------------------------- diff --git a/comp/base/misc/clk_gen/clk_gen_pkg.vhd b/comp/base/misc/clk_gen/clk_gen_pkg.vhd deleted file mode 100644 index 32607ae84..000000000 --- a/comp/base/misc/clk_gen/clk_gen_pkg.vhd +++ /dev/null @@ -1,41 +0,0 @@ --- clk_gen_pkg.vhd: Package for CLK_GEN module --- Copyright (C) 2009 CESNET --- Author(s): Viktor Pus --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package clk_gen_pkg is - - function cv2_clkper (is_125 : boolean) return real; - function cv2_mult (is_125 : boolean) return integer; - -end clk_gen_pkg; - -package body clk_gen_pkg is - - function cv2_clkper (is_125 : boolean) return real is - begin - if is_125 then - return 8.0; - else - return 4.0; - end if; - end cv2_clkper; - - function cv2_mult (is_125 : boolean) return integer is - begin - if is_125 then - return 8; - else - return 4; - end if; - end cv2_mult; - -end clk_gen_pkg; - diff --git a/comp/base/misc/clk_gen/doc/spec.xml b/comp/base/misc/clk_gen/doc/spec.xml deleted file mode 100644 index 34a535732..000000000 --- a/comp/base/misc/clk_gen/doc/spec.xml +++ /dev/null @@ -1,79 +0,0 @@ - - - - - -Clk gen - - - - - - - - - - - - - - - - - - - - - - - - - Documentation under construction.. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/comp/base/misc/clk_gen/sim/clk_gen.fdo b/comp/base/misc/clk_gen/sim/clk_gen.fdo deleted file mode 100644 index 45bae7795..000000000 --- a/comp/base/misc/clk_gen/sim/clk_gen.fdo +++ /dev/null @@ -1,35 +0,0 @@ -# Modelsim script - behavioral simulation -# $Id$ - -# Create library -vlib work - -# Compile files -vcom -93 ../clk2x.vhd -vcom -93 ../clk_gen.vhd -vcom -93 clk_gen_tb.vhd - -# Run simulator -vsim -t 1ps -L xilinxcorelib -lib work testbench - -view wave -view signals -add wave * - -add wave -divider {DCM} -add wave /testbench/uut/clk100_u/u_dcm/clkin -add wave /testbench/uut/clk100_u/u_dcm/rst -add wave /testbench/uut/clk100_u/u_dcm/clk0_out -add wave /testbench/uut/clk100_u/u_dcm/clk2x_out -add wave /testbench/uut/clk100_u/u_dcm/clkdv_out -add wave /testbench/uut/clk100_u/u_dcm/locked_out - -add wave -divider {DCM_V} -add wave /testbench/uut/clk100_u/u_dcmdv/clkin -add wave /testbench/uut/clk100_u/u_dcmdv/rst -add wave /testbench/uut/clk100_u/u_dcmdv/clk0_out -add wave /testbench/uut/clk100_u/u_dcmdv/clk2x_out -add wave /testbench/uut/clk100_u/u_dcmdv/clkdv_out -add wave /testbench/uut/clk100_u/u_dcmdv/locked_out - -run 8000 ns diff --git a/comp/base/misc/clk_gen/sim/clk_gen.tdo b/comp/base/misc/clk_gen/sim/clk_gen.tdo deleted file mode 100644 index ca3a2a428..000000000 --- a/comp/base/misc/clk_gen/sim/clk_gen.tdo +++ /dev/null @@ -1,13 +0,0 @@ -# Modelsim script - time simulation -# $Id$ - -vlib work -vcom -93 ../clk_gen.sim.vhd clk_gen_tb.vhd -vsim -t 1ps -sdfmax /UUT=../clk_gen.sim.sdf -lib work testbench - -view wave -view signals - -add wave * - -run 8000 ns diff --git a/comp/base/misc/clk_gen/sim/clk_gen_tb.vhd b/comp/base/misc/clk_gen/sim/clk_gen_tb.vhd deleted file mode 100644 index f927a1ac0..000000000 --- a/comp/base/misc/clk_gen/sim/clk_gen_tb.vhd +++ /dev/null @@ -1,96 +0,0 @@ --- clk_gen_tb.vhd: Clock generation entity testbench --- Copyright (C) 2003 CESNET, Liberouter project --- Author(s): Jan Korenek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- ---------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------- - -entity testbench is -end testbench; - -architecture behavioral of testbench is - --- Component instantion -component CLK_GEN is - Port ( - -- Input - CLK50_IN : in std_logic; -- Input clock freqvency (50MHz) - RESET : in std_logic; -- Global reset signal - -- Output - CLK25 : out std_logic; -- 25MHz output clock - CLK25_PH90 : out std_logic; -- 25MHz output clock (90' phase shift) - CLK50_OUT : out std_logic; -- 50MHz output clock - CLK50_PH90 : out std_logic; -- 50MHz output clock (90' phase shift) - CLK50_PH180 : out std_logic; -- 50MHz output clock (180' phase shift) - CLK100 : out std_logic; -- 100MHz output clock - CLK100_PH180: out std_logic; -- 100MHz output clock (180' phase shift) - CLK200 : out std_logic; -- 200MHz output clock - LOCK : out std_logic - ); -end component CLK_GEN; - - signal clk50_in : std_logic; -- Input clock freqvency (50MHz) - signal reset : std_logic; -- Global reset signal - signal clk25 : std_logic; -- 25MHz output clock - signal clk25_ph90 : std_logic; -- 25MHz output clock (90' phase shift) - signal clk50_out : std_logic; -- 50MHz output clock - signal clk50_ph90 : std_logic; -- 50MHz output clock (90' phase shift) - signal clk50_ph180 : std_logic; -- 50MHz output clock (180' phase shift) - signal clk100 : std_logic; -- 100MHz output clock - signal clk100_ph180: std_logic; -- 100MHz output clock (180' phase shift) - signal clk200 : std_logic; -- 200MHz output clock - signal lock : std_logic; - - constant period : time := 20 ns; -begin - - -- ------------------- Generation of input clock ----------------- - c_gen : process - begin - clk50_in <= '0'; - wait for period / 2; - clk50_in <= '1'; - wait for period / 2; - end process c_gen; - - -- ------------------------ Reset generation --------------------- - res : process - begin - reset<='1'; - wait for 300 ns; - reset<='0'; - wait; - end process res; - - -- ------------------- Clock generation component ---------------- - uut : clk_gen - port map ( - -- Input - CLK50_IN => clk50_in, -- Input clock freqvency (50MHz) - RESET => reset, -- Global reset signal - -- Output - CLK25 => clk25, -- 25MHz output clock - CLK25_PH90 => clk25_ph90, -- 25MHz output clock (90' phase shift) - CLK50_OUT => clk50_out, -- 50MHz output clock - CLK50_PH90 => clk50_ph90, -- 50MHz output clock (90' phase shift) - CLK50_PH180 => clk50_ph180, -- 50MHz output clock (180' phase shift) - CLK100 => clk100, -- 100MHz output clock - CLK100_PH180 => clk100_ph180, -- 100MHz output clock (180' phase shift) - CLK200 => clk200, -- 200MHz output clock - LOCK => lock - ); - -end behavioral; diff --git a/comp/base/misc/clk_gen/synth/Makefile b/comp/base/misc/clk_gen/synth/Makefile deleted file mode 100644 index 7def7b2e7..000000000 --- a/comp/base/misc/clk_gen/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=clk_gen - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/base/misc/fifo_pipe/Modules.tcl b/comp/base/misc/fifo_pipe/Modules.tcl deleted file mode 100644 index 0c3e01d8f..000000000 --- a/comp/base/misc/fifo_pipe/Modules.tcl +++ /dev/null @@ -1,18 +0,0 @@ -# Modules.tcl: Local include tcl script -# Copyright (C) 2016 CESNET -# Author: Vaclav Hummel -# -# SPDX-License-Identifier: BSD-3-Clause - -set MATH_PKG "$OFM_PATH/comp/base/pkg" - -set MOD "$MOD $ENTITY_BASE/fifo_pipe.vhd" -set FIFO_BASE "$OFM_PATH/comp/base/fifo/fifo" -set SH_FIFO_BASE "$OFM_PATH/comp/base/fifo/sh_fifo" - -set COMPONENTS [ list \ - [ list "FIFO" $FIFO_BASE "FULL" ] \ - [ list "SH_FIFO" $SH_FIFO_BASE "FULL" ] \ - ] - -set PACKAGES "$PACKAGES $MATH_PKG/math_pack.vhd" diff --git a/comp/base/misc/fifo_pipe/fifo_pipe.vhd b/comp/base/misc/fifo_pipe/fifo_pipe.vhd deleted file mode 100644 index 12d23762f..000000000 --- a/comp/base/misc/fifo_pipe/fifo_pipe.vhd +++ /dev/null @@ -1,227 +0,0 @@ --- fifo_pipe.vhd : FIFO PIPE entity and architecture ---! ---! \file ---! \brief FIFO PIPE entity and architecture ---! \author Jan Kubalek ---! \date 2018 ---! ---! \section License ---! ---! Copyright (C) 2018 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; -use work.math_pack.all; - - ---! ----------------------------------------------------------------------------- ---! Entity declaration ---! ----------------------------------------------------------------------------- - -entity fifo_pipe is -generic ( - -- transafer data width - DATA_WIDTH : integer := 64; - -- pipeline levels before FIFO - PIPE_N : integer := 4; - -- FIFO output register - OUT_REG : boolean := false -); -port ( - - -- ------------------------------------------------------------------------- - -- Clock & Reset - -- ------------------------------------------------------------------------- - - CLK : in std_logic; - RESET : in std_logic; - - -- ------------------------------------------------------------------------- - -- RX interface - -- ------------------------------------------------------------------------- - - -- source ready - RX_SRC_RDY : in std_logic; - -- destination ready - RX_DST_RDY : out std_logic; - - -- data - RX_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - - -- ------------------------------------------------------------------------- - -- TX interface - -- ------------------------------------------------------------------------- - - -- source ready - TX_SRC_RDY : out std_logic; - -- destination ready - TX_DST_RDY : in std_logic; - - -- data - TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0) - -); -end entity fifo_pipe; - -architecture full of fifo_pipe is - - -- ------------------------------------------------------------------------- - - constant FIFO_SIZE : integer := PIPE_N*4+2; - constant FIFO_AFULL_LIMIT : integer := PIPE_N*2+2; - - constant SMALL_FIFO_MAX : integer := 31; - - -- ------------------------------------------------------------------------- - - -- pipeline - signal data_pipeline : std_logic_vector(PIPE_N*(DATA_WIDTH+1)-1 downto 0); - signal afull_pipeline : std_logic_vector(PIPE_N-1 downto 0); - - -- FIFO fill - signal fifo_fill : unsigned(log2(FIFO_SIZE+1)-1 downto 0); - signal fifo_almost_full : std_logic; - signal fifo_empty : std_logic; - - -- reset counter - signal reset_cnt : std_logic_vector(PIPE_N-1 downto 0); - - -- ------------------------------------------------------------------------- - -begin - - -- ------------------------------------------------------------------------- - -- pipeline - -- ------------------------------------------------------------------------- - - pipeline_gen : process (CLK) - begin - if (CLK'event and CLK='1') then - -- data pipeline - data_pipeline(PIPE_N*(DATA_WIDTH+1)-1 downto (PIPE_N-1)*(DATA_WIDTH+1)+1) <= RX_DATA; - data_pipeline((PIPE_N-1)*(DATA_WIDTH+1)) <= '1' when RX_SRC_RDY='1' and afull_pipeline(PIPE_N-1)='0' else '0'; - - for i in PIPE_N-1-1 downto 0 loop - data_pipeline((i+1)*(DATA_WIDTH+1)-1 downto i*(DATA_WIDTH+1)) <= data_pipeline((i+1+1)*(DATA_WIDTH+1)-1 downto (i+1)*(DATA_WIDTH+1)); - end loop; - - -- alfull pipeline - afull_pipeline(0) <= fifo_almost_full; - - for i in 1 to PIPE_N-1 loop - afull_pipeline(i) <= afull_pipeline(i-1); - end loop; - end if; - end process; - - RX_DST_RDY <= not afull_pipeline(PIPE_N-1); - - -- ------------------------------------------------------------------------- - - -- ------------------------------------------------------------------------- - -- reset counter - -- ------------------------------------------------------------------------- - - reset_cnt_gen : process (RESET,CLK) - begin - if (CLK'event and CLK='1') then - reset_cnt(PIPE_N-1) <= '0'; - for i in PIPE_N-1-1 downto 0 loop - reset_cnt(i) <= reset_cnt(i+1); - end loop; - - if (RESET='1') then - reset_cnt <= (others => '1'); - end if; - end if; - end process; - - -- ------------------------------------------------------------------------- - - -- ------------------------------------------------------------------------- - -- FIFO fill - -- ------------------------------------------------------------------------- - - fifo_fill_gen : process (RESET,CLK) - begin - if (CLK'event and CLK='1') then - if (data_pipeline(0)='1' and (TX_DST_RDY='0' or fifo_empty='1')) then -- writing, not reading - fifo_fill <= fifo_fill+1; - elsif (data_pipeline(0)='0' and (TX_DST_RDY='1' and fifo_empty='0')) then -- reading, not writing - fifo_fill <= fifo_fill-1; - end if; - - if (RESET='1') then - fifo_fill <= (others => '0'); - end if; - end if; - end process; - - fifo_almost_full <= '1' when fifo_fill>=FIFO_AFULL_LIMIT else '0'; - fifo_empty <= (nor fifo_fill); - - TX_SRC_RDY <= not fifo_empty; - - -- ------------------------------------------------------------------------- - - -- ------------------------------------------------------------------------- - -- output FIFO - -- ------------------------------------------------------------------------- - - small_fifo_gen : if FIFO_SIZE<=SMALL_FIFO_MAX generate - sh_fifo_gen : entity work.sh_fifo - generic map ( - FIFO_WIDTH => DATA_WIDTH, - FIFO_DEPTH => FIFO_SIZE, - USE_INREG => false, - USE_OUTREG => OUT_REG - ) - port map ( - CLK => CLK, - RESET => RESET, - - DIN => data_pipeline(DATA_WIDTH+1-1 downto 0+1), - WE => data_pipeline(0) and not reset_cnt(0), - - DOUT => TX_DATA, - RE => TX_DST_RDY and not fifo_empty, - - EMPTY => open, - STATUS => open, - FULL => open - ); - end generate; - - big_fifo_gen : if FIFO_SIZE>SMALL_FIFO_MAX generate - fifo_gen : entity work.fifo - generic map ( - DATA_WIDTH => DATA_WIDTH, - ITEMS => FIFO_SIZE, - DO_REG => OUT_REG - ) - port map ( - CLK => CLK, - RESET => RESET, - - DATA_IN => data_pipeline(DATA_WIDTH+1-1 downto 0+1), - WRITE_REQ => data_pipeline(0) and not reset_cnt(0), - - DATA_OUT => TX_DATA, - READ_REQ => TX_DST_RDY and not fifo_empty, - - EMPTY => open, - FULL => open, - LSTBLK => open, - STATUS => open - ); - end generate; - - -- ------------------------------------------------------------------------- - -end full; diff --git a/comp/base/misc/fifo_pipe/sim/fifo_pipe.fdo b/comp/base/misc/fifo_pipe/sim/fifo_pipe.fdo deleted file mode 100644 index 31e1869ac..000000000 --- a/comp/base/misc/fifo_pipe/sim/fifo_pipe.fdo +++ /dev/null @@ -1,24 +0,0 @@ -# fifo_pipe.fdo: Functional simulation file for merger from n inputs to m outputs -# Copyright (C) 2018 CESNET -# Author: Jan Kubalek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -set FIRMWARE_BASE "../../../../.." - -set FIFO_PIPE_BASE "$OFM_PATH/comp/base/misc/fifo_pipe" -set MATH_PKG_BASE "$OFM_PATH/comp/base/pkg" - -set SIG_FILE "$FIFO_PIPE_BASE/sim/fifo_pipe_sig.fdo" -set TB_FILE "$FIFO_PIPE_BASE/sim/testbench.vhd" - - -set COMPONENTS [list \ - [ list "FIFO_PIPE" $FIFO_PIPE_BASE "FULL" ] \ -] - -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -nb_sim_run 250us diff --git a/comp/base/misc/fifo_pipe/sim/fifo_pipe_sig.fdo b/comp/base/misc/fifo_pipe/sim/fifo_pipe_sig.fdo deleted file mode 100644 index f6c22e4fa..000000000 --- a/comp/base/misc/fifo_pipe/sim/fifo_pipe_sig.fdo +++ /dev/null @@ -1,29 +0,0 @@ -# fifo_pipe_sig.fdo : Include file with signals -# Copyright (C) 2018 CESNET -# Author: Jan Kubalek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -# Paths -set FIFO_PIPE_PATH "/testbench/uut" -set TB_PATH "/testbench" - -source "signals.fdo" - -add wave -divider "" -add wave -divider "TB internals" -add wave -divider "" -tb_internals "$TB_PATH" "" - -add wave -divider "" -add wave -divider "FIFO_PIPE ports" -add wave -divider "" -fifo_pipe_ports "$FIFO_PIPE_PATH" "" - -add wave -divider "" -add wave -divider "FIFO_PIPE internals" -add wave -divider "" -fifo_pipe_internals "$FIFO_PIPE_PATH" "" - diff --git a/comp/base/misc/fifo_pipe/sim/signals.fdo b/comp/base/misc/fifo_pipe/sim/signals.fdo deleted file mode 100644 index b60994f1a..000000000 --- a/comp/base/misc/fifo_pipe/sim/signals.fdo +++ /dev/null @@ -1,41 +0,0 @@ -# signals.fdo : Include file with signals -# Copyright (C) 2018 CESNET -# Author: Jan Kubalek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -proc tb_internals { PATH GROUP } { - eval "add wave $GROUP -divider {TB internals}" - add_wave "$GROUP -noupdate -hex -label TEST_STATUS" $PATH/TEST_STATUS - add_wave "$GROUP -noupdate -hex -label false_fifo" $PATH/false_fifo - add_wave "$GROUP -noupdate -hex -label false_wr_ptr" $PATH/false_wr_ptr - add_wave "$GROUP -noupdate -hex -label false_rd_ptr" $PATH/false_rd_ptr -} - -proc fifo_pipe_ports { PATH GROUP } { - - eval "add wave $GROUP -divider {Synchronization}" - add_wave "$GROUP -noupdate -hex -label CLK -color yellow" $PATH/CLK - add_wave "$GROUP -noupdate -hex -label RESET -color yellow" $PATH/RESET - - eval "add wave $GROUP -divider {Ports}" - add_wave "$GROUP -noupdate -hex -label RX_SRC_RDY" $PATH/RX_SRC_RDY - add_wave "$GROUP -noupdate -hex -label RX_DST_RDY" $PATH/RX_DST_RDY - add_wave "$GROUP -noupdate -hex -label RX_DATA" $PATH/RX_DATA - add_wave "$GROUP -noupdate -hex -label TX_SRC_RDY" $PATH/TX_SRC_RDY - add_wave "$GROUP -noupdate -hex -label TX_DST_RDY" $PATH/TX_DST_RDY - add_wave "$GROUP -noupdate -hex -label TX_DATA" $PATH/TX_DATA -} - -proc fifo_pipe_internals { PATH GROUP } { - - eval "add wave $GROUP -divider {Internals}" - add_wave "$GROUP -noupdate -hex -label data_pipeline" $PATH/data_pipeline - add_wave "$GROUP -noupdate -hex -label afull_pipeline" $PATH/afull_pipeline - add_wave "$GROUP -noupdate -hex -label fifo_fill" $PATH/fifo_fill - add_wave "$GROUP -noupdate -hex -label fifo_almost_full" $PATH/fifo_almost_full - add_wave "$GROUP -noupdate -hex -label fifo_empty" $PATH/fifo_empty - add_wave "$GROUP -noupdate -hex -label reset_cnt" $PATH/reset_cnt -} diff --git a/comp/base/misc/fifo_pipe/sim/testbench.vhd b/comp/base/misc/fifo_pipe/sim/testbench.vhd deleted file mode 100644 index 177c3c853..000000000 --- a/comp/base/misc/fifo_pipe/sim/testbench.vhd +++ /dev/null @@ -1,204 +0,0 @@ --- testbench.vhd: Testbench for merger from n inputs to m outputs --- Copyright (C) 2018 CESNET --- Author(s): Jan Kubalek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; - -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use ieee.numeric_std.all; -use ieee.math_real.all; -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- - -entity testbench is -end entity testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- - -architecture behavioral of testbench is - - -- Constants declaration --------------------------------------------------- - - -- Synchronization - constant C_CLK_PER : time := 5.0 ns; - constant C_RST_TIME : time := 10 * C_CLK_PER + 1 ns; - - --! \brief Data width - constant DATA_WIDTH : integer := 16; - - constant FALSE_FIFO_SIZE : integer := 512; - - -- Signals declaration ----------------------------------------------------- - - -- Synchronization - signal clk : std_logic; - signal rst : std_logic; - - signal rx_src_rdy : std_logic := '0'; - signal rx_dst_rdy : std_logic; - signal rx_data : std_logic_vector(DATA_WIDTH-1 downto 0); - signal tx_src_rdy : std_logic; - signal tx_dst_rdy : std_logic := '0'; - signal tx_data : std_logic_vector(DATA_WIDTH-1 downto 0); - - signal false_fifo : std_logic_vector(FALSE_FIFO_SIZE*DATA_WIDTH-1 downto 0); - signal false_rd_ptr : unsigned(log2(FALSE_FIFO_SIZE)-1 downto 0) := (others => '0'); - signal false_wr_ptr : unsigned(log2(FALSE_FIFO_SIZE)-1 downto 0) := (others => '0'); - - signal TEST_STATUS : std_logic := '1'; - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- - -begin - - -- ------------------------------------------------------------------------- - -- CROSSBAR SCHEDULER planner - -- ------------------------------------------------------------------------- - - uut: entity work.fifo_pipe - generic map( - DATA_WIDTH => DATA_WIDTH, - PIPE_N => 4, - OUT_REG => false - ) - port map( - - CLK => clk, - RESET => rst, - - RX_SRC_RDY => rx_src_rdy, - RX_DST_RDY => rx_dst_rdy, - - RX_DATA => rx_data, - - TX_SRC_RDY => tx_src_rdy, - TX_DST_RDY => tx_dst_rdy, - - TX_DATA => tx_data - ); - - -- ------------------------------------------------------------------------- - -- clk and reset generators - -- ------------------------------------------------------------------------- - - -- generating clk - clk_gen: process - begin - clk <= '1'; - wait for C_CLK_PER / 2; - clk <= '0'; - wait for C_CLK_PER / 2; - end process clk_gen; - - -- generating reset - rst_gen: process - begin - rst <= '1'; - wait for C_RST_TIME; - rst <= '0'; - wait; - end process rst_gen; - - -- ------------------------------------------------------------------------- - - tb: process - variable seed1 : positive := 42; - variable seed2 : positive := 42; - - variable rand : real; - variable X : integer; - - variable src_rdy_ch : integer := 50; - variable not_src_rdy_ch : integer := 1; - - variable dst_rdy_ch : integer := 1; - variable not_dst_rdy_ch : integer := 0; - - variable rx_rdy : std_logic := '1'; - variable tx_rdy : std_logic := '0'; - - variable d_i : unsigned(DATA_WIDTH-1 downto 0) := (others => '0'); - variable d_o : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); - - variable d_r : std_logic; - - variable i : integer; - - variable n_r_burst_ch : integer := 80; - variable n_r_burst_s : integer := 22; - variable n_r_burst : integer := 0; - begin - -- Wait for the reset - if (rst='1') then - wait until rst='0'; - end if; - - if (rx_src_rdy='1' and rx_rdy='1') then - i := to_integer(false_wr_ptr); - false_fifo((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= std_logic_vector(d_i); - false_wr_ptr <= false_wr_ptr+1; - d_i := d_i+1; - end if; - - if (rx_rdy='1' or rx_src_rdy='0') then - rx_src_rdy <= '0'; - rx_data <= std_logic_vector(d_i); - - uniform(seed1,seed2,rand); - X := integer(rand*real(src_rdy_ch+not_src_rdy_ch)); - if (X<=src_rdy_ch) then - rx_src_rdy <= '1'; - end if; - - end if; - - if (tx_rdy='1' or tx_dst_rdy='0') then - - tx_dst_rdy <= '0'; - d_r := '0'; - - uniform(seed1,seed2,rand); - X := integer(rand*real(dst_rdy_ch+not_dst_rdy_ch)); - if (X<=dst_rdy_ch and n_r_burst=0) then - tx_dst_rdy <= '1'; - d_r := '1'; - elsif (n_r_burst>0) then - n_r_burst := n_r_burst-1; - end if; - - uniform(seed1,seed2,rand); - X := integer(rand*real(n_r_burst_ch)); - if (X=0) then - uniform(seed1,seed2,rand); - X := integer(rand*real(n_r_burst_s)); - n_r_burst := n_r_burst + X; - end if; - - end if; - - rx_rdy := rx_dst_rdy; - tx_rdy := tx_src_rdy; - d_o := tx_data; - - if (tx_src_rdy='1' and d_r='1') then - i := to_integer(false_rd_ptr); - TEST_STATUS <= '1' when false_fifo((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH)=tx_data else '0'; - false_rd_ptr <= false_rd_ptr+1; - end if; - - wait for C_CLK_PER; - end process; -end architecture behavioral; diff --git a/comp/base/misc/fifo_pipe/synth/Makefile b/comp/base/misc/fifo_pipe/synth/Makefile deleted file mode 100644 index fe207176a..000000000 --- a/comp/base/misc/fifo_pipe/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=FIFO_PIPE - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/base/misc/hyper_pipe/Modules.tcl b/comp/base/misc/hyper_pipe/Modules.tcl deleted file mode 100644 index e6b49b91b..000000000 --- a/comp/base/misc/hyper_pipe/Modules.tcl +++ /dev/null @@ -1,8 +0,0 @@ -# Modules.tcl: Components include script -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -# Source files for implemented component -set MOD "$MOD $ENTITY_BASE/hyper_pipe.vhd" diff --git a/comp/base/misc/hyper_pipe/hyper_pipe.vhd b/comp/base/misc/hyper_pipe/hyper_pipe.vhd deleted file mode 100644 index 11de874ec..000000000 --- a/comp/base/misc/hyper_pipe/hyper_pipe.vhd +++ /dev/null @@ -1,54 +0,0 @@ --- hyper_pipe.vhd: Hyper Pipe Registers optimized for Stratix 10 --- Copyright (C) 2019 CESNET z. s. p. o. --- Author(s): Jakub Cabal --- --- SPDX-License-Identifier: BSD-3-Clause - -library IEEE; -use IEEE.std_logic_1164.all; - -entity HYPER_PIPE is - generic( - -- Data word width in bits. - DATA_WIDTH : natural := 8; - -- Latency in clock cycles, specifies the number of Hyper-Registers. - LATENCY : natural := 2 - ); - port( - CLK : in std_logic; - DIN : in std_logic_vector(DATA_WIDTH-1 downto 0); - DOUT : out std_logic_vector(DATA_WIDTH-1 downto 0) - ); -end entity; - -architecture behavioral of HYPER_PIPE is - - type reg_array_t is array (LATENCY-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); - - signal hyper_pipe : reg_array_t; - - -- Prevent large hyper-pipes from going into memory-based altshift_taps. - attribute ALTERA_ATTRIBUTE : string; - attribute ALTERA_ATTRIBUTE of hyper_pipe : - signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; - -begin - - -- Only wire without Hyper-Registers - only_wires_g : if LATENCY = 0 generate - DOUT <= DIN; - end generate; - - -- Pipe of Hyper-Registers - hyper_pipe_on_g : if LATENCY > 0 generate - hyper_pipe_p : process (CLK) - begin - if (rising_edge(CLK)) then - hyper_pipe <= hyper_pipe(LATENCY-2 downto 0) & DIN; - end if; - end process; - - DOUT <= hyper_pipe(LATENCY-1); - end generate; - -end architecture; diff --git a/comp/base/misc/hyper_pipe/synth/Makefile b/comp/base/misc/hyper_pipe/synth/Makefile deleted file mode 100644 index 5af135863..000000000 --- a/comp/base/misc/hyper_pipe/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=HYPER_PIPE - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/base/misc/watchdog/Modules.tcl b/comp/base/misc/watchdog/Modules.tcl deleted file mode 100644 index 7448dfc62..000000000 --- a/comp/base/misc/watchdog/Modules.tcl +++ /dev/null @@ -1,14 +0,0 @@ -# Modules.tcl: Components include script -# Copyright (C) 2015 CESNET -# Author: Adam Piecek -# -# SPDX-License-Identifier: BSD-3-Clause - -# packages -set PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd" - -# modules -set MOD "$MOD $ENTITY_BASE/watchdog_ent.vhd" -set MOD "$MOD $ENTITY_BASE/watchdog_mi32_ent.vhd" -set MOD "$MOD $ENTITY_BASE/watchdog_mi32_arch.vhd" -set MOD "$MOD $ENTITY_BASE/watchdog_arch.vhd" diff --git a/comp/base/misc/watchdog/sim/watchdog.fdo b/comp/base/misc/watchdog/sim/watchdog.fdo deleted file mode 100644 index 0e44ca7ea..000000000 --- a/comp/base/misc/watchdog/sim/watchdog.fdo +++ /dev/null @@ -1,33 +0,0 @@ -# watchdog.fdo : Include file with signals -# Copyright (C) 2015 CESNET -# Authors: Adam Piecek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# For whole design testing -set FIRMWARE_BASE "../../../../.." -set WATCHDOG_BASE "$OFM_PATH/comp/base/misc/watchdog" -set TB_FILE "watchdog_tb.vhd" -set SIG_FILE "watchdog_sig.fdo" - -set MOD $TB_FILE - -set PACKAGES "" - -# Modules definition -set COMPONENTS [list \ - [list "Watchdog" $WATCHDOG_BASE FULL] \ -] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -puts "Std Arith Warnings - Disabled" -set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 2us diff --git a/comp/base/misc/watchdog/sim/watchdog_sig.fdo b/comp/base/misc/watchdog/sim/watchdog_sig.fdo deleted file mode 100644 index e0c1feafa..000000000 --- a/comp/base/misc/watchdog/sim/watchdog_sig.fdo +++ /dev/null @@ -1,41 +0,0 @@ -# watchdog_sig.fdo : Include file with signals -# Copyright (C) 2015 CESNET -# Authors: Adam Piecek -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Components paths -set TB_PATH "/testbench" -set UUT_PATH "/testbench/uut" - -# Common interface -add_wave "-noupdate -label reset" /testbench/uut/reset -add_wave "-noupdate -label clk" /testbench/uut/clk - -add wave -divider "Datasource" -add_wave "-noupdate -hex -label data_in " $TB_PATH/data_in -add_wave "-noupdate -hex -label src_rdy_in " $TB_PATH/src_rdy_in -add_wave "-noupdate -hex -label dst_rdy_in " $TB_PATH/dst_rdy_in - -add wave -divider "Data destination" -add_wave "-noupdate -hex -label data_out " $TB_PATH/data_out -add_wave "-noupdate -hex -label src_rdy_out " $TB_PATH/src_rdy_out -add_wave "-noupdate -hex -label dst_rdy_out " $TB_PATH/dst_rdy_out - -add wave -divider "Special signals" -add_wave "-noupdate -hex -label counter " $TB_PATH/counter -add_wave "-noupdate -hex -label locked " $TB_PATH/locked - -add wave -divider "MI32 interface" -add wave -noupdate -hex -label dwr $TB_PATH/dwr -add wave -noupdate -hex -label addr $TB_PATH/addr -add wave -noupdate -hex -label rd $TB_PATH/rd -add wave -noupdate -hex -label wr $TB_PATH/wr -add wave -noupdate -hex -label be $TB_PATH/be -add wave -noupdate -hex -label drd $TB_PATH/drd -add wave -noupdate -hex -label ardy $TB_PATH/ardy -add wave -noupdate -hex -label drdy $TB_PATH/drdy - diff --git a/comp/base/misc/watchdog/sim/watchdog_tb.vhd b/comp/base/misc/watchdog/sim/watchdog_tb.vhd deleted file mode 100644 index 45c3a88ea..000000000 --- a/comp/base/misc/watchdog/sim/watchdog_tb.vhd +++ /dev/null @@ -1,193 +0,0 @@ --- --- watchdog_testbench.vhd: Component testbench. --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - --- math package - log2 function -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity testbench is -end entity testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture behavioral of testbench is - - constant DATA_WIDTH : positive := 10; - constant EDGE_DETECT : boolean := false; - constant COUNT : positive := 9; - constant COUNTER_WIDTH : positive := 32; - signal TIMING : boolean := false; - - constant clkper : time := 10 ns; - constant RESET_TIME : time := 3*clkper - 1ns ; - - signal clk : std_logic; - signal reset : std_logic; - - signal data_in : std_logic_vector(DATA_WIDTH-1 downto 0) - := (others => '0'); - signal src_rdy_in : std_logic; - signal dst_rdy_in : std_logic; - - signal data_out : std_logic_vector(DATA_WIDTH-1 downto 0); - signal src_rdy_out : std_logic; - signal dst_rdy_out : std_logic; - - signal counter : std_logic_vector(COUNTER_WIDTH-1 downto 0); - signal locked : std_logic; - - -- MI32 - signal dwr : std_logic_vector(31 downto 0); - signal addr : std_logic_vector(31 downto 0); - signal rd : std_logic; - signal wr : std_logic; - signal be : std_logic_vector(3 downto 0); - signal drd : std_logic_vector(31 downto 0); - signal ardy : std_logic; - signal drdy : std_logic; - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- -begin - - uut: entity work.watchdog_mi32 - generic map ( - DATA_WIDTH => DATA_WIDTH, - EDGE_DETECT => EDGE_DETECT, - COUNT => COUNT, - COUNTER_WIDTH => COUNTER_WIDTH, - TIMING => TIMING - ) - port map( - -- Common interface - CLK => clk, - RESET => reset, - - DATA_IN => data_in, - SRC_RDY_IN => src_rdy_in, - DST_RDY_IN => dst_rdy_in, - - DATA_OUT => data_out, - SRC_RDY_OUT => src_rdy_out, - DST_RDY_OUT => dst_rdy_out, - COUNTER => counter, - LOCKED => locked, - - -- MI32 - DWR => dwr, - ADDR => addr, - RD => rd, - WR => wr, - BE => be, - DRD => drd, - ARDY => ardy, - DRDY => drdy - ); - - be <= "0001"; - --- ---------------------------------------------------- --- CLK clock generator - clkgen : process - begin - clk <= '1'; - wait for clkper/2; - clk <= '0'; - wait for clkper/2; - end process; - --- ---------------------------------------------------------------------------- --- Main testbench process --- ---------------------------------------------------------------------------- - tb : process - - begin - - -- RESET --------------------------------------------------------------- - wr <= '0'; - rd <= '0'; - addr <= (others => '0'); - dwr <= (others => '0'); - reset <= '1'; - src_rdy_in <= '1'; - dst_rdy_out <= '1'; - - wait for RESET_TIME; - reset <= '0'; - - -- test IN signals----- - wait for 4*clkper; - src_rdy_in <= '0'; - wait for 4*clkper; - src_rdy_in <= '1'; - wait for 4*clkper; - wr <= '1'; - dwr(0) <= '1'; - wait for 2*clkper; - dwr(0) <= '0'; - wait for clkper; - wr <= '0'; - - wait for 4*clkper; - dst_rdy_out <= '0'; - wait for 4*clkper; - reset <= '1'; - dst_rdy_out <= '1'; - wait for RESET_TIME; - reset <= '0'; - rd <= '1'; - - -- test wr signal - dwr(0) <= '1'; - wait for 2*clkper; - rd <= '0'; - wr <= '1'; - wait for 3*clkper; - wr <= '1'; - rd <= '1'; - - -- test keep_alive --- - addr(2) <= '1'; - wait for (COUNT/2)*clkper; - dwr(0) <= '1'; - wait for clkper; - dwr(0) <= '0'; - - wait for COUNT*clkper*2; - rd <= '0'; - dwr(0) <= '1'; - wait for clkper*3; - rd <= '1'; - dwr(0) <= '0'; - wait for clkper*4; - rd <= '0'; - - reset <= '1'; - wait for RESET_TIME; - reset <= '0'; - - wait for 5*clkper; - - wait; - end process; -end architecture behavioral; diff --git a/comp/base/misc/watchdog/synth/Makefile b/comp/base/misc/watchdog/synth/Makefile deleted file mode 100644 index 00acfb312..000000000 --- a/comp/base/misc/watchdog/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=WATCHDOG_MI32 - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/base/misc/watchdog/watchdog_arch.vhd b/comp/base/misc/watchdog/watchdog_arch.vhd deleted file mode 100644 index 0c426ead0..000000000 --- a/comp/base/misc/watchdog/watchdog_arch.vhd +++ /dev/null @@ -1,93 +0,0 @@ --- watchdog_arch.vhd: watchdog architecture --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - - -library IEEE; -use IEEE.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all; - -architecture watchdog of WATCHDOG is --- output signal of D-type flip-flop register -signal reg_keep_alive : std_logic; --- output signal of comparator under edge_det_t process -signal comp_out : std_logic; --- reset signal going to couter -signal rst : std_logic; ---! output value of counter -signal counter_out : std_logic_vector(COUNTER_WIDTH-1 downto 0); ---! maximum value of counter -signal limit : std_logic_vector(COUNTER_WIDTH-1 downto 0); ---! input signal to counter -signal ce : std_logic; ---! the comparison result of the counter and limit signal -signal comp_limit_out : std_logic; ---! destination and source components are ready to recieve/send the DATA -signal flow_rdy : std_logic; - - begin - edge_det_t : if EDGE_DETECT generate - --! D-type flip-flop - reg_d : process(CLK) - begin - if (CLK'event) and (CLK='1') then - reg_keep_alive <= KEEP_ALIVE; - end if; - end process; - - --! comparator - comp_out <= '1' when (not KEEP_ALIVE) = reg_keep_alive else '0'; - - rst <= RESET or comp_out; - end generate; - - edge_det_f : if EDGE_DETECT = false generate - rst <= RESET or KEEP_ALIVE; - end generate; - - --! set maximum value of counter - limit <= std_logic_vector(to_unsigned(COUNT-1,limit'length)); - --! counter - cnt : process(CLK) - begin - if (CLK'event) and (CLK='1') then - if rst = '1' then - counter_out <= (others => '0'); - elsif ce = '1' then - counter_out <= counter_out + '1'; - end if; - end if; - end process; - - COUNTER <= counter_out; - comp_limit_out <= '1' when counter_out = limit else '0'; - - timing_t : if TIMING generate - --! counter counts regardless of if adjacent components are ready - ce <= (not comp_limit_out); - end generate; - - timing_f : if TIMING = false generate - --! if counter hasn't reached the limit and if adjacent components are ready - --! then counter may be enabled - flow_rdy <= SRC_RDY_IN and DST_RDY_OUT; - ce <= (not comp_limit_out) and flow_rdy; - end generate; - - - LOCKED <= comp_limit_out; - - SRC_RDY_OUT <= (not comp_limit_out) and SRC_RDY_IN; - DST_RDY_IN <= (not comp_limit_out) and DST_RDY_OUT; - - DATA_OUT <= DATA_IN; - - end; diff --git a/comp/base/misc/watchdog/watchdog_ent.vhd b/comp/base/misc/watchdog/watchdog_ent.vhd deleted file mode 100644 index 1540f2d2f..000000000 --- a/comp/base/misc/watchdog/watchdog_ent.vhd +++ /dev/null @@ -1,56 +0,0 @@ --- watchdog_ent.vhd: watchdog entity --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; -use WORK.math_pack.all; - -entity WATCHDOG is - generic( - --! width of the the data flow - DATA_WIDTH : positive := 10; - --! enable edge detection on signal KEEP_ALIVE - EDGE_DETECT : boolean := false; - --! maximum value of steps to the counter - COUNT : positive := 8; - --! width of the counter - COUNTER_WIDTH : positive := 32; - --! if TIMING is true, counter counts clock's periods, not data flowing - TIMING : boolean := false - ); - - port( - --! Common interface - CLK : in std_logic; - RESET : in std_logic; - - --! data flow - DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0); - --! source is ready to send data - SRC_RDY_IN : in std_logic; - --! watchdog is ready to receive data - DST_RDY_IN : out std_logic; - - --! data flow - DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0); - --! watchdog is ready to send data - SRC_RDY_OUT : out std_logic; - --! destination is ready to receive data - DST_RDY_OUT : in std_logic; - - --! counter keep counting - KEEP_ALIVE : in std_logic; - --! contains exact status of internal counter - COUNTER : out std_logic_vector(COUNTER_WIDTH-1 downto 0); - --! if watchdog releases data or if it is locked - LOCKED : out std_logic - ); -end; diff --git a/comp/base/misc/watchdog/watchdog_framelink_arch.vhd b/comp/base/misc/watchdog/watchdog_framelink_arch.vhd deleted file mode 100644 index af9c21b60..000000000 --- a/comp/base/misc/watchdog/watchdog_framelink_arch.vhd +++ /dev/null @@ -1,75 +0,0 @@ --- watchdog_framelink_arch.vhd: watchdog FrameLink architecture --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; - -architecture framelink of WATCHDOG_FRAMELINK is ---! DATA_WIDTH for watchdog must be recalculated -signal aux_data_width : std_logic_vector - ((DATA_WIDTH-1 + RX_REM'length +4) downto 0); - -signal src_rdy_in : std_logic; -signal src_rdy_out : std_logic; -signal dst_rdy_in : std_logic; -signal dst_rdy_out : std_logic; - ---! input signal to DATA_IN -signal data_in : std_logic_vector(aux_data_width'range); ---! output signal form DATA_OUT -signal data_out : std_logic_vector(aux_data_width'range); - -begin - watch_comp: entity work.watchdog - generic map ( - DATA_WIDTH => aux_data_width'length, - EDGE_DETECT => EDGE_DETECT, - COUNT => COUNT, - COUNTER_WIDTH => COUNTER_WIDTH, - TIMING => TIMING - ) - port map( - CLK => CLK, - RESET => RESET, - - DATA_IN => data_in, - SRC_RDY_IN => src_rdy_in, - DST_RDY_IN => DST_RDY_IN, - - DATA_OUT => data_out, - SRC_RDY_OUT => src_rdy_out, - DST_RDY_OUT => dst_rdy_out, - - KEEP_ALIVE => KEEP_ALIVE, - COUNTER => COUNTER, - LOCKED => LOCKED - ); - - --! src_rdy is active in 0 - src_rdy_in <= not RX_SRC_RDY_IN; - TX_SRC_RDY_OUT <= not src_rdy_out; - - --! dst_rdy is active in 0 - dst_rdy_out <= not TX_DST_RDY_OUT; - RX_DST_RDY_IN <= not dst_rdy_in; - - --! composition of DATA_IN - data_in <= RX_SOF_N & RX_SOP_N & RX_EOP_N & RX_EOF_N & RX_REM & RX_DATA; - - --! decomposition of DATA_OUT - TX_SOF_N <= data_out(data_out'high); - TX_SOP_N <= data_out(data_out'high -1); - TX_EOP_N <= data_out(data_out'high -2); - TX_EOF_N <= data_out(data_out'high -3); - TX_REM <= data_out((RX_DATA'length + RX_REM'length-1) downto RX_DATA'length); - TX_DATA <= data_out(RX_DATA'range); - -end framelink; diff --git a/comp/base/misc/watchdog/watchdog_framelink_ent.vhd b/comp/base/misc/watchdog/watchdog_framelink_ent.vhd deleted file mode 100644 index efeffc6e8..000000000 --- a/comp/base/misc/watchdog/watchdog_framelink_ent.vhd +++ /dev/null @@ -1,68 +0,0 @@ --- watchdog_framelink_ent.vhd: watchdog FrameLink entity --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; -use WORK.math_pack.all; - -entity WATCHDOG_FRAMELINK is - generic( - --! width of the the data flow - DATA_WIDTH : positive := 32; - --! enable edge detection on signal KEEP_ALIVE - EDGE_DETECT : boolean := false; - --! maximum value of steps to the counter - COUNT : positive := 8; - --! width of the counter - COUNTER_WIDTH : positive := 32; - --! if TIMING is true, counter counts clock's periods, not data flowing - TIMING : boolean := false - ); - - port( - ----------------------------------------- - --- watchdog signals --- - ----------------------------------------- - CLK : in std_logic; - RESET : in std_logic; - - --! counter keep counting - KEEP_ALIVE : in std_logic; - --! contains exact status of internal counter - COUNTER : out std_logic_vector(COUNTER_WIDTH-1 downto 0); - --! if watchdog releases data or if it is locked - LOCKED : out std_logic; - - ----------------------------------------- - --- FrameLink signals --- - ----------------------------------------- - - --! input interface - RX_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - RX_REM : in std_logic_vector(LOG2(DATA_WIDTH/8)-1 downto 0); - RX_SOF_N : in std_logic; - RX_EOF_N : in std_logic; - RX_SOP_N : in std_logic; - RX_EOP_N : in std_logic; - RX_SRC_RDY_IN : in std_logic; - RX_DST_RDY_IN : out std_logic; - - --! output interface - TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); - TX_REM : out std_logic_vector(LOG2(DATA_WIDTH/8)-1 downto 0); - TX_SOF_N : out std_logic; - TX_EOF_N : out std_logic; - TX_SOP_N : out std_logic; - TX_EOP_N : out std_logic; - TX_SRC_RDY_OUT : out std_logic; - TX_DST_RDY_OUT : in std_logic - ); -end; diff --git a/comp/base/misc/watchdog/watchdog_framelink_unaligned_arch.vhd b/comp/base/misc/watchdog/watchdog_framelink_unaligned_arch.vhd deleted file mode 100644 index 31f82153d..000000000 --- a/comp/base/misc/watchdog/watchdog_framelink_unaligned_arch.vhd +++ /dev/null @@ -1,64 +0,0 @@ --- watchdog_framelink_arch.vhd: watchdog FrameLink architecture --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; -use WORK.math_pack.all; - -architecture framelink of WATCHDOG_FRAMELINK_UNALIGNED is ---! DATA_WIDTH for watchdog must be recalculated -signal aux_data_width : std_logic_vector - ((DATA_WIDTH-1 + RX_SOP_POS'length + RX_EOP_POS'length +2) downto 0); - ---! input signal to DATA_IN -signal data_in : std_logic_vector(aux_data_width'range); ---! output signal form DATA_OUT -signal data_out : std_logic_vector(aux_data_width'range); - -begin - watch_comp: entity work.watchdog - generic map ( - DATA_WIDTH => aux_data_width'length, - EDGE_DETECT => EDGE_DETECT, - COUNT => COUNT, - COUNTER_WIDTH => COUNTER_WIDTH, - TIMING => TIMING - ) - port map( - CLK => CLK, - RESET => RESET, - - DATA_IN => data_in, - SRC_RDY_IN => RX_SRC_RDY, - DST_RDY_IN => RX_DST_RDY, - - DATA_OUT => data_out, - SRC_RDY_OUT => TX_SRC_RDY, - DST_RDY_OUT => TX_DST_RDY, - - KEEP_ALIVE => KEEP_ALIVE, - COUNTER => COUNTER, - LOCKED => LOCKED - ); - - --! composition of DATA_IN - data_in <= RX_EOP & RX_SOP & RX_EOP_POS & RX_SOP_POS & RX_DATA; - - --! decomposition of DATA_OUT - TX_EOP <= data_out(data_out'high); - TX_SOP <= data_out(data_out'high -1); - TX_EOP_POS <= data_out((data_out'high-2) downto - ((data_out'high-2) - (RX_EOP_POS'length-1))); - TX_SOP_POS <= data_out((RX_DATA'length + RX_SOP_POS'length -1) downto RX_DATA'length); - TX_DATA <= data_out(RX_DATA'range); - - -end framelink; diff --git a/comp/base/misc/watchdog/watchdog_framelink_unaligned_ent.vhd b/comp/base/misc/watchdog/watchdog_framelink_unaligned_ent.vhd deleted file mode 100644 index e3640a1a4..000000000 --- a/comp/base/misc/watchdog/watchdog_framelink_unaligned_ent.vhd +++ /dev/null @@ -1,65 +0,0 @@ --- watchdog_framelink_unaligned_ent.vhd: watchdog FrameLinkUnaligned entity --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; -use WORK.math_pack.all; - -entity WATCHDOG_FRAMELINK_UNALIGNED is - generic( - --! width of the the data flow - DATA_WIDTH : positive := 32; - --! enable edge detection on signal KEEP_ALIVE - EDGE_DETECT : boolean := false; - --! maximum value of steps to the counter - COUNT : positive := 8; - --! width of the counter - COUNTER_WIDTH : positive := 32; - --! if TIMING is true, counter counts clock's periods, not data flowing - TIMING : boolean := false - ); - port( - ----------------------------------------- - --- watchdog signals --- - ----------------------------------------- - CLK : in std_logic; - RESET : in std_logic; - - --! counter keep counting - KEEP_ALIVE : in std_logic; - --! contains exact status of internal counter - COUNTER : out std_logic_vector(COUNTER_WIDTH-1 downto 0); - --! if watchdog releases data or if it is locked - LOCKED : out std_logic; - - ----------------------------------------- - --- FrameLinkUnaligned signals --- - ----------------------------------------- - - --! input interface - RX_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - RX_SOP_POS : in std_logic_vector(LOG2(DATA_WIDTH/8)-1 downto 0); - RX_EOP_POS : in std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0); - RX_SOP : in std_logic; - RX_EOP : in std_logic; - RX_SRC_RDY : in std_logic; - RX_DST_RDY : out std_logic; - - --! output interface - TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); - TX_SOP_POS : out std_logic_vector(LOG2(DATA_WIDTH/8)-1 downto 0); - TX_EOP_POS : out std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0); - TX_SOP : out std_logic; - TX_EOP : out std_logic; - TX_SRC_RDY : out std_logic; - TX_DST_RDY : in std_logic - ); -end; diff --git a/comp/base/misc/watchdog/watchdog_mi32_arch.vhd b/comp/base/misc/watchdog/watchdog_mi32_arch.vhd deleted file mode 100644 index 447c86d77..000000000 --- a/comp/base/misc/watchdog/watchdog_mi32_arch.vhd +++ /dev/null @@ -1,84 +0,0 @@ --- watchdog_mi32_arch.vhd: watchdog m32 architecture --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; - -architecture mi32 of WATCHDOG_MI32 is ---! output signal of D-type flip-flop register -signal reg_keep_alive : std_logic; ---! enable write signal for keep_alive register -signal we : std_logic; ---! signal contains bits from the vectors locked and reg_keep_alive -signal read_0 : std_logic_vector(31 downto 0); ---! signal contains COUNTER bits -signal read_4 : std_logic_vector(31 downto 0); - -signal counter_mi32 : std_logic_vector(COUNTER'range); -signal locked_mi32 : std_logic; - -begin - watch_comp: entity work.watchdog - generic map ( - DATA_WIDTH => DATA_WIDTH, - EDGE_DETECT => EDGE_DETECT, - COUNT => COUNT, - COUNTER_WIDTH => COUNTER_WIDTH, - TIMING => TIMING - ) - port map( - CLK => CLK, - RESET => RESET, - - DATA_IN => DATA_IN, - SRC_RDY_IN => SRC_RDY_IN, - DST_RDY_IN => DST_RDY_IN, - - DATA_OUT => DATA_OUT, - SRC_RDY_OUT => SRC_RDY_OUT, - DST_RDY_OUT => DST_RDY_OUT, - KEEP_ALIVE => reg_keep_alive, - COUNTER => counter_mi32, - LOCKED => locked_mi32 - ); - - LOCKED <= locked_mi32; - COUNTER <= counter_mi32; - -------------------------- - --! Read section - -------------------------- - ARDY <= '1'; - DRDY <= RD; - - read_0 <= (31 downto 2 => '0') & locked_mi32 & reg_keep_alive; - read_4 <= (31 downto counter_mi32'length => '0') & counter_mi32; - - with ADDR(2) select - DRD <= read_0 when '1', - read_4 when '0', - (DRD'range => '0') when others; - - -------------------------- - --! Write section - -------------------------- - - we <= WR and BE(0) and ADDR(2); - - reg_d_keep_alive : process(CLK) - begin - if (CLK'event) and (CLK='1') then - if we = '1' then - reg_keep_alive <= DWR(0); - end if; - end if; - end process; - -end mi32; diff --git a/comp/base/misc/watchdog/watchdog_mi32_ent.vhd b/comp/base/misc/watchdog/watchdog_mi32_ent.vhd deleted file mode 100644 index fc6818e73..000000000 --- a/comp/base/misc/watchdog/watchdog_mi32_ent.vhd +++ /dev/null @@ -1,69 +0,0 @@ --- watchdog_mi32_ent.vhd: watchdog m32 entity --- Copyright (C) 2015 CESNET --- Author(s): Adam Piecek --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - - -library IEEE; -use IEEE.std_logic_1164.all; - -entity WATCHDOG_MI32 is - generic( - --! width of the data flow - DATA_WIDTH : positive := 10; - --! enable edge detection on signal KEEP_ALIVE - EDGE_DETECT : boolean := false; - --! maximum value of steps to the counter - COUNT : positive := 8; - --! width of the counter - COUNTER_WIDTH : positive := 32; - --! if TIMING is true, counter counts clock's periods, not data flowing - TIMING : boolean := false - ); - - port( - ----------------------------------------- - --- watchdog signals --- - ----------------------------------------- - CLK : in std_logic; - RESET : in std_logic; - - --! data flow - DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0); - --! source is ready to send data - SRC_RDY_IN : in std_logic; - --! watchdog is ready to receive data - DST_RDY_IN : out std_logic; - - --! data flow - DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0); - --! watchdog is ready to send data - SRC_RDY_OUT : out std_logic; - --! destination is ready to receive data - DST_RDY_OUT : in std_logic; - - --! contains exact status of internal counter - COUNTER : out std_logic_vector(COUNTER_WIDTH-1 downto 0); - --! if watchdog releases data or if it is locked - LOCKED : out std_logic; - - ----------------------------------------- - --- mi32 signals --- - ----------------------------------------- - DWR : in std_logic_vector(31 downto 0); -- Input Data - ADDR : in std_logic_vector(31 downto 0); -- Address - RD : in std_logic; -- Read Request - WR : in std_logic; -- Write Request - BE : in std_logic_vector(3 downto 0); -- Byte Enable - DRD : out std_logic_vector(31 downto 0); -- Output Data - ARDY : out std_logic; -- Address Ready - DRDY : out std_logic -- Data Ready - ); - -end WATCHDOG_MI32; diff --git a/comp/ctrls/led/Modules.tcl b/comp/ctrls/led/Modules.tcl deleted file mode 100644 index 245469c96..000000000 --- a/comp/ctrls/led/Modules.tcl +++ /dev/null @@ -1,9 +0,0 @@ -# Modules.tcl: Local include Leonardo tcl script -# Copyright (C) 2016 CESNET -# Author: Juraj Kubiš -# -# SPDX-License-Identifier: BSD-3-Clause - -set MOD "$MOD $ENTITY_BASE/clk_div.vhd" -set MOD "$MOD $ENTITY_BASE/led_ctrl.vhd" -set MOD "$MOD $ENTITY_BASE/led_ctrl_top.vhd" diff --git a/comp/ctrls/led/clk_div.vhd b/comp/ctrls/led/clk_div.vhd deleted file mode 100644 index f43706cf5..000000000 --- a/comp/ctrls/led/clk_div.vhd +++ /dev/null @@ -1,78 +0,0 @@ --- clk_div.vhd: Frequency divider --- Copyright (C) 2016 CESNET --- Author(s): Juraj Kubis --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; - --- ---------------------------------------------------------------------------- --- entity declaration --- ---------------------------------------------------------------------------- -entity clk_div is - generic ( - --! Clk period in ns - CLK_PERIOD : integer; - --! Blink period in ms - PTRN_STEP_PERIOD : integer - ); - - port ( - --! Input clock signal - CLK : in std_logic; - --! Global synchronous reset - RESET : in std_logic; - - --! One-stroke signal with PTRN_STEP_PERIOD - STATE_CHANGE : out std_logic; - --! High frequency signal for yellow color - PWM_YELLOW_SYNC : out std_logic - ); - -end entity clk_div; - --- ---------------------------------------------------------------------------- --- architecture declaration --- ---------------------------------------------------------------------------- -architecture clk_div_arch of clk_div is - constant INTERVAL : integer := (PTRN_STEP_PERIOD * 500000) / CLK_PERIOD - 1; - signal cnt_clock : std_logic_vector(31 downto 0) := (others => '0'); - signal cnt_pwm_sync : std_logic_vector(16 downto 0) := (others => '0'); - signal out_clk : std_logic; -begin - process (RESET, CLK) - begin - if (CLK'EVENT and CLK = '1') then - --! Synchronous reset - if (RESET = '1') then - out_clk <= '0'; - cnt_clock <= (others => '0'); - --! Clock dividers - else - if (cnt_clock = INTERVAL) then - out_clk <= '1'; - cnt_clock <= (others => '0'); - else - out_clk <= '0'; - cnt_clock <= cnt_clock + 1; - end if; - - if (cnt_pwm_sync(16) = '1') then - cnt_pwm_sync <= (others => '0'); - else - cnt_pwm_sync <= cnt_pwm_sync + 1; - end if; - end if; - end if; - end process; - - STATE_CHANGE <= out_clk; - PWM_YELLOW_SYNC <= cnt_pwm_sync(15); - -end architecture clk_div_arch; diff --git a/comp/ctrls/led/led_ctrl.vhd b/comp/ctrls/led/led_ctrl.vhd deleted file mode 100644 index 02058f958..000000000 --- a/comp/ctrls/led/led_ctrl.vhd +++ /dev/null @@ -1,97 +0,0 @@ --- led_ctrl.vhd: LED controler --- Copyright (C) 2016 CESNET --- Author(s): Juraj Kubis --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; - --- ---------------------------------------------------------------------------- --- entity declaration --- ---------------------------------------------------------------------------- -entity led_ctrl is - generic ( - --! LED active value ('0' or '1') - ON_VALUE : std_logic; - --! Pattern length - PTRN_LENGTH : integer - ); - - port ( - --! Clock signal - CLK : in std_logic; - --! Global synchronous reset - RESET : in std_logic; - - --! Enable the change of state - STATE_CHANGE : in std_logic; - --! High frequency signal for generating yellow color - PWM_YELLOW_SYNC : in std_logic; - - --! Blink pattern - PTRN : in std_logic_vector(PTRN_LENGTH*2-1 downto 0); - - --! Green LED control - LED_GREEN : out std_logic; - --! Red LED control - LED_RED : out std_logic - ); - -end entity led_ctrl; - --- ---------------------------------------------------------------------------- --- architecture declaration --- ---------------------------------------------------------------------------- -architecture led_ctrl_arch of led_ctrl is - signal cnt_pattern_step : integer range 0 to PTRN_LENGTH-1 := 0; -begin - process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - --! No light - LED_RED <= not ON_VALUE; - LED_GREEN <= not ON_VALUE; - --! Reset step counter - cnt_pattern_step <= 0; - else - --! No light - if (PTRN(2*cnt_pattern_step+1 downto 2*cnt_pattern_step) = "11") then - LED_RED <= not ON_VALUE; - LED_GREEN <= not ON_VALUE; - - --! Red - elsif (PTRN(2*cnt_pattern_step+1 downto 2*cnt_pattern_step) = "10") then - LED_RED <= ON_VALUE; - LED_GREEN <= not ON_VALUE; - - --! Green - elsif (PTRN(2*cnt_pattern_step+1 downto 2*cnt_pattern_step) = "01") then - LED_RED <= not ON_VALUE; - LED_GREEN <= ON_VALUE; - - --! Yellow - elsif (PTRN(2*cnt_pattern_step+1 downto 2*cnt_pattern_step) = "00") then - LED_RED <= PWM_YELLOW_SYNC; - LED_GREEN <= not PWM_YELLOW_SYNC; - end if; - - --! Step counting - if (STATE_CHANGE = '1') then - if (cnt_pattern_step = PTRN_LENGTH-1) then - cnt_pattern_step <= 0; - else - cnt_pattern_step <= cnt_pattern_step + 1; - end if; - end if; - end if; - end if; - end process; - -end architecture led_ctrl_arch; diff --git a/comp/ctrls/led/led_ctrl_top.vhd b/comp/ctrls/led/led_ctrl_top.vhd deleted file mode 100644 index ca0127d33..000000000 --- a/comp/ctrls/led/led_ctrl_top.vhd +++ /dev/null @@ -1,92 +0,0 @@ --- led_ctrl_top.vhd: Generic multi LED controler --- Copyright (C) 2016 CESNET --- Author(s): Juraj Kubis --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; - --- ---------------------------------------------------------------------------- --- entity declaration --- ---------------------------------------------------------------------------- -entity led_ctrl_top is - generic ( - --! Number of LEDs - LED_COUNT : integer := 8; - --! LED active value ('0' or '1') - ON_VALUE : std_logic := '0'; - --! Clk period in ns - CLK_PERIOD : integer := 8; - --! Pattern step period in ms - PTRN_STEP_PERIOD : integer := 100; - --! Pattern length - PTRN_LENGTH : integer := 16 - ); - - port ( - --! Common clock - CLK : in std_logic; - --! Common reset for controlers and divider - RESET : in std_logic; - - --! Patterns for all LEDs - PTRNS : in std_logic_vector(LED_COUNT*PTRN_LENGTH*2-1 downto 0); - - --! Green LED control - LED_GREEN : out std_logic_vector(LED_COUNT - 1 downto 0); - --! Red LED control - LED_RED : out std_logic_vector(LED_COUNT - 1 downto 0) - ); - -end entity led_ctrl_top; - --- ---------------------------------------------------------------------------- --- architecture declaration --- ---------------------------------------------------------------------------- -architecture led_ctrl_top_arch of led_ctrl_top is - signal state_change, pwm_yellow_sync : std_logic; -begin - --! Clock frequency divider for blink states - clk_div_i: entity work.clk_div - generic map ( - CLK_PERIOD => CLK_PERIOD, - PTRN_STEP_PERIOD => PTRN_STEP_PERIOD - ) - - port map ( - CLK => CLK, - RESET => RESET, - - STATE_CHANGE => state_change, - PWM_YELLOW_SYNC => pwm_yellow_sync - ); - - --! LED controlers for each LED - led_ctrl_gen : for x in 0 to LED_COUNT - 1 generate - led_ctrl_i: entity work.led_ctrl - generic map ( - ON_VALUE => ON_VALUE, - PTRN_LENGTH => PTRN_LENGTH - ) - - port map ( - CLK => CLK, - RESET => RESET, - - STATE_CHANGE => state_change, - PWM_YELLOW_SYNC => pwm_yellow_sync, - - PTRN => PTRNS (2*(x+1)*PTRN_LENGTH-1 downto 2*x*PTRN_LENGTH), - - LED_GREEN => LED_GREEN(x), - LED_RED => LED_RED(x) - ); - end generate; - -end led_ctrl_top_arch; diff --git a/comp/ctrls/led/sim/led_ctrl_top.fdo b/comp/ctrls/led/sim/led_ctrl_top.fdo deleted file mode 100644 index 8a23507a6..000000000 --- a/comp/ctrls/led/sim/led_ctrl_top.fdo +++ /dev/null @@ -1,24 +0,0 @@ -# led_ctrl_top.fdo: Simulation script -# Copyright (C) 2016 CESNET -# Author: Juraj Kubiš -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# For whole design testing -set FIRMWARE_BASE "../../../.." -set TB_FILE "./testbench.vhd" -set SIG_FILE "led_ctrl_top_sig.fdo" - -# Modules definition -set COMPONENTS [list \ - [list "LED_CTRL_TOP" ".." "FULL"] \ - ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# File with signals -nb_sim_run 100ms diff --git a/comp/ctrls/led/sim/led_ctrl_top_sig.fdo b/comp/ctrls/led/sim/led_ctrl_top_sig.fdo deleted file mode 100644 index eebdf7d5f..000000000 --- a/comp/ctrls/led/sim/led_ctrl_top_sig.fdo +++ /dev/null @@ -1,17 +0,0 @@ -# led_ctrl_top_sig.fdo : Include file with signals -# Copyright (C) 2016 CESNET -# Author: Juraj Kubiš -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths -set LED_CTRL_TOP_PATH "/testbench" - -# include signals -source "signals.fdo" - -blk_LED_CTRL_TOP\{ \} - diff --git a/comp/ctrls/led/sim/signals.fdo b/comp/ctrls/led/sim/signals.fdo deleted file mode 100644 index c13164051..000000000 --- a/comp/ctrls/led/sim/signals.fdo +++ /dev/null @@ -1,35 +0,0 @@ -# signals.fdo: Include file with signals -# Copyright (C) 2016 CESNET -# Author: Juraj Kubiš -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -proc blk_LED_CTRL_TOP{ } { - - global LED_CTRL_TOP_PATH - - add wave -divider "SYNC" - add_wave "-noupdate -color green -label RESET" $LED_CTRL_TOP_PATH/RESET - add_wave "-noupdate -color green -label CLK" $LED_CTRL_TOP_PATH/CLK - - add wave -divider "pattern_0" - add_wave "-noupdate -color cyan -label PATTERN" $LED_CTRL_TOP_PATH/led/led_ctrl_gen(0)/led_ctrl_i/ptrn - add_wave "-noupdate -color yellow -label STEP" $LED_CTRL_TOP_PATH/led/led_ctrl_gen(0)/led_ctrl_i/cnt_pattern_step - add_wave "-noupdate -color green -label LED_GREEN" $LED_CTRL_TOP_PATH/led_green(0) - add_wave "-noupdate -color firebrick -label LED_RED" $LED_CTRL_TOP_PATH/led_red(0) - - add wave -divider "pattern_1" - add_wave "-noupdate -color cyan -label PATTERN" $LED_CTRL_TOP_PATH/led/led_ctrl_gen(1)/led_ctrl_i/ptrn - add_wave "-noupdate -color yellow -label STEP" $LED_CTRL_TOP_PATH/led/led_ctrl_gen(1)/led_ctrl_i/cnt_pattern_step - add_wave "-noupdate -color green -label LED_GREEN" $LED_CTRL_TOP_PATH/led_green(1) - add_wave "-noupdate -color firebrick -label LED_RED" $LED_CTRL_TOP_PATH/led_red(1) - - add wave -divider "pattern_2" - add_wave "-noupdate -color cyan -label PATTERN" $LED_CTRL_TOP_PATH/led/led_ctrl_gen(2)/led_ctrl_i/ptrn - add_wave "-noupdate -color yellow -label STEP" $LED_CTRL_TOP_PATH/led/led_ctrl_gen(2)/led_ctrl_i/cnt_pattern_step - add_wave "-noupdate -color green -label LED_GREEN" $LED_CTRL_TOP_PATH/led_green(2) - add_wave "-noupdate -color firebrick -label LED_RED" $LED_CTRL_TOP_PATH/led_red(2) -} diff --git a/comp/ctrls/led/sim/testbench.vhd b/comp/ctrls/led/sim/testbench.vhd deleted file mode 100644 index 454ab952b..000000000 --- a/comp/ctrls/led/sim/testbench.vhd +++ /dev/null @@ -1,102 +0,0 @@ - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -library unisim; -use unisim.VCOMPONENTS.all; - -entity testbench is -end testbench; - -architecture Behavioral of testbench is - -signal CLK : std_logic := '0'; -signal RESET : std_logic := '1'; -signal LED_GREEN, LED_RED : std_logic_vector(2 downto 0); - -constant ptrn_0 : std_logic_vector(15 downto 0) := "0001101100011011"; -constant ptrn_1 : std_logic_vector(15 downto 0) := "1100110011001100"; -constant ptrn_2 : std_logic_vector(15 downto 0) := "1111000110001111"; - -signal WR_CLK : std_logic; -signal RD_CLK : std_logic; - -signal WR_RESET : std_logic; -signal RD_RESET : std_logic; - -signal WR_ADDR : std_logic_vector(16-1 downto 0); -signal RD_ADDR : std_logic_vector(16-1 downto 0); - - -signal RX_MVB_DATA : std_logic_vector(64-1 downto 0); -signal RX_MVB_VLD : std_logic; --WR_EN - -signal RD_DATA : std_logic_vector(64-1 downto 0); -signal RD_EN : std_logic; - -signal RD_DATA_VLD : std_logic; - -begin - ram: RAMB36E1 - generic map ( - RAM_MODE => "SDP", - READ_WIDTH_A => 72 - ) - port map ( - --! Clock - CLKBWRCLK => WR_CLK, - CLKARDCLK => RD_CLK, - --! Reset - RSTRAMARSTRAM => WR_RESET, - -- => RD_RESET, - --! Address - ADDRBWRADDR => WR_ADDR, - ADDRARDADDR => RD_ADDR, - --! Input - DIADI => RX_MVB_DATA(31 downto 0), - DIBDI => RX_MVB_DATA(63 downto 32), - ENBWREN => RX_MVB_VLD, - --! Output - DOADO => RD_DATA(31 downto 0), - DOBDO => RD_DATA(63 downto 32), - ENARDEN => RD_EN, - --! Other - REGCEAREGCE => '1', - REGCEB => '1', - CASCADEINA => '0', - CASCADEINB => '0', - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RSTRAMB => '0', - RSTREGARSTREG => '0', - RSTREGB => '0', - DIPADIP => (others => 'X'), - DIPBDIP => (others => 'X'), - WEA => (others => '1'), - WEBWE => (others => '1') - ); - - led : entity work.led_ctrl_top - generic map ( - LED_COUNT => 3, - ON_VALUE => '0', - CLK_PERIOD => 10, - PTRN_STEP_PERIOD => 5, - PTRN_LENGTH => 8 - ) - - port map ( - CLK => CLK, - RESET => RESET, - - PTRNS => ptrn_2 & ptrn_1 & ptrn_0, - - LED_GREEN => LED_GREEN, - LED_RED => LED_RED - ); - - CLK <= not CLK after 10 ns; - RESET <= '0' after 10 ms; - -end Behavioral; diff --git a/comp/ctrls/led/synth/Makefile b/comp/ctrls/led/synth/Makefile deleted file mode 100644 index fce87d96e..000000000 --- a/comp/ctrls/led/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=LED_CTRL_TOP - -.PHONY: all -all: comp - -include ../../../../build/Makefile diff --git a/comp/dma/bus/asfifo/Modules.tcl b/comp/dma/bus/asfifo/Modules.tcl deleted file mode 100644 index ed147e437..000000000 --- a/comp/dma/bus/asfifo/Modules.tcl +++ /dev/null @@ -1,15 +0,0 @@ -# Modules.tcl: Modules.tcl script -# Copyright (C) 2014 CESNET -# Author(s): Jiri Matousek -# -# SPDX-License-Identifier: BSD-3-Clause - - -set ASFIFO_BASE "$OFM_PATH/comp/base/fifo/asfifo_bram_xilinx" - -set COMPONENTS [ list \ - [ list "ASFIFO" $ASFIFO_BASE "FULL" ] \ - ] - -set MOD "$MOD $ENTITY_BASE/asfifo_dma_bus_ent.vhd" -set MOD "$MOD $ENTITY_BASE/asfifo_dma_bus.vhd" diff --git a/comp/dma/bus/asfifo/asfifo_dma_bus.vhd b/comp/dma/bus/asfifo/asfifo_dma_bus.vhd deleted file mode 100644 index 88e5a958c..000000000 --- a/comp/dma/bus/asfifo/asfifo_dma_bus.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- asfifo_dma_bus.vhd : Architecture of asynchronous FIFO for DMA bus ---! ---! \file ---! \brief Architecture of asynchronous FIFO for DMA bus ---! \author Jiri Matousek ---! \date 2014 ---! ---! \section License ---! ---! Copyright (C) 2014 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- - -architecture full of asfifo_dma_bus is - - --! Constants declaration - -- ------------------------------------------------------------------------- - - constant INTERNAL_DATA_WIDTH : integer := DATA_WIDTH + HDR_WIDTH + 2; - - --! Signals declaration - -- ------------------------------------------------------------------------- - - --! write interface - signal wr_data : std_logic_vector(INTERNAL_DATA_WIDTH-1 downto 0); - signal wr_enable : std_logic; - signal full : std_logic; - signal afull_sig : std_logic; - signal full_sig : std_logic; - - --! read interface - signal rd_data : std_logic_vector(INTERNAL_DATA_WIDTH-1 downto 0); - signal rd_enable : std_logic; - signal empty : std_logic; - - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- - -begin - - --! aggregation of input port to write data signal - wr_data <= WR_DMA_EOP & WR_DMA_SOP & WR_DMA_HDR & WR_DMA_DATA; - - --! wite interface logic - wr_enable <= WR_DMA_SRC_RDY AND NOT full; - WR_DMA_DST_RDY <= NOT full; - --! select desired full signal along to generic - full <= afull_sig when USE_ALMOST_FULL = true else full_sig; - - --! DMA asynchronous FIFO for downstream - asfifo_dma_bus_i : entity work.ASFIFO_BRAM_XILINX - generic map ( - DEVICE => DEVICE, - DATA_WIDTH => INTERNAL_DATA_WIDTH, - ITEMS => ITEMS, - FIRST_WORD_FALL_THROUGH => true, - DO_REG => true, - ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, - PRECISE_FULL => false, - FAST_EMPTY => FAST_EMPTY, - FAST_EMPTY_DEPTH => FAST_EMPTY_DEPTH - ) - port map ( - --! Write interface - CLK_WR => WR_CLK, - RST_WR => WR_RESET, - DI => wr_data, - WR => wr_enable, - AFULL => afull_sig, - FULL => full_sig, - - --! Read interface - CLK_RD => RD_CLK, - RST_RD => RD_RESET, - DO => rd_data, - RD => rd_enable, - AEMPTY => open, - EMPTY => empty - ); - - --! de-aggregation of read data signal to output ports - RD_DMA_DATA <= rd_data(DATA_WIDTH-1 downto 0); - RD_DMA_HDR <= rd_data(INTERNAL_DATA_WIDTH-3 downto DATA_WIDTH); - RD_DMA_SOP <= rd_data(INTERNAL_DATA_WIDTH-2); - RD_DMA_EOP <= rd_data(INTERNAL_DATA_WIDTH-1); - - --! read interface logic - rd_enable <= RD_DMA_DST_RDY AND NOT empty; - RD_DMA_SRC_RDY <= NOT empty; - -end architecture full; diff --git a/comp/dma/bus/asfifo/asfifo_dma_bus_ent.vhd b/comp/dma/bus/asfifo/asfifo_dma_bus_ent.vhd deleted file mode 100644 index 830b0f067..000000000 --- a/comp/dma/bus/asfifo/asfifo_dma_bus_ent.vhd +++ /dev/null @@ -1,85 +0,0 @@ --- asfifo_dma_bus_ent.vhd : Entity of asynchronous FIFO for DMA bus ---! ---! \file ---! \brief Entity of asynchronous FIFO for DMA bus ---! \author Jiri Matousek ---! \date 2014 ---! ---! \section License ---! ---! Copyright (C) 2014 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity asfifo_dma_bus is -generic ( - --! \brief Width of DMA data - DATA_WIDTH : integer := 512; - --! \brief Width of DMA header - HDR_WIDTH : integer := 96; - --! \brief Use almost-full signal insted of full for DST_RDY - USE_ALMOST_FULL: boolean := false; - --! \brief Generic almost-full threshold. Valid range is 4-504 for Virtex 7 - ALMOST_FULL_OFFSET : integer := 4; - - ITEMS : integer := 512; - - FAST_EMPTY : boolean := true; - - FAST_EMPTY_DEPTH : integer := 2; - - DEVICE : string := "7SERIES" -); -port ( - --! \name Write interface - -- ------------------------------------------------------------------------- - --! \brief Write clock - WR_CLK : in std_logic; - --! \brief Write reset - WR_RESET : in std_logic; - --! \brief DMA transaction data - WR_DMA_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - --! \brief DMA transaction header - --! \details Valid when WR_DMA_SOP is valid. - WR_DMA_HDR : in std_logic_vector(HDR_WIDTH-1 downto 0); - --! \brief Start of DMA transaction - --! \details Valid when WR_DMA_SRC_RDY = WR_DMA_DST_RDY = '1'. - WR_DMA_SOP : in std_logic; - --! \brief End of DMA transaction - --! \details Valid when WR_DMA_SRC_RDY = WR_DMA_DST_RDY = '1'. - WR_DMA_EOP : in std_logic; - --! \brief Source is ready to transmit DMA data - WR_DMA_SRC_RDY : in std_logic; - --! \brief Destination is ready to receive DMA data - WR_DMA_DST_RDY : out std_logic; - - --! \name Read interface - -- ------------------------------------------------------------------------- - --! \brief Read clock - RD_CLK : in std_logic; - --! \brief Read reset - RD_RESET : in std_logic; - --! \brief DMA transaction data - RD_DMA_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); - --! \brief DMA transaction header - --! \details Valid when RD_DMA_SOP is valid. - RD_DMA_HDR : out std_logic_vector(HDR_WIDTH-1 downto 0); - --! \brief Start of DMA transaction - --! \details Valid when RD_DMA_SRC_RDY = RD_DMA_DST_RDY = '1'. - RD_DMA_SOP : out std_logic; - --! \brief End of DMA transaction - --! \details Valid when RD_DMA_SRC_RDY = RD_DMA_DST_RDY = '1'. - RD_DMA_EOP : out std_logic; - --! \brief Source is ready to transmit DMA data - RD_DMA_SRC_RDY : out std_logic; - --! \brief Destination is ready to receive DMA data - RD_DMA_DST_RDY : in std_logic -); -end entity asfifo_dma_bus; diff --git a/comp/dma/bus/asfifo/sim/signals.fdo b/comp/dma/bus/asfifo/sim/signals.fdo deleted file mode 100644 index 202c039f2..000000000 --- a/comp/dma/bus/asfifo/sim/signals.fdo +++ /dev/null @@ -1,36 +0,0 @@ -# signals.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Author: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -proc write_part {NAME PATH} { - add wave -divider "$NAME" - add_wave "-noupdate -label WR_CLK" $PATH/wr_clk - add_wave "-noupdate -label WR_RESET" $PATH/wr_rst - add_wave "-noupdate -dec -label WR_DMA_DATA" $PATH/wr_dma_data - add_wave "-noupdate -dec -label WR_DMA_HDR" $PATH/wr_dma_hdr - add_wave "-noupdate -label WR_DMA_SOP" $PATH/wr_dma_sop - add_wave "-noupdate -label WR_DMA_EOP" $PATH/wr_dma_eop - add_wave "-noupdate -label WR_DMA_SRC_RDY" $PATH/wr_dma_src_rdy - add_wave "-noupdate -label WR_DMA_DST_RDY" $PATH/wr_dma_dst_rdy -} - -proc read_part {NAME PATH} { - add wave -divider "$NAME" - add_wave "-noupdate -label RD_CLK" $PATH/rd_clk - add_wave "-noupdate -label RD_RESET" $PATH/rd_rst - add_wave "-noupdate -dec -label RD_DMA_DATA" $PATH/rd_dma_data - add_wave "-noupdate -dec -label RD_DMA_HDR" $PATH/rd_dma_hdr - add_wave "-noupdate -label RD_DMA_SOP" $PATH/rd_dma_sop - add_wave "-noupdate -label RD_DMA_EOP" $PATH/rd_dma_eop - add_wave "-noupdate -label RD_DMA_SRC_RDY" $PATH/rd_dma_src_rdy - add_wave "-noupdate -label RD_DMA_DST_RDY" $PATH/rd_dma_dst_rdy -} - -proc internal {NAME PATH} { - add wave -divider "$NAME" - -} diff --git a/comp/dma/bus/asfifo/sim/signals_sig.fdo b/comp/dma/bus/asfifo/sim/signals_sig.fdo deleted file mode 100644 index cf6f41117..000000000 --- a/comp/dma/bus/asfifo/sim/signals_sig.fdo +++ /dev/null @@ -1,15 +0,0 @@ -# signals_sig.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Authors: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -source "./signals.fdo" - -write_part "Write part" /testbench/uut -read_part "Read part" /testbench/uut -internal "Internal signals" /testbench/uut - diff --git a/comp/dma/bus/asfifo/sim/top_level.fdo b/comp/dma/bus/asfifo/sim/top_level.fdo deleted file mode 100644 index 7b3da2b27..000000000 --- a/comp/dma/bus/asfifo/sim/top_level.fdo +++ /dev/null @@ -1,26 +0,0 @@ -# top_level.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Authors: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -set FIRMWARE_BASE "../../../../.." -set COMP_BASE "$FIRMWARE_BASE/comp" - -set TB_FILE "top_level_tb.vhd" -set SIG_FILE "signals_sig.fdo" - -set COMPONENTS [list [list "asfifo_dma_bus" ".." "FULL"] ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 500ns diff --git a/comp/dma/bus/asfifo/sim/top_level_tb.vhd b/comp/dma/bus/asfifo/sim/top_level_tb.vhd deleted file mode 100644 index ee7836805..000000000 --- a/comp/dma/bus/asfifo/sim/top_level_tb.vhd +++ /dev/null @@ -1,234 +0,0 @@ --- testbench.vhd: Testbench --- Copyright (C) 2014 CESNET --- Author(s): Jakub Cabal --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_textio.all; -use ieee.numeric_std.all; -use std.textio.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity testbench is -end entity testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture behavioral of testbench is - - constant DATA_WIDTH : integer := 512; - constant HDR_WIDTH : integer := 96; - constant clkper_rd : time := 4 ns; - constant clkper_wr : time := 7 ns; - - signal wr_clk : std_logic; - signal wr_rst : std_logic; - signal wr_dma_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal wr_dma_hdr : std_logic_vector(HDR_WIDTH - 1 downto 0); - signal wr_dma_sop : std_logic; - signal wr_dma_eop : std_logic; - signal wr_dma_src_rdy : std_logic; - signal wr_dma_dst_rdy : std_logic; - - signal rd_clk : std_logic; - signal rd_rst : std_logic; - signal rd_dma_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal rd_dma_hdr : std_logic_vector(HDR_WIDTH - 1 downto 0); - signal rd_dma_sop : std_logic; - signal rd_dma_eop : std_logic; - signal rd_dma_src_rdy : std_logic; - signal rd_dma_dst_rdy : std_logic; - - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- -begin - -uut : entity work.asfifo_dma_bus -generic map( - --! \brief Width of DMA data - DATA_WIDTH => DATA_WIDTH, - --! \brief Width of DMA header - HDR_WIDTH => HDR_WIDTH, - SAFE_RESET => true -) -port map( - -- Write interface - WR_CLK => wr_clk, - WR_RESET => wr_rst, - WR_DMA_DATA => wr_dma_data, - WR_DMA_HDR => wr_dma_hdr, - WR_DMA_SOP => wr_dma_sop, - WR_DMA_EOP => wr_dma_eop, - WR_DMA_SRC_RDY => wr_dma_src_rdy, - WR_DMA_DST_RDY => wr_dma_dst_rdy, - - -- Read interface - RD_CLK => rd_clk, - RD_RESET => rd_rst, - RD_DMA_DATA => rd_dma_data, - RD_DMA_HDR => rd_dma_hdr, - RD_DMA_SOP => rd_dma_sop, - RD_DMA_EOP => rd_dma_eop, - RD_DMA_SRC_RDY => rd_dma_src_rdy, - RD_DMA_DST_RDY => rd_dma_dst_rdy -); - --- ---------------------------------------------------- --- CLK clock generator - -clk_wr_p: process -begin - wr_clk <= '1'; - wait for clkper_wr/2; - wr_clk <= '0'; - wait for clkper_wr/2; -end process; - -clk_rd_p: process -begin - rd_clk <= '1'; - wait for clkper_rd/2; - rd_clk <= '0'; - wait for clkper_rd/2; -end process; - -rst_wr_p: process -begin - wr_rst <= '1'; - wait for 10*clkper_wr; - wait for 1 ns; - wr_rst <= '0'; - wait; -end process; - -rst_rd_p: process -begin - rd_rst <= '1'; - wait for 10*clkper_rd; - wait for 1 ns; - rd_rst <= '0'; - wait; -end process; --- ---------------------------------------------------------------------------- --- Main testbench process --- ---------------------------------------------------------------------------- -tb_rd : process -begin - - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - - for i in 1 to 10 loop - rd_dma_dst_rdy <= '1'; - wait until (rising_edge(rd_clk) AND rd_rst='0'); - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - end loop; - - wait for 77 ns; - - for i in 11 to 40 loop - rd_dma_dst_rdy <= '1'; - wait until (rising_edge(rd_clk) AND rd_rst='0'); - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - end loop; - - wait; - -end process; - -tb_wr : process -begin - wr_dma_data <= (others => '0'); - wr_dma_hdr <= (others => '0'); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '0'; - - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - - for i in 1 to 5 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 6 to 6 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 7 to 22 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 23 to 23 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 24 to 24 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 25 to 32 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 33 to 33 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - wr_dma_src_rdy <= '0'; - - wait; -end process; - --- ---------------------------------------------------------------------------- -end architecture behavioral; diff --git a/comp/dma/bus/asfifo/synth/Makefile b/comp/dma/bus/asfifo/synth/Makefile deleted file mode 100644 index 2aee9bccd..000000000 --- a/comp/dma/bus/asfifo/synth/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# Makefile: Makefile script to compile specified module -# Copyright (C) 2021 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=ASFIFO_DMA_BUS - -CLK_PORTS=WR_CLK RD_CLK -CLK_PERIOD=3 7.7 - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/dma/bus/asfifo_bram/Modules.tcl b/comp/dma/bus/asfifo_bram/Modules.tcl deleted file mode 100644 index d99d2b1b3..000000000 --- a/comp/dma/bus/asfifo_bram/Modules.tcl +++ /dev/null @@ -1,19 +0,0 @@ -# Modules.tcl: Modules.tcl script -# Copyright (C) 2014 CESNET -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - - -set MATH_PKG "$OFM_PATH/comp/base/pkg" - -set PACKAGES "$PACKAGES $MATH_PKG/math_pack.vhd" -set PACKAGES "$PACKAGES $MATH_PKG/type_pack.vhd" - -set ASFIFO_BASE "$OFM_PATH/comp/base/fifo/asfifo_bram" - -set COMPONENTS [ list \ - [ list "ASFIFO_BRAM" $ASFIFO_BASE "FULL" ] \ - ] - -set MOD "$MOD $ENTITY_BASE/dma_asfifo_bram.vhd" diff --git a/comp/dma/bus/asfifo_bram/dma_asfifo_bram.vhd b/comp/dma/bus/asfifo_bram/dma_asfifo_bram.vhd deleted file mode 100644 index f97eca120..000000000 --- a/comp/dma/bus/asfifo_bram/dma_asfifo_bram.vhd +++ /dev/null @@ -1,161 +0,0 @@ ---! dma_asfifo_bram.vhd : Entity of asynchronous FIFO for DMA bus ---! ---! \file ---! \brief Entity of asynchronous FIFO for DMA bus ---! \author Jakub Cabal ---! \date 2014 ---! ---! \section License ---! ---! Copyright (C) 2014 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -use work.math_pack.all; -use work.type_pack.all; - -entity DMA_ASFIFO_BRAM is -generic ( - --! \brief Width of DMA data - DATA_WIDTH : integer := 512; - --! \brief Width of DMA header - HDR_WIDTH : integer := 96; - --! \brief number of items - ITEMS : integer := 512; - -- additional status signal width (default must be 0, other option 1 to express status on log2(ITEMS+1) bits) - STATUS_ADD_WIDTH : integer := 0 -); -port ( - --! \name Write interface - --! ------------------------------------------------------------------------- - --! \brief Write clock - WR_CLK : in std_logic; - --! \brief Write reset - WR_RESET : in std_logic; - --! \brief DMA transaction data - WR_DMA_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - --! \brief DMA transaction header - --! \details Valid when WR_DMA_SOP is valid. - WR_DMA_HDR : in std_logic_vector(HDR_WIDTH-1 downto 0); - --! \brief Start of DMA transaction - --! \details Valid when WR_DMA_SRC_RDY = WR_DMA_DST_RDY = '1'. - WR_DMA_SOP : in std_logic; - --! \brief End of DMA transaction - --! \details Valid when WR_DMA_SRC_RDY = WR_DMA_DST_RDY = '1'. - WR_DMA_EOP : in std_logic; - --! \brief Source is ready to transmit DMA data - WR_DMA_SRC_RDY : in std_logic; - --! \brief Destination is ready to receive DMA data - WR_DMA_DST_RDY : out std_logic; - - --! \brief Status signal - WR_STATUS : out std_logic_vector(log2(ITEMS+STATUS_ADD_WIDTH)-1 downto 0); - - - --! \name Read interface - --! ------------------------------------------------------------------------- - --! \brief Read clock - RD_CLK : in std_logic; - --! \brief Read reset - RD_RESET : in std_logic; - --! \brief DMA transaction data - RD_DMA_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); - --! \brief DMA transaction header - --! \details Valid when RD_DMA_SOP is valid. - RD_DMA_HDR : out std_logic_vector(HDR_WIDTH-1 downto 0); - --! \brief Start of DMA transaction - --! \details Valid when RD_DMA_SRC_RDY = RD_DMA_DST_RDY = '1'. - RD_DMA_SOP : out std_logic; - --! \brief End of DMA transaction - --! \details Valid when RD_DMA_SRC_RDY = RD_DMA_DST_RDY = '1'. - RD_DMA_EOP : out std_logic; - --! \brief Source is ready to transmit DMA data - RD_DMA_SRC_RDY : out std_logic; - --! \brief Destination is ready to receive DMA data - RD_DMA_DST_RDY : in std_logic -); -end entity DMA_ASFIFO_BRAM; - ---! ---------------------------------------------------------------------------- ---! Architecture declaration ---! ---------------------------------------------------------------------------- - -architecture full of DMA_ASFIFO_BRAM is - - --! Constants declaration - --! ------------------------------------------------------------------------- - - constant INTERNAL_DATA_WIDTH : integer := DATA_WIDTH + HDR_WIDTH + 2; - - --! Signals declaration - --! ------------------------------------------------------------------------- - - --! write interface - signal wr_data : std_logic_vector(INTERNAL_DATA_WIDTH-1 downto 0); - signal wr_enable : std_logic; - signal full : std_logic; - - --! read interface - signal rd_data : std_logic_vector(INTERNAL_DATA_WIDTH-1 downto 0); - signal rd_enable : std_logic; - signal do_vd : std_logic; - ---! ---------------------------------------------------------------------------- ---! Architecture body ---! ---------------------------------------------------------------------------- - -begin - - --! aggregation of input port to write data signal - wr_data <= WR_DMA_EOP & WR_DMA_SOP & WR_DMA_HDR & WR_DMA_DATA; - - --! wite interface logic - wr_enable <= WR_DMA_SRC_RDY AND NOT full; - WR_DMA_DST_RDY <= NOT full; - - --! DMA asynchronous FIFO for downstream - asfifo_dma_bus_i : entity work.ASFIFO_BRAM - generic map ( - DATA_WIDTH => INTERNAL_DATA_WIDTH, - --! Item in memory needed, one item size is DATA_WIDTH - ITEMS => ITEMS, - AUTO_PIPELINE => true, - STATUS_WIDTH => log2(ITEMS+STATUS_ADD_WIDTH), - STATUS_ADD_WIDTH => STATUS_ADD_WIDTH - ) - port map ( - --! Write interface - CLK_WR => WR_CLK, - RST_WR => WR_RESET, - DI => wr_data, - WR => wr_enable, - STATUS => WR_STATUS, - FULL => full, - - --! Read interface - CLK_RD => RD_CLK, - RST_RD => RD_RESET, - DO => rd_data, - RD => rd_enable, - DO_DV => do_vd, - EMPTY => open - ); - - --! de-aggregation of read data signal to output ports - RD_DMA_DATA <= rd_data(DATA_WIDTH-1 downto 0); - RD_DMA_HDR <= rd_data(INTERNAL_DATA_WIDTH-3 downto DATA_WIDTH); - RD_DMA_SOP <= rd_data(INTERNAL_DATA_WIDTH-2); - RD_DMA_EOP <= rd_data(INTERNAL_DATA_WIDTH-1); - - --! read interface logic - rd_enable <= RD_DMA_DST_RDY AND do_vd; - RD_DMA_SRC_RDY <= do_vd; - -end architecture full; diff --git a/comp/dma/bus/asfifo_bram/sim/signals.fdo b/comp/dma/bus/asfifo_bram/sim/signals.fdo deleted file mode 100644 index 202c039f2..000000000 --- a/comp/dma/bus/asfifo_bram/sim/signals.fdo +++ /dev/null @@ -1,36 +0,0 @@ -# signals.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Author: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -proc write_part {NAME PATH} { - add wave -divider "$NAME" - add_wave "-noupdate -label WR_CLK" $PATH/wr_clk - add_wave "-noupdate -label WR_RESET" $PATH/wr_rst - add_wave "-noupdate -dec -label WR_DMA_DATA" $PATH/wr_dma_data - add_wave "-noupdate -dec -label WR_DMA_HDR" $PATH/wr_dma_hdr - add_wave "-noupdate -label WR_DMA_SOP" $PATH/wr_dma_sop - add_wave "-noupdate -label WR_DMA_EOP" $PATH/wr_dma_eop - add_wave "-noupdate -label WR_DMA_SRC_RDY" $PATH/wr_dma_src_rdy - add_wave "-noupdate -label WR_DMA_DST_RDY" $PATH/wr_dma_dst_rdy -} - -proc read_part {NAME PATH} { - add wave -divider "$NAME" - add_wave "-noupdate -label RD_CLK" $PATH/rd_clk - add_wave "-noupdate -label RD_RESET" $PATH/rd_rst - add_wave "-noupdate -dec -label RD_DMA_DATA" $PATH/rd_dma_data - add_wave "-noupdate -dec -label RD_DMA_HDR" $PATH/rd_dma_hdr - add_wave "-noupdate -label RD_DMA_SOP" $PATH/rd_dma_sop - add_wave "-noupdate -label RD_DMA_EOP" $PATH/rd_dma_eop - add_wave "-noupdate -label RD_DMA_SRC_RDY" $PATH/rd_dma_src_rdy - add_wave "-noupdate -label RD_DMA_DST_RDY" $PATH/rd_dma_dst_rdy -} - -proc internal {NAME PATH} { - add wave -divider "$NAME" - -} diff --git a/comp/dma/bus/asfifo_bram/sim/signals_sig.fdo b/comp/dma/bus/asfifo_bram/sim/signals_sig.fdo deleted file mode 100644 index cf6f41117..000000000 --- a/comp/dma/bus/asfifo_bram/sim/signals_sig.fdo +++ /dev/null @@ -1,15 +0,0 @@ -# signals_sig.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Authors: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -source "./signals.fdo" - -write_part "Write part" /testbench/uut -read_part "Read part" /testbench/uut -internal "Internal signals" /testbench/uut - diff --git a/comp/dma/bus/asfifo_bram/sim/top_level.fdo b/comp/dma/bus/asfifo_bram/sim/top_level.fdo deleted file mode 100644 index eae71b073..000000000 --- a/comp/dma/bus/asfifo_bram/sim/top_level.fdo +++ /dev/null @@ -1,26 +0,0 @@ -# top_level.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Authors: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -set FIRMWARE_BASE "../../../../.." -set COMP_BASE "$FIRMWARE_BASE/comp" - -set TB_FILE "top_level_tb.vhd" -set SIG_FILE "signals_sig.fdo" - -set COMPONENTS [list [list "DMA_ASFIFO_BRAM" ".." "FULL"] ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 500ns diff --git a/comp/dma/bus/asfifo_bram/sim/top_level_tb.vhd b/comp/dma/bus/asfifo_bram/sim/top_level_tb.vhd deleted file mode 100644 index 03d4452f3..000000000 --- a/comp/dma/bus/asfifo_bram/sim/top_level_tb.vhd +++ /dev/null @@ -1,233 +0,0 @@ --- testbench.vhd: Testbench --- Copyright (C) 2014 CESNET --- Author(s): Jakub Cabal --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_textio.all; -use ieee.numeric_std.all; -use std.textio.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity testbench is -end entity testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture behavioral of testbench is - - constant DATA_WIDTH : integer := 512; - constant HDR_WIDTH : integer := 96; - constant clkper_rd : time := 4 ns; - constant clkper_wr : time := 7 ns; - - signal wr_clk : std_logic; - signal wr_rst : std_logic; - signal wr_dma_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal wr_dma_hdr : std_logic_vector(HDR_WIDTH - 1 downto 0); - signal wr_dma_sop : std_logic; - signal wr_dma_eop : std_logic; - signal wr_dma_src_rdy : std_logic; - signal wr_dma_dst_rdy : std_logic; - - signal rd_clk : std_logic; - signal rd_rst : std_logic; - signal rd_dma_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal rd_dma_hdr : std_logic_vector(HDR_WIDTH - 1 downto 0); - signal rd_dma_sop : std_logic; - signal rd_dma_eop : std_logic; - signal rd_dma_src_rdy : std_logic; - signal rd_dma_dst_rdy : std_logic; - - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- -begin - -uut : entity work.dma_asfifo_bram -generic map( - --! \brief Width of DMA data - DATA_WIDTH => DATA_WIDTH, - --! \brief Width of DMA header - HDR_WIDTH => HDR_WIDTH -) -port map( - -- Write interface - WR_CLK => wr_clk, - WR_RESET => wr_rst, - WR_DMA_DATA => wr_dma_data, - WR_DMA_HDR => wr_dma_hdr, - WR_DMA_SOP => wr_dma_sop, - WR_DMA_EOP => wr_dma_eop, - WR_DMA_SRC_RDY => wr_dma_src_rdy, - WR_DMA_DST_RDY => wr_dma_dst_rdy, - - -- Read interface - RD_CLK => rd_clk, - RD_RESET => rd_rst, - RD_DMA_DATA => rd_dma_data, - RD_DMA_HDR => rd_dma_hdr, - RD_DMA_SOP => rd_dma_sop, - RD_DMA_EOP => rd_dma_eop, - RD_DMA_SRC_RDY => rd_dma_src_rdy, - RD_DMA_DST_RDY => rd_dma_dst_rdy -); - --- ---------------------------------------------------- --- CLK clock generator - -clk_wr_p: process -begin - wr_clk <= '1'; - wait for clkper_wr/2; - wr_clk <= '0'; - wait for clkper_wr/2; -end process; - -clk_rd_p: process -begin - rd_clk <= '1'; - wait for clkper_rd/2; - rd_clk <= '0'; - wait for clkper_rd/2; -end process; - -rst_wr_p: process -begin - wr_rst <= '1'; - wait for 10*clkper_wr; - wait for 1 ns; - wr_rst <= '0'; - wait; -end process; - -rst_rd_p: process -begin - rd_rst <= '1'; - wait for 10*clkper_rd; - wait for 1 ns; - rd_rst <= '0'; - wait; -end process; --- ---------------------------------------------------------------------------- --- Main testbench process --- ---------------------------------------------------------------------------- -tb_rd : process -begin - - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - - for i in 1 to 10 loop - rd_dma_dst_rdy <= '1'; - wait until (rising_edge(rd_clk) AND rd_rst='0'); - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - end loop; - - wait for 77 ns; - - for i in 11 to 40 loop - rd_dma_dst_rdy <= '1'; - wait until (rising_edge(rd_clk) AND rd_rst='0'); - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - end loop; - - wait; - -end process; - -tb_wr : process -begin - wr_dma_data <= (others => '0'); - wr_dma_hdr <= (others => '0'); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '0'; - - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - - for i in 1 to 5 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 6 to 6 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 7 to 22 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 23 to 23 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 24 to 24 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 25 to 32 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 33 to 33 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - wr_dma_src_rdy <= '0'; - - wait; -end process; - --- ---------------------------------------------------------------------------- -end architecture behavioral; diff --git a/comp/dma/bus/asfifo_bram/synth/Makefile b/comp/dma/bus/asfifo_bram/synth/Makefile deleted file mode 100644 index 46afe69df..000000000 --- a/comp/dma/bus/asfifo_bram/synth/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=DMA_ASFIFO_BRAM - -CLK_PORTS=WR_CLK RD_CLK -CLK_PERIOD=3 7.7 - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/dma/bus/asfifo_lut/Modules.tcl b/comp/dma/bus/asfifo_lut/Modules.tcl deleted file mode 100644 index 515ad80f5..000000000 --- a/comp/dma/bus/asfifo_lut/Modules.tcl +++ /dev/null @@ -1,14 +0,0 @@ -# Modules.tcl: Modules.tcl script -# Copyright (C) 2014 CESNET -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - - -set ASFIFO_BASE "$OFM_PATH/comp/base/fifo/asfifo" - -set COMPONENTS [ list \ - [ list "ASFIFO" $ASFIFO_BASE "FULL" ] \ - ] - -set MOD "$MOD $ENTITY_BASE/dma_asfifo_lut.vhd" diff --git a/comp/dma/bus/asfifo_lut/dma_asfifo_lut.vhd b/comp/dma/bus/asfifo_lut/dma_asfifo_lut.vhd deleted file mode 100644 index 420ba20e7..000000000 --- a/comp/dma/bus/asfifo_lut/dma_asfifo_lut.vhd +++ /dev/null @@ -1,148 +0,0 @@ ---! dma_asfifo_lut.vhd : Entity of asynchronous FIFO for DMA bus ---! ---! \file ---! \brief Entity of asynchronous FIFO for DMA bus ---! \author Jakub Cabal ---! \date 2014 ---! ---! \section License ---! ---! Copyright (C) 2014 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity DMA_ASFIFO_LUT is -generic ( - --! \brief Width of DMA data - DATA_WIDTH : integer := 512; - --! \brief Width of DMA header - HDR_WIDTH : integer := 96 -); -port ( - --! \name Write interface - --! ------------------------------------------------------------------------- - --! \brief Write clock - WR_CLK : in std_logic; - --! \brief Write reset - WR_RESET : in std_logic; - --! \brief DMA transaction data - WR_DMA_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - --! \brief DMA transaction header - --! \details Valid when WR_DMA_SOP is valid. - WR_DMA_HDR : in std_logic_vector(HDR_WIDTH-1 downto 0); - --! \brief Start of DMA transaction - --! \details Valid when WR_DMA_SRC_RDY = WR_DMA_DST_RDY = '1'. - WR_DMA_SOP : in std_logic; - --! \brief End of DMA transaction - --! \details Valid when WR_DMA_SRC_RDY = WR_DMA_DST_RDY = '1'. - WR_DMA_EOP : in std_logic; - --! \brief Source is ready to transmit DMA data - WR_DMA_SRC_RDY : in std_logic; - --! \brief Destination is ready to receive DMA data - WR_DMA_DST_RDY : out std_logic; - - --! \name Read interface - --! ------------------------------------------------------------------------- - --! \brief Read clock - RD_CLK : in std_logic; - --! \brief Read reset - RD_RESET : in std_logic; - --! \brief DMA transaction data - RD_DMA_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); - --! \brief DMA transaction header - --! \details Valid when RD_DMA_SOP is valid. - RD_DMA_HDR : out std_logic_vector(HDR_WIDTH-1 downto 0); - --! \brief Start of DMA transaction - --! \details Valid when RD_DMA_SRC_RDY = RD_DMA_DST_RDY = '1'. - RD_DMA_SOP : out std_logic; - --! \brief End of DMA transaction - --! \details Valid when RD_DMA_SRC_RDY = RD_DMA_DST_RDY = '1'. - RD_DMA_EOP : out std_logic; - --! \brief Source is ready to transmit DMA data - RD_DMA_SRC_RDY : out std_logic; - --! \brief Destination is ready to receive DMA data - RD_DMA_DST_RDY : in std_logic -); -end entity DMA_ASFIFO_LUT; - ---! ---------------------------------------------------------------------------- ---! Architecture declaration ---! ---------------------------------------------------------------------------- - -architecture full of DMA_ASFIFO_LUT is - - --! Constants declaration - --! ------------------------------------------------------------------------- - - constant INTERNAL_DATA_WIDTH : integer := DATA_WIDTH + HDR_WIDTH + 2; - - --! Signals declaration - --! ------------------------------------------------------------------------- - - --! write interface - signal wr_data : std_logic_vector(INTERNAL_DATA_WIDTH-1 downto 0); - signal wr_enable : std_logic; - signal full : std_logic; - - --! read interface - signal rd_data : std_logic_vector(INTERNAL_DATA_WIDTH-1 downto 0); - signal rd_enable : std_logic; - signal empty : std_logic; - - ---! ---------------------------------------------------------------------------- ---! Architecture body ---! ---------------------------------------------------------------------------- - -begin - - --! aggregation of input port to write data signal - wr_data <= WR_DMA_EOP & WR_DMA_SOP & WR_DMA_HDR & WR_DMA_DATA; - - --! wite interface logic - wr_enable <= WR_DMA_SRC_RDY AND NOT full; - WR_DMA_DST_RDY <= NOT full; - - --! DMA asynchronous FIFO for downstream - asfifo_dma_bus_i : entity work.ASFIFO - generic map ( - DATA_WIDTH => INTERNAL_DATA_WIDTH, - --! Item in memory needed, one item size is DATA_WIDTH - ITEMS => 16, - STATUS_WIDTH => 1 - ) - port map ( - --! Write interface - CLK_WR => WR_CLK, - RST_WR => WR_RESET, - DI => wr_data, - WR => wr_enable, - STATUS => open, - FULL => full, - - --! Read interface - CLK_RD => RD_CLK, - RST_RD => RD_RESET, - DO => rd_data, - RD => rd_enable, - EMPTY => empty - ); - - --! de-aggregation of read data signal to output ports - RD_DMA_DATA <= rd_data(DATA_WIDTH-1 downto 0); - RD_DMA_HDR <= rd_data(INTERNAL_DATA_WIDTH-3 downto DATA_WIDTH); - RD_DMA_SOP <= rd_data(INTERNAL_DATA_WIDTH-2); - RD_DMA_EOP <= rd_data(INTERNAL_DATA_WIDTH-1); - - --! read interface logic - rd_enable <= RD_DMA_DST_RDY AND NOT empty; - RD_DMA_SRC_RDY <= NOT empty; - -end architecture full; diff --git a/comp/dma/bus/asfifo_lut/sim/signals.fdo b/comp/dma/bus/asfifo_lut/sim/signals.fdo deleted file mode 100644 index 202c039f2..000000000 --- a/comp/dma/bus/asfifo_lut/sim/signals.fdo +++ /dev/null @@ -1,36 +0,0 @@ -# signals.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Author: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -proc write_part {NAME PATH} { - add wave -divider "$NAME" - add_wave "-noupdate -label WR_CLK" $PATH/wr_clk - add_wave "-noupdate -label WR_RESET" $PATH/wr_rst - add_wave "-noupdate -dec -label WR_DMA_DATA" $PATH/wr_dma_data - add_wave "-noupdate -dec -label WR_DMA_HDR" $PATH/wr_dma_hdr - add_wave "-noupdate -label WR_DMA_SOP" $PATH/wr_dma_sop - add_wave "-noupdate -label WR_DMA_EOP" $PATH/wr_dma_eop - add_wave "-noupdate -label WR_DMA_SRC_RDY" $PATH/wr_dma_src_rdy - add_wave "-noupdate -label WR_DMA_DST_RDY" $PATH/wr_dma_dst_rdy -} - -proc read_part {NAME PATH} { - add wave -divider "$NAME" - add_wave "-noupdate -label RD_CLK" $PATH/rd_clk - add_wave "-noupdate -label RD_RESET" $PATH/rd_rst - add_wave "-noupdate -dec -label RD_DMA_DATA" $PATH/rd_dma_data - add_wave "-noupdate -dec -label RD_DMA_HDR" $PATH/rd_dma_hdr - add_wave "-noupdate -label RD_DMA_SOP" $PATH/rd_dma_sop - add_wave "-noupdate -label RD_DMA_EOP" $PATH/rd_dma_eop - add_wave "-noupdate -label RD_DMA_SRC_RDY" $PATH/rd_dma_src_rdy - add_wave "-noupdate -label RD_DMA_DST_RDY" $PATH/rd_dma_dst_rdy -} - -proc internal {NAME PATH} { - add wave -divider "$NAME" - -} diff --git a/comp/dma/bus/asfifo_lut/sim/signals_sig.fdo b/comp/dma/bus/asfifo_lut/sim/signals_sig.fdo deleted file mode 100644 index cf6f41117..000000000 --- a/comp/dma/bus/asfifo_lut/sim/signals_sig.fdo +++ /dev/null @@ -1,15 +0,0 @@ -# signals_sig.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Authors: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -source "./signals.fdo" - -write_part "Write part" /testbench/uut -read_part "Read part" /testbench/uut -internal "Internal signals" /testbench/uut - diff --git a/comp/dma/bus/asfifo_lut/sim/top_level.fdo b/comp/dma/bus/asfifo_lut/sim/top_level.fdo deleted file mode 100644 index f5af69786..000000000 --- a/comp/dma/bus/asfifo_lut/sim/top_level.fdo +++ /dev/null @@ -1,26 +0,0 @@ -# top_level.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Authors: Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -set FIRMWARE_BASE "../../../../.." -set COMP_BASE "$FIRMWARE_BASE/comp" - -set TB_FILE "top_level_tb.vhd" -set SIG_FILE "signals_sig.fdo" - -set COMPONENTS [list [list "DMA_ASFIFO_LUT" ".." "FULL"] ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 500ns diff --git a/comp/dma/bus/asfifo_lut/sim/top_level_tb.vhd b/comp/dma/bus/asfifo_lut/sim/top_level_tb.vhd deleted file mode 100644 index 2d458b442..000000000 --- a/comp/dma/bus/asfifo_lut/sim/top_level_tb.vhd +++ /dev/null @@ -1,233 +0,0 @@ --- testbench.vhd: Testbench --- Copyright (C) 2014 CESNET --- Author(s): Jakub Cabal --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_textio.all; -use ieee.numeric_std.all; -use std.textio.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity testbench is -end entity testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture behavioral of testbench is - - constant DATA_WIDTH : integer := 512; - constant HDR_WIDTH : integer := 96; - constant clkper_rd : time := 4 ns; - constant clkper_wr : time := 7 ns; - - signal wr_clk : std_logic; - signal wr_rst : std_logic; - signal wr_dma_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal wr_dma_hdr : std_logic_vector(HDR_WIDTH - 1 downto 0); - signal wr_dma_sop : std_logic; - signal wr_dma_eop : std_logic; - signal wr_dma_src_rdy : std_logic; - signal wr_dma_dst_rdy : std_logic; - - signal rd_clk : std_logic; - signal rd_rst : std_logic; - signal rd_dma_data : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal rd_dma_hdr : std_logic_vector(HDR_WIDTH - 1 downto 0); - signal rd_dma_sop : std_logic; - signal rd_dma_eop : std_logic; - signal rd_dma_src_rdy : std_logic; - signal rd_dma_dst_rdy : std_logic; - - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- -begin - -uut : entity work.dma_asfifo_lut -generic map( - --! \brief Width of DMA data - DATA_WIDTH => DATA_WIDTH, - --! \brief Width of DMA header - HDR_WIDTH => HDR_WIDTH -) -port map( - -- Write interface - WR_CLK => wr_clk, - WR_RESET => wr_rst, - WR_DMA_DATA => wr_dma_data, - WR_DMA_HDR => wr_dma_hdr, - WR_DMA_SOP => wr_dma_sop, - WR_DMA_EOP => wr_dma_eop, - WR_DMA_SRC_RDY => wr_dma_src_rdy, - WR_DMA_DST_RDY => wr_dma_dst_rdy, - - -- Read interface - RD_CLK => rd_clk, - RD_RESET => rd_rst, - RD_DMA_DATA => rd_dma_data, - RD_DMA_HDR => rd_dma_hdr, - RD_DMA_SOP => rd_dma_sop, - RD_DMA_EOP => rd_dma_eop, - RD_DMA_SRC_RDY => rd_dma_src_rdy, - RD_DMA_DST_RDY => rd_dma_dst_rdy -); - --- ---------------------------------------------------- --- CLK clock generator - -clk_wr_p: process -begin - wr_clk <= '1'; - wait for clkper_wr/2; - wr_clk <= '0'; - wait for clkper_wr/2; -end process; - -clk_rd_p: process -begin - rd_clk <= '1'; - wait for clkper_rd/2; - rd_clk <= '0'; - wait for clkper_rd/2; -end process; - -rst_wr_p: process -begin - wr_rst <= '1'; - wait for 10*clkper_wr; - wait for 1 ns; - wr_rst <= '0'; - wait; -end process; - -rst_rd_p: process -begin - rd_rst <= '1'; - wait for 10*clkper_rd; - wait for 1 ns; - rd_rst <= '0'; - wait; -end process; --- ---------------------------------------------------------------------------- --- Main testbench process --- ---------------------------------------------------------------------------- -tb_rd : process -begin - - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - - for i in 1 to 10 loop - rd_dma_dst_rdy <= '1'; - wait until (rising_edge(rd_clk) AND rd_rst='0'); - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - end loop; - - wait for 77 ns; - - for i in 11 to 40 loop - rd_dma_dst_rdy <= '1'; - wait until (rising_edge(rd_clk) AND rd_rst='0'); - rd_dma_dst_rdy <= '0'; - wait until (rising_edge(rd_clk) AND rd_rst='0' AND rd_dma_src_rdy='1'); - end loop; - - wait; - -end process; - -tb_wr : process -begin - wr_dma_data <= (others => '0'); - wr_dma_hdr <= (others => '0'); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '0'; - - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - - for i in 1 to 5 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 6 to 6 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 7 to 22 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 23 to 23 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 24 to 24 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '1'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 25 to 32 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '0'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - for i in 33 to 33 loop - wr_dma_data <= conv_std_logic_vector(i, wr_dma_data'length); - wr_dma_hdr <= conv_std_logic_vector(i, wr_dma_hdr'length); - wr_dma_sop <= '0'; - wr_dma_eop <= '1'; - wr_dma_src_rdy <= '1'; - wait until (rising_edge(wr_clk) AND wr_rst='0' AND wr_dma_dst_rdy='1'); - end loop; - - wr_dma_src_rdy <= '0'; - - wait; -end process; - --- ---------------------------------------------------------------------------- -end architecture behavioral; diff --git a/comp/dma/bus/asfifo_lut/synth/Makefile b/comp/dma/bus/asfifo_lut/synth/Makefile deleted file mode 100644 index a4dedf7d7..000000000 --- a/comp/dma/bus/asfifo_lut/synth/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=DMA_ASFIFO_LUT - -CLK_PORTS=WR_CLK RD_CLK -CLK_PERIOD=3 7.7 - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/proc/packet_stats/Modules.tcl b/comp/proc/packet_stats/Modules.tcl deleted file mode 100644 index b2354c431..000000000 --- a/comp/proc/packet_stats/Modules.tcl +++ /dev/null @@ -1,21 +0,0 @@ -# Modules.tcl: Local include tcl script -# Copyright (C) 2016 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause - -set BRAM "$OFM_PATH/comp/base/mem/dp_bmem_V7" - -set COMPONENTS [ list \ - [ list "DP_BRAM_V7" $BRAM "FULL" ] \ - ] - -set PACKAGES "$PACKAGES $OFM_PATH/comp/base/pkg/math_pack.vhd" - -set MOD "$MOD $ENTITY_BASE/comp/alu_stats.vhd" -set MOD "$MOD $ENTITY_BASE/comp/cnt_stats.vhd" -set MOD "$MOD $ENTITY_BASE/comp/mem_stats.vhd" -set MOD "$MOD $ENTITY_BASE/comp/stats.vhd" -set MOD "$MOD $ENTITY_BASE/comp/trans.vhd" -set MOD "$MOD $ENTITY_BASE/pac_stats_top_ent.vhd" -set MOD "$MOD $ENTITY_BASE/pac_stats_top_arch.vhd" diff --git a/comp/proc/packet_stats/comp/alu_stats.vhd b/comp/proc/packet_stats/comp/alu_stats.vhd deleted file mode 100644 index 813060efc..000000000 --- a/comp/proc/packet_stats/comp/alu_stats.vhd +++ /dev/null @@ -1,203 +0,0 @@ ---! \Author: Mario Kuka ---! \date 2016 ---! ---! \section License ---! ---! Copyright (C) 2016 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; -Library UNISIM; -use UNISIM.vcomponents.all; - ---! \brief DSP slice ALU entity -entity ALU_STATS is - generic ( - EN_DSP : boolean := true; - --! Width max 48 bits - A_WIDTH : integer := 48; - B_WIDTH : integer := 16; - P_WIDTH : integer := 48; - REG_OUT : integer := 0 - ); - port ( - --! Clock input - CLK : in std_logic; - --! Reset input - RESET : in std_logic; - --! Enable adder - EN_ADD : in std_logic; - --! Reset adder - RST_ADD : in std_logic; - --! Data input - A : in std_logic_vector(A_WIDTH-1 downto 0); - --! Data input - B : in std_logic_vector(B_WIDTH-1 downto 0); - --! Latency = 0 + REG_OUT - P : out std_logic_vector(P_WIDTH-1 downto 0) - ); -end entity; - ---! Vitrex-7 architecture of ALU48 -architecture FULL of ALU_STATS is - --! signals - signal zeros : std_logic_vector(63 downto 0); -begin - zeros <= X"0000000000000000"; - - gen_dps : if(EN_DSP = true) generate - signal in_a : std_logic_vector(47 downto 0); - signal in_b : std_logic_vector(47 downto 0); - signal out_p : std_logic_vector(47 downto 0); - signal en_B : std_logic; - signal en_A : std_logic; - signal opmode : std_logic_vector(6 downto 0); - begin - - in_a(A_WIDTH-1 downto 0) <= A; - in_a(47 downto A_WIDTH) <= (others => '0'); - in_b(B_WIDTH-1 downto 0) <= B; - in_b(47 downto B_WIDTH) <= (others => '0'); - P <= out_p(P_WIDTH-1 downto 0); - - -- enable B in - en_B <= '0' when RST_ADD = '1' else - '1' when EN_ADD = '1' else - '0'; - -- enable A in - en_A <= '0' when RST_ADD = '1' else - '1'; - - opmode <= '0' & en_A & en_A & "00" & en_B & en_B; - - --! DSP slice instantion - DSP48E1_inst : DSP48E1 - generic map ( - -- Feature Control Attributes: Data Path Selection - A_INPUT => "DIRECT",-- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) - B_INPUT => "DIRECT",-- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) - USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE) - USE_MULT => "NONE", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE") - -- Pattern Detector Attributes: Pattern Detection Configuration - AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" - MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore) - PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect - SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" - SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C") - USE_PATTERN_DETECT => "NO_PATDET",-- Enable pattern detect ("PATDET" or "NO_PATDET") - -- Register Control Attributes: Pipeline Register Configuration - ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2) - ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1) - ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1) - AREG => 0, -- Number of pipeline stages for A (0, 1 or 2) - BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2) - BREG => 0, -- Number of pipeline stages for B (0, 1 or 2) - CARRYINREG => 0, -- Number of pipeline stages for CARRYIN (0 or 1) - CARRYINSELREG => 0, -- Number of pipeline stages for CARRYINSEL (0 or 1) - CREG => 0, -- Number of pipeline stages for C (0 or 1) - DREG => 0, -- Number of pipeline stages for D (0 or 1) - INMODEREG => 0, -- Number of pipeline stages for INMODE (0 or 1) - MREG => 0, -- Number of multiplier pipeline stages (0 or 1) - OPMODEREG => 0, -- Number of pipeline stages for OPMODE (0 or 1) - PREG => REG_OUT, -- Number of pipeline stages for P (0 or 1) - USE_SIMD => "ONE48" -- SIMD selection ("ONE48", "TWO24", "FOUR12") - ) port map ( - -- Cascade: 30-bit (each) output: Cascade Ports - ACOUT => open, -- 30-bit output: A port cascade output - BCOUT => open, -- 18-bit output: B port cascade output - CARRYCASCOUT => open, -- 1-bit output: Cascade carry output - MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output - PCOUT => open, -- 48-bit output: Cascade output - -- Control: 1-bit (each) output: Control Inputs/Status Bits - OVERFLOW => open, -- 1-bit output: Overflow in add/acc output - PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output - PATTERNDETECT => open, -- 1-bit output: Pattern detect output - UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output - -- Data: 4-bit (each) output: Data Ports - CARRYOUT => open, -- 4-bit output: Carry output - P => out_p, -- 48-bit output: Primary data output - -- Cascade: 30-bit (each) input: Cascade Ports - ACIN => zeros(29 downto 0), -- 30-bit input: A cascade data input - BCIN => zeros(17 downto 0), -- 18-bit input: B cascade input - CARRYCASCIN => '0', -- 1-bit input: Cascade carry input - MULTSIGNIN => '1', -- 1-bit input: Multiplier sign input - PCIN => zeros(47 downto 0), -- 48-bit input: P cascade input - -- Control: 4-bit (each) input: Control Inputs/Status Bits - ALUMODE => "0000", -- 4-bit input: ALU control input (X XOR Z) - CARRYINSEL => (others => '0'),-- 3-bit input: Carry select input - CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG - CLK => CLK, -- 1-bit input: Clock input - INMODE => "00000", -- 5-bit input: INMODE control input - OPMODE => opmode, -- 7-bit input: Operation mode input - RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG - -- Data: 30-bit (each) input: Data Ports - A => in_b(47 downto 18), -- 30-bit input: A data input - B => in_b(17 downto 0), -- 18-bit input: B data input - C => in_a, -- 48-bit input: C data input - CARRYIN => '0', -- 1-bit input: Carry input signal - D => zeros(24 downto 0), -- 25-bit input: D data input - -- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs - CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG - CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG - CEAD => '1', -- 1-bit input: Clock enable input for ADREG - CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODERE - CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG - CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG - CEC => '1', -- 1-bit input: Clock enable input for CREG - CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG - CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG - CED => '1', -- 1-bit input: Clock enable input for DREG - CEM => '1', -- 1-bit input: Clock enable input for MREG - CEP => '1', -- 1-bit input: Clock enable input for PREG - RSTA => RESET, -- 1-bit input: Reset input for AREG - RSTALLCARRYIN => RESET,-- 1-bit input: Reset input for CARRYINREG - RSTALUMODE => RESET, -- 1-bit input: Reset input for ALUMODEREG - RSTB => RESET, -- 1-bit input: Reset input for BREG - RSTC => RESET, -- 1-bit input: Reset input for CREG - RSTCTRL => RESET, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG - RSTD => RESET, -- 1-bit input: Reset input for DREG and ADREG - RSTM => RESET, -- 1-bit input: Reset input for MREG - RSTP => RESET -- 1-bit input: Reset input for PREG - ); - end generate; - - - BEH_ALU : if(EN_DSP = false) generate - signal in_a : std_logic_vector(A'range); - signal in_b : std_logic_vector(B'range); - signal out_p : std_logic_vector(P'range); - begin - - in_b <= (others => '0') when RST_ADD = '1' else - B when EN_ADD = '1' else - (others => '0'); - - in_a <= (others => '0') when RST_ADD = '1' else - A; - - out_p <= in_a + in_b; - - GEN_REG_on : if(REG_OUT = 1) generate - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if (RESET = '1') then - P <= (others => '0'); - else - P <= out_p; - end if; - end if; - end process; - end generate; - - GEN_REG_off : if(REG_OUT = 0) generate - P <= out_p; - end generate; - - end generate; -end architecture; diff --git a/comp/proc/packet_stats/comp/cnt_stats.vhd b/comp/proc/packet_stats/comp/cnt_stats.vhd deleted file mode 100644 index d9e31ee5c..000000000 --- a/comp/proc/packet_stats/comp/cnt_stats.vhd +++ /dev/null @@ -1,80 +0,0 @@ ---! \Author: Mario Kuka ---! \date 2016 ---! ---! \section License ---! ---! Copyright (C) 2016 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; -Library UNISIM; -use UNISIM.vcomponents.all; - ---! \brief DSP slice ALU entity -entity CNT_STATS is - generic ( - EN_DSP : boolean := true; - NUM_BYTES_WD : integer := 48; - NUM_PACKETS_WD : integer := 48; - PACKET_LENGTH_WD : integer := 16; - REG_OUT : integer := 0 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - PACKET_LENGTH : in std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - ADD_PACKET : in std_logic; - RST_COUNTERS : in std_logic; - IN_NUM_BYTES : in std_logic_vector(NUM_BYTES_WD-1 downto 0); - IN_NUM_PACKETS : in std_logic_vector(NUM_PACKETS_WD-1 downto 0); - OUT_NUM_BYTES : out std_logic_vector(NUM_BYTES_WD-1 downto 0); - OUT_NUM_PACKETS : out std_logic_vector(NUM_PACKETS_WD-1 downto 0) - ); -end entity; - ---! Vitrex-7 architecture of ALU48 -architecture FULL of CNT_STATS is -begin - - FIRST_CNT_i : entity work.ALU_STATS - generic map ( - EN_DSP => EN_DSP, - A_WIDTH => NUM_BYTES_WD, - B_WIDTH => PACKET_LENGTH_WD, - P_WIDTH => NUM_BYTES_WD, - REG_OUT => REG_OUT - ) - port map ( - CLK => CLK, - RESET => RESET, - EN_ADD => ADD_PACKET, - RST_ADD => RST_COUNTERS, - A => IN_NUM_BYTES, - B => PACKET_LENGTH, - P => OUT_NUM_BYTES - ); - - SECOND_CNT_i : entity work.ALU_STATS - generic map ( - EN_DSP => EN_DSP, - A_WIDTH => NUM_PACKETS_WD, - B_WIDTH => 1, - P_WIDTH => NUM_PACKETS_WD, - REG_OUT => REG_OUT - ) - port map ( - CLK => CLK, - RESET => RESET, - EN_ADD => ADD_PACKET, - RST_ADD => RST_COUNTERS, - A => IN_NUM_PACKETS, - B => "1", - P => OUT_NUM_PACKETS - ); - -end architecture; diff --git a/comp/proc/packet_stats/comp/mem_stats.vhd b/comp/proc/packet_stats/comp/mem_stats.vhd deleted file mode 100644 index 0ce1e2a05..000000000 --- a/comp/proc/packet_stats/comp/mem_stats.vhd +++ /dev/null @@ -1,92 +0,0 @@ ---! \Author: Mario Kuka ---! \date 2016 ---! ---! \section License ---! ---! Copyright (C) 2016 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; -Library UNISIM; -use UNISIM.vcomponents.all; - ---! \brief DSP slice ALU entity -entity MEM_STATS is - generic ( - NUM_BYTES_WD : integer := 48; - NUM_PACKETS_WD : integer := 48; - ADDRESS_WIDTH : integer := 10 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - RD_NUM_BYTES : out std_logic_vector(NUM_BYTES_WD-1 downto 0); - RD_NUM_PACKETS : out std_logic_vector(NUM_PACKETS_WD-1 downto 0); - RD_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - WR_NUM_BYTES : in std_logic_vector(NUM_BYTES_WD-1 downto 0); - WR_NUM_PACKETS : in std_logic_vector(NUM_PACKETS_WD-1 downto 0); - WR_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0) - ); -end entity; - ---! Vitrex-7 architecture of ALU48 -architecture FULL of MEM_STATS is - constant bram_width : integer := NUM_BYTES_WD + NUM_PACKETS_WD; - signal bram_rd : std_logic_vector(bram_width-1 downto 0); - signal bram_wr : std_logic_vector(bram_width-1 downto 0); - signal pipe_bram_wr : std_logic_vector(bram_width-1 downto 0); - signal address_cmp : std_logic; - signal pipe_address_cmp : std_logic; -begin - - address_cmp <= '1' when WR_ADDRESS = RD_ADDRESS else - '0'; - - -- register mux pipe ------------------------------------------------------ - muxp: process(CLK) - begin - if (CLK'event AND CLK = '1') then - pipe_address_cmp <= address_cmp; - pipe_bram_wr <= bram_wr; - end if; - end process; - - RD_NUM_BYTES <= bram_rd(NUM_BYTES_WD-1 downto 0) when pipe_address_cmp = '0' else - pipe_bram_wr(NUM_BYTES_WD-1 downto 0); - RD_NUM_PACKETS <= bram_rd(NUM_PACKETS_WD + NUM_BYTES_WD-1 downto NUM_BYTES_WD) when pipe_address_cmp = '0' else - pipe_bram_wr(NUM_PACKETS_WD + NUM_BYTES_WD-1 downto NUM_BYTES_WD); - - bram_wr <= WR_NUM_PACKETS & WR_NUM_BYTES; - - BRAM_i : entity work.DP_BRAM_V7 - generic map ( - DATA_WIDTH => bram_width, - ADDRESS_WIDTH => ADDRESS_WIDTH - ) - port map ( - CLKA => CLK, - RSTA => RESET, - PIPE_ENA => '1', - REA => '1', - WEA => '0', - ADDRA => RD_ADDRESS, - DIA => (others => '0'), - DOA_DV => open, - DOA => bram_rd, - - CLKB => CLK, - RSTB => RESET, - PIPE_ENB => '1', - REB => '0', - WEB => '1', - ADDRB => WR_ADDRESS, - DIB => bram_wr, - DOB_DV => open, - DOB => open - ); -end architecture; diff --git a/comp/proc/packet_stats/comp/stats.vhd b/comp/proc/packet_stats/comp/stats.vhd deleted file mode 100644 index 7ba5147ba..000000000 --- a/comp/proc/packet_stats/comp/stats.vhd +++ /dev/null @@ -1,205 +0,0 @@ ---! \Author: Mario Kuka ---! \date 2016 ---! ---! \section License ---! ---! Copyright (C) 2016 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; -Library UNISIM; -use UNISIM.vcomponents.all; - ---! \brief DSP slice ALU entity -entity STATS is - generic ( - EN_DSP : boolean := true; - NUM_BYTES_WD : integer := 48; - NUM_PACKETS_WD : integer := 48; - PACKET_LENGTH_WD : integer := 16; - REG_OUT : integer := 0; - ADDRESS_WIDTH : integer := 10 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - - CNT_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - PACKET_LENGTH : in std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - ADD_PACKET : in std_logic; - RST_COUNTERS : in std_logic; - - R_NUM_BYTES : out std_logic_vector(NUM_BYTES_WD-1 downto 0); - R_NUM_PACKETS : out std_logic_vector(NUM_PACKETS_WD-1 downto 0); - R_VLD : out std_logic; - R_NEXT : in std_logic - ); -end entity; - -architecture FULL of STATS is - signal cnt_num_bytes : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal cnt_num_packets : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal pipe0_num_bytes : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal pipe0_num_packets : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal pipe1_num_bytes : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal pipe1_num_packets : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal mem_num_bytes : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal mem_num_packets : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal pipe_mem_num_bytes : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal pipe_mem_num_packets : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal mux_num_bytes : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal mux_num_packets : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal mux_sel : std_logic_vector(1 downto 0); - signal pipe0_mux_sel : std_logic_vector(1 downto 0); - signal pipe1_mux_sel : std_logic_vector(1 downto 0); - - signal pipe0_cnt_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal pipe0_packet_length : std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - signal pipe0_add_packet : std_logic; - signal pipe0_rst_countesr : std_logic; - signal pipe1_cnt_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal pipe1_packet_length : std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - signal pipe1_add_packet : std_logic; - signal pipe1_rst_countesr : std_logic; - signal pipe2_cnt_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal pipe2_packet_length : std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - signal pipe2_add_packet : std_logic; - signal pipe2_rst_countesr : std_logic; - - signal cmp_addr0 : std_logic; - signal cmp_addr1 : std_logic; - signal mem_rw_addr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - - signal tmp_r_vld : std_logic; - signal pipe_r_vld : std_logic; -begin - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if(RESET = '1') then - pipe0_add_packet <= '0'; - pipe0_rst_countesr <= '0'; - pipe1_add_packet <= '0'; - pipe1_rst_countesr <= '0'; - pipe2_add_packet <= '0'; - pipe2_rst_countesr <= '0'; - else - pipe0_cnt_address <= CNT_ADDRESS; - pipe0_packet_length <= PACKET_LENGTH; - pipe0_add_packet <= ADD_PACKET; - pipe0_rst_countesr <= RST_COUNTERS; - pipe1_cnt_address <= pipe0_cnt_address; - pipe1_packet_length <= pipe0_packet_length; - pipe1_add_packet <= pipe0_add_packet; - pipe1_rst_countesr <= pipe0_rst_countesr; - pipe2_cnt_address <= pipe1_cnt_address; - pipe2_packet_length <= pipe1_packet_length; - pipe2_add_packet <= pipe1_add_packet; - pipe2_rst_countesr <= pipe1_rst_countesr; - pipe_mem_num_bytes <= mem_num_bytes; - pipe_mem_num_packets<= mem_num_packets; - end if; - end if; - end process; - - MEM_i : entity work.MEM_STATS - generic map ( - NUM_BYTES_WD => NUM_BYTES_WD, - NUM_PACKETS_WD => NUM_PACKETS_WD, - ADDRESS_WIDTH => ADDRESS_WIDTH - ) - port map( - CLK => CLK, - RESET => RESET, - RD_NUM_BYTES => mem_num_bytes, - RD_NUM_PACKETS => mem_num_packets, - RD_ADDRESS => pipe0_cnt_address, - WR_NUM_BYTES => pipe0_num_bytes, - WR_NUM_PACKETS => pipe0_num_packets, - WR_ADDRESS => mem_rw_addr - ); - - CNT_i : entity work.CNT_STATS - generic map( - EN_DSP => EN_DSP, - NUM_BYTES_WD => NUM_BYTES_WD, - NUM_PACKETS_WD => NUM_PACKETS_WD, - PACKET_LENGTH_WD => PACKET_LENGTH_WD, - REG_OUT => REG_OUT - ) - port map( - CLK => CLK, - RESET => RESET, - PACKET_LENGTH => pipe2_packet_length, - ADD_PACKET => pipe2_add_packet, - RST_COUNTERS => pipe2_rst_countesr, - IN_NUM_BYTES => mux_num_bytes, - IN_NUM_PACKETS => mux_num_packets, - OUT_NUM_BYTES => cnt_num_bytes, - OUT_NUM_PACKETS => cnt_num_packets - ); - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - pipe0_num_bytes <= cnt_num_bytes; - pipe0_num_packets <= cnt_num_packets; - pipe1_num_bytes <= pipe0_num_bytes; - pipe1_num_packets <= pipe0_num_packets; - - mem_rw_addr <= pipe2_cnt_address; - pipe0_mux_sel <= mux_sel; - pipe1_mux_sel <= pipe0_mux_sel; - end if; - end process; - - cmp_addr0 <= '1' when pipe0_cnt_address = pipe1_cnt_address else - '0'; - - cmp_addr1 <= '1' when pipe0_cnt_address = pipe2_cnt_address else - '0'; - - mux_sel <= "10" when cmp_addr0 = '0' and cmp_addr1 = '0' else - "01" when cmp_addr0 = '0' and cmp_addr1 = '1' else - "00"; - - mux_num_bytes <= pipe0_num_bytes when pipe1_mux_sel = "00" else - pipe1_num_bytes when pipe1_mux_sel = "01" else - pipe_mem_num_bytes; - - mux_num_packets <= pipe0_num_packets when pipe1_mux_sel = "00" else - pipe1_num_packets when pipe1_mux_sel = "01" else - pipe_mem_num_packets; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if(pipe2_add_packet = '1' and pipe2_rst_countesr = '1') then - R_NUM_BYTES <= mux_num_bytes; - R_NUM_PACKETS <= mux_num_packets; - end if; - end if; - end process; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if RESET = '1' then - R_VLD <= '0'; - else - if(pipe2_add_packet = '1' and pipe2_rst_countesr = '1') then - R_VLD <= '1'; - elsif(R_NEXT = '1') then - R_VLD <= '0'; - end if; - end if; - end if; - end process; - -end architecture; diff --git a/comp/proc/packet_stats/comp/trans.vhd b/comp/proc/packet_stats/comp/trans.vhd deleted file mode 100644 index cf32e38ba..000000000 --- a/comp/proc/packet_stats/comp/trans.vhd +++ /dev/null @@ -1,72 +0,0 @@ ---! \Author: Mario Kuka ---! \date 2016 ---! ---! \section License ---! ---! Copyright (C) 2016 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; -Library UNISIM; -use UNISIM.vcomponents.all; - ---! \brief DSP slice ALU entity -entity TRANS_STATS is - generic ( - PACKET_LENGTH_WD : integer := 16; - ADDRESS_WIDTH : integer := 10 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - - RM_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - RM_RD_ENABLE : in std_logic; - RM_REQ : in std_logic; - - IN_CNT_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - IN_PACKET_LENGTH : in std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - IN_ADD_PACKET : in std_logic; - IN_SRC_RDY : in std_logic; - IN_DST_RDY : out std_logic; - - OUT_CNT_ADDRESS : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); - OUT_PACKET_LENGTH : out std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - OUT_ADD_PACKET : out std_logic; - OUT_RST_COUNTERS : out std_logic - ); -end entity; - -architecture FULL of TRANS_STATS is -begin - - IN_DST_RDY <= '1' when RM_REQ = '0' else - '0'; - - OUT_CNT_ADDRESS <= IN_CNT_ADDRESS when RM_REQ = '0' else - RM_ADDRESS; - - OUT_PACKET_LENGTH <= IN_PACKET_LENGTH; - - process(RM_REQ, IN_SRC_RDY, IN_ADD_PACKET, RM_RD_ENABLE) - begin - OUT_ADD_PACKET <= '0'; - OUT_RST_COUNTERS <= '0'; - if(RM_REQ = '1') then - if(RM_RD_ENABLE = '1') then - OUT_ADD_PACKET <= '1'; - else - OUT_ADD_PACKET <= '0'; - end if; - OUT_RST_COUNTERS <= '1'; - elsif(IN_SRC_RDY = '1' and IN_ADD_PACKET = '1') then - OUT_ADD_PACKET <= '1'; - end if; - end process; - -end architecture; diff --git a/comp/proc/packet_stats/control_modul/Modules.tcl b/comp/proc/packet_stats/control_modul/Modules.tcl deleted file mode 100644 index 7c4c96658..000000000 --- a/comp/proc/packet_stats/control_modul/Modules.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# Modules.tcl: Local include tcl script -# Copyright (C) 2016 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause - -set MUX "$OFM_PATH/comp/base/logic/mux" -set PAC_STATS "$ENTITY_BASE/.." - -set COMPONENTS [ list \ - [ list "MUX_GEN" $MUX "FULL" ] \ - [ list "PAC_STATS" $PAC_STATS "FULL" ] \ - ] - -set PACKAGES "$PACKAGES $OFM_PATH/comp/base/pkg/math_pack.vhd" - -set MOD "$MOD $ENTITY_BASE/comp/cnt_trans.vhd" -set MOD "$MOD $ENTITY_BASE/comp/init_stats.vhd" -set MOD "$MOD $ENTITY_BASE/comp/cnt_wait.vhd" -set MOD "$MOD $ENTITY_BASE/comp/tr_wait.vhd" -set MOD "$MOD $ENTITY_BASE/comp/filter_trans.vhd" -set MOD "$MOD $ENTITY_BASE/comp/mi32_control.vhd" -set MOD "$MOD $ENTITY_BASE/comp/mux_tr.vhd" -set MOD "$MOD $ENTITY_BASE/control_stats_top_ent.vhd" -set MOD "$MOD $ENTITY_BASE/control_stats_top_arch.vhd" diff --git a/comp/proc/packet_stats/control_modul/comp/cnt_trans.vhd b/comp/proc/packet_stats/control_modul/comp/cnt_trans.vhd deleted file mode 100644 index 8072fbd24..000000000 --- a/comp/proc/packet_stats/control_modul/comp/cnt_trans.vhd +++ /dev/null @@ -1,59 +0,0 @@ ---! \Author: Mario Kuka ---! \date 2016 ---! ---! \section License ---! ---! Copyright (C) 2016 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; -Library UNISIM; -use UNISIM.vcomponents.all; - -entity CNT_TRAN is - generic ( - CNT_WIDTH : integer := 10 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - ADD_TR : in std_logic; - ADD_RDY : in std_logic; - RM_TR : in std_logic; - RM_RDY : in std_logic; - TRANS_NUM : out std_logic_vector(CNT_WIDTH-1 downto 0) - ); -end entity; - -architecture FULL of CNT_TRAN is - signal cnt_up : std_logic; - signal cnt_down : std_logic; - signal cnt_value : std_logic_vector(CNT_WIDTH-1 downto 0); -begin - - cnt_up <= ADD_TR and ADD_RDY; - cnt_down <= RM_TR and RM_RDY; - TRANS_NUM <= cnt_value; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if RESET = '1' then - cnt_value <= (others => '0'); - else - if(cnt_up = '1' and cnt_down = '0') then - cnt_value <= cnt_value + 1; - end if; - if(cnt_up = '0' and cnt_down = '1') then - cnt_value <= cnt_value - 1; - end if; - end if; - end if; - end process; - -end architecture; diff --git a/comp/proc/packet_stats/control_modul/comp/cnt_wait.vhd b/comp/proc/packet_stats/control_modul/comp/cnt_wait.vhd deleted file mode 100644 index 4f3bf7101..000000000 --- a/comp/proc/packet_stats/control_modul/comp/cnt_wait.vhd +++ /dev/null @@ -1,57 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity CNT_WAIT is - generic( - CNT_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - TR_NUM : in std_logic_vector(CNT_WIDTH-1 downto 0); - TR_RDY : in std_logic; - CNT_END : out std_logic - ); -end entity; - -architecture FULL of CNT_WAIT is - signal cnt_value : std_logic_vector(CNT_WIDTH-1 downto 0); - signal cnt_zero : std_logic; -begin - - cnt_zero <= '1' when cnt_value = conv_std_logic_vector(0, CNT_WIDTH) else - '0'; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if RESET = '1' then - cnt_value <= (others => '0'); - else - if(TR_RDY = '1') then - cnt_value <= TR_NUM; - elsif(cnt_zero = '0') then - cnt_value <= cnt_value - 1; - end if; - end if; - end if; - end process; - - CNT_END <= '0' when TR_RDY = '1' or cnt_zero = '0' else - '1'; - -end architecture; - diff --git a/comp/proc/packet_stats/control_modul/comp/filter_trans.vhd b/comp/proc/packet_stats/control_modul/comp/filter_trans.vhd deleted file mode 100644 index b412f59d2..000000000 --- a/comp/proc/packet_stats/control_modul/comp/filter_trans.vhd +++ /dev/null @@ -1,124 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity FILTER_TR is - generic( - ADDRESS_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - FILTER_ADDR : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - FILTER_RM : in std_logic; - FILTER_RM_ALL : in std_logic; - FILTER_NEXT : out std_logic; - - RM_ADDRESS : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); - RM_RD_ENABLE : out std_logic; - RM_REQ : out std_logic - ); -end entity; - -architecture full of FILTER_TR is - - signal pipe_FILTER_ADDR : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal pipe_FILTER_RM : std_logic; - signal pipe_FILTER_RM_ALL : std_logic; - - signal tr_next : std_logic; - signal pipe_tr_next : std_logic; - - signal one_req_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal one_req_rd_enable : std_logic; - signal one_req_rm : std_logic; - - signal cnt_en : std_logic; - signal cnt_value : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal cnt_zero : std_logic; - - signal other_req_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal other_req_rd_enable : std_logic; - signal other_req_rm : std_logic; - - signal in_tr_enable : std_logic; -begin - - in_tr_enable <= pipe_FILTER_RM and pipe_tr_next; - - one_req_address <= pipe_FILTER_ADDR; - one_req_rm <= in_tr_enable when pipe_FILTER_RM_ALL = '0' else - '0'; - - cnt_en <= in_tr_enable and pipe_FILTER_RM_ALL; - cnt_zero <= '1' when cnt_value = conv_std_logic_vector(0, cnt_value'length) else - '0'; - - FILTER_NEXT <= tr_next; - - process(pipe_tr_next, other_req_rm, cnt_en, in_tr_enable) - begin - tr_next <= pipe_tr_next; - if(in_tr_enable = '1') then - tr_next <= '0'; - end if; - if(other_req_rm = '0' and cnt_en = '0') then - tr_next <= '1'; - end if; - end process; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if(RESET = '1') then - pipe_FILTER_RM <= '0'; - pipe_tr_next <= '1'; - else - pipe_FILTER_ADDR <= FILTER_ADDR; - pipe_FILTER_RM <= FILTER_RM; - pipe_FILTER_RM_ALL <= FILTER_RM_ALL; - pipe_tr_next <= tr_next; - end if; - end if; - end process; - - other_req_rd_enable <= '0'; - other_req_address <= cnt_value; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if RESET = '1' then - cnt_value <= (others => '0'); - other_req_rm <= '0'; - elsif(cnt_en = '1') then - cnt_value <= (others => '1'); - other_req_rm <= '1'; - elsif(cnt_zero = '0') then - cnt_value <= cnt_value - 1; - else - other_req_rm <= '0'; - end if; - end if; - end process; - - RM_ADDRESS <= one_req_address when other_req_rm = '0' else - other_req_address; - RM_RD_ENABLE <= '0'; - RM_REQ <= one_req_rm when other_req_rm = '0' else - '1'; - -end architecture; diff --git a/comp/proc/packet_stats/control_modul/comp/init_stats.vhd b/comp/proc/packet_stats/control_modul/comp/init_stats.vhd deleted file mode 100644 index 6b1d9d4ed..000000000 --- a/comp/proc/packet_stats/control_modul/comp/init_stats.vhd +++ /dev/null @@ -1,60 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity INIT_STATS is - generic( - ADDRESS_WIDTH : integer := 10; - CNT_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - IN_ADDR : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - IN_RM : in std_logic; - IN_RM_ALL : in std_logic; - IN_NEXT : out std_logic; - - OUT_ADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); - OUT_RM : out std_logic; - OUT_RM_ALL : out std_logic; - OUT_NEXT : in std_logic - ); -end entity; - -architecture FULL of INIT_STATS is - signal pipe_reset : std_logic; - signal sel : std_logic; -begin - - process(CLK) - begin - if(CLK'event and CLK = '1') then - pipe_reset <= RESET; - end if; - end process; - - sel <= '1' when pipe_reset = '1' and RESET = '0' else - '0'; - - OUT_ADDR <= IN_ADDR; - OUT_RM <= IN_RM when sel = '0' else - '1'; - OUT_RM_ALL <= IN_RM_ALL when sel = '0' else - '1'; - IN_NEXT <= OUT_NEXT; - -end architecture; diff --git a/comp/proc/packet_stats/control_modul/comp/mi32_control.vhd b/comp/proc/packet_stats/control_modul/comp/mi32_control.vhd deleted file mode 100644 index ba1eb74ef..000000000 --- a/comp/proc/packet_stats/control_modul/comp/mi32_control.vhd +++ /dev/null @@ -1,171 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity MI32_CONTROL is - generic( - NUM_BYTES_WD : integer := 48; - NUM_PACKETS_WD : integer := 48; - ADDRESS_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - --! MI32 interface - MI32_ADDR : in std_logic_vector(31 downto 0); - MI32_WR : in std_logic; - MI32_DWR : in std_logic_vector(31 downto 0); - MI32_RD : in std_logic; - MI32_DRD : out std_logic_vector(31 downto 0); - MI32_DRDY : out std_logic; - MI32_ARDY : out std_logic; - MI32_BE : in std_logic_vector(3 downto 0); - - RM_ADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); - RM_RD_ENABLE : out std_logic; - RM : out std_logic; - RM_ARDY : in std_logic; - - CNT_NUM_BYTES : in std_logic_vector(NUM_BYTES_WD-1 downto 0); - CNT_NUM_PACKETS : in std_logic_vector(NUM_PACKETS_WD-1 downto 0); - CNT_VLD : in std_logic; - CNT_NEXT : out std_logic - ); -end entity; - -architecture full of MI32_CONTROL is - constant num_regs_bytes : integer := div_roundup(NUM_BYTES_WD, 32); - constant num_regs_packets : integer := div_roundup(NUM_PACKETS_WD, 32); - constant num_regs : integer := 3 + num_regs_bytes + num_regs_packets; - constant log_regs : integer := log2(num_regs); - signal mux_rd : std_logic_vector(32*num_regs-1 downto 0); - - signal rm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal next_req : std_logic; - signal bytes_reg : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal packets_reg : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - - signal addr_wr : std_logic; - -begin - - MI32_ARDY <= MI32_RD or MI32_WR; - MI32_DRDY <= MI32_RD; - RM_RD_ENABLE <= '1'; - - addr_wr <= MI32_WR when MI32_ADDR(log_regs+1 downto 2) = conv_std_logic_vector(0, log_regs) else - '0'; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if(addr_wr = '1') then - rm_address <= MI32_DWR(ADDRESS_WIDTH-1 downto 0); - end if; - end if; - end process; - RM_ADDR <= rm_address; - mux_rd(ADDRESS_WIDTH-1 downto 0) <= rm_address; - mux_rd(31 downto ADDRESS_WIDTH) <= (others => '0'); - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if RESET = '1' then - RM <= '0'; - else - if(addr_wr = '1') then - RM <= '1'; - elsif(RM_ARDY = '1') then - RM <= '0'; - end if; - end if; - end if; - end process; - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if RESET = '1' then - next_req <= '1'; - else - if(addr_wr = '1') then - next_req <= '0'; - elsif(CNT_VLD = '1') then - next_req <= '1'; - end if; - end if; - end if; - end process; - mux_rd(32) <= next_req; - mux_rd(32*2-1 downto 33) <= (others => '0'); - - mux_rd(32*3-1 downto 32*2) <= conv_std_logic_vector(NUM_PACKETS_WD, 11) & - conv_std_logic_vector(NUM_BYTES_WD, 11) & - conv_std_logic_vector(ADDRESS_WIDTH, 10); - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if(CNT_VLD = '1') then - bytes_reg <= CNT_NUM_BYTES; - packets_reg <= CNT_NUM_PACKETS; - end if; - end if; - end process; - CNT_NEXT <= '1'; - - gen_bytes_regs : for I in 0 to num_regs_bytes-1 generate - constant reg_range : integer := 32 * (I + 3 + 1); - begin - gen_others : if I < num_regs_bytes - 1 generate - mux_rd(reg_range-1 downto reg_range-32) <= CNT_NUM_BYTES(32*(I+1)-1 downto 32*I); - end generate; - - gen_last : if I = num_regs_bytes - 1 generate - constant vld_bist : integer := 32 - (num_regs_bytes * 32 - NUM_BYTES_WD); - begin - mux_rd(reg_range-1 downto reg_range - vld_bist) <= (others => '0'); - mux_rd(reg_range-vld_bist-1 downto reg_range-32) <= CNT_NUM_BYTES(CNT_NUM_BYTES'length-1 downto 32*I); - end generate; - end generate; - - gen_packets_regs : for I in 0 to num_regs_packets-1 generate - constant reg_range : integer := 32 * (I + 3 + 1 + num_regs_bytes); - begin - gen_others : if I < num_regs_packets - 1 generate - mux_rd(reg_range-1 downto reg_range-32) <= CNT_NUM_PACKETS(32*(I+1)-1 downto 32*I); - end generate; - - gen_last : if I = num_regs_packets - 1 generate - constant vld_bist : integer := 32 - (num_regs_packets * 32 - NUM_PACKETS_WD); - begin - mux_rd(reg_range-1 downto reg_range - vld_bist) <= (others => '0'); - mux_rd(reg_range - vld_bist-1 downto reg_range-32) <= CNT_NUM_PACKETS(CNT_NUM_PACKETS'length-1 downto 32*I); - end generate; - end generate; - - mi_rd_mux : entity work.GEN_MUX - generic map( - DATA_WIDTH => 32, - MUX_WIDTH => num_regs - ) - port map( - DATA_IN => mux_rd, - SEL => MI32_ADDR(log_regs+1 downto 2), - DATA_OUT => MI32_DRD - ); - -end architecture; diff --git a/comp/proc/packet_stats/control_modul/comp/mux_tr.vhd b/comp/proc/packet_stats/control_modul/comp/mux_tr.vhd deleted file mode 100644 index aa2c837c2..000000000 --- a/comp/proc/packet_stats/control_modul/comp/mux_tr.vhd +++ /dev/null @@ -1,57 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity MUX_TR is - generic( - ADDRESS_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - MI_RM_ADDR : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - MI_RM_RD_ENABLE : in std_logic; - MI_RM : in std_logic; - MI_RM_ARDY : out std_logic; - - SEL : in std_logic; - - FLT_RM_ADDR : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - FLT_RM_RD_ENABLE : in std_logic; - FLT_RM_REQ : in std_logic; - - RM_ADDRESS : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); - RM_RD_ENABLE : out std_logic; - RM_REQ : out std_logic - - ); -end entity; - -architecture full of MUX_TR is -begin - - RM_ADDRESS <= FLT_RM_ADDR when SEL = '1' else - MI_RM_ADDR; - - RM_RD_ENABLE <= FLT_RM_RD_ENABLE when SEL = '1' else - MI_RM_RD_ENABLE; - - RM_REQ <= FLT_RM_REQ when SEL = '1' else - MI_RM; - - MI_RM_ARDY <= not SEL; - -end architecture; diff --git a/comp/proc/packet_stats/control_modul/comp/tr_wait.vhd b/comp/proc/packet_stats/control_modul/comp/tr_wait.vhd deleted file mode 100644 index 246046be4..000000000 --- a/comp/proc/packet_stats/control_modul/comp/tr_wait.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity WAIT_TR is - generic( - ADDRESS_WIDTH : integer := 10; - CNT_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - TR_NUM : in std_logic_vector(CNT_WIDTH-1 downto 0); - - IN_ADDR : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - IN_RM : in std_logic; - IN_RM_ALL : in std_logic; - IN_NEXT : out std_logic; - - OUT_ADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); - OUT_RM : out std_logic; - OUT_RM_ALL : out std_logic; - OUT_NEXT : in std_logic - ); -end entity; - -architecture FULL of WAIT_TR is - signal mem_rdy : std_logic; - signal cnt_zero : std_logic; - - signal pipe_IN_ADDR : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal pipe_IN_RM : std_logic; - signal pipe_IN_RM_ALL : std_logic; - - signal tr_next : std_logic; - signal pipe_tr_next : std_logic; - signal cnt_rdy : std_logic; - signal cnt_end : std_logic; -begin - - process(CLK) - begin - if (CLK'event) and (CLK = '1') then - if(RESET = '1') then - pipe_tr_next <= '1'; - pipe_IN_RM <= '0'; - else - pipe_tr_next <= tr_next; - if(tr_next = '1') then - pipe_IN_ADDR <= IN_ADDR; - pipe_IN_RM <= IN_RM; - pipe_IN_RM_ALL <= IN_RM_ALL; - end if; - end if; - end if; - end process; - - IN_NEXT <= tr_next; - - process(pipe_tr_next, pipe_IN_RM, cnt_end, OUT_NEXT) - begin - tr_next <= pipe_tr_next; - if(pipe_IN_RM = '1' and pipe_tr_next = '1') then - tr_next <= '0'; - end if; - if(cnt_end = '1' and OUT_NEXT = '1') then - tr_next <= '1'; - end if; - end process; - - cnt_rdy <= pipe_IN_RM and pipe_tr_next; - cnt_wait_i : entity work.CNT_WAIT - generic map( - CNT_WIDTH => CNT_WIDTH - ) - port map( - CLK => CLK, - RESET => RESET, - TR_NUM => TR_NUM, - TR_RDY => cnt_rdy, - CNT_END => cnt_end - ); - - OUT_ADDR <= pipe_IN_ADDR; - OUT_RM_ALL <= pipe_IN_RM_ALL; - OUT_RM <= cnt_end and pipe_IN_RM; - -end architecture; - diff --git a/comp/proc/packet_stats/control_modul/control_stats_top_arch.vhd b/comp/proc/packet_stats/control_modul/control_stats_top_arch.vhd deleted file mode 100644 index 6c227675e..000000000 --- a/comp/proc/packet_stats/control_modul/control_stats_top_arch.vhd +++ /dev/null @@ -1,89 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- ARCHITECTURE DECLARATION -- --- ---------------------------------------------------------------------------- - -architecture full of CONTROL_STATS is - signal mi_addr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal mi_rm : std_logic; - signal mi_rd_enable : std_logic; - signal mi_ardy : std_logic; - - signal stats_num_bytes : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal stats_num_packets : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal stats_vld : std_logic; - signal stats_next : std_logic; -begin - - MI32_CONTROL_i : entity work.MI32_CONTROL - generic map( - NUM_BYTES_WD => NUM_BYTES_WD, - NUM_PACKETS_WD => NUM_PACKETS_WD, - ADDRESS_WIDTH => ADDRESS_WIDTH - ) - port map( - CLK => CLK, - RESET => RESET, - MI32_ADDR => MI32_ADDR, - MI32_WR => MI32_WR, - MI32_DWR => MI32_DWR , - MI32_RD => MI32_RD, - MI32_DRD => MI32_DRD, - MI32_DRDY => MI32_DRDY, - MI32_ARDY => MI32_ARDY, - MI32_BE => MI32_BE, - RM_ADDR => mi_addr, - RM_RD_ENABLE => mi_rd_enable, - RM => mi_rm, - RM_ARDY => mi_ardy, - CNT_NUM_BYTES => stats_num_bytes, - CNT_NUM_PACKETS => stats_num_packets, - CNT_VLD => stats_vld, - CNT_NEXT => stats_next - ); - mi_ardy <= '1'; - - - PACKET_STAT_i : entity work.PAC_STATS - generic map( - EN_DSP => EN_DSP, - NUM_BYTES_WD => NUM_BYTES_WD, - NUM_PACKETS_WD => NUM_PACKETS_WD, - PACKET_LENGTH_WD => PACKET_LENGTH_WD, - REG_OUT => 0, - ADDRESS_WIDTH => ADDRESS_WIDTH - ) - port map( - CLK => CLK, - RESET => RESET, - RM_ADDRESS => mi_addr, - RM_RD_ENABLE => mi_rd_enable, - RM_REQ => mi_rm, - CNT_ADDRESS => CNT_ADDRESS, - PACKET_LENGTH => PACKET_LENGTH, - ADD_PACKET => ADD_PACKET, - SRC_RDY => SRC_RDY, - DST_RDY => DST_RDY, - RD_NUM_BYTES => stats_num_bytes, - RD_NUM_PACKETS => stats_num_packets, - RD_VLD => stats_vld, - RD_NEXT => stats_next - ); - -end architecture; diff --git a/comp/proc/packet_stats/control_modul/control_stats_top_ent.vhd b/comp/proc/packet_stats/control_modul/control_stats_top_ent.vhd deleted file mode 100644 index a9466830c..000000000 --- a/comp/proc/packet_stats/control_modul/control_stats_top_ent.vhd +++ /dev/null @@ -1,45 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity CONTROL_STATS is - generic( - EN_DSP : boolean := true; - PACKET_LENGTH_WD : integer := 16; - NUM_BYTES_WD : integer := 48; - NUM_PACKETS_WD : integer := 48; - ADDRESS_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - --! MI32 interface - MI32_ADDR : in std_logic_vector(31 downto 0); - MI32_WR : in std_logic; - MI32_DWR : in std_logic_vector(31 downto 0); - MI32_RD : in std_logic; - MI32_DRD : out std_logic_vector(31 downto 0); - MI32_DRDY : out std_logic; - MI32_ARDY : out std_logic; - MI32_BE : in std_logic_vector(3 downto 0); - --! add packets - CNT_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - PACKET_LENGTH : in std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - ADD_PACKET : in std_logic; - SRC_RDY : in std_logic; - DST_RDY : out std_logic - ); -end entity; - diff --git a/comp/proc/packet_stats/control_modul/sim/signals.fdo b/comp/proc/packet_stats/control_modul/sim/signals.fdo deleted file mode 100644 index e24c49c7d..000000000 --- a/comp/proc/packet_stats/control_modul/sim/signals.fdo +++ /dev/null @@ -1,81 +0,0 @@ -# signals.fdo: Include file with signals -# Copyright (C) 2015 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -proc blk_STATS { } { - - global STATS_PATH - - set GROUP "{MI32}" - add_wave "-group $GROUP -noupdate -hex -label MI32_ADDR" $STATS_PATH/MI32_ADDR - add_wave "-group $GROUP -noupdate -hex -label MI32_WR " $STATS_PATH/MI32_WR - add_wave "-group $GROUP -noupdate -hex -label MI32_DWR " $STATS_PATH/MI32_DWR - add_wave "-group $GROUP -noupdate -hex -label MI32_RD " $STATS_PATH/MI32_RD - add_wave "-group $GROUP -noupdate -hex -label MI32_DRD " $STATS_PATH/MI32_DRD - add_wave "-group $GROUP -noupdate -hex -label MI32_DRDY" $STATS_PATH/MI32_DRDY - add_wave "-group $GROUP -noupdate -hex -label MI32_ARDY" $STATS_PATH/MI32_ARDY - add_wave "-group $GROUP -noupdate -hex -label MI32_BE " $STATS_PATH/MI32_BE - - set GROUP "{TANS NUM}" - add_wave "-group $GROUP -noupdate -hex -label ADD_TR " $STATS_PATH/ADD_TR - add_wave "-group $GROUP -noupdate -hex -label ADD_RDY" $STATS_PATH/ADD_RDY - add_wave "-group $GROUP -noupdate -hex -label RM_TR " $STATS_PATH/RM_TR - add_wave "-group $GROUP -noupdate -hex -label RM_RDY " $STATS_PATH/RM_RDY - add_wave "-group $GROUP -noupdate -hex -label cnt_trans_num " /testbench/uut/cnt_tran_num - - set GROUP "{FILTER}" - add_wave "-group $GROUP -noupdate -hex -label FILTER_ADDR " $STATS_PATH/FILTER_ADDR - add_wave "-group $GROUP -noupdate -hex -label FILTER_RM " $STATS_PATH/FILTER_RM - add_wave "-group $GROUP -noupdate -hex -label FILTER_RM_ALL" $STATS_PATH/FILTER_RM_ALL - add_wave "-group $GROUP -noupdate -hex -label FILTER_NEXT " $STATS_PATH/FILTER_NEXT - - set GROUP "{STATS RM}" - add_wave "-group $GROUP -noupdate -hex -label RM_ADDRESS " $STATS_PATH/RM_ADDRESS - add_wave "-group $GROUP -noupdate -hex -label RM_RD_ENABLE" $STATS_PATH/RM_RD_ENABLE - add_wave "-group $GROUP -noupdate -hex -label RM_REQ " $STATS_PATH/RM_REQ - - set GROUP "{STATS RD}" - add_wave "-group $GROUP -noupdate -hex -label RD_NUM_BYTES " $STATS_PATH/RD_NUM_BYTES - add_wave "-group $GROUP -noupdate -hex -label RD_NUM_PACKETS" $STATS_PATH/RD_NUM_PACKETS - add_wave "-group $GROUP -noupdate -hex -label RD_VLD " $STATS_PATH/RD_VLD - add_wave "-group $GROUP -noupdate -hex -label RD_NEXT " $STATS_PATH/RD_NEXT - - set GROUP "{WAIT BLOCK}" - add_wave "-group $GROUP -noupdate -hex -label FILTER_ADDR " $STATS_PATH/FILTER_ADDR - add_wave "-group $GROUP -noupdate -hex -label FILTER_RM " $STATS_PATH/FILTER_RM - add_wave "-group $GROUP -noupdate -hex -label FILTER_RM_ALL" $STATS_PATH/FILTER_RM_ALL - add_wave "-group $GROUP -noupdate -hex -label FILTER_NEXT " $STATS_PATH/FILTER_NEXT - add_wave "-group $GROUP -noupdate -hex -label wait_addr " /testbench/uut/wait_addr - add_wave "-group $GROUP -noupdate -hex -label wait_rm " /testbench/uut/wait_rm - add_wave "-group $GROUP -noupdate -hex -label wait_rm_all " /testbench/uut/wait_rm_all - add_wave "-group $GROUP -noupdate -hex -label wait_next " /testbench/uut/wait_next - add_wave "-group $GROUP -noupdate -hex -label cnt_value " /testbench/uut/WAIT_TR_i/cnt_wait_i/cnt_value - - set GROUP "{TR GEN BLOCK}" - add_wave "-group $GROUP -noupdate -hex -label wait_addr " /testbench/uut/wait_addr - add_wave "-group $GROUP -noupdate -hex -label wait_rm " /testbench/uut/wait_rm - add_wave "-group $GROUP -noupdate -hex -label wait_rm_all " /testbench/uut/wait_rm_all - add_wave "-group $GROUP -noupdate -hex -label wait_next " /testbench/uut/wait_next - add_wave "-group $GROUP -noupdate -hex -label flt_addr " /testbench/uut/flt_addr - add_wave "-group $GROUP -noupdate -hex -label flt_rd_enable" /testbench/uut/flt_rd_enable - add_wave "-group $GROUP -noupdate -hex -label flt_rm_req " /testbench/uut/flt_rm_req - - set GROUP "{PAC STATS BLOK}" - add_wave "-group $GROUP -noupdate -hex -label RM_ADDRESS " /testbench/uut/PACKET_STAT_i/RM_ADDRESS - add_wave "-group $GROUP -noupdate -hex -label RM_RD_ENABLE " /testbench/uut/PACKET_STAT_i/RM_RD_ENABLE - add_wave "-group $GROUP -noupdate -hex -label RM_REQ " /testbench/uut/PACKET_STAT_i/RM_REQ - add_wave "-group $GROUP -noupdate -hex -label CNT_ADDRESS " /testbench/uut/PACKET_STAT_i/CNT_ADDRESS - add_wave "-group $GROUP -noupdate -hex -label PACKET_LENGTH " /testbench/uut/PACKET_STAT_i/PACKET_LENGTH - add_wave "-group $GROUP -noupdate -hex -label ADD_PACKET " /testbench/uut/PACKET_STAT_i/ADD_PACKET - add_wave "-group $GROUP -noupdate -hex -label SRC_RDY " /testbench/uut/PACKET_STAT_i/SRC_RDY - add_wave "-group $GROUP -noupdate -hex -label DST_RDY " /testbench/uut/PACKET_STAT_i/DST_RDY - add_wave "-group $GROUP -noupdate -hex -label RD_NUM_BYTES " /testbench/uut/PACKET_STAT_i/RD_NUM_BYTES - add_wave "-group $GROUP -noupdate -hex -label RD_NUM_PACKETS" /testbench/uut/PACKET_STAT_i/RD_NUM_PACKETS - add_wave "-group $GROUP -noupdate -hex -label RD_VLD " /testbench/uut/PACKET_STAT_i/RD_VLD - add_wave "-group $GROUP -noupdate -hex -label RD_NEXT " /testbench/uut/PACKET_STAT_i/RD_NEXT -} diff --git a/comp/proc/packet_stats/control_modul/sim/stats.fdo b/comp/proc/packet_stats/control_modul/sim/stats.fdo deleted file mode 100644 index 95f5b370c..000000000 --- a/comp/proc/packet_stats/control_modul/sim/stats.fdo +++ /dev/null @@ -1,30 +0,0 @@ -# editor.fdo: Simulation script -# Copyright (C) 2015 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# For whole design testing -set FIRMWARE_BASE "../../../../.." -set STATS_BASE "$OFM_PATH/comp/proc/packet_stats/control_modul" - -set TB_FILE "$STATS_BASE/sim/testbench.vhd" -set SIG_FILE "$STATS_BASE/sim/stats_sig.fdo" - -# Modules definition -set COMPONENTS [list \ - [list "CONTROL_STATS" $STATS_BASE "FULL"] \ - ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 500ns diff --git a/comp/proc/packet_stats/control_modul/sim/stats_sig.fdo b/comp/proc/packet_stats/control_modul/sim/stats_sig.fdo deleted file mode 100644 index e817daaf3..000000000 --- a/comp/proc/packet_stats/control_modul/sim/stats_sig.fdo +++ /dev/null @@ -1,21 +0,0 @@ -# editor_sig.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths -set TB_PATH "/testbench" -set STATS_PATH "/testbench/uut" - -# include signals -source "signals.fdo" - -add wave -noupdate -label RESET -color magenta $TB_PATH/reset -add wave -noupdate -label CLK -color magenta $TB_PATH/clk -blk_STATS - - diff --git a/comp/proc/packet_stats/control_modul/sim/testbench.vhd b/comp/proc/packet_stats/control_modul/sim/testbench.vhd deleted file mode 100644 index 2964428c1..000000000 --- a/comp/proc/packet_stats/control_modul/sim/testbench.vhd +++ /dev/null @@ -1,326 +0,0 @@ --- # Copyright (C) 2016 CESNET --- # Author: Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -use work.math_pack.all; - -entity testbench is - -end testbench; - -architecture behavioral of testbench is - - constant clkper : time := 10 ns; --Clock period - constant reset_time : time := 2*clkper + 0.5 ns; --Reset durati - - constant EN_DSP : boolean := true; - constant PACKET_LENGTH_WD : integer := 16; - constant NUM_BYTES_WD : integer := 48; - constant NUM_PACKETS_WD : integer := 48; - constant ADDRESS_WIDTH : integer := 10; - constant CNT_WIDTH : integer := 10; - - signal CLK : std_logic; - signal RESET : std_logic; - - type flt_pac_t is record - CNT_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - PACKET_LENGTH : std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - ADD_PACKET : std_logic; - SRC_RDY : std_logic; - DST_RDY : std_logic; - end record; - - type mi_t is record - MI32_ADDR : std_logic_vector(31 downto 0); - MI32_WR : std_logic; - MI32_DWR : std_logic_vector(31 downto 0); - MI32_RD : std_logic; - MI32_DRD : std_logic_vector(31 downto 0); - MI32_DRDY : std_logic; - MI32_ARDY : std_logic; - MI32_BE : std_logic_vector(3 downto 0); - end record; - - type tr_num_t is record - ADD_TR : std_logic; - ADD_RDY : std_logic; - RM_TR : std_logic; - RM_RDY : std_logic; - end record; - - type flt_t is record - FILTER_ADDR : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - FILTER_RM : std_logic; - FILTER_RM_ALL : std_logic; - FILTER_NEXT : std_logic; - end record; - - signal mi_i : mi_t; - signal tr_num_i : tr_num_t; - signal flt_i : flt_t; - signal flt_pac_i : flt_pac_t; - - signal mi_o : mi_t; - signal tr_num_o : tr_num_t; - signal flt_o : flt_t; - signal flt_pac_o : flt_pac_t; - - procedure init ( - signal mi : out mi_t; - signal tr_num : out tr_num_t; - signal flt_pac : out flt_pac_t; - signal flt : out flt_t - )is - begin - mi.MI32_ADDR <= (others => '0'); - mi.MI32_WR <= '0'; - mi.MI32_DWR <= (others => '0'); - mi.MI32_RD <= '0'; - mi.MI32_BE <= (others => '0'); - - tr_num.ADD_TR <= '0'; - tr_num.ADD_RDY <= '0'; - tr_num.RM_TR <= '0'; - tr_num.RM_RDY <= '0'; - - flt.FILTER_ADDR <= (others => '0'); - flt.FILTER_RM <= '0'; - flt.FILTER_RM_ALL <= '0'; - - flt_pac.CNT_ADDRESS <= (others => '0'); - flt_pac.PACKET_LENGTH <= (others => '0'); - flt_pac.ADD_PACKET <= '0'; - flt_pac.SRC_RDY <= '1'; - wait for reset_time; - wait for clkper; - end procedure; - - procedure tr_add ( - signal tr_num : out tr_num_t; - num : in integer - ) is - begin - tr_num.ADD_TR <= '1'; - for I in 0 to num-1 loop - tr_num.ADD_RDY <= '1'; - wait for clkper; - tr_num.ADD_RDY <= '0'; - end loop; - end procedure; - - procedure tr_remove ( - signal tr_num : out tr_num_t; - num : in integer - ) is - begin - tr_num.RM_TR <= '1'; - for I in 0 to num-1 loop - tr_num.RM_RDY <= '1'; - wait for clkper; - tr_num.RM_RDY <= '0'; - end loop; - end procedure; - - - procedure flt_send ( - signal flt_in : out flt_t; - signal flt_out : in flt_t; - addr : in integer; - rm_all : in boolean; - num : in integer - )is - begin - for I in 0 to num-1 loop - flt_in.FILTER_ADDR <= conv_std_logic_vector(addr, ADDRESS_WIDTH); - if(rm_all = true) then - flt_in.FILTER_RM_ALL <= '1'; - else - flt_in.FILTER_RM_ALL <= '0'; - end if; - flt_in.FILTER_RM <= '1'; - - while flt_out.FILTER_NEXT = '0' loop - wait for clkper; - end loop; - wait for clkper; - flt_in.FILTER_RM <= '0'; - end loop; - end procedure; - - procedure test_tr_num ( - signal tr_num : out tr_num_t - )is - begin - tr_add(tr_num, 20); - tr_remove(tr_num, 5); - wait for 2*clkper; - tr_remove(tr_num, 2); - tr_add(tr_num, 9); - wait for 2*clkper; - tr_num.RM_TR <= '1'; - tr_num.RM_RDY <= '1'; - tr_num.ADD_TR <= '1'; - tr_num.ADD_RDY <= '1'; - wait for clkper; - tr_num.RM_RDY <= '0'; - tr_num.ADD_RDY <= '0'; - tr_remove(tr_num, 22); - end procedure; - - procedure test_wait ( - signal flt_in : out flt_t; - signal flt_out : in flt_t; - signal tr_num : out tr_num_t - ) is - begin - flt_send(flt_in, flt_out, 0, false, 2); - tr_add(tr_num, 1); - flt_send(flt_in, flt_out, 0, false, 2); - tr_add(tr_num, 9); - flt_send(flt_in, flt_out, 0, false, 2); - tr_remove(tr_num, 10); - flt_send(flt_in, flt_out, 0, false, 2); - end procedure; - - procedure test_tr_gen ( - signal flt_in : out flt_t; - signal flt_out : in flt_t - ) is - begin - flt_send(flt_in, flt_out, 4, false, 2); - flt_send(flt_in, flt_out, 5, true, 1); - wait for 5*clkper; - flt_send(flt_in, flt_out, 6, false, 1); - end procedure; - - - procedure mi_wr_req ( - signal mi : out mi_t; - cnt : in integer - ) is - begin - mi.MI32_ADDR <= conv_std_logic_vector(0, 32); - mi.MI32_WR <= '1'; - mi.MI32_DWR <= conv_std_logic_vector(cnt, 32); - wait for clkper; - mi.MI32_WR <= '0'; - end procedure; - - procedure mi_rd_req ( - signal mi_in : out mi_t; - signal mi_out : in mi_t - ) is - begin - mi_in.MI32_ADDR <= conv_std_logic_vector(4, 32); - mi_in.MI32_RD <= '1'; - wait for clkper; - while mi_out.MI32_DRD(0) = '0' loop - wait for clkper; - end loop; - wait for clkper; - mi_in.MI32_ADDR <= conv_std_logic_vector(12, 32); - wait for clkper; - mi_in.MI32_ADDR <= conv_std_logic_vector(16, 32); - wait for clkper; - mi_in.MI32_ADDR <= conv_std_logic_vector(20, 32); - wait for clkper; - mi_in.MI32_ADDR <= conv_std_logic_vector(24, 32); - wait for clkper; - mi_in.MI32_RD <= '0'; - end procedure; - - procedure send_pac ( - signal flt_pac_in : out flt_pac_t; - signal flt_pac_out : in flt_pac_t; - num : in integer; - address : in integer; - length : in integer - ) is - begin - for I in 0 to num-1 loop - flt_pac_in.CNT_ADDRESS <= conv_std_logic_vector(address, ADDRESS_WIDTH); - flt_pac_in.PACKET_LENGTH <= conv_std_logic_vector(length, PACKET_LENGTH_WD); - flt_pac_in.ADD_PACKET <= '1'; - flt_pac_in.SRC_RDY <= '1'; - - while flt_pac_out.DST_RDY = '0' loop - wait for clkper; - end loop; - wait for clkper; - flt_pac_in.SRC_RDY <= '0'; - end loop; - end procedure; - -begin - - uut : entity work.CONTROL_STATS - generic map ( - EN_DSP => EN_DSP, - PACKET_LENGTH_WD => PACKET_LENGTH_WD, - NUM_BYTES_WD => NUM_BYTES_WD, - NUM_PACKETS_WD => NUM_PACKETS_WD, - ADDRESS_WIDTH => ADDRESS_WIDTH, - CNT_WIDTH => CNT_WIDTH - ) - port map ( - CLK => CLK, - RESET => RESET, - MI32_ADDR => mi_i.MI32_ADDR, - MI32_WR => mi_i.MI32_WR, - MI32_DWR => mi_i.MI32_DWR , - MI32_RD => mi_i.MI32_RD, - MI32_DRD => mi_o.MI32_DRD , - MI32_DRDY => mi_o.MI32_DRDY, - MI32_ARDY => mi_o.MI32_ARDY, - MI32_BE => mi_i.MI32_BE, - ADD_TR => tr_num_i.ADD_TR, - ADD_RDY => tr_num_i.ADD_RDY, - RM_TR => tr_num_i.RM_TR, - RM_RDY => tr_num_i.RM_RDY, - FILTER_ADDR => flt_i.FILTER_ADDR, - FILTER_RM => flt_i.FILTER_RM, - FILTER_RM_ALL => flt_i.FILTER_RM_ALL, - FILTER_NEXT => flt_o.FILTER_NEXT, - CNT_ADDRESS => flt_pac_i.CNT_ADDRESS, - PACKET_LENGTH => flt_pac_i.PACKET_LENGTH, - ADD_PACKET => flt_pac_i.ADD_PACKET, - SRC_RDY => flt_pac_i.SRC_RDY, - DST_RDY => flt_pac_o.DST_RDY - ); - - --Generate clock - clk_gen_p : process - begin - CLK <= '1'; - wait for clkper/2; - CLK <= '0'; - wait for clkper/2; - end process clk_gen_p; - - --Generate reset - reset_gen : process - begin - RESET <= '1'; - wait for reset_time; - RESET <= '0'; - wait; - end process; - - -- Simulating input flow - input_flow : process - begin - init(mi_i, tr_num_i, flt_pac_i, flt_i); - mi_wr_req(mi_i, 1); - mi_rd_req(mi_i, mi_o); - wait; - end process input_flow; -end architecture; diff --git a/comp/proc/packet_stats/control_modul/synth/Makefile b/comp/proc/packet_stats/control_modul/synth/Makefile deleted file mode 100644 index a6e32592d..000000000 --- a/comp/proc/packet_stats/control_modul/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=CONTROL_STATS - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/proc/packet_stats/pac_stats_top_arch.vhd b/comp/proc/packet_stats/pac_stats_top_arch.vhd deleted file mode 100644 index 966854472..000000000 --- a/comp/proc/packet_stats/pac_stats_top_arch.vhd +++ /dev/null @@ -1,75 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - --- ---------------------------------------------------------------------------- --- ARCHITECTURE DECLARATION -- --- ---------------------------------------------------------------------------- - -architecture full of PAC_STATS is - signal tran_CNT_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - signal tran_PACKET_LENGTH : std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - signal tran_ADD_PACKET : std_logic; - signal tran_RST_COUNTERS : std_logic; -begin - - TRAN_i : entity work.TRANS_STATS - generic map( - PACKET_LENGTH_WD => PACKET_LENGTH_WD, - ADDRESS_WIDTH => ADDRESS_WIDTH - ) - port map( - CLK => CLK, - RESET => RESET, - RM_ADDRESS => RM_ADDRESS, - RM_RD_ENABLE => RM_RD_ENABLE, - RM_REQ => RM_REQ, - IN_CNT_ADDRESS => CNT_ADDRESS, - IN_PACKET_LENGTH => PACKET_LENGTH, - IN_ADD_PACKET => ADD_PACKET, - IN_SRC_RDY => SRC_RDY, - IN_DST_RDY => DST_RDY, - OUT_CNT_ADDRESS => tran_CNT_ADDRESS, - OUT_PACKET_LENGTH => tran_PACKET_LENGTH, - OUT_ADD_PACKET => tran_ADD_PACKET, - OUT_RST_COUNTERS => tran_RST_COUNTERS - ); - - STATS_i : entity work.STATS - generic map ( - EN_DSP => EN_DSP, - NUM_BYTES_WD => NUM_BYTES_WD, - NUM_PACKETS_WD => NUM_PACKETS_WD, - PACKET_LENGTH_WD => PACKET_LENGTH_WD, - REG_OUT => REG_OUT, - ADDRESS_WIDTH => ADDRESS_WIDTH - ) - port map ( - CLK => CLK, - RESET => RESET, - - CNT_ADDRESS => tran_CNT_ADDRESS, - PACKET_LENGTH => tran_PACKET_LENGTH, - ADD_PACKET => tran_ADD_PACKET, - RST_COUNTERS => tran_RST_COUNTERS, - - R_NUM_BYTES => RD_NUM_BYTES, - R_NUM_PACKETS => RD_NUM_PACKETS, - R_VLD => RD_VLD, - R_NEXT => RD_NEXT - ); - -end architecture; diff --git a/comp/proc/packet_stats/pac_stats_top_ent.vhd b/comp/proc/packet_stats/pac_stats_top_ent.vhd deleted file mode 100644 index 06f041ac9..000000000 --- a/comp/proc/packet_stats/pac_stats_top_ent.vhd +++ /dev/null @@ -1,46 +0,0 @@ --- Copyright (C) 2016 CESNET --- Author(s): Mário Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; - -use work.math_pack.all; - -entity PAC_STATS is - generic( - EN_DSP : boolean := true; - NUM_BYTES_WD : integer := 48; - NUM_PACKETS_WD : integer := 48; - PACKET_LENGTH_WD : integer := 16; - REG_OUT : integer := 0; - ADDRESS_WIDTH : integer := 10 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - RM_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - RM_RD_ENABLE : in std_logic; - RM_REQ : in std_logic; - - CNT_ADDRESS : in std_logic_vector(ADDRESS_WIDTH-1 downto 0); - PACKET_LENGTH : in std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - ADD_PACKET : in std_logic; - SRC_RDY : in std_logic; - DST_RDY : out std_logic; - - RD_NUM_BYTES : out std_logic_vector(NUM_BYTES_WD-1 downto 0); - RD_NUM_PACKETS : out std_logic_vector(NUM_PACKETS_WD-1 downto 0); - RD_VLD : out std_logic; - RD_NEXT : in std_logic - ); -end entity; - diff --git a/comp/proc/packet_stats/sim/signals.fdo b/comp/proc/packet_stats/sim/signals.fdo deleted file mode 100644 index 02f554455..000000000 --- a/comp/proc/packet_stats/sim/signals.fdo +++ /dev/null @@ -1,24 +0,0 @@ -# signals.fdo: Include file with signals -# Copyright (C) 2015 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -proc blk_STATS { } { - - global STATS_PATH - add_wave "-noupdate -hex -label RM_ADDRESS " /$STATS_PATH/RM_ADDRESS - add_wave "-noupdate -hex -label RM_REQ " /$STATS_PATH/RM_REQ - add_wave "-noupdate -hex -label CNT_ADDRESS " /$STATS_PATH/CNT_ADDRESS - add_wave "-noupdate -hex -label PACKET_LENGTH " /$STATS_PATH/PACKET_LENGTH - add_wave "-noupdate -hex -label ADD_PACKET " /$STATS_PATH/ADD_PACKET - add_wave "-noupdate -hex -label SRC_RDY " /$STATS_PATH/SRC_RDY - add_wave "-noupdate -hex -label DST_RDY " /$STATS_PATH/DST_RDY - add_wave "-noupdate -hex -label RD_NUM_BYTES " /$STATS_PATH/RD_NUM_BYTES - add_wave "-noupdate -hex -label RD_NUM_PACKETS" /$STATS_PATH/RD_NUM_PACKETS - add_wave "-noupdate -hex -label RD_VLD " /$STATS_PATH/RD_VLD - add_wave "-noupdate -hex -label RD_NEXT " /$STATS_PATH/RD_NEXT -} diff --git a/comp/proc/packet_stats/sim/stats.fdo b/comp/proc/packet_stats/sim/stats.fdo deleted file mode 100644 index 936ce8ca0..000000000 --- a/comp/proc/packet_stats/sim/stats.fdo +++ /dev/null @@ -1,30 +0,0 @@ -# editor.fdo: Simulation script -# Copyright (C) 2015 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# For whole design testing -set FIRMWARE_BASE "../../../.." -set STATS_BASE "$OFM_PATH/comp/proc/packet_stats" - -set TB_FILE "$STATS_BASE/sim/testbench.vhd" -set SIG_FILE "$STATS_BASE/sim/stats_sig.fdo" - -# Modules definition -set COMPONENTS [list \ - [list "PAC_STATS" $STATS_BASE "FULL"] \ - ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 10010000ns diff --git a/comp/proc/packet_stats/sim/stats_sig.fdo b/comp/proc/packet_stats/sim/stats_sig.fdo deleted file mode 100644 index e8758bd6a..000000000 --- a/comp/proc/packet_stats/sim/stats_sig.fdo +++ /dev/null @@ -1,20 +0,0 @@ -# editor_sig.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths -set TB_PATH "/testbench" -set STATS_PATH "/testbench/uut" - -# include signals -source "signals.fdo" - - -add wave -noupdate -label RESET -color magenta $TB_PATH/reset -add wave -noupdate -label CLK -color magenta $TB_PATH/clk -blk_STATS diff --git a/comp/proc/packet_stats/sim/testbench.vhd b/comp/proc/packet_stats/sim/testbench.vhd deleted file mode 100644 index b9a7ce043..000000000 --- a/comp/proc/packet_stats/sim/testbench.vhd +++ /dev/null @@ -1,195 +0,0 @@ --- # Copyright (C) 2016 CESNET --- # Author: Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -use work.math_pack.all; - -entity testbench is - -end testbench; - -architecture behavioral of testbench is - - constant clkper : time := 10 ns; --Clock period - constant reset_time : time := 2*clkper + 0.2 ns; --Reset durati - - constant EN_DSP : boolean := true; - constant NUM_BYTES_WD : integer := 48; - constant NUM_PACKETS_WD : integer := 48; - constant PACKET_LENGTH_WD : integer := 16; - constant REG_OUT : integer := 0; - constant ADDRESS_WIDTH : integer := 10; - - type ifc_t is record - RM_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - RM_RD_ENABLE : std_logic; - RM_REQ : std_logic; - CNT_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0); - PACKET_LENGTH : std_logic_vector(PACKET_LENGTH_WD-1 downto 0); - ADD_PACKET : std_logic; - SRC_RDY : std_logic; - RD_NEXT : std_logic; - end record; - - signal CLK : std_logic; - signal RESET : std_logic; - - signal ifc : ifc_t; - signal DST_RDY : std_logic; - signal RD_NUM_BYTES : std_logic_vector(NUM_BYTES_WD-1 downto 0); - signal RD_NUM_PACKETS : std_logic_vector(NUM_PACKETS_WD-1 downto 0); - signal RD_VLD : std_logic; - - procedure init (signal ifc : out ifc_t) is - begin - ifc.RM_ADDRESS <= (others => '0'); - ifc.RM_REQ <= '0'; - ifc.CNT_ADDRESS <= (others => '0'); - ifc.PACKET_LENGTH <= (others => '0'); - ifc.ADD_PACKET <= '0'; - ifc.SRC_RDY <= '0'; - ifc.RD_NEXT <= '1'; - wait for reset_time; - wait for clkper; - end procedure; - - procedure send_rm ( - read : in boolean; - address : in integer; - signal ifc : out ifc_t - ) is - begin - ifc.RM_ADDRESS <= conv_std_logic_vector(address, ADDRESS_WIDTH); - ifc.RM_REQ <= '1'; - if(read = false) then - ifc.RM_RD_ENABLE <= '0'; - else - ifc.RM_RD_ENABLE <= '1'; - end if; - ifc.SRC_RDY <= '1'; - wait for clkper; - ifc.RM_REQ <= '0'; - ifc.SRC_RDY <= '0'; - end procedure; - - procedure send_pac ( - num : in integer; - address : in integer; - length : in integer; - signal ifc : out ifc_t - ) is - begin - for I in 0 to num-1 loop - ifc.CNT_ADDRESS <= conv_std_logic_vector(address, ADDRESS_WIDTH); - ifc.PACKET_LENGTH <= conv_std_logic_vector(length, PACKET_LENGTH_WD); - ifc.ADD_PACKET <= '1'; - ifc.SRC_RDY <= '1'; - wait for clkper; - ifc.SRC_RDY <= '0'; - end loop; - end procedure; - - procedure combine_test ( - base_address : in integer; - signal ifc : out ifc_t - ) is - type int_array is array(0 to 5-1) of integer; - variable num : integer := 10; - variable addrs : int_array; - begin - for I7 in 0 to num-1 loop - send_rm(true, base_address + I7, ifc); - end loop; - - for I1 in 0 to num-1 loop - addrs(0) := I1; - for I2 in 0 to num-1 loop - addrs(1) := I2; - for I3 in 0 to num-1 loop - addrs(2) := I3; - for I4 in 0 to num-1 loop - addrs(3) := I4; - for I5 in 0 to num-1 loop - addrs(4) := I5; - - for I6 in 0 to 5-1 loop - send_pac(1, base_address + addrs(I6), addrs(I6)+1, ifc); - end loop; - - end loop; - end loop; - end loop; - end loop; - end loop; - - for I8 in 0 to num-1 loop - send_rm(true, base_address + I8, ifc); - end loop; - - for I8 in 0 to num-1 loop - send_rm(true, base_address + I8, ifc); - end loop; - end procedure; - -begin - - -- packet editor - uut : entity work.PAC_STATS - generic map ( - EN_DSP => EN_DSP, - NUM_BYTES_WD => NUM_BYTES_WD, - NUM_PACKETS_WD => NUM_PACKETS_WD, - PACKET_LENGTH_WD => PACKET_LENGTH_WD, - ADDRESS_WIDTH => ADDRESS_WIDTH - ) - port map ( - CLK => CLK, - RESET => RESET, - RM_ADDRESS => ifc.RM_ADDRESS, - RM_RD_ENABLE => ifc.RM_RD_ENABLE, - RM_REQ => ifc.RM_REQ, - CNT_ADDRESS => ifc.CNT_ADDRESS, - PACKET_LENGTH => ifc.PACKET_LENGTH, - ADD_PACKET => ifc.ADD_PACKET, - SRC_RDY => ifc.SRC_RDY, - DST_RDY => DST_RDY, - RD_NUM_BYTES => RD_NUM_BYTES, - RD_NUM_PACKETS => RD_NUM_PACKETS, - RD_VLD => RD_VLD, - RD_NEXT => ifc.RD_NEXT - ); - - --Generate clock - clk_gen_p : process - begin - CLK <= '1'; - wait for clkper/2; - CLK <= '0'; - wait for clkper/2; - end process clk_gen_p; - - --Generate reset - reset_gen : process - begin - RESET <= '1'; - wait for reset_time; - RESET <= '0'; - wait; - end process; - - -- Simulating input flow - input_flow : process - begin - init(ifc); - combine_test(400, ifc); - wait; - end process input_flow; -end architecture; diff --git a/comp/proc/packet_stats/synth/Makefile b/comp/proc/packet_stats/synth/Makefile deleted file mode 100644 index 92afbfa90..000000000 --- a/comp/proc/packet_stats/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=PAC_STATS - -.PHONY: all -all: comp - -include ../../../../build/Makefile diff --git a/comp/proc/rate_limiter/Modules.tcl b/comp/proc/rate_limiter/Modules.tcl deleted file mode 100644 index ae15fa736..000000000 --- a/comp/proc/rate_limiter/Modules.tcl +++ /dev/null @@ -1,19 +0,0 @@ -# Modules.tcl: Component include tcl script. -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause - -set MEM "$OFM_PATH/comp/base/mem/dp_bmem_V7" -set CORE "$COMP_BASE/proc/rate_limiter/rate_limiter_core" - -set PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd" -set COMPONENTS [ list \ - [ list "DP_BRAM_V7" $MEM "STRUCTUAL" ] \ - [ list "RATE_LIM_MEM" $CORE "STRUCTUAL" ] \ - ] - -set MOD "$MOD $ENTITY_BASE/rate_limiter_mi32_ent.vhd" -set MOD "$MOD $ENTITY_BASE/rate_limiter_mi32_arch.vhd" -set MOD "$MOD $ENTITY_BASE/rate_limiter_top_ent.vhd" -set MOD "$MOD $ENTITY_BASE/rate_limiter_top_arch.vhd" diff --git a/comp/proc/rate_limiter/rate_limiter_core/Modules.tcl b/comp/proc/rate_limiter/rate_limiter_core/Modules.tcl deleted file mode 100644 index aa81cb17e..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/Modules.tcl +++ /dev/null @@ -1,24 +0,0 @@ -# Modules.tcl: Component include tcl script. -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause - -set ALU "$OFM_PATH/comp/base/logic/alu" -set CMP "$OFM_PATH/comp/base/logic/cmp" -set MUL48 "$OFM_PATH/comp/base/logic/mul48" -set CNT "$OFM_PATH/comp/base/logic/cnt" -set MEM "$OFM_PATH/comp/base/mem/dp_bmem_V7" - -set PACKAGES "$CNT/cnt_types.vhd" -set COMPONENTS [ list \ - [ list "ALU_DSP" $ALU "STRUCTUAL" ] \ - [ list "CMP_DSP" $CMP "STRUCTUAL" ] \ - [ list "MUL48" $MUL48 "STRUCTUAL" ] \ - [ list "CNT" $CNT "FULL" ] \ - [ list "DP_BRAM_V7" $MEM "STRUCTUAL" ] \ - ] - -set MOD "$MOD $ENTITY_BASE/rate_limiter_core_ent.vhd" -set MOD "$MOD $ENTITY_BASE/rate_limiter_core_arch.vhd" -set MOD "$MOD $ENTITY_BASE/rate_limiter_mem.vhd" diff --git a/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_core_arch.vhd b/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_core_arch.vhd deleted file mode 100644 index 9ed881350..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_core_arch.vhd +++ /dev/null @@ -1,472 +0,0 @@ --- rate_limiter_core_arch.vhd ---! ---! \file rate_limiter_core_arch.vhd ---! \brief The packet flow rate limiter, based on connection speed and tokens ---! Core component with arithmetic operations ---! DSP component are used for those arithmetic operations ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -architecture limiter of rate_lim is - - constant bucket_width : integer := SPEED_WIDTH + LIMIT_WIDTH; - constant delta_width : integer := 64; - - signal delta_t : std_logic_vector(63 downto 0); - signal bucket_limit_t : std_logic_vector(47 downto 0); - signal needed_tokens : std_logic_vector(47 downto 0); - signal new_tokens : std_logic_vector((delta_width+CONST_WIDTH-1) downto 0); - signal token_level : std_logic_vector((delta_width+CONST_WIDTH) downto 0); - signal bucket_level : std_logic_vector((delta_width+CONST_WIDTH) downto 0); - signal flag : std_logic; - signal carry : std_logic; - - signal zeros : std_logic_vector(63 downto 0); - signal zero : std_logic; - signal one : std_logic; - signal add : std_logic_vector(3 downto 0); - signal sub : std_logic_vector(3 downto 0); - - signal add_b : std_logic_vector((delta_width+CONST_WIDTH-1) downto 0); - signal sub_b : std_logic_vector(delta_width+CONST_WIDTH downto 0); - signal speed_25 : std_logic_vector(24 downto 0); - signal bucket_lim_18 : std_logic_vector(17 downto 0); - signal packet_len_18 : std_logic_vector(17 downto 0); - signal cmp_a : std_logic_vector((delta_width+CONST_WIDTH) downto 0); - signal sel : std_logic_vector(1 downto 0); - - signal stage1_en : std_logic; - signal stage2_en : std_logic; - signal stage3_en : std_logic; - signal stage4_en : std_logic; - signal stage5_en : std_logic; - signal stage6_en : std_logic; - signal stage7_en : std_logic; - - signal reg1_in_src_rdy : std_logic; - signal reg2_in_src_rdy : std_logic; - signal reg3_in_src_rdy : std_logic; - signal reg4_in_src_rdy : std_logic; - signal reg5_in_src_rdy : std_logic; - signal reg6_in_src_rdy : std_logic; - signal reg_in_src_rdy : std_logic; - - signal reg1_packet_ts : std_logic_vector(63 downto 0); - signal reg2_packet_ts : std_logic_vector(63 downto 0); - signal reg3_packet_ts : std_logic_vector(63 downto 0); - signal reg4_packet_ts : std_logic_vector(63 downto 0); - signal reg5_packet_ts : std_logic_vector(63 downto 0); - signal reg6_packet_ts : std_logic_vector(63 downto 0); - signal reg_packet_ts : std_logic_vector(63 downto 0); - - signal reg1_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal reg2_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal reg3_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal reg4_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal reg5_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal reg6_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal reg_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - - signal reg1_addr_vld : std_logic; - signal reg2_addr_vld : std_logic; - signal reg3_addr_vld : std_logic; - signal reg4_addr_vld : std_logic; - signal reg5_addr_vld : std_logic; - signal reg6_addr_vld : std_logic; - signal reg_addr_vld : std_logic; - - signal reg1_b_value : std_logic_vector(bucket_width-1 downto 0); - signal reg2_b_value : std_logic_vector(bucket_width-1 downto 0); - signal reg3_b_value : std_logic_vector(bucket_width-1 downto 0); - signal reg4_b_value : std_logic_vector(bucket_width-1 downto 0); - signal reg_b_value : std_logic_vector(bucket_width-1 downto 0); - - signal reg3_b_lim : std_logic_vector(bucket_width-1 downto 0); - signal reg4_b_lim : std_logic_vector(bucket_width-1 downto 0); - signal reg5_b_lim : std_logic_vector(bucket_width-1 downto 0); - signal reg6_b_lim : std_logic_vector(bucket_width-1 downto 0); - signal reg_b_lim : std_logic_vector(bucket_width-1 downto 0); - - signal reg_time_const : std_logic_vector(CONST_WIDTH-1 downto 0); - - signal reg3_needed_tokens : std_logic_vector(bucket_width-1 downto 0); - signal reg4_needed_tokens : std_logic_vector(bucket_width-1 downto 0); - signal reg5_needed_tokens : std_logic_vector(bucket_width-1 downto 0); - signal reg_needed_tokens : std_logic_vector(bucket_width-1 downto 0); - -begin - - zeros <= X"0000000000000000"; - zero <= '0'; - one <= '1'; - --! ALU modes - add <= "0000"; - sub <= "0001"; - - --! Pipeline enable/disable logic - DST/SRC ready propagation - IN_DST_RDY <= stage1_en; - stage1_en <= '0' when stage2_en = '0' and reg1_in_src_rdy = '1' else - '1'; - stage2_en <= stage3_en; - stage3_en <= stage4_en; - stage4_en <= stage5_en; - -- stage2_en <= '0' when stage3_en = '0' and reg2_in_src_rdy = '1' else - -- '1'; - -- stage3_en <= '0' when stage4_en = '0' and reg3_in_src_rdy = '1' else - -- '1'; - -- stage4_en <= '0' when stage5_en = '0' and reg4_in_src_rdy = '1' else - -- '1'; - stage5_en <= '0' when stage6_en = '0' and reg5_in_src_rdy = '1' else - '1'; - stage6_en <= '0' when stage7_en = '0' and reg6_in_src_rdy = '1' else - '1'; - stage7_en <= '0' when OUT_DST_RDY = '0' and reg_in_src_rdy = '1' else - '1'; - - --! Pipeline - --! stage 1 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg1_in_src_rdy <= '0'; - reg1_packet_ts <= (others => '0'); - reg1_addr <= (others => '0'); - reg1_b_value <= (others => '0'); - reg_time_const <= (others => '0'); - reg1_addr_vld <= '0'; - elsif stage1_en = '1' then - reg1_in_src_rdy <= IN_SRC_RDY; - reg1_packet_ts <= PACKET_TS; - reg1_addr <= RECORD_ADDR; - reg1_addr_vld <= ADDR_VLD; - reg1_b_value <= BUCKET_VALUE; - reg_time_const <= TIME_CONST; - end if; - end if; - end process; - --! stage 2 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg2_in_src_rdy <= '0'; - reg2_packet_ts <= (others => '0'); - reg2_addr <= (others => '0'); - reg2_b_value <= (others => '0'); - reg2_addr_vld <= '0'; - elsif stage2_en = '1' then - reg2_in_src_rdy <= reg1_in_src_rdy; - reg2_packet_ts <= reg1_packet_ts; - reg2_addr <= reg1_addr; - reg2_addr_vld <= reg1_addr_vld; - reg2_b_value <= reg1_b_value; - end if; - end if; - end process; - --! stage 3 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg3_in_src_rdy <= '0'; - reg3_packet_ts <= (others => '0'); - reg3_addr <= (others => '0'); - reg3_b_value <= (others => '0'); - reg3_b_lim <= (others => '0'); - reg3_needed_tokens <= (others => '0'); - reg3_addr_vld <= '0'; - elsif stage3_en = '1' then - reg3_in_src_rdy <= reg2_in_src_rdy; - reg3_packet_ts <= reg2_packet_ts; - reg3_addr <= reg2_addr; - reg3_addr_vld <= reg2_addr_vld; - reg3_b_value <= reg2_b_value; - reg3_b_lim <= bucket_limit_t(bucket_width-1 downto 0); - reg3_needed_tokens <= needed_tokens(bucket_width-1 downto 0); - end if; - end if; - end process; - --! stage 4 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg4_in_src_rdy <= '0'; - reg4_packet_ts <= (others => '0'); - reg4_addr <= (others => '0'); - reg4_b_value <= (others => '0'); - reg4_b_lim <= (others => '0'); - reg4_needed_tokens <= (others => '0'); - reg4_addr_vld <= '0'; - elsif stage4_en = '1' then - reg4_in_src_rdy <= reg3_in_src_rdy; - reg4_packet_ts <= reg3_packet_ts; - reg4_addr <= reg3_addr; - reg4_addr_vld <= reg3_addr_vld; - reg4_b_value <= reg3_b_value; - reg4_b_lim <= reg3_b_lim; - reg4_needed_tokens <= reg3_needed_tokens; - end if; - end if; - end process; - --! stage 5 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg5_in_src_rdy <= '0'; - reg5_packet_ts <= (others => '0'); - reg5_addr <= (others => '0'); - reg_b_value <= (others => '0'); - reg5_b_lim <= (others => '0'); - reg5_needed_tokens <= (others => '0'); - reg5_addr_vld <= '0'; - elsif stage5_en = '1' then - reg5_in_src_rdy <= reg4_in_src_rdy; - reg5_packet_ts <= reg4_packet_ts; - reg5_addr <= reg4_addr; - reg5_addr_vld <= reg4_addr_vld; - reg_b_value <= reg4_b_value; - reg5_b_lim <= reg4_b_lim; - reg5_needed_tokens <= reg4_needed_tokens; - end if; - end if; - end process; - --! stage 6 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg6_in_src_rdy <= '0'; - reg6_packet_ts <= (others => '0'); - reg6_addr <= (others => '0'); - reg6_b_lim <= (others => '0'); - reg_needed_tokens <= (others => '0'); - reg6_addr_vld <= '0'; - elsif stage6_en = '1' then - reg6_in_src_rdy <= reg5_in_src_rdy; - reg6_packet_ts <= reg5_packet_ts; - reg6_addr <= reg5_addr; - reg6_addr_vld <= reg5_addr_vld; - reg6_b_lim <= reg5_b_lim; - reg_needed_tokens <= reg5_needed_tokens; - end if; - end if; - end process; - --! stage 7 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_in_src_rdy <= '0'; - reg_packet_ts <= (others => '0'); - reg_addr <= (others => '0'); - reg_b_lim <= (others => '0'); - reg_addr_vld <= '0'; - elsif stage7_en = '1' then - reg_in_src_rdy <= reg6_in_src_rdy; - reg_packet_ts <= reg6_packet_ts; - reg_addr <= reg6_addr; - reg_addr_vld <= reg6_addr_vld; - reg_b_lim <= reg6_b_lim; - end if; - end if; - end process; - - OUT_SRC_RDY <= reg_in_src_rdy; - - --! difference between time stemps - ---------------------------------------------------------------------------- - -- delta_t <= PACKET_TS - BUCKET_TS; - ---------------------------------------------------------------------------- - SUB1_inst: entity work.ALU_DSP - generic map ( - DATA_WIDTH => 64, - REG_IN => 0, - REG_OUT => 1 - ) - port map ( - CLK => CLK, - RESET => RESET, - A => PACKET_TS, - B => BUCKET_TS, - CE_IN => one, - CE_OUT => stage1_en, - ALUMODE => sub, - CARRY_IN => zero, - CARRY_OUT => open, - P => delta_t - ); - - --! time is converted to tokens - ---------------------------------------------------------------------------- - -- new_tokens <= delta_t * reg_time_const; - ---------------------------------------------------------------------------- - - MUL64_inst: entity work.MUL_DSP - generic map ( - A_DATA_WIDTH => CONST_WIDTH, - B_DATA_WIDTH => delta_width, - REG_IN => 1, - REG_OUT => 1 - ) - port map ( - CLK => CLK, - RESET => RESET, - A => reg_time_const, - B => delta_t, - CE => stage5_en, - P => new_tokens - ); - - --! BUCKET_LIMIT in bytes converted to tokens - ---------------------------------------------------------------------------- - -- bucket_limit_t <= BUCKET_LIMIT * SPEED; - ---------------------------------------------------------------------------- - speed_25 <= (zeros(24 downto SPEED_WIDTH) & SPEED); - bucket_lim_18 <= (zeros(17 downto LIMIT_WIDTH) & BUCKET_LIMIT); - MUL1_inst: entity work.MUL48 - generic map ( - REG_IN => 1, - REG_OUT => 1 - ) - port map ( - CLK => CLK, - RESET => RESET, - A => speed_25, - B => bucket_lim_18, - CE_IN => stage1_en, - CE_OUT => stage2_en, - P => bucket_limit_t - ); - - --! packet of length PACKET_LEN is converted to tokens - ---------------------------------------------------------------------------- - -- needed_tokens <= SPEED * PACKET_LEN; - ---------------------------------------------------------------------------- - packet_len_18 <= (zeros(1 downto 0) & PACKET_LEN); - MUL2_inst: entity work.MUL48 - generic map ( - REG_IN => 1, - REG_OUT => 1 - ) - port map ( - CLK => CLK, - RESET => RESET, - A => speed_25, - B => packet_len_18, - CE_IN => stage1_en, - CE_OUT => stage2_en, - P => needed_tokens - ); - - --! token level is set when packet arrives - ---------------------------------------------------------------------------- - -- token_level <= new_tokens + BUCKET_VALUE - ---------------------------------------------------------------------------- - add_b <= (zeros((delta_width+CONST_WIDTH-bucket_width)-1 downto 0) & reg_b_value); - ADD_inst: entity work.ALU_DSP - generic map ( - DATA_WIDTH => delta_width+CONST_WIDTH, - REG_IN => 0, - REG_OUT => 1 - ) - port map ( - CLK => CLK, - RESET => RESET, - A => std_logic_vector(new_tokens), - B => add_b, - CE_IN => one, - CE_OUT => stage6_en, - ALUMODE => add, - CARRY_IN => zero, - CARRY_OUT => token_level(delta_width+CONST_WIDTH), - P => token_level((delta_width+CONST_WIDTH)-1 downto 0) - ); - - --! packet validity is checked and packet get GREEN(1) or RED(0) flag - ---------------------------------------------------------------------------- - -- bucket_level <= token_level - needed_tokens; - -- flag <= '0' when (bucket_level <= 0) else - -- '1'; - ---------------------------------------------------------------------------- - sub_b <= (zeros((delta_width+CONST_WIDTH-bucket_width) downto 0) & reg_needed_tokens); - SUB2_inst: entity work.ALU_DSP - generic map ( - DATA_WIDTH => delta_width+CONST_WIDTH+1, --! +1 because of CARRY_OUT - REG_IN => 0, - REG_OUT => 1 - ) - port map ( - CLK => CLK, - RESET => RESET, - A => token_level, - B => sub_b, - CE_IN => one, - CE_OUT => stage7_en, - ALUMODE => sub, - CARRY_IN => zero, - CARRY_OUT => carry, - P => bucket_level - ); - - ---------------------------------------------------------------------------- - -- PASS <= flag; - ---------------------------------------------------------------------------- - converted_carry : if ((delta_width+CONST_WIDTH+1) mod 48) = 0 generate - flag <= carry; - end generate; - - normal_carry : if ((delta_width+CONST_WIDTH+1) mod 48) /= 0 generate - flag <= not carry; - end generate; - - PASS <= flag when reg_addr_vld = '1' else - '1'; - - --! rewrite values in bucket - - BUCKET_WE <= flag and reg_in_src_rdy and reg_addr_vld; - RECORD_ADDR_OUT <= reg_addr; - - ---------------------------------------------------------------------------- - -- BUCKET_VAL_OUT <= bucket_limit_t when (bucket_limit_t <= bucket_level ) else - -- bucket_level(bucket_width-1 downto 0); - ---------------------------------------------------------------------------- - cmp_a <= (zeros((delta_width+CONST_WIDTH-bucket_width) downto 0) & reg_b_lim); - CMP_inst: entity work.CMP_DSP - generic map ( - DATA_WIDTH => delta_width+CONST_WIDTH+1, --! +1 because of CARRY_OUT - REG_IN => 0, - REG_OUT => 0 - ) - port map ( - CLK => CLK, - RESET => RESET, - A => cmp_a, - B => bucket_level, - CE_IN => one, - CE_OUT => one, - P => sel - ); - - --! bucket_limit_t <= bucket_level when sel(1) is '1' - BUCKET_VAL_OUT <= reg_b_lim when (sel(1) = '1') else - bucket_level(bucket_width-1 downto 0); - - BUCKET_TS_OUT <= reg_packet_ts; - -end architecture limiter; diff --git a/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_core_ent.vhd b/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_core_ent.vhd deleted file mode 100644 index 771ba469b..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_core_ent.vhd +++ /dev/null @@ -1,57 +0,0 @@ --- rate_limiter_core_ent.vhd ---! ---! \file rate_limiter_core_ent.vhd ---! \brief Interfaces for packet rate limiter ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity rate_lim is - - generic ( - ADDR_WIDTH : integer := 8; - LIMIT_WIDTH : integer := 16; --! maximal value: 17 - SPEED_WIDTH : integer := 20; --! maximal value: 24 - CONST_WIDTH : integer := 10 --! maximal value: 17 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - --! packet info - PACKET_LEN : in std_logic_vector(15 downto 0); - PACKET_TS : in std_logic_vector(63 downto 0); --! time stemp, unit: ns - --! bucket record - RECORD_ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0); - ADDR_VLD : in std_logic; - BUCKET_VALUE : in std_logic_vector(SPEED_WIDTH+LIMIT_WIDTH-1 downto 0); --! amount of avaliable tokens - BUCKET_TS : in std_logic_vector(63 downto 0); --! time stemp, unit: ns - BUCKET_LIMIT : in std_logic_vector(LIMIT_WIDTH-1 downto 0); - SPEED : in std_logic_vector(SPEED_WIDTH-1 downto 0); --! unit: TOKENS per BYTE - TIME_CONST : in std_logic_vector(CONST_WIDTH-1 downto 0); --! unit: TOKENs per ns - - --! packet passed signal - PASS : out std_logic; - --! renew bucket record - BUCKET_WE : out std_logic; - RECORD_ADDR_OUT : out std_logic_vector(ADDR_WIDTH-1 downto 0); - BUCKET_VAL_OUT : out std_logic_vector(SPEED_WIDTH+LIMIT_WIDTH-1 downto 0); - BUCKET_TS_OUT : out std_logic_vector(63 downto 0); - - IN_SRC_RDY : in std_logic; - IN_DST_RDY : out std_logic; - OUT_SRC_RDY : out std_logic; - OUT_DST_RDY : in std_logic - ); - -end entity rate_lim; diff --git a/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_mem.vhd b/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_mem.vhd deleted file mode 100644 index ba431eb17..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/rate_limiter_mem.vhd +++ /dev/null @@ -1,313 +0,0 @@ --- rate_limiter_mem.vhd ---! ---! \file rate_limiter_mem.vhd ---! \brief Memory modul for rate_limiter_core ---! BUCKET_VALUE and BUCKET_TS are saved in BRAMs ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use WORK.cnt_types.all; - --- ----------------------------------------------------------------------------- --- Entity declaration --- ----------------------------------------------------------------------------- -entity rate_lim_mem is - - generic ( - ADDR_WIDTH_M : integer := 8; - LIMIT_WIDTH_M : integer := 16; --! maximal value: 17 - SPEED_WIDTH_M : integer := 20; --! maximal value: 24 - CONST_WIDTH_M : integer := 10 --! maximal value: 17 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - --! packet info - PACKET_LEN : in std_logic_vector(15 downto 0); - PACKET_TS : in std_logic_vector(63 downto 0); --! time stemp, unit: ns - --! bucket record - RECORD_ADDR : in std_logic_vector(ADDR_WIDTH_M-1 downto 0); - ADDR_VLD : in std_logic; - BUCKET_LIMIT : in std_logic_vector(LIMIT_WIDTH_M-1 downto 0); - SPEED : in std_logic_vector(SPEED_WIDTH_M-1 downto 0); --! unit: TOKENS per BYTE - TIME_CONST : in std_logic_vector(CONST_WIDTH_M-1 downto 0); --! unit: TOKENs per ns - - --! packet passed signal - PASS : out std_logic; - - IN_SRC_RDY : in std_logic; - IN_DST_RDY : out std_logic; - OUT_SRC_RDY : out std_logic; - OUT_DST_RDY : in std_logic - ); - -end rate_lim_mem; - --- ----------------------------------------------------------------------------- --- Architecture declaration --- ----------------------------------------------------------------------------- -architecture mem_modul of rate_lim_mem is - - constant bucket_width : integer := SPEED_WIDTH_M + LIMIT_WIDTH_M; - constant data_width : integer := bucket_width + 64; - - signal zeros : std_logic_vector(63 downto 0); - signal zero : std_logic; - signal one : std_logic; - - signal cnt : std_logic_vector(ADDR_WIDTH_M downto 0); - signal init : std_logic; - signal write_init : std_logic_vector(1+ADDR_WIDTH_M+data_width-1 downto 0); - signal write_data : std_logic_vector(1+ADDR_WIDTH_M+data_width-1 downto 0); - signal write_mux_out : std_logic_vector(1+ADDR_WIDTH_M+data_width-1 downto 0); - signal in_src_rdy_check : std_logic; - signal read_enable : std_logic; - - signal data_valid : std_logic; - signal mem_read : std_logic_vector(data_width-1 downto 0); - signal mem_write : std_logic_vector(data_width-1 downto 0); - - signal pass_core : std_logic; - signal bucket_we : std_logic; - signal record_addr_out : std_logic_vector(ADDR_WIDTH_M-1 downto 0); - signal bucket_val_out : std_logic_vector(bucket_width-1 downto 0); - signal bucket_ts_out : std_logic_vector(63 downto 0); - signal in_src_rdy_core : std_logic; - signal in_dst_rdy_core : std_logic; - signal out_src_rdy_core : std_logic; - signal out_dst_rdy_core : std_logic; - - signal stage1_en : std_logic; - signal stage2_en : std_logic; - - signal reg1_addr_vld : std_logic; - signal reg_addr_vld : std_logic; - - signal reg1_in_src_rdy : std_logic; - signal reg_in_src_rdy : std_logic; - - signal reg1_packet_len : std_logic_vector(15 downto 0); - signal reg_packet_len : std_logic_vector(15 downto 0); - - signal reg1_packet_ts : std_logic_vector(63 downto 0); --! time stemp, unit: ns - signal reg_packet_ts : std_logic_vector(63 downto 0); --! time stemp, unit: ns - - signal reg1_record_addr : std_logic_vector(ADDR_WIDTH_M-1 downto 0); - signal reg_record_addr : std_logic_vector(ADDR_WIDTH_M-1 downto 0); - - signal reg1_limit : std_logic_vector(LIMIT_WIDTH_M-1 downto 0); - signal reg_limit : std_logic_vector(LIMIT_WIDTH_M-1 downto 0); - - signal reg1_speed : std_logic_vector(SPEED_WIDTH_M-1 downto 0); --! unit: TOKENS per BYTE - signal reg_speed : std_logic_vector(SPEED_WIDTH_M-1 downto 0); --! unit: TOKENS per BYTE - - signal reg1_const : std_logic_vector(CONST_WIDTH_M-1 downto 0); --! unit: TOKENs per ns - signal reg_const : std_logic_vector(CONST_WIDTH_M-1 downto 0); --! unit: TOKENs per ns - - signal stage1_out_en : std_logic; - signal reg_pass : std_logic; - signal reg_we : std_logic; - signal reg_addr_write : std_logic_vector(ADDR_WIDTH_M-1 downto 0); - signal reg_mem_write : std_logic_vector(data_width-1 downto 0); - signal reg_out_src_rdy : std_logic; - -begin - - zeros <= X"0000000000000000"; - zero <= '0'; - one <= '1'; - - --! MEM init logic, saves zeros to BRAM after RESET - INIT_CNT: entity work.cnt - generic map( - WIDTH => ADDR_WIDTH_M + 1 - ) - port map( - RESET => RESET, - CLK => CLK, - CE => init, - CLR => zero, - DO => cnt - ); - - init <= not cnt(ADDR_WIDTH_M); - --! switch between init and data write mod - write_init <= '1' & cnt(ADDR_WIDTH_M-1 downto 0) & zeros(bucket_width-1 downto 0) & zeros; - write_data <= reg_we & reg_addr_write & reg_mem_write; - write_mux_out <= write_init when init = '1' else - write_data; - - in_src_rdy_check <= IN_SRC_RDY and cnt(ADDR_WIDTH_M); - - read_enable <= in_src_rdy_check and stage1_en; --TODO - - MEM: entity work.DP_BRAM_V7 - generic map( - DATA_WIDTH => data_width, - ADDRESS_WIDTH => ADDR_WIDTH_M, - ENABLE_OUT_REG => true - ) - port map( - -- interface A - reading - CLKA => CLK, - RSTA => RESET, - PIPE_ENA => stage2_en, - REA => read_enable, - WEA => zero, - ADDRA => RECORD_ADDR, - DIA => (others => '0'), - DOA_DV => data_valid, - DOA => mem_read, - -- interface B - writing - CLKB => CLK, - RSTB => RESET, - PIPE_ENB => one, - REB => zero, - WEB => write_mux_out(ADDR_WIDTH_M+data_width), - ADDRB => write_mux_out(ADDR_WIDTH_M+data_width-1 downto data_width), - DIB => write_mux_out(data_width-1 downto 0), - DOB_DV => open, - DOB => open - ); - - --! Pipeline enable/disable logic - DST/SRC ready propagation - -- output IN_DST_RDY signal, component can receive new data after it initialize BRAM - -- and its core can receive data too - IN_DST_RDY <= cnt(ADDR_WIDTH_M) and stage1_en; - stage1_en <= '0' when stage2_en = '0' and reg1_in_src_rdy = '1' else - '1'; - stage2_en <= '0' when in_dst_rdy_core = '0' and reg_in_src_rdy = '1' else - '1'; - - --! Pipeline - input data - --! stage 1 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg1_in_src_rdy <= '0'; - reg1_packet_len <= (others => '0'); - reg1_packet_ts <= (others => '0'); - reg1_record_addr <= (others => '0'); - reg1_limit <= (others => '0'); - reg1_speed <= (others => '0'); - reg1_const <= (others => '0'); - reg1_addr_vld <= '0'; - elsif stage1_en = '1' then - reg1_in_src_rdy <= in_src_rdy_check; - reg1_packet_len <= PACKET_LEN; - reg1_packet_ts <= PACKET_TS; - reg1_record_addr <= RECORD_ADDR; - reg1_addr_vld <= ADDR_VLD; - reg1_limit <= BUCKET_LIMIT; - reg1_speed <= SPEED; - reg1_const <= TIME_CONST; - end if; - end if; - end process; - - --! stage 2 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_in_src_rdy <= '0'; - reg_packet_len <= (others => '0'); - reg_packet_ts <= (others => '0'); - reg_record_addr <= (others => '0'); - reg_limit <= (others => '0'); - reg_speed <= (others => '0'); - reg_const <= (others => '0'); - reg_addr_vld <= '0'; - elsif stage2_en = '1' then - reg_in_src_rdy <= reg1_in_src_rdy; - reg_packet_len <= reg1_packet_len; - reg_packet_ts <= reg1_packet_ts; - reg_record_addr <= reg1_record_addr; - reg_addr_vld <= reg1_addr_vld; - reg_limit <= reg1_limit; - reg_speed <= reg1_speed; - reg_const <= reg1_const; - end if; - end if; - end process; - - in_src_rdy_core <= reg_in_src_rdy and data_valid; - - CORE: entity work.rate_lim - generic map ( - ADDR_WIDTH => ADDR_WIDTH_M, - LIMIT_WIDTH => LIMIT_WIDTH_M, - SPEED_WIDTH => SPEED_WIDTH_M, - CONST_WIDTH => CONST_WIDTH_M - ) - port map ( - CLK => CLK, - RESET => RESET, - PACKET_LEN => reg_packet_len, - PACKET_TS => reg_packet_ts, - RECORD_ADDR => reg_record_addr, - ADDR_VLD => reg_addr_vld, - BUCKET_VALUE => mem_read(data_width-1 downto 64), - BUCKET_TS => mem_read(63 downto 0), - BUCKET_LIMIT => reg_limit, - SPEED => reg_speed, - TIME_CONST => reg_const, - - PASS => pass_core, - BUCKET_WE => bucket_we, - RECORD_ADDR_OUT=> record_addr_out, - BUCKET_VAL_OUT => bucket_val_out, - BUCKET_TS_OUT => bucket_ts_out, - - IN_SRC_RDY => in_src_rdy_core, - IN_DST_RDY => in_dst_rdy_core, - OUT_SRC_RDY => out_src_rdy_core, - OUT_DST_RDY => out_dst_rdy_core - ); - - mem_write <= (bucket_val_out & bucket_ts_out); - - --! Pipeline enable/disable logic - DST/SRC ready propagation - out_dst_rdy_core <= stage1_out_en; - stage1_out_en <= '0' when OUT_DST_RDY = '0' and reg_out_src_rdy = '1' else - '1'; - - --! Pipeline - output data - --! stage 1 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_pass <= '0'; - reg_we <= '0'; - reg_addr_write <= (others => '0'); - reg_mem_write <= (others => '0'); - reg_out_src_rdy <= '0'; - elsif stage1_out_en = '1' then - reg_pass <= pass_core; - reg_we <= bucket_we; - reg_addr_write <= record_addr_out; - reg_mem_write <= mem_write; - reg_out_src_rdy <= out_src_rdy_core; - end if; - end if; - end process; - - PASS <= reg_pass; - - OUT_SRC_RDY <= reg_out_src_rdy; - -end mem_modul; diff --git a/comp/proc/rate_limiter/rate_limiter_core/sim/rate_limiter.fdo b/comp/proc/rate_limiter/rate_limiter_core/sim/rate_limiter.fdo deleted file mode 100644 index 5065d670a..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/sim/rate_limiter.fdo +++ /dev/null @@ -1,30 +0,0 @@ -# rate_limiter.fdo: Simulation script -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# For whole design testing -set FIRMWARE_BASE "../../../../.." -set RATE_LIMITER_BASE "$OFM_PATH/comp/proc/rate_limiter/rate_limiter_core" - -set TB_FILE "$RATE_LIMITER_BASE/sim/testbench.vhd" -set SIG_FILE "$RATE_LIMITER_BASE/sim/rate_limiter_sig.fdo" - -# Modules definition -set COMPONENTS [list \ - [list "rate_limiter" $RATE_LIMITER_BASE "FULL"] \ - ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 2.5us diff --git a/comp/proc/rate_limiter/rate_limiter_core/sim/rate_limiter_sig.fdo b/comp/proc/rate_limiter/rate_limiter_core/sim/rate_limiter_sig.fdo deleted file mode 100644 index 177aa3a3e..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/sim/rate_limiter_sig.fdo +++ /dev/null @@ -1,21 +0,0 @@ -# rate_limiter_sig.fdo : Include file with signals -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths -set TB_PATH "/testbench" -set RATE_LIMITER_PATH "/testbench/uut" - -# Include signals -source "signals.fdo" - -add wave -noupdate -label RESET -color magenta $TB_PATH/RESET -add wave -noupdate -label CLK -color magenta $TB_PATH/CLK - -blk_rate_limiter - diff --git a/comp/proc/rate_limiter/rate_limiter_core/sim/signals.fdo b/comp/proc/rate_limiter/rate_limiter_core/sim/signals.fdo deleted file mode 100644 index ecd8bdbfa..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/sim/signals.fdo +++ /dev/null @@ -1,43 +0,0 @@ -# signals.fdo: Include file with signals -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -proc blk_rate_limiter { } { - - global RATE_LIMITER_PATH - - add wave -divider -height 25 "I/O" - add_wave "-noupdate -uns -label PACKET_LEN" /$RATE_LIMITER_PATH/PACKET_LEN - add_wave "-noupdate -hex -label PACKET_TS" /$RATE_LIMITER_PATH/PACKET_TS - add_wave "-noupdate -uns -label BUCKET_LIMIT" /$RATE_LIMITER_PATH/BUCKET_LIMIT - add_wave "-noupdate -uns -label SPEED" /$RATE_LIMITER_PATH/SPEED - add_wave "-noupdate -uns -label TIME_CONST" /$RATE_LIMITER_PATH/TIME_CONST - add_wave "-noupdate -hex -label PASS" /$RATE_LIMITER_PATH/PASS - add wave -divider -height 25 "SRC/DST RDY" - add_wave "-noupdate -hex -label IN_SRC_RDY" /$RATE_LIMITER_PATH/IN_SRC_RDY - add_wave "-noupdate -hex -label IN_DST_RDY" /$RATE_LIMITER_PATH/IN_DST_RDY - add_wave "-noupdate -hex -label OUT_SRC_RDY" /$RATE_LIMITER_PATH/OUT_SRC_RDY - add_wave "-noupdate -hex -label OUT_DST_RDY" /$RATE_LIMITER_PATH/OUT_DST_RDY - add wave -divider -height 25 "Memory INIT" - add_wave "-noupdate -hex -label init" /$RATE_LIMITER_PATH/init - add_wave "-noupdate -hex -label cnt" /$RATE_LIMITER_PATH/cnt - add_wave "-noupdate -hex -label write_init" /$RATE_LIMITER_PATH/write_init - add wave -divider -height 25 "Memory READ" - add_wave "-noupdate -hex -label read_enable" /$RATE_LIMITER_PATH/read_enable - add_wave "-noupdate -hex -label RECORD_ADDR" /$RATE_LIMITER_PATH/RECORD_ADDR - add_wave "-noupdate -hex -label data_valid" /$RATE_LIMITER_PATH/data_valid - add_wave "-noupdate -hex -label mem_read_addr" /$RATE_LIMITER_PATH/reg_record_addr - add_wave "-noupdate -hex -label mem_read" /$RATE_LIMITER_PATH/mem_read - add wave -divider -height 25 "Memory WRITE" - add_wave "-noupdate -hex -label bucket_we" /$RATE_LIMITER_PATH/bucket_we - add_wave "-noupdate -hex -label record_addr_out" /$RATE_LIMITER_PATH/record_addr_out - add_wave "-noupdate -hex -label mem_write" /$RATE_LIMITER_PATH/mem_write - add_wave "-noupdate -uns -label bucket_val_out" /$RATE_LIMITER_PATH/bucket_val_out - add_wave "-noupdate -uns -label bucket_ts_out" /$RATE_LIMITER_PATH/bucket_ts_out - -} diff --git a/comp/proc/rate_limiter/rate_limiter_core/sim/testbench.vhd b/comp/proc/rate_limiter/rate_limiter_core/sim/testbench.vhd deleted file mode 100644 index 0731f6d39..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/sim/testbench.vhd +++ /dev/null @@ -1,355 +0,0 @@ --- testbench.vhd ---! ---! \file testbench.vhd ---! \brief Testbench for rate_limiter ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity testbench is - -end testbench; - -architecture behavioral of testbench is - - --! simulation constants - constant clkper : time := 10 ns; --Clock period - constant reset_time : time := 2*clkper + 1 ns; --Reset duration - constant ADDR_WIDTH : integer := 4; - constant LIMIT_WIDTH : integer := 16; - constant SPEED_WIDTH : integer := 20; - constant CONST_WIDTH : integer := 10; - - constant time_width : integer := 64; - constant bucket_width : integer := SPEED_WIDTH + LIMIT_WIDTH; - - --! clock and reset signals - signal CLK : std_logic; - signal RESET : std_logic; - - --! input and output - signal PACKET_LEN : std_logic_vector(15 downto 0); - signal PACKET_TS : std_logic_vector(time_width-1 downto 0); - signal RECORD_ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal BUCKET_LIMIT : std_logic_vector(15 downto 0); - signal SPEED : std_logic_vector(SPEED_WIDTH-1 downto 0); - signal TIME_CONST : std_logic_vector(CONST_WIDTH-1 downto 0); - - signal PASS : std_logic; - - signal IN_SRC_RDY : std_logic; - signal IN_DST_RDY : std_logic; - signal OUT_SRC_RDY : std_logic; - signal OUT_DST_RDY : std_logic; - -begin - - --! rate_limiter - core and memory - UUT : entity work.rate_lim_mem - generic map ( - ADDR_WIDTH_M => ADDR_WIDTH, - LIMIT_WIDTH_M => LIMIT_WIDTH, - SPEED_WIDTH_M => SPEED_WIDTH, - CONST_WIDTH_M => CONST_WIDTH - ) - port map ( - CLK => CLK, - RESET => RESET, - - PACKET_LEN => PACKET_LEN, - PACKET_TS => PACKET_TS, - RECORD_ADDR => RECORD_ADDR, - BUCKET_LIMIT => BUCKET_LIMIT, - SPEED => SPEED, - TIME_CONST => TIME_CONST, - - PASS => PASS, - - IN_SRC_RDY => IN_SRC_RDY, - IN_DST_RDY => IN_DST_RDY, - OUT_SRC_RDY => OUT_SRC_RDY, - OUT_DST_RDY => OUT_DST_RDY - ); - - --! generate clock - clk_gen_p : process - begin - CLK <= '1'; - wait for clkper/2; - CLK <= '0'; - wait for clkper/2; - end process clk_gen_p; - - --! generate reset - reset_gen : process - begin - RESET <= '1'; - wait for reset_time; - RESET <= '0'; - wait; - end process; - - --! simulating input flow - input_flow : process - --! flow 1 - --! speed: 30 MB/s, packet length 1024 B - constant flow1_speed : integer := 34133; - constant flow1_len : integer := 1024; - --! speed limit: 3 MB/s - constant flow1_addr : integer := 0; - constant flow1_limit : integer := 1000; - constant flow1_t_const : integer := 3; - --! flow 2 - --! speed: 200 MB/s, packet length 550 B - constant flow2_speed : integer := 2750; - constant flow2_len : integer := 550; - --! speed limit: 10 MB/s - constant flow2_addr : integer := 1; - constant flow2_limit : integer := 100; - constant flow2_t_const : integer := 1; - --! flow 3 - --! speed: 200 MB/s, packet length 550 B - constant flow3_speed : integer := 2750; - constant flow3_len : integer := 550; - --! speed limit: 40 MB/s - constant flow3_addr : integer := 2; - constant flow3_limit : integer := 25; - constant flow3_t_const : integer := 1; - --! flow 4 - --! speed: 200 MB/s, packet length 550 B - constant flow4_speed : integer := 2750; - constant flow4_len : integer := 550; - --! speed limit: 50 MB/s - constant flow4_addr : integer := 3; - constant flow4_limit : integer := 20; - constant flow4_t_const : integer := 1; - --! flow 5 - --! speed: 200 MB/s, packet length 550 B - constant flow5_speed : integer := 2750; - constant flow5_len : integer := 550; - --! speed limit: flow is disabled - constant flow5_addr : integer := 4; - constant flow5_limit : integer := 1; - constant flow5_t_const : integer := 0; - --! flow 6 - --! speed: 200 MB/s, packet length 550 B - constant flow6_speed : integer := 2750; - constant flow6_len : integer := 550; - --! speed limit: flow is disabled - constant flow6_addr : integer := 5; - constant flow6_limit : integer := 1; - constant flow6_t_const : integer := 0; - --! flow 7 - --! speed: 200 MB/s, packet length 550 B - constant flow7_speed : integer := 2750; - constant flow7_len : integer := 550; - --! speed limit: flow is disabled - constant flow7_addr : integer := 6; - constant flow7_limit : integer := 1; - constant flow7_t_const : integer := 0; - --! flow 8 - --! speed: 200 MB/s, packet length 550 B - constant flow8_speed : integer := 2750; - constant flow8_len : integer := 550; - --! speed limit: OFF - constant flow8_addr : integer := 7; - constant flow8_limit : integer := 0; - constant flow8_t_const : integer := 0; - --! flow 9 - --! speed: 200 MB/s, packet length 550 B - constant flow9_speed : integer := 2750; - constant flow9_len : integer := 550; - --! speed limit: OFF - constant flow9_addr : integer := 8; - constant flow9_limit : integer := 0; - constant flow9_t_const : integer := 1; - --! flow 10 - --! speed: 200 MB/s, packet length 550 B - constant flow10_speed : integer := 2750; - constant flow10_len : integer := 550; - --! speed limit: OFF - constant flow10_addr : integer := 9; - constant flow10_limit : integer := 0; - constant flow10_t_const : integer := 1; - --! flow 11 - --! speed: 200 MB/s, packet length 550 B - constant flow11_speed : integer := 2750; - constant flow11_len : integer := 550; - --! speed limit: OFF - constant flow11_addr : integer := 10; - constant flow11_limit : integer := 0; - constant flow11_t_const : integer := 1; - - begin - - --! initialize input interface - IN_SRC_RDY <= '0'; - OUT_DST_RDY <= '1'; - - PACKET_LEN <= std_logic_vector(to_unsigned(1024, PACKET_LEN'length)); - PACKET_TS <= (others => '0'); - RECORD_ADDR <= (others => '0'); - BUCKET_LIMIT <= (others => '1'); - SPEED <= (others => '0'); - TIME_CONST <= std_logic_vector(to_unsigned(1, CONST_WIDTH)); - - wait for reset_time; - - IN_SRC_RDY <= '1'; - - for i in 1 to 20 loop - - --! flow 1 - PACKET_LEN <= std_logic_vector(to_unsigned(flow1_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow1_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow1_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow1_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow1_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 2 - PACKET_LEN <= std_logic_vector(to_unsigned(flow2_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow2_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow2_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow2_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow2_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 3 - PACKET_LEN <= std_logic_vector(to_unsigned(flow3_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow3_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow3_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow3_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow3_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 4 - PACKET_LEN <= std_logic_vector(to_unsigned(flow4_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow4_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow4_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow4_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow4_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 5 - PACKET_LEN <= std_logic_vector(to_unsigned(flow5_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow5_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow5_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow5_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow5_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 6 - PACKET_LEN <= std_logic_vector(to_unsigned(flow6_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow6_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow6_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow6_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow6_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 7 - PACKET_LEN <= std_logic_vector(to_unsigned(flow7_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow7_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow7_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow7_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow7_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 8 - PACKET_LEN <= std_logic_vector(to_unsigned(flow8_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow8_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow8_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow8_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow8_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 9 - PACKET_LEN <= std_logic_vector(to_unsigned(flow9_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow9_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow9_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow9_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow9_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 10 - PACKET_LEN <= std_logic_vector(to_unsigned(flow10_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow10_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow10_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow10_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow10_t_const, CONST_WIDTH)); - - wait for clkper; - - --! flow 11 - PACKET_LEN <= std_logic_vector(to_unsigned(flow11_len, PACKET_LEN'length)); - PACKET_TS <= std_logic_vector(to_unsigned(i*flow11_speed, time_width)); - RECORD_ADDR <= std_logic_vector(to_unsigned(flow11_addr, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow11_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow11_t_const, CONST_WIDTH)); - - wait for clkper; - - end loop; - - IN_SRC_RDY <= '0'; - PACKET_TS <= (others => '0'); - BUCKET_LIMIT <= (others => '1'); - SPEED <= (others => '0'); - TIME_CONST <= (others => '0'); - - wait for clkper*5; - - IN_SRC_RDY <= '1'; - - --! speed and limit are used from flow 2 - - --! token level above BUCKET_LIMIT - --! long time difference - PACKET_LEN <= std_logic_vector(to_unsigned(flow2_len, PACKET_LEN'length)); - PACKET_TS <= x"0000007C00000000"; - RECORD_ADDR <= std_logic_vector(to_unsigned(10, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow2_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow2_t_const, CONST_WIDTH)); - - wait for clkper; - IN_SRC_RDY <= '0'; - wait for clkper; - - IN_SRC_RDY <= '1'; - - --! large BUCKET_LIMIT, high speed limit and long time difference - PACKET_LEN <= std_logic_vector(to_unsigned(flow3_len, PACKET_LEN'length)); - PACKET_TS <= x"000000000000F000"; - RECORD_ADDR <= std_logic_vector(to_unsigned(20, ADDR_WIDTH)); - SPEED <= std_logic_vector(to_unsigned(flow3_limit, SPEED_WIDTH)); - TIME_CONST <= std_logic_vector(to_unsigned(flow3_t_const, CONST_WIDTH)); - - wait for clkper; - - IN_SRC_RDY <= '0'; - - wait; - - end process input_flow; - -end architecture; diff --git a/comp/proc/rate_limiter/rate_limiter_core/synth/Makefile b/comp/proc/rate_limiter/rate_limiter_core/synth/Makefile deleted file mode 100644 index a823c1bc0..000000000 --- a/comp/proc/rate_limiter/rate_limiter_core/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=RATE_LIM_MEM - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/proc/rate_limiter/rate_limiter_mi32_arch.vhd b/comp/proc/rate_limiter/rate_limiter_mi32_arch.vhd deleted file mode 100644 index 6eb70fbd6..000000000 --- a/comp/proc/rate_limiter/rate_limiter_mi32_arch.vhd +++ /dev/null @@ -1,156 +0,0 @@ --- rate_limiter_mi32_arch.vhd ---! ---! \file rate_limiter_mi32_arch.vhd ---! \brief Memory modul with MI32 interface for rate_limiter ---! BUCKET_LIMIT, SPEED and TIME_CONST are saved in BRAMs ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -architecture mi32_interface of rate_lim_mi32 is - - constant data_width : integer := LIMIT_WIDTH + SPEED_WIDTH + CONST_WIDTH; - - constant zeros : std_logic_vector(31 downto 0) := X"00000000"; - constant zero : std_logic := '0'; - constant one : std_logic := '1'; - - signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0); - signal we : std_logic; - signal we_BRAM : std_logic; - signal re_BRAM : std_logic; - signal sel : std_logic_vector(1 downto 0); - signal decoded_part : std_logic_vector(3 downto 0); - signal mux_in_input : std_logic_vector(data_width-1 downto 0); - signal mux_in_read : std_logic_vector(data_width-1 downto 0); - signal mux_reg_data : std_logic_vector(data_width-1 downto 0); - - signal data_read : std_logic; - signal sel_out : std_logic_vector(2 downto 0); - signal limit_out : std_logic_vector(31 downto 0); - signal speed_out : std_logic_vector(31 downto 0); - signal const_out : std_logic_vector(31 downto 0); - signal reg_generics : std_logic_vector(31 downto 0); - - signal reg_limit : std_logic_vector(LIMIT_WIDTH-1 downto 0); - signal reg_speed : std_logic_vector(SPEED_WIDTH-1 downto 0); - signal reg_const : std_logic_vector(CONST_WIDTH-1 downto 0); - signal reg_data_all : std_logic_vector(data_width-1 downto 0); - - function int2vec(int, width: integer) return std_logic_vector is - begin - return std_logic_vector(to_unsigned(int, width)); - end int2vec; - -begin - - addr <= MI32_DWR(ADDR_WIDTH-1 downto 0); - we <= MI32_DWR(31); - sel <= MI32_ADDR(3 downto 2); - -- sel: 00 - write/read limit register - -- 01 - write/read speed register - -- 10 - write/read const register - -- 11 - write/read to/from BRAM, use address in MI32_DWR - - decoded_part <= ("0001") when sel = "00" else - ("0010") when sel = "01" else - ("0100") when sel = "10" else - ("1000"); - - --! Writing logic - - we_BRAM <= decoded_part(3) and MI32_WR and we; - - --! select data for regs - mux_in_input <= (MI32_DWR(LIMIT_WIDTH-1 downto 0)) & (MI32_DWR(SPEED_WIDTH-1 downto 0)) & (MI32_DWR(CONST_WIDTH-1 downto 0)); - mux_reg_data <= mux_in_input when data_read = '0' else - mux_in_read; - - --! Pipeline - write/read data - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_limit <= (others => '0'); - reg_speed <= (others => '0'); - reg_const <= (others => '0'); - else - if ((decoded_part(0) and MI32_WR) or data_read) = '1' then - reg_limit <= mux_reg_data(data_width-1 downto data_width-LIMIT_WIDTH); - end if; - if ((decoded_part(1) and MI32_WR) or data_read) = '1' then - reg_speed <= mux_reg_data(data_width-LIMIT_WIDTH-1 downto CONST_WIDTH); - end if; - if ((decoded_part(2) and MI32_WR) or data_read) = '1' then - reg_const <=mux_reg_data (CONST_WIDTH-1 downto 0); - end if; - end if; - end if; - end process; - - --! Reading logic - - re_BRAM <= decoded_part(3) and MI32_WR and (not we); - - sel_out <= MI32_ADDR(4) & sel; - - limit_out <= zeros(31 downto LIMIT_WIDTH) & reg_limit; - speed_out <= zeros(31 downto SPEED_WIDTH) & reg_speed; - const_out <= zeros(31 downto CONST_WIDTH) & reg_const; - - reg_generics <= int2vec(ADDR_WIDTH, 8) & int2vec(LIMIT_WIDTH, 8) & int2vec(SPEED_WIDTH, 8) & int2vec(CONST_WIDTH, 8); - - MI32_DRD <= limit_out when sel_out = "000" else - speed_out when sel_out = "001" else - const_out when sel_out = "010" else - reg_generics when sel_out = "100" else - (others => '0'); - - MI32_DRDY <= (decoded_part(0) or decoded_part(1) or decoded_part(2)) and MI32_RD; - - reg_data_all <= reg_limit & reg_speed & reg_const; - - MEM_MI32: entity work.DP_BRAM_V7 - generic map( - DATA_WIDTH => data_width, - ADDRESS_WIDTH => ADDR_WIDTH, - ENABLE_OUT_REG => false - ) - port map( - -- interface A - read only - CLKA => CLK, - RSTA => RESET, - PIPE_ENA => one, - REA => USER_RD, - WEA => zero, - ADDRA => USER_ADDR, - DIA => (others => '0'), - DOA_DV => open, - DOA => USER_DRD, - -- interface B - MI32 - CLKB => CLK, - RSTB => RESET, - PIPE_ENB => one, - REB => re_BRAM, - WEB => we_BRAM, - ADDRB => addr, - DIB => reg_data_all, - DOB_DV => data_read, - DOB => mux_in_read - ); - - --! Output - MI32_ARDY <= MI32_RD or MI32_WR; - -end mi32_interface; diff --git a/comp/proc/rate_limiter/rate_limiter_mi32_ent.vhd b/comp/proc/rate_limiter/rate_limiter_mi32_ent.vhd deleted file mode 100644 index c4596039e..000000000 --- a/comp/proc/rate_limiter/rate_limiter_mi32_ent.vhd +++ /dev/null @@ -1,61 +0,0 @@ --- rate_limiter_mi32_ent.vhd ---! ---! \file rate_limiter_mi32_ent.vhd ---! \brief Interfaces for memory unit with limiting constants ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity rate_lim_mi32 is - - generic ( - ADDR_WIDTH : integer := 8; - LIMIT_WIDTH : integer := 16; --! maximal value: 17 - SPEED_WIDTH : integer := 20; --! maximal value: 24 - CONST_WIDTH : integer := 10 --! maximal value: 17 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - - --! MI32 interface - ------------------------------------------------ - --! Address - MI32_ADDR : in std_logic_vector(31 downto 0); - --! Write request - MI32_WR : in std_logic; - --! Input data - MI32_DWR : in std_logic_vector(31 downto 0); - --! Read request - MI32_RD : in std_logic; - --! Output data - MI32_DRD : out std_logic_vector(31 downto 0); - --! Data ready - MI32_DRDY : out std_logic; - --! Address ready - MI32_ARDY : out std_logic; - --! Byte enable - MI32_BE : in std_logic_vector(3 downto 0); - ------------------------------------------------ - - --! User interface - read only - --! Address - USER_ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0); - --! Read request - USER_RD : in std_logic; - --! Output data - USER_DRD : out std_logic_vector(LIMIT_WIDTH+SPEED_WIDTH+CONST_WIDTH-1 downto 0) - ); - -end rate_lim_mi32; diff --git a/comp/proc/rate_limiter/rate_limiter_top_arch.vhd b/comp/proc/rate_limiter/rate_limiter_top_arch.vhd deleted file mode 100644 index 1b143fab8..000000000 --- a/comp/proc/rate_limiter/rate_limiter_top_arch.vhd +++ /dev/null @@ -1,119 +0,0 @@ --- rate_limiter_top_arch.vhd ---! ---! \file rate_limiter_top_arch.vhd ---! \brief The packet flow rate limiter, based on connection speed and tokens ---! Top level architecture ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.math_pack.all; - -architecture top of rate_lim_top is - - constant data_width : integer := LIMIT_WIDTH + SPEED_WIDTH + CONST_WIDTH; - constant addr_width : integer := log2(ITEMS_IN_MEM); - - signal read_enable : std_logic; - signal limit_data : std_logic_vector(data_width-1 downto 0); - - signal stage1_en : std_logic; - signal reg_in_src_rdy : std_logic; - signal reg_addr_vld : std_logic; - signal reg_packet_len : std_logic_vector(15 downto 0); - signal reg_packet_ts : std_logic_vector(63 downto 0); - signal reg_record_addr : std_logic_vector(addr_width-1 downto 0); - - signal in_dst_rdy_mem : std_logic; - -begin - - read_enable <= IN_SRC_RDY and stage1_en; --TODO - - MI32: entity work.rate_lim_mi32 - generic map ( - ADDR_WIDTH => addr_width, - LIMIT_WIDTH => LIMIT_WIDTH, - SPEED_WIDTH => SPEED_WIDTH, - CONST_WIDTH => CONST_WIDTH - ) - port map ( - CLK => CLK, - RESET => RESET, - MI32_ADDR => MI32_ADDR, - MI32_WR => MI32_WR, - MI32_DWR => MI32_DWR, - MI32_RD => MI32_RD, - MI32_DRD => MI32_DRD, - MI32_DRDY => MI32_DRDY, - MI32_ARDY => MI32_ARDY, - MI32_BE => MI32_BE, - - USER_ADDR => RECORD_ADDR, - USER_RD => read_enable, - USER_DRD => limit_data - ); - - --! Pipeline enable/disable logic - DST/SRC ready propagation - IN_DST_RDY <= stage1_en; - stage1_en <= '0' when in_dst_rdy_mem = '0' and reg_in_src_rdy = '1' else - '1'; - - --! Pipeline - input data - --! stage 1 - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_in_src_rdy <= '0'; - reg_packet_len <= (others => '0'); - reg_packet_ts <= (others => '0'); - reg_record_addr <= (others => '0'); - elsif stage1_en = '1' then - reg_in_src_rdy <= IN_SRC_RDY; - reg_packet_len <= PACKET_LEN; - reg_packet_ts <= PACKET_TS; - reg_record_addr <= RECORD_ADDR; - reg_addr_vld <= ADDR_VLD; - end if; - end if; - end process; - - RATE_LIMITER: entity work.rate_lim_mem - generic map ( - ADDR_WIDTH_M => addr_width, - LIMIT_WIDTH_M => LIMIT_WIDTH, - SPEED_WIDTH_M => SPEED_WIDTH, - CONST_WIDTH_M => CONST_WIDTH - ) - port map ( - CLK => CLK, - RESET => RESET, - PACKET_LEN => reg_packet_len, - PACKET_TS => reg_packet_ts, - RECORD_ADDR => reg_record_addr, - ADDR_VLD => reg_addr_vld, - BUCKET_LIMIT => limit_data(data_width-1 downto data_width-LIMIT_WIDTH), - SPEED => limit_data(data_width-LIMIT_WIDTH-1 downto CONST_WIDTH), - TIME_CONST => limit_data(CONST_WIDTH-1 downto 0), - - PASS => PASS, - - IN_SRC_RDY => reg_in_src_rdy, - IN_DST_RDY => in_dst_rdy_mem, - OUT_SRC_RDY => OUT_SRC_RDY, - OUT_DST_RDY => OUT_DST_RDY - ); - -end top; diff --git a/comp/proc/rate_limiter/rate_limiter_top_ent.vhd b/comp/proc/rate_limiter/rate_limiter_top_ent.vhd deleted file mode 100644 index a6e8dd40c..000000000 --- a/comp/proc/rate_limiter/rate_limiter_top_ent.vhd +++ /dev/null @@ -1,70 +0,0 @@ --- rate_limiter_top_ent.vhd ---! ---! \file rate_limiter_top_ent.vhd ---! \brief Interfaces for top architecture of packet rate limiter ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.math_pack.all; - -entity rate_lim_top is - - generic ( - ITEMS_IN_MEM : integer := 1024; - LIMIT_WIDTH : integer := 16; --! maximal value: 17 - SPEED_WIDTH : integer := 20; --! maximal value: 24 - CONST_WIDTH : integer := 10 --! maximal value: 17 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - --! packet info - PACKET_LEN : in std_logic_vector(15 downto 0); - PACKET_TS : in std_logic_vector(63 downto 0); --! time stemp, unit: ns - --! bucket record address - RECORD_ADDR : in std_logic_vector(log2(ITEMS_IN_MEM)-1 downto 0); - ADDR_VLD : in std_logic; - - --! packet passed signal - PASS : out std_logic; - - --! source destination ready interfaces - IN_SRC_RDY : in std_logic; -- source is ready to send data - IN_DST_RDY : out std_logic; -- rate_limiter is ready to receive data - OUT_SRC_RDY : out std_logic; -- rate_limiter is ready to send data - OUT_DST_RDY : in std_logic; -- destination is ready to receive data - - --! MI32 interface - ------------------------------------------------ - --! Address - MI32_ADDR : in std_logic_vector(31 downto 0); - --! Write request - MI32_WR : in std_logic; - --! Input data - MI32_DWR : in std_logic_vector(31 downto 0); - --! Read request - MI32_RD : in std_logic; - --! Output data - MI32_DRD : out std_logic_vector(31 downto 0); - --! Data ready - MI32_DRDY : out std_logic; - --! Address ready - MI32_ARDY : out std_logic; - --! Byte enable - MI32_BE : in std_logic_vector(3 downto 0) - ------------------------------------------------ - ); - -end rate_lim_top; diff --git a/comp/proc/rate_limiter/sim/rate_limiter.fdo b/comp/proc/rate_limiter/sim/rate_limiter.fdo deleted file mode 100644 index d72603def..000000000 --- a/comp/proc/rate_limiter/sim/rate_limiter.fdo +++ /dev/null @@ -1,30 +0,0 @@ -# rate_limiter.fdo: Simulation script -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# For whole design testing -set FIRMWARE_BASE "../../../.." -set RATE_LIMITER_BASE "$OFM_PATH/comp/proc/rate_limiter" - -set TB_FILE "$RATE_LIMITER_BASE/sim/testbench.vhd" -set SIG_FILE "$RATE_LIMITER_BASE/sim/rate_limiter_sig.fdo" - -# Modules definition -set COMPONENTS [list \ - [list "rate_limiter" $RATE_LIMITER_BASE "FULL"] \ - ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 3us diff --git a/comp/proc/rate_limiter/sim/rate_limiter_sig.fdo b/comp/proc/rate_limiter/sim/rate_limiter_sig.fdo deleted file mode 100644 index 177aa3a3e..000000000 --- a/comp/proc/rate_limiter/sim/rate_limiter_sig.fdo +++ /dev/null @@ -1,21 +0,0 @@ -# rate_limiter_sig.fdo : Include file with signals -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths -set TB_PATH "/testbench" -set RATE_LIMITER_PATH "/testbench/uut" - -# Include signals -source "signals.fdo" - -add wave -noupdate -label RESET -color magenta $TB_PATH/RESET -add wave -noupdate -label CLK -color magenta $TB_PATH/CLK - -blk_rate_limiter - diff --git a/comp/proc/rate_limiter/sim/signals.fdo b/comp/proc/rate_limiter/sim/signals.fdo deleted file mode 100644 index 62d5ad6f3..000000000 --- a/comp/proc/rate_limiter/sim/signals.fdo +++ /dev/null @@ -1,43 +0,0 @@ -# signals.fdo: Include file with signals -# Copyright (C) 2015 CESNET -# Author: Jakub Lukac -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -proc blk_rate_limiter { } { - - global RATE_LIMITER_PATH - - add wave -divider -height 25 "I/O" - add_wave "-noupdate -uns -label PACKET_LEN" /$RATE_LIMITER_PATH/PACKET_LEN - add_wave "-noupdate -hex -label PACKET_TS" /$RATE_LIMITER_PATH/PACKET_TS - add_wave "-noupdate -hex -label RECORD_ADDR" /$RATE_LIMITER_PATH/RECORD_ADDR - add_wave "-noupdate -hex -label ADDR_VLD" /$RATE_LIMITER_PATH/ADDR_VLD - add wave -divider -height 25 "Pass" - add_wave "-noupdate -hex -label PASS" /$RATE_LIMITER_PATH/PASS - add wave -divider -height 25 "SRC/DST RDY" - add_wave "-noupdate -hex -label IN_SRC_RDY" /$RATE_LIMITER_PATH/IN_SRC_RDY - add_wave "-noupdate -hex -label IN_DST_RDY" /$RATE_LIMITER_PATH/IN_DST_RDY - add_wave "-noupdate -hex -label OUT_SRC_RDY" /$RATE_LIMITER_PATH/OUT_SRC_RDY - add_wave "-noupdate -hex -label OUT_DST_RDY" /$RATE_LIMITER_PATH/OUT_DST_RDY - add wave -divider -height 25 "MI32" - add_wave "-noupdate -hex -label ADDR" /$RATE_LIMITER_PATH/MI32_ADDR - add_wave "-noupdate -hex -label ARDY" /$RATE_LIMITER_PATH/MI32_ARDY - add wave -divider -height 25 "Write" - add_wave "-noupdate -hex -label WR" /$RATE_LIMITER_PATH/MI32_WR - add_wave "-noupdate -hex -label DWR" /$RATE_LIMITER_PATH/MI32_DWR - add wave -divider -height 25 "Read" - add_wave "-noupdate -hex -label RD" /$RATE_LIMITER_PATH/MI32_RD - add_wave "-noupdate -hex -label DRD" /$RATE_LIMITER_PATH/MI32_DRD - add_wave "-noupdate -hex -label DRDY" /$RATE_LIMITER_PATH/MI32_DRDY - add wave -divider -height 25 "Data" - add_wave "-noupdate -hex -label read_enable" /$RATE_LIMITER_PATH/read_enable - add_wave "-noupdate -hex -label limit_data" /$RATE_LIMITER_PATH/limit_data - add_wave "-noupdate -hex -label stage1_en" /$RATE_LIMITER_PATH/stage1_en - add_wave "-noupdate -hex -label reg_in_src_rdy" /$RATE_LIMITER_PATH/reg_in_src_rdy - add_wave "-noupdate -hex -label in_dst_rdy_mem" /$RATE_LIMITER_PATH/in_dst_rdy_mem - -} diff --git a/comp/proc/rate_limiter/sim/testbench.vhd b/comp/proc/rate_limiter/sim/testbench.vhd deleted file mode 100644 index 28cae0648..000000000 --- a/comp/proc/rate_limiter/sim/testbench.vhd +++ /dev/null @@ -1,515 +0,0 @@ --- testbench.vhd ---! ---! \file testbench.vhd ---! \brief Testbench for rate_limiter ---! ---! \Author: Jakub Lukac ---! \date 2015 ---! ---! \section License ---! ---! Copyright (C) 2015 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.math_pack.all; - -entity testbench is - -end testbench; - -architecture behavioral of testbench is - - --! simulation constants - constant clkper : time := 10 ns; --Clock period - constant reset_time : time := 2*clkper + 1 ns; --Reset duration - constant ITEMS_IN_MEM : integer := 16; - constant LIMIT_WIDTH : integer := 16; - constant SPEED_WIDTH : integer := 20; - constant CONST_WIDTH : integer := 10; - - constant time_width : integer := 64; - constant addr_width : integer := log2(ITEMS_IN_MEM); - - --! clock and reset signals - signal CLK : std_logic; - signal RESET : std_logic; - - --! input and output - signal PACKET_LEN : std_logic_vector(15 downto 0); - signal PACKET_TS : std_logic_vector(time_width-1 downto 0); - signal RECORD_ADDR : std_logic_vector(addr_width-1 downto 0); - - signal PASS : std_logic; - - signal IN_SRC_RDY : std_logic; - signal IN_DST_RDY : std_logic; - signal OUT_SRC_RDY : std_logic; - signal OUT_DST_RDY : std_logic; - - signal ADDR_VLD : std_logic; - - --! MI32 - signal MI32_ADDR : std_logic_vector(31 downto 0); - signal MI32_WR : std_logic; - signal MI32_DWR : std_logic_vector(31 downto 0); - signal MI32_RD : std_logic; - signal MI32_DRD : std_logic_vector(31 downto 0); - signal MI32_DRDY : std_logic; - signal MI32_ARDY : std_logic; - signal MI32_BE : std_logic_vector(3 downto 0); - - function int2vec(int, width: integer) return std_logic_vector is - begin - return std_logic_vector(to_unsigned(int, width)); - end int2vec; - - function decaddr32(addr: integer; pos: std_logic_vector) return std_logic_vector is - variable addr_ret : std_logic_vector(31 downto 0); - constant zeros : std_logic_vector(31 downto 0) := X"00000000"; - begin - addr_ret := zeros(31 downto addr_width+4) & int2vec(addr, addr_width) & pos & zeros(1 downto 0); - return addr_ret; - end decaddr32; - - --! addresses - constant flow1_addr : integer := 0; - constant flow2_addr : integer := 1; - constant flow3_addr : integer := 2; - constant flow4_addr : integer := 3; - constant flow5_addr : integer := 4; - constant flow6_addr : integer := 5; - constant flow7_addr : integer := 6; - constant flow8_addr : integer := 7; - constant flow9_addr : integer := 8; - constant flow10_addr : integer := 9; - constant flow11_addr : integer := 10; - -begin - - --! rate_limiter_top - UUT : entity work.rate_lim_top - generic map ( - ITEMS_IN_MEM => ITEMS_IN_MEM, - LIMIT_WIDTH => LIMIT_WIDTH, - SPEED_WIDTH => SPEED_WIDTH, - CONST_WIDTH => CONST_WIDTH - ) - port map ( - CLK => CLK, - RESET => RESET, - - PACKET_LEN => PACKET_LEN, - PACKET_TS => PACKET_TS, - RECORD_ADDR => RECORD_ADDR, - ADDR_VLD => ADDR_VLD, - - PASS => PASS, - - IN_SRC_RDY => IN_SRC_RDY, - IN_DST_RDY => IN_DST_RDY, - OUT_SRC_RDY => OUT_SRC_RDY, - OUT_DST_RDY => OUT_DST_RDY, - - MI32_ADDR => MI32_ADDR, - MI32_WR => MI32_WR, - MI32_DWR => MI32_DWR, - MI32_RD => MI32_RD, - MI32_DRD => MI32_DRD, - MI32_DRDY => MI32_DRDY, - MI32_ARDY => MI32_ARDY, - MI32_BE => MI32_BE - ); - - --! generate clock - clk_gen_p : process - begin - CLK <= '1'; - wait for clkper/2; - CLK <= '0'; - wait for clkper/2; - end process clk_gen_p; - - --! generate reset - reset_gen : process - begin - RESET <= '1'; - wait for reset_time; - RESET <= '0'; - wait; - end process; - - --! simulating MI32 communication - MI32 : process - --! flow 1 - --! speed limit: 3 MB/s - constant flow1_s_limit : integer := 1000; - constant flow1_t_const : integer := 3; - --! flow 2 - --! speed limit: 10 MB/s - constant flow2_s_limit : integer := 100; - constant flow2_t_const : integer := 1; - --! flow 3 - --! speed limit: 40 MB/s - constant flow3_s_limit : integer := 25; - constant flow3_t_const : integer := 1; - --! flow 4 - --! speed limit: 50 MB/s - constant flow4_s_limit : integer := 20; - constant flow4_t_const : integer := 1; - --! flow 5 - --! speed limit: flow is disabled - constant flow5_s_limit : integer := 1; - constant flow5_t_const : integer := 0; - --! flow 6 - --! speed limit: flow is disabled - constant flow6_s_limit : integer := 1; - constant flow6_t_const : integer := 0; - --! flow 7 - --! speed limit: flow is disabled - constant flow7_s_limit : integer := 1; - constant flow7_t_const : integer := 0; - --! flow 8 - --! speed limit: OFF - constant flow8_s_limit : integer := 0; - constant flow8_t_const : integer := 1; - -- not set !, BRAM is initialized to zeros in simulation - --! flow 9 - --! speed limit: OFF - constant flow9_s_limit : integer := 0; - constant flow9_t_const : integer := 0; - --! flow 10 - --! speed limit: OFF - constant flow10_s_limit : integer := 0; - constant flow10_t_const : integer := 0; - --! flow 11 - --! speed limit: OFF - constant flow11_s_limit : integer := 0; - constant flow11_t_const : integer := 0; - - begin - - --! initialize input interface - MI32_ADDR <= (others => '0'); - MI32_WR <= '0'; - MI32_DWR <= (others => '0'); - MI32_RD <= '0'; - MI32_BE <= (others => '0'); - - wait for reset_time; - - --! initialize BRAM with MI32 interface - - MI32_WR <= '1'; - - --! flow 1 - MI32_ADDR <= decaddr32(flow1_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_ADDR <= decaddr32(flow1_addr, "01"); - MI32_DWR <= int2vec(flow1_s_limit, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow1_addr, "10"); - MI32_DWR <= int2vec(flow1_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow1_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow1_addr, MI32_DWR'length-1); - wait for clkper; - - --! flow 2 - --! write parts in wrong order - MI32_ADDR <= decaddr32(flow2_addr, "01"); - MI32_DWR <= int2vec(flow2_s_limit, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow2_addr, "10"); - MI32_DWR <= int2vec(flow2_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow2_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_ADDR <= decaddr32(flow2_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow2_addr, MI32_DWR'length-1); - wait for clkper; - - --! flow 3 - --! try write one part of item twice - MI32_ADDR <= decaddr32(flow3_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_ADDR <= decaddr32(flow3_addr, "01"); - MI32_DWR <= int2vec(flow3_s_limit, MI32_DWR'length); - wait for clkper; - wait for clkper; --! second attempt - MI32_ADDR <= decaddr32(flow3_addr, "10"); - MI32_DWR <= int2vec(flow3_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow3_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow3_addr, MI32_DWR'length-1); - wait for clkper; - - --! flow 4 - --! interrupted write of one item - MI32_ADDR <= decaddr32(flow4_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_WR <= '0'; - wait for clkper; - MI32_WR <= '1'; - MI32_ADDR <= decaddr32(flow4_addr, "01"); - MI32_DWR <= int2vec(flow4_s_limit, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow4_addr, "10"); - MI32_DWR <= int2vec(flow4_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow4_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow4_addr, MI32_DWR'length-1); - wait for clkper; - - --! flow 5 - MI32_ADDR <= decaddr32(flow5_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_ADDR <= decaddr32(flow5_addr, "01"); - MI32_DWR <= int2vec(flow5_s_limit, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow5_addr, "10"); - MI32_DWR <= int2vec(flow5_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow5_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow5_addr, MI32_DWR'length-1); - wait for clkper; - - --! flow 6 - MI32_ADDR <= decaddr32(flow6_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_ADDR <= decaddr32(flow6_addr, "01"); - MI32_DWR <= int2vec(flow6_s_limit, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow6_addr, "10"); - MI32_DWR <= int2vec(flow6_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow6_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow6_addr, MI32_DWR'length-1); - wait for clkper; - - --! flow 7 - MI32_ADDR <= decaddr32(flow7_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_ADDR <= decaddr32(flow7_addr, "01"); - MI32_DWR <= int2vec(flow7_s_limit, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow7_addr, "10"); - MI32_DWR <= int2vec(flow7_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow7_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow7_addr, MI32_DWR'length-1); - wait for clkper; - - --! flow 8 - MI32_ADDR <= decaddr32(flow8_addr, "00"); - MI32_DWR <= (others => '1'); - wait for clkper; - MI32_ADDR <= decaddr32(flow8_addr, "01"); - MI32_DWR <= int2vec(flow8_s_limit, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow8_addr, "10"); - MI32_DWR <= int2vec(flow8_t_const, MI32_DWR'length); - wait for clkper; - MI32_ADDR <= decaddr32(flow8_addr, "11"); - MI32_DWR <= MI32_WR & int2vec(flow8_addr, MI32_DWR'length-1); - wait for clkper; - - MI32_WR <= '0'; - wait for clkper*5; - - --! read values in BRAM with MI32 interface - - --! read values of flow4 - MI32_WR <= '1'; - MI32_ADDR <= decaddr32(0, "11"); - MI32_DWR <= '0' & int2vec(flow4_addr, MI32_DWR'length-1); - wait for clkper; - MI32_WR <= '0'; - MI32_RD <= '1'; - MI32_ADDR <= decaddr32(0, "00"); - wait for clkper; - MI32_ADDR <= decaddr32(0, "01"); - wait for clkper; - MI32_ADDR <= decaddr32(0, "10"); - wait for clkper; - - MI32_RD <= '0'; - wait for clkper; - - --! read settings of generic parameters - MI32_RD <= '1'; - MI32_ADDR <= x"00000010"; - wait for clkper; - - MI32_RD <= '0'; - - wait; - - end process MI32; - - --! simulating input flow - input_flow : process - --! flow 1 - --! speed: 30 MB/s, packet length 1024 B - constant flow1_speed : integer := 34133; - constant flow1_len : integer := 1024; - --! flow 2 - --! speed: 200 MB/s, packet length 550 B - constant flow2_speed : integer := 2750; - constant flow2_len : integer := 550; - --! flow 3 - --! speed: 200 MB/s, packet length 550 B - constant flow3_speed : integer := 2750; - constant flow3_len : integer := 10240; - --! flow 4 - --! speed: 200 MB/s, packet length 550 B - constant flow4_speed : integer := 2750; - constant flow4_len : integer := 550; - --! flow 5 - --! speed: 200 MB/s, packet length 550 B - constant flow5_speed : integer := 2750; - constant flow5_len : integer := 550; - --! flow 6 - --! speed: 200 MB/s, packet length 550 B - constant flow6_speed : integer := 2750; - constant flow6_len : integer := 550; - --! flow 7 - --! speed: 200 MB/s, packet length 550 B - constant flow7_speed : integer := 2750; - constant flow7_len : integer := 550; - --! flow 8 - --! speed: 200 MB/s, packet length 550 B - constant flow8_speed : integer := 10000; - constant flow8_len : integer := 50; - --! flow 9 - --! speed: 200 MB/s, packet length 550 B - constant flow9_speed : integer := 2750; - constant flow9_len : integer := 550; - --! flow 10 - --! speed: 200 MB/s, packet length 550 B - constant flow10_speed : integer := 2750; - constant flow10_len : integer := 550; - --! flow 11 - --! speed: 200 MB/s, packet length 550 B - constant flow11_speed : integer := 2750; - constant flow11_len : integer := 550; - - begin - - --! initialize input interface - IN_SRC_RDY <= '0'; - OUT_DST_RDY <= '1'; - ADDR_VLD <= '1'; - PACKET_LEN <= int2vec(1024, PACKET_LEN'length); - PACKET_TS <= (others => '0'); - RECORD_ADDR <= (others => '0'); - - wait for reset_time; - - IN_SRC_RDY <= '1'; - - for i in 1 to 25 loop - - if(i >= 15 and i <= 17) then - ADDR_VLD <= '0'; - else - ADDR_VLD <= '1'; - end if; - - --! flow 1 - PACKET_LEN <= int2vec(flow1_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow1_speed, time_width); - RECORD_ADDR <= int2vec(flow1_addr, addr_width); - - wait for clkper; - - --! flow 2 - PACKET_LEN <= int2vec(flow2_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow2_speed, time_width); - RECORD_ADDR <= int2vec(flow2_addr, addr_width); - - wait for clkper; - - --! flow 3 - PACKET_LEN <= int2vec(flow3_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow3_speed, time_width); - RECORD_ADDR <= int2vec(flow3_addr, addr_width); - - wait for clkper; - - --! flow 4 - PACKET_LEN <= int2vec(flow4_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow4_speed, time_width); - RECORD_ADDR <= int2vec(flow4_addr, addr_width); - - wait for clkper; - - --! flow 5 - PACKET_LEN <= int2vec(flow5_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow5_speed, time_width); - RECORD_ADDR <= int2vec(flow5_addr, addr_width); - - wait for clkper; - - --! flow 6 - PACKET_LEN <= int2vec(flow6_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow6_speed, time_width); - RECORD_ADDR <= int2vec(flow6_addr, addr_width); - - wait for clkper; - - --! flow 7 - PACKET_LEN <= int2vec(flow7_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow7_speed, time_width); - RECORD_ADDR <= int2vec(flow7_addr, addr_width); - - wait for clkper; - - --! flow 8 - PACKET_LEN <= int2vec(flow8_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow8_speed, time_width); - RECORD_ADDR <= int2vec(flow8_addr, addr_width); - - wait for clkper; - - --! flow 9 - PACKET_LEN <= int2vec(flow9_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow9_speed, time_width); - RECORD_ADDR <= int2vec(flow9_addr, addr_width); - - wait for clkper; - - --! flow 10 - PACKET_LEN <= int2vec(flow10_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow10_speed, time_width); - RECORD_ADDR <= int2vec(flow10_addr, addr_width); - - wait for clkper; - - --! flow 11 - PACKET_LEN <= int2vec(flow11_len, PACKET_LEN'length); - PACKET_TS <= int2vec(i*flow11_speed, time_width); - RECORD_ADDR <= int2vec(flow11_addr, addr_width); - - wait for clkper; - - end loop; - - IN_SRC_RDY <= '0'; - - wait; - - end process input_flow; - -end architecture; diff --git a/comp/proc/rate_limiter/sw/lib/frl.h b/comp/proc/rate_limiter/sw/lib/frl.h deleted file mode 100644 index f7d74144e..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * \file frl.h - * \author Jakub Lukac - * \date 2015-09 - * \brief Header file for the flow rate limiter(FRL) library - * - * Copyright (C) 2015 CESNET - * - * SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later - * - */ - -#ifndef FRL_H_ -#define FRL_H_ - -#include -#include -#include -#include -#include -#include - -/** - * Data type for one FRL item - */ -typedef struct { - uint32_t b_limit; - uint32_t speed; - uint32_t t_const; - uint32_t item_addr; -} frl_item_t; - -/** - * MSb of item address is used as Write/Read flag - */ -#define WR_FLAG 0x80000000 -#define RD_FLAG 0x7FFFFFFF - -/** - * Address offsets - */ -#define OFFS_BUCKET_LIMIT 0x00000000 -#define OFFS_SPEED 0x00000004 -#define OFFS_TIME_CONST 0x00000008 -#define OFFS_ITEM_ADDR 0x0000000C -#define OFFS_READ_GENS 0x00000010 - -/** - * Masks to extract generic params from 32-bit word - */ -#define GEN_ADDR_W 0xFF000000 -#define GEN_B_LIM_W 0x00FF0000 -#define GEN_SPEED_W 0x0000FF00 -#define GEN_CONST_W 0x000000FF - -/** - * Function type shortcuts - * - * Each function should return zero on success or negative error value - */ -typedef int (*frl_write_func)(uint32_t offs, uint32_t val, void *device_specific_data); -typedef int (*frl_read_func)(uint32_t offs, uint32_t *val_ptr, void *device_specific_data); - -/** - * Generics read and parse - */ -int frl_read_gens(uint32_t *gens, frl_read_func fn, void *device_specific_data); -int frl_get_gen(uint32_t g_mask, uint32_t gens); - -/** - * Set speed limit, covert speed \a s [kBps] to item values and write them - */ -double frl_set_limit(uint32_t s, uint32_t b_l, uint32_t addr, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data); - -/** - * Read item values and covert them to speed limit [kBps] - */ -double frl_read_limit(uint32_t addr, uint32_t *r_b_l, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data); - -/** - * Convert speed limit [kBps] to item parts \a speed and \a t_const - */ -int frl_spdconv(uint32_t s, uint32_t max_s, uint32_t max_t_c, uint32_t *r_speed, uint32_t *r_t_const); - -/** - * Convert item parts \a speed and \a t_const to speed limit [kBps] - */ -double frl_itmconv(uint32_t speed, uint32_t t_const); - -/** - * Turn off FRL for specific flow - */ -int frl_turnoff(uint32_t addr, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data); - -/* Private section - please use functions above */ - -/** - * Write/read item values - */ -int frl_write(frl_item_t *i, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data); -int frl_read(uint32_t addr, frl_item_t *i, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data); - -/** - * Rational approximation - */ -int rat(double x, uint32_t max_num, uint32_t max_denom, uint32_t *r_num, uint32_t *r_denom); - -#endif diff --git a/comp/proc/rate_limiter/sw/lib/frl_get_gen.c b/comp/proc/rate_limiter/sw/lib/frl_get_gen.c deleted file mode 100644 index 1ed1dc9a6..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_get_gen.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * \file frl_get_gen.c - * \author Jakub Lukac - * \date 2015-08 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Parse one of generic parameter from 32-bit word - * \param g_mask Mask to select generic, one of defined mask - * \param gens All generic params as one 32-bit word - * \retval gen Selected generic parameter on success or -1 - */ -int frl_get_gen(uint32_t g_mask, uint32_t gens) -{ - int gen = -1; - gens &= g_mask; - - switch (g_mask) { - case GEN_ADDR_W: - gen = gens >> 24; - break; - case GEN_B_LIM_W: - gen = gens >> 16; - break; - case GEN_SPEED_W: - gen = gens >> 8; - break; - case GEN_CONST_W: - gen = gens; - break; - } - - return gen; -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_itmconv.c b/comp/proc/rate_limiter/sw/lib/frl_itmconv.c deleted file mode 100644 index 65c227d69..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_itmconv.c +++ /dev/null @@ -1,25 +0,0 @@ -/** - * \file frl_itmconv.c - * \author Jakub Lukac - * \date 2015-08 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Convert item speed and t_const to speed limit [kBps] - * \param speed Item speed value - * \param t_const Item time constant value - * \return Speed limit in [kBps] or INFINITY when FRL is turned off - */ -double frl_itmconv(uint32_t speed, uint32_t t_const) -{ - if (speed == 0) { - return INFINITY; /* FRL is turned off */ - } - else { - return ((double)t_const/speed) * 1000000; - } -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_read.c b/comp/proc/rate_limiter/sw/lib/frl_read.c deleted file mode 100644 index abfdd155c..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_read.c +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file frl_read.c - * \author Jakub Lukac - * \date 2015-09 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Read FLR item values from address \a addr - * \param addr Item address - * \param i Reference to an item type, whose values are set by the function - * \param fn_w Write function - * \param fn_r Read function - * \param device_specific_data Pointer to needed device data - * \retval err Zero on success or negative error value - */ -int frl_read(uint32_t addr, frl_item_t *i, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data) -{ - int err = 0; - - /* check validity of addr */ - uint32_t gens; - if ((err = frl_read_gens(&gens, fn_r, device_specific_data)) != 0) { - return err; - } - if (addr >= pow(2, frl_get_gen(GEN_ADDR_W, gens))) { - errno = EINVAL; - return -errno; - } - - /* MSb of reading item address has to be '0' */ - uint32_t r_addr = addr & RD_FLAG; - - /* prepare item values on address addr to reading */ - if ((err = fn_w(OFFS_ITEM_ADDR, r_addr, device_specific_data)) != 0) { return err; } - /* read each value */ - uint32_t b_l, s, t_c; - if ((err = fn_r(OFFS_BUCKET_LIMIT, &b_l, device_specific_data)) != 0) { return err; } - if ((err = fn_r(OFFS_SPEED, &s, device_specific_data)) != 0) { return err; } - if ((err = fn_r(OFFS_TIME_CONST, &t_c, device_specific_data)) != 0) { return err; } - - /* store read values */ - i->b_limit = b_l; - i->speed = s; - i->t_const = t_c; - i->item_addr = addr; - - return err; -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_read_gens.c b/comp/proc/rate_limiter/sw/lib/frl_read_gens.c deleted file mode 100644 index 140f780f2..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_read_gens.c +++ /dev/null @@ -1,21 +0,0 @@ -/** - * \file frl_read_gens.c - * \author Jakub Lukac - * \date 2015-08 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Read all generic params from FRL - * \param gens Reference to an int type, whose value is set by the function - * \param fn Read function - * \param device_specific_data Pointer to needed device data - * \return Zero on success or negative error value of read function - */ -int frl_read_gens(uint32_t *gens, frl_read_func fn, void *device_specific_data) -{ - return fn(OFFS_READ_GENS, gens, device_specific_data); -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_read_limit.c b/comp/proc/rate_limiter/sw/lib/frl_read_limit.c deleted file mode 100644 index d848c18f5..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_read_limit.c +++ /dev/null @@ -1,39 +0,0 @@ -/** - * \file frl_read_limit.c - * \author Jakub Lukac - * \date 2015-08 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Read item speed limit - * \param addr Item address - * \param r_b_l Reference to an int type, whose value is set by the function - * \param fn_w Write function - * \param fn_r Read function - * \param device_specific_data Pointer to needed device data - * \retval limit Converted item speed limit [kBps] on success or INFINITY when FRL is turned off - * \retval err Negative error value, as defined by frl_read - * - * \note - * BUCKET_LIMIT value is returned as *r_b_l unless *r_b_l is NULL - */ -double frl_read_limit(uint32_t addr, uint32_t *r_b_l, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data) -{ - int err = 0; - frl_item_t tmp_item; - - if ((err = frl_read(addr, &tmp_item, fn_w, fn_r, device_specific_data)) != 0) { - return (double)err; - } - - if (r_b_l != NULL) - *r_b_l = tmp_item.b_limit; - - double limit = frl_itmconv(tmp_item.speed, tmp_item.t_const); - - return limit; -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_set_limit.c b/comp/proc/rate_limiter/sw/lib/frl_set_limit.c deleted file mode 100644 index 6deb0a2ee..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_set_limit.c +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file frl_set_limit.c - * \author Jakub Lukac - * \date 2015-09 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Set speed limit - * \param s Speed limit [kBps], positive integer or zero - * \param b_l Bucket value - * \param addr Item address - * \param fn_w Write function - * \param fn_r Read function - * \param device_specific_data Pointer to needed device data - * \retval approx_val Zero on success or positive value of set speed - * \retval err Negative error value, as defined by frl_read or frl_write - * - * \note - * Covert speed \a s [kBps] to item values and then write them - * Speed is set to the best approximation of \a s - */ -double frl_set_limit(uint32_t s, uint32_t b_l, uint32_t addr, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data) -{ - int err = 0; - double approx_val = 0.0; - - uint32_t gens; - if ((err = frl_read_gens(&gens, fn_r, device_specific_data)) != 0) { - return (double)err; - } - uint32_t max_s = pow(2, frl_get_gen(GEN_SPEED_W, gens)); - uint32_t max_t_c = pow(2, frl_get_gen(GEN_CONST_W, gens)); - uint32_t speed; - uint32_t t_const; - - if ((frl_spdconv(s, max_s, max_t_c, &speed, &t_const)) != 0) { - approx_val = (double)t_const/speed; - } - - frl_item_t tmp_item = {.b_limit = b_l, .speed = speed, .t_const = t_const, .item_addr = addr}; - - if ((err = frl_write(&tmp_item, fn_w, fn_r, device_specific_data)) != 0) { - return (double)err; - } - - return approx_val; -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_spdconv.c b/comp/proc/rate_limiter/sw/lib/frl_spdconv.c deleted file mode 100644 index e86d0dc4d..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_spdconv.c +++ /dev/null @@ -1,96 +0,0 @@ -/** - * \file frl_spdconv.c - * \author Jakub Lukac - * \date 2015-09 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Convert speed limit [kBps] to item parts speed and t_const - * Wrapper function for rational approximation - * \param s Speed limit [kBps], positive integer or zero - * \param max_s Maximal speed value - * \param max_t_c Maximal time constant value - * \param r_speed Reference to an int type, whose value is set by the function - * \param r_t_const Reference to an int type, whose value is set by the function - * \retval zero Exact conversion - * \retval one Best approximation of speed \a s - * - * \note - * SPEED value is returned as *r_speed and TIME_CONST value is returned as *r_t_const - */ -int frl_spdconv(uint32_t s, uint32_t max_s, uint32_t max_t_c, uint32_t *r_speed, uint32_t *r_t_const) -{ - return rat((double)s/1000000, max_t_c, max_s, r_t_const, r_speed); -} - -/** - * \brief Rational approximation with numerator and denominator below a given limit - * (farey approximation) - * \param x Value which be converted to fraction - * \param max_num Maximal value of numerator (this not included) - * \param max_denom Maximal value of denominator (this not included) - * \param r_num Reference to an int type, whose value is set by the function - * \param r_denom Reference to an int type, whose value is set by the function - * \retval zero Exact conversion - * \retval one Best approximation of \a x - * - * \note - * Function always return irreducible fraction parts - */ -int rat(double x, uint32_t max_num, uint32_t max_denom, uint32_t *r_num, uint32_t *r_denom) -{ - uint32_t a, b, c, d; - a = floor(x); b = 1; - c = floor(x) + 1; d = 1; - - double mediant; - while (a < max_num && - c < max_num && - b < max_denom && - d < max_denom) { - mediant = (double)(a+c)/(b+d); - - if (x == mediant) { - if (a+c < max_num && b+d < max_denom) { - *r_num = a+c; - *r_denom = b+d; - return 0; - } - else { - *r_num = b > d ? a : c; - *r_denom = b > d ? b : d; - return 1; - } - } - else if (x > mediant) { - *r_num = a; - *r_denom = b; - a = a+c; - b = b+d; - } - else { - *r_num = c; - *r_denom = d; - c = a+c; - d = b+d; - } - } // end while - - if (a < max_num && b < max_denom) { - if (fabs((double)a/b - x) < fabs((double)*r_num/ *r_denom - x)) { - *r_num = a; - *r_denom = b; - } - } - else { - if (fabs((double)c/d - x) < fabs((double)*r_num/ *r_denom - x)) { - *r_num = c; - *r_denom = d; - } - } - return 1; -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_turnoff.c b/comp/proc/rate_limiter/sw/lib/frl_turnoff.c deleted file mode 100644 index 218279fe8..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_turnoff.c +++ /dev/null @@ -1,25 +0,0 @@ -/** - * \file frl_turnoff.c - * \author Jakub Lukac - * \date 2015-08 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Turn off FRL for flow limited by item on address addr - * \param addr Item address - * \param fn_w Write function - * \param fn_r Read function - * \param device_specific_data Pointer to needed device data - * \return Zero on success or negative error value, as defined by frl_read or frl_write - */ -int frl_turnoff(uint32_t addr, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data) -{ - /* item speed value must be zero to turn off FRL */ - frl_item_t tmp_item = {.b_limit = 0, .speed = 0, .t_const = 0, .item_addr = addr}; - - return frl_write(&tmp_item, fn_w, fn_r, device_specific_data); -} diff --git a/comp/proc/rate_limiter/sw/lib/frl_write.c b/comp/proc/rate_limiter/sw/lib/frl_write.c deleted file mode 100644 index bea15c82d..000000000 --- a/comp/proc/rate_limiter/sw/lib/frl_write.c +++ /dev/null @@ -1,46 +0,0 @@ -/** - * \file frl_write.c - * \author Jakub Lukac - * \date 2015-09 - * - * Copyright (C) 2015 CESNET - */ - -#include "frl.h" - -/** - * \brief Write FLR item values on address \a addr - * \param i Pointer to valid item, which should be written - * \param fn_w Write function - * \param fn_r Read function - * \param device_specific_data Pointer to needed device data - * \return Zero on success - * \retval err Zero on success or negative error value - */ -int frl_write(frl_item_t *i, frl_write_func fn_w, frl_read_func fn_r, void *device_specific_data) -{ - int err = 0; - - /* check validity of item values */ - uint32_t gens; - if ((err = frl_read_gens(&gens, fn_r, device_specific_data)) != 0) { - return err; - } - if (i->b_limit >= pow(2, frl_get_gen(GEN_B_LIM_W, gens)) || - i->speed >= pow(2, frl_get_gen(GEN_SPEED_W, gens)) || - i->t_const >= pow(2, frl_get_gen(GEN_CONST_W, gens)) || - i->item_addr >= pow(2, frl_get_gen(GEN_ADDR_W, gens))) { - errno = EINVAL; - return -errno; - } - - /* MSb of writing address has to be '1' */ - uint32_t w_addr = i->item_addr | WR_FLAG; - - if ((err = fn_w(OFFS_BUCKET_LIMIT, i->b_limit, device_specific_data)) != 0) { return err; } - if ((err = fn_w(OFFS_SPEED, i->speed, device_specific_data)) != 0) { return err; } - if ((err = fn_w(OFFS_TIME_CONST, i->t_const, device_specific_data)) != 0) { return err; } - if ((err = fn_w(OFFS_ITEM_ADDR, w_addr, device_specific_data)) != 0) { return err; } - - return err; -} diff --git a/comp/proc/rate_limiter/synth/Makefile b/comp/proc/rate_limiter/synth/Makefile deleted file mode 100644 index 6f1b53587..000000000 --- a/comp/proc/rate_limiter/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=RATE_LIM_TOP - -.PHONY: all -all: comp - -include ../../../../build/Makefile diff --git a/doc/source/logic.rst b/doc/source/logic.rst index 41132ab03..620c19de8 100644 --- a/doc/source/logic.rst +++ b/doc/source/logic.rst @@ -80,8 +80,6 @@ Tries to use as simple adders as the set latency allows. It has a valid bit for **SHIFTER** - Behavioral implementation of left or right block-by-block shifter. -**SQUARER** - The unit is used for calculation square (n^2** of input vector). - **SR_SYNC_LATCH** - Synchronous SR latch whose forbidden state has been removed. Latches data of variable length. Detailed documentation can be found :ref:`here`. **SUM_ONE** - Behavioral implementation of generic counter of ones in input vector. diff --git a/doc/source/memory.rst b/doc/source/memory.rst index c29648f05..25ddb1849 100644 --- a/doc/source/memory.rst +++ b/doc/source/memory.rst @@ -1,8 +1,6 @@ Memory modules ============== -**CAM** - Ternary content addressable memory implemented in memory LUTs, optimized for Xilinx only. Also there is **light variant** implemented using register array, simpler but less effective. - **DP_BMEM** - Behavioral implementation of dual clock BRAM memory with two read/write ports. .. warning:: diff --git a/doc/source/misc.rst b/doc/source/misc.rst index b6c3b7d8e..bcce26a96 100644 --- a/doc/source/misc.rst +++ b/doc/source/misc.rst @@ -3,8 +3,6 @@ Miscellaneous **ADC_SENSORS** - Controller of the Temperature and Voltage ADC IPs for Intel Stratix 10 FPGA. It is controlled via the MI bus. ``CANDIDATE FOR MOVE to CTRLs folder!`` -**CLK_GEN** - Old clock generator, is used in some simulation only. ``CANDIDATE FOR REMOVAL!`` - **CROSSBARX** - This unit performs data transfer between two buffers connected on SRC_BUF and DST_BUF interfaces based on Transactions passed on the TRANS interface. Detailed :ref:`documentation can be found here`. @@ -13,12 +11,8 @@ Detailed :ref:`documentation can be found here`. **EVENT_COUNTER** - The Event Counter is a debuging unit for receiving statistics of occurence frequency of a certain event. It is made accessible through MI interface using the Event Counter MI Wrapper. Detailed :ref:`documentation can be found here`. -**FIFO_PIPE** - Generic pipe implemented using registers and FIFO memory in almost full mode. ``UNUSED, CANDIDATE FOR REMOVAL!`` - **FIRST_ONE_DETECTOR** - Old behavioral implementation of first one detector in vector. ``CANDIDATE FOR REMOVAL! Use FIRST_ONE from base logic!`` -**HYPER_PIPE** - Generic hyper pipe implemented using registers, optimized for Intel Stratix 10 FPGA. ``UNUSED, CANDIDATE FOR REMOVAL!`` - **ID32** - Identification component, is a small component, which is used to detect design inside FPGA. Informations are stored inside registers which are accessible through dedicated 32 bit interface. **INTERRUPT_MANAGER** - Interrupt agregator module, TODO description. @@ -39,8 +33,6 @@ so that they are placed one after another with the needed inter-packet gaps and **TRANS_SORTER** - This unit converts out-of-order confirmations of transactions to the original order of the transactions. Detailed :ref:`documentation can be found here`. -**WATCHDOG** - Data flow watchdog module, which checks whether the monitored bus is not stuck. TODO - .. toctree:: :maxdepth: 1 :hidden: