diff --git a/devel/.buildinfo b/devel/.buildinfo index 7274281f3..5887465b4 100644 --- a/devel/.buildinfo +++ b/devel/.buildinfo @@ -1,4 +1,4 @@ # Sphinx build info version 1 # This file records the configuration used when building these files. When it is not found, a full rebuild will be done. -config: db1c1339d69cc589c6f4db3cbf231b40 +config: 387d82d8e5a626c2378cde45ec213aad tags: 645f666f9bcd5a90fca523b33c5a78b7 diff --git a/devel/_images/ndk_fpga_logo.png b/devel/_images/ndk_fpga_logo.png new file mode 100644 index 000000000..a2838018c Binary files /dev/null and b/devel/_images/ndk_fpga_logo.png differ diff --git a/devel/_sources/base.rst.txt b/devel/_sources/base.rst.txt index 17a3b4dcb..15f6b19af 100644 --- a/devel/_sources/base.rst.txt +++ b/devel/_sources/base.rst.txt @@ -2,7 +2,7 @@ Basic Tools =========== This chapter describes the basic components such as FIFOs, RAMs, multiplexers, encoders, decoders, etc. -The basic components are typically located in the ``comp/base/`` directory in the OFM repository. +The basic components are typically located in the ``comp/base/`` directory in the NDK-FPGA repository. .. toctree:: :maxdepth: 1 @@ -12,6 +12,5 @@ The basic components are typically located in the ``comp/base/`` directory in th memory fifo dsp - shift logic misc diff --git a/devel/_sources/fifo.rst.txt b/devel/_sources/fifo.rst.txt index 549fc5b86..8fab2e755 100644 --- a/devel/_sources/fifo.rst.txt +++ b/devel/_sources/fifo.rst.txt @@ -6,9 +6,17 @@ FIFO components Dual clock (asynchronous) FIFOs ------------------------------- -**ASFIFO** - Behavioral dual clock FIFO implementation based on LUTMEMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use ASFIFOX!`` +**ASFIFO** - Behavioral dual clock FIFO implementation, based on LUTMEMs and optimized for Xilinx only. Includes status signal. -**ASFIFO_BRAM** - Behavioral dual clock FIFO implementation based on BRAMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use ASFIFOX!`` +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **ASFIFOX** instead. + +**ASFIFO_BRAM** - Behavioral dual clock FIFO implementation, based on BRAMs and optimized for Xilinx only. Includes status signal. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **ASFIFOX** instead. **ASFIFO_BRAM_BLOCK** - Similar to ASFIFO_BRAM but with extra signal to mark end of input data block, output remains in empty state until such mark is received. Located in the same folder as ASFIFO_BRAM. @@ -34,13 +42,25 @@ Detailed :ref:`documentation can be found here`. Single clock FIFOs ------------------ -**FIFO** - Behavioral FIFO implementation based on LUTMEMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use FIFOX!`` +**FIFO** - Behavioral FIFO implementation, based on LUTMEMs and optimized for Xilinx only. Includes status signal. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **FIFOX** instead. -**FIFO_BRAM** - Behavioral FIFO implementation based on BRAMs and optimized for Xilinx only. Include status signal. ``OBSOLETE, use FIFOX!`` +**FIFO_BRAM** - Behavioral FIFO implementation, based on BRAMs and optimized for Xilinx only. Includes status signal. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **FIFOX** instead. **FIFO_BRAM_XILINX** - Structural implementation of FIFO based on Xilinx specific BRAM FIFO primitives (no extra logic). Include almost full and almost empty signal. -**FIFO_N1** - Behavioral implementation of FIFO with multiple write ports, it based on LUTMEMs and optimized for Xilinx only. ``OBSOLETE, use FIFOX_MULTI!`` +**FIFO_N1** - Behavioral implementation of FIFO with multiple write ports, it is based on LUTMEMs and optimized for Xilinx only. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **FIFOX** instead. **FIFOX** - Universal FIFO for Xilinx and Intel FPGAs. It support various memory implementation: LUTMEMs, BRAMs, URAMs (Xilinx only) and shift-registers in LUT slices (effective on Xilinx only). Include almost full, almost empty and status signal. Possible automatic selection of a suitable memory implementation. Detailed :ref:`documentation can be found here`. @@ -50,7 +70,11 @@ Include almost full, almost empty and status signal. Possible automatic selectio **MULTI_FIFO** - Behavioral implementation of FIFO for Xilinx and Intel FPGAs with multiple independent channels. It support various memory implementation: LUTMEMs, BRAMs, URAMs (Xilinx only). The memory type is selected automatically. -**SH_FIFO** - Behavioral FIFO implementation based on shift-registers in LUT slices and optimized for Xilinx only. ``OBSOLETE, use FIFOX!`` +**SH_FIFO** - Behavioral FIFO implementation, based on shift-registers in LUT slices and optimized for Xilinx only. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **FIFOX** instead. .. toctree:: :maxdepth: 1 diff --git a/devel/_sources/index.rst.txt b/devel/_sources/index.rst.txt index 7ed52d61e..97c525385 100644 --- a/devel/_sources/index.rst.txt +++ b/devel/_sources/index.rst.txt @@ -1,26 +1,10 @@ -Documentation of Minimal NDK Application -**************************************** +.. currentmodule:: ndk_fpga -**Welcome to documentation of Minimal NDK Application!** +.. image:: img/ndk_fpga_logo.png + :width: 500px -The NDK-APP-Minimal is a reference application based on the Network Development Kit (NDK) for FPGAs. The NDK allows users to quickly and easily develop FPGA-accelerated network applications. The NDK is optimized for high throughput and scalability to support up to 400 Gigabit Ethernet. - -.. image:: img/liberouter_logo.svg - :align: center - :width: 50 % - -The NDK-based Minimal application is a simple example of how to build an FPGA application using the NDK. It can also be a starting point for your NDK-based application. The NDK-based Minimal application does not process network packets in any way; it only sends and receives them. If the DMA IP is enabled (see the :ref:`DMA Module chapter `), then it forwards the network packets to and from the computer memory. - -.. warning:: - - The DMA Medusa IP is not part of the open-source NDK. `You can get the NDK, including the DMA Medusa IP and professional support, through our partner BrnoLogic. `_ - -.. toctree:: - :maxdepth: 2 - :caption: Application: - :hidden: - - app-minimal +Overview +======== .. toctree:: :maxdepth: 2 @@ -36,10 +20,80 @@ The NDK-based Minimal application is a simple example of how to build an FPGA ap ndk_core/doc/devtree ndk_core/doc/faq +The **Network Development Kit (NDK) for FPGAs** is a comprehensive framework designed +for the rapid and efficient development of FPGA-accelerated network applications. Optimized +for scalability and high throughput, the NDK supports speeds up to **400 Gigabit Ethernet**. + +-------- + +The NDK provides a minimal example application. The **NDK Minimal Application** +demonstrates how to build an FPGA application using the NDK and serves as a starting point +for your own development. The minimal application doesn't process network packets; it simply +sends and receives them. If a DMA IP is enabled (see the :ref:`DMA Module `), +the packets are forwarded to and from the host's memory. Otherwise, DMA IP is replaced with +a loopback and packets may be forwarded from RX to TX ethernet interface. + +Other example applications will be added in the future, stay tuned! + .. toctree:: - :maxdepth: 2 - :caption: Supported cards: - :hidden: + :maxdepth: 1 + :caption: Applications + + app-minimal + +-------- + +In addition, the NDK provides a collection of reusable components, some of which are vendor and +vendor- and tool-independent, while others are optimized for specific FPGA vendors and architectures. +For transferring packets (frames) and auxiliary data at such high rates, the NDK uses its own set of what are called +"multibuses" that can transfer multiple frames and values, respectively, within a single clock cycle. +For details on these protocols, see the specifications for the :ref:`Multi Value Bus` and +:ref:`Multi Frame Bus`. + +To simplify module development, the NDK includes components for common operations on these buses, +multiplexers, FIFOs, BRAMs and lookup tables. To improve compatibility with other popular buses, +it also provides converters: + +* MFB to AXI stream, +* MFB to Avalon stream, +* MI to Avalon MM, +* MI to AXI4, +* MVB to MFB. + +.. toctree:: + :maxdepth: 1 + :caption: Reusable Modules Library + + base + ctrls + mi + mfb + mvb + nic + pcie + debug + ver + +-------- + +.. toctree :: + :maxdepth: 1 + :caption: Bus Specifications + + comp/mi_tools/readme + comp/mvb_tools/readme + comp/mfb_tools/readme + +-------- + +The NDK supports a wide range of FPGA cards, providing access to features such as DDR and HBM +memories, PCIe, and Ethernet in your applications. However, different applications may only +support a subset of these cards. A complete list of supported FPGA cards can be found below +(minimal app supports all of them). + +.. toctree:: + :caption: Supported Cards + :maxdepth: 1 ndk_cards/reflexces/agi-fh400g/readme ndk_cards/intel/dk-dev-1sdx-p/readme @@ -51,20 +105,26 @@ The NDK-based Minimal application is a simple example of how to build an FPGA ap ndk_cards/amd/alveo-u200/readme ndk_cards/amd/alveo-u55c/readme ndk_cards/amd/vcu118/readme - ndk_extra/nfb-200g2ql/readme + extra/nfb-200g2ql/readme ndk_cards/prodesign/pd-falcon/readme -.. toctree:: - :maxdepth: 2 - :caption: VHDL components: - :hidden: +-------- - base - ctrls - mi - mfb - mvb - nic - pcie - debug - ver +NDK provides two implementations of DMA IPs: + +* DMA Medusa +* DMA Calypte + +DMA Medusa is a state-of-the-art DMA module that supports up to 400Gbps of throughput to +host memory. DMA Calypte is an open-source low-latency DMA supporting throughput up +to tens of Gigabits per second. However, the DMA Calypte is still under development +and is not yet officially released (stay tuned). + +.. warning:: + + The DMA Medusa IP is not included in the open-source version of the NDK. `You can obtain the full NDK package, including DMA Medusa IP and professional support, from our partner BrnoLogic. `_ + + +.. image:: img/liberouter_logo.svg + :align: center + :width: 50 % diff --git a/devel/_sources/memory.rst.txt b/devel/_sources/memory.rst.txt index 4788b1d4d..14e253585 100644 --- a/devel/_sources/memory.rst.txt +++ b/devel/_sources/memory.rst.txt @@ -3,9 +3,17 @@ Memory modules **CAM** - Ternary content addressable memory implemented in memory LUTs, optimized for Xilinx only. Also there is **light variant** implemented using register array, simpler but less effective. -**DP_BMEM** - Behavioral implementation of dual clock BRAM memory with two read/write port. ``OBSOLETE, use DP_BRAM or DP_BRAM_XILINX!`` +**DP_BMEM** - Behavioral implementation of dual clock BRAM memory with two read/write ports. -**DP_BMEM_V7** - Structural implementation of dual clock BRAM memory based on Virtex 7 specific primitives with two read/write ports. ``OBSOLETE, use DP_BRAM or DP_BRAM_XILINX!`` +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **DP_BRAM** or **DP_BRAM_XILINX** instead. + +**DP_BMEM_V7** - Structural implementation of dual clock BRAM memory based on Virtex 7 specific primitives with two read/write ports. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **DP_BRAM** or **DP_BRAM_XILINX** instead. **DP_BRAM** - Behavioral implementation of single clock BRAM memory with two read/write port. Optimized for Xilinx and Intel FPGAs. @@ -25,21 +33,28 @@ The read latency is 0 clock cycles. Optimized for same FPGAs as GEN_LUTRAM. **NP_LUTRAM_PRO** - An alternative version of NP_LUTRAM, which uses additional multiple frequency clock signal. Ports are registered and the read latency is 2 clock cycles. Expert knowledge is required to use this component! -**SDP_BMEM** - Behavioral implementation of dual clock BRAM memory with one read port and one write port. Located in the same folder as DP_BMEM. ``OBSOLETE, use DP_BRAM or DP_BRAM_XILINX!`` +**SDP_BMEM** - Behavioral implementation of dual clock BRAM memory with one read port and one write port. Located in the same folder as DP_BMEM. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **DP_BRAM** or **DP_BRAM_XILINX** instead. **SDP_BMEM_V7** - Structural implementation of dual clock BRAM memory based on Virtex 7 specific primitives with one read port and one write port. -Located in the same folder as DP_BMEM_V7. ``OBSOLETE, use SDP_BRAM or SDP_BRAM_XILINX!`` +Located in the same folder as DP_BMEM_V7. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **DP_BRAM** or **DP_BRAM_XILINX** instead. **SDP_BRAM** - Structural implementation of dual clock BRAM memory based on Xilinx and Intel specific primitives (xpm_memory_sdpram, altera_syncram) with one read port and one write port. It supports the byte enable feature! -**MP_BRAM** - Generic multiported single clock BRAM memory based on **SDP_BRAM**. Currently supports only 1 write port. Amount of read ports is not restricted. Also supports byte enable -feature. +**MP_BRAM** - Generic multi-port single-clock BRAM memory based on **SDP_BRAM**. -**LVT_MEM** - Multiported memory implemented suitable for shallow memories, supports generic amount of write/read ports and has customizable read during write behaviour. +**LVT_MEM** - Multi-port memory is suitable for shallow memories, supports a generic amount of write/read ports, and has customizable read during write behavior. **SDP_BRAM_BEHAV** - Another behavioral implementation of dual clock BRAM memory with one read port and one write port. -Located in the same folder as SDP_BRAM. ``OBSOLETE, use DP_BRAM or DP_BRAM_XILINX!`` +Located in the same folder as SDP_BRAM. **SDP_BRAM_XILINX** - Structural implementation of dual clock BRAM memory based on Xilinx specific primitives with one read port and one write port. Only for Xilinx FPGAs. @@ -48,7 +63,11 @@ Allows setting type of memory (LUT, BRAM, URAM) or automatic mode. Optimized for **SDP_URAM_XILINX** - Structural implementation of single clock URAM memory based on Xilinx specific primitives with one read port and one write port. Only for Xilinx UltraScale+ FPGAs. -**SP_BMEM** - Old behavioral implementation of single clock BRAM memory with one read/write port. ``OBSOLETE, use SP_BRAM or SP_BRAM_XILINX!`` +**SP_BMEM** - Old behavioral implementation of a single-clock BRAM memory with one read/write port. + +.. warning:: + .. deprecated:: 0.7.0 + This component is obsolete and is a candidate for removal, use **SP_BRAM** or **SP_BRAM_XILINX** instead. **SP_BRAM** - Behavioral implementation of single clock BRAM memory with one read/write port. Optimized for Xilinx and Intel FPGAs. diff --git a/devel/_sources/mfb.rst.txt b/devel/_sources/mfb.rst.txt index e432cfc3a..b9cee458f 100644 --- a/devel/_sources/mfb.rst.txt +++ b/devel/_sources/mfb.rst.txt @@ -9,7 +9,6 @@ Components using the MFB bus are typically located in the ``comp/mfb_tools/`` di :maxdepth: 1 :caption: Content: - comp/mfb_tools/readme comp/mfb_tools/flow/reconfigurator/readme comp/mfb_tools/flow/frame_packer/readme comp/mfb_tools/flow/frame_unpacker/readme diff --git a/devel/_sources/mi.rst.txt b/devel/_sources/mi.rst.txt index 26eb15ee5..01d1d10c8 100644 --- a/devel/_sources/mi.rst.txt +++ b/devel/_sources/mi.rst.txt @@ -8,7 +8,6 @@ Components using the MI bus are typically located in the ``comp/mi_tools/`` dire :maxdepth: 1 :caption: Content: - comp/mi_tools/readme comp/mi_tools/async/readme comp/mi_tools/pipe/readme comp/mi_tools/indirect_access/readme diff --git a/devel/_sources/mvb.rst.txt b/devel/_sources/mvb.rst.txt index a623f3c58..facb915ab 100644 --- a/devel/_sources/mvb.rst.txt +++ b/devel/_sources/mvb.rst.txt @@ -1,5 +1,5 @@ -MVB Tools -========= +MVB Components +============== This chapter contains the specifications of the MVB bus and a description of the components that use MVB bus. The MVB bus was developed to support multiple items/values in one clock cycle. @@ -9,7 +9,6 @@ Components using the MFB bus are typically located in the ``comp/mvb_tools/`` di :maxdepth: 1 :caption: Content: - comp/mvb_tools/readme comp/mvb_tools/flow/channel_router/readme comp/mvb_tools/flow/discard/readme comp/mvb_tools/flow/item_collision_resolver/readme diff --git a/devel/_static/_sphinx_javascript_frameworks_compat.js b/devel/_static/_sphinx_javascript_frameworks_compat.js deleted file mode 100644 index 81415803e..000000000 --- a/devel/_static/_sphinx_javascript_frameworks_compat.js +++ /dev/null @@ -1,123 +0,0 @@ -/* Compatability shim for jQuery and underscores.js. - * - * Copyright Sphinx contributors - * Released under the two clause BSD licence - */ - -/** - * small helper function to urldecode strings - * - * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Objects/decodeURIComponent#Decoding_query_parameters_from_a_URL - */ -jQuery.urldecode = function(x) { - if (!x) { - return x - } - return decodeURIComponent(x.replace(/\+/g, ' ')); -}; - -/** - * small helper function to urlencode strings - */ -jQuery.urlencode = encodeURIComponent; - -/** - * This function returns the parsed url parameters of the - * current request. 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jQuery.each(node.childNodes, function() { - highlight(this, addItems); - }); - } - } - var addItems = []; - var result = this.each(function() { - highlight(this, addItems); - }); - for (var i = 0; i < addItems.length; ++i) { - jQuery(addItems[i].parent).before(addItems[i].target); - } - return result; -}; - -/* - * backward compatibility for jQuery.browser - * This will be supported until firefox bug is fixed. - */ -if (!jQuery.browser) { - jQuery.uaMatch = function(ua) { - ua = ua.toLowerCase(); - - var match = /(chrome)[ \/]([\w.]+)/.exec(ua) || - /(webkit)[ \/]([\w.]+)/.exec(ua) || - /(opera)(?:.*version|)[ \/]([\w.]+)/.exec(ua) || - /(msie) ([\w.]+)/.exec(ua) || - ua.indexOf("compatible") < 0 && /(mozilla)(?:.*? rv:([\w.]+)|)/.exec(ua) || - []; - - return { - browser: match[ 1 ] || "", - version: match[ 2 ] || "0" - }; - }; - jQuery.browser = {}; - jQuery.browser[jQuery.uaMatch(navigator.userAgent).browser] = true; -} diff --git a/devel/_static/basic_mod.css b/devel/_static/basic_mod.css new file mode 100644 index 000000000..0df77588f --- /dev/null +++ b/devel/_static/basic_mod.css @@ -0,0 +1,1194 @@ +@font-face { + font-family: Roboto; + font-style: normal; + font-weight: 400; + src: local("Roboto"), local("Roboto-Regular"), url(fonts/roboto/roboto.woff2) format("woff2"); +} +@font-face { + font-family: Roboto; + font-style: italic; + font-weight: 400; + src: local("Roboto Italic"), local("Roboto-Italic"), url(fonts/roboto/roboto-italic.woff2) format("woff2"); +} +@font-face { + font-family: Roboto; + font-style: normal; + font-weight: 700; + src: local("Roboto Bold"), local("Roboto-Bold"), url(fonts/roboto/roboto-bold.woff2) format("woff2"); +} +@font-face { + font-family: Roboto Mono; + font-style: normal; + font-weight: 400; + src: local("Roboto Mono Regular"), local("RobotoMono-Regular"), url(fonts/roboto-mono/roboto-mono.woff2) format("woff2"); +} +@font-face { + font-family: Roboto Mono; + font-style: italic; + font-weight: 400; + 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1.17rem; +} + +a { + color: var(--linkColor); + text-decoration: none; +} + +/*****************************************************************************/ +html { + height: 100%; + scroll-padding-top: var(--navbarHeight); +} + +html, +body { + padding: 0; + margin: 0; + min-height: 100%; +} + +body { + display: flex; + flex-direction: column; +} + +/*****************************************************************************/ +/* Top nav */ +#searchbox h3#searchlabel { + display: none; +} +#searchbox form.search { + display: flex; + flex-direction: row; +} +#searchbox form.search input { + display: block; + box-sizing: border-box; + padding: 0.3rem; + color: rgba(0, 0, 0, 0.7); + border-radius: 0.2rem; +} +#searchbox form.search input[type=text] { + border: none; + background-color: rgba(255, 255, 255, 0.6); + flex-grow: 1; + margin-right: 0.2rem; +} +#searchbox form.search input[type=text]::placeholder { + color: rgba(0, 0, 0, 0.6); +} +#searchbox form.search input[type=submit] { + cursor: pointer; + color: var(--mainNavColor); + flex-grow: 0; + border: none; + background-color: white; +} + +div#top_nav { + position: fixed; + top: 0; + left: 0; + right: 0; + color: white; + z-index: 100; +} +div#top_nav div#notification_banner { + background-color: var(--notificationBannerColor); + box-sizing: border-box; + padding: 0.1rem 1rem; + display: flex; + flex-direction: row; + align-items: center; + justify-content: right; +} +div#top_nav div#notification_banner a.close { + flex-grow: 0; + flex-shrink: 0; + color: rgba(255, 255, 255, 0.85); + text-align: right; + font-size: 0.6rem; + text-transform: uppercase; + display: block; + text-decoration: none; + margin-left: 0.5rem; +} +div#top_nav div#notification_banner a.close:hover { + color: white; +} +div#top_nav div#notification_banner p { + flex-grow: 1; + margin: 0; + text-align: center; + font-size: 0.9rem; + line-height: 1.2; + padding: 0.4rem 0; +} +div#top_nav div#notification_banner p a { + color: white; + text-decoration: underline; +} +div#top_nav nav { + background-color: var(--mainNavColor); + box-sizing: border-box; + padding: 1rem; + display: flex; + flex-direction: row; + align-items: center; +} +div#top_nav nav h1 { + flex-grow: 1; + font-size: 1.2rem; + margin: 0; + padding: 0 0 0 0.8rem; + line-height: 1; +} +div#top_nav nav h1 a { + color: white; +} +div#top_nav nav h1 img { + height: 1.3rem; + width: auto; +} +div#top_nav nav p#toggle_sidebar { + transform: rotate(90deg); + letter-spacing: 0.1rem; + flex-grow: 0; + margin: 0; + padding: 0; +} +div#top_nav nav p#toggle_sidebar a { + color: white; + font-weight: bold; +} +div#top_nav nav a#mode_toggle, div#top_nav nav a#source_link { + margin-right: 1rem; + display: block; + flex-grow: 0; +} +div#top_nav nav a#mode_toggle svg, div#top_nav nav a#source_link svg { + height: 1.3rem; + width: 1.3rem; + vertical-align: middle; +} +div#top_nav nav p.mobile_search_link { + margin: 0; +} +@media (min-width: 50rem) { + div#top_nav nav p.mobile_search_link { + display: none; + } +} +div#top_nav nav p.mobile_search_link a { + color: white; +} +div#top_nav nav p.mobile_search_link a svg { + height: 1rem; + vertical-align: middle; +} +@media (max-width: 50rem) { + div#top_nav nav div.searchbox_wrapper { + display: none; + } +} +div#top_nav nav div.searchbox_wrapper #searchbox { + align-items: center; + display: flex !important; + flex-direction: row-reverse; +} +div#top_nav nav div.searchbox_wrapper #searchbox p.highlight-link { + margin: 0 0.5rem 0 0; +} +div#top_nav nav div.searchbox_wrapper #searchbox p.highlight-link a { + color: rgba(255, 255, 255, 0.8); + font-size: 0.8em; + padding-right: 0.5rem; + text-decoration: underline; +} +div#top_nav nav div.searchbox_wrapper #searchbox p.highlight-link a:hover { + color: white; +} + +/*****************************************************************************/ +/* Main content */ +div.document { + flex-grow: 1; + margin-top: 2rem; + margin-bottom: 5rem; + margin-left: 15rem; + margin-right: 15rem; + padding-top: var(--navbarHeight); + /***************************************************************************/ + /***************************************************************************/ +} +@media (max-width: 50rem) { + div.document { + margin-left: 0px; + margin-right: 0px; + } +} +div.document section, +div.document div.section { + margin: 4rem 0; +} +div.document section:first-child, +div.document div.section:first-child { + margin-top: 0; +} +div.document section > section, +div.document div.section > div.section { + margin: 4rem 0; +} +div.document section > section > section, +div.document div.section > div.section > div.section { + margin: 2rem 0 0 0; +} +div.document section > section > section > section, +div.document div.section > div.section > div.section > div.section { + margin: 1.5rem 0 0 0; +} +div.document h1 + section, +div.document h1 + div.section { + margin-top: 2.5rem !important; +} +div.document h2 + section, +div.document h2 + div.section { + margin-top: 1.5rem !important; +} +div.document img { + max-width: 100%; +} +div.document code { + padding: 2px 4px; + background-color: var(--inlineCodeBackgroundColor); + border-radius: 0.2rem; + font-family: "Roboto Mono", monospace, Monaco, Consolas, Andale Mono; + font-size: 0.9em; +} +div.document div.documentwrapper { + max-width: 45rem; + margin: 0 auto; + flex-grow: 1; + box-sizing: border-box; + padding: 1rem; +} +div.document div.highlight { + color: #252630; + box-sizing: border-box; + padding: 0.2rem 1rem; + margin: 0.5rem 0; + border-radius: 0.2rem; + font-size: 0.9rem; +} +div.document div.highlight pre { + font-family: "Roboto Mono", monospace, Monaco, Consolas, Andale Mono; +} +div.document div[class*=highlight] { + overflow-x: auto; +} +div.document a.headerlink { + font-size: 0.6em; + display: none; + padding-left: 0.5rem; + vertical-align: middle; +} +div.document h1, +div.document h2, +div.document h3, +div.document h4, +div.document h5, +div.document h6, +div.document str, +div.document b { + font-weight: 700; +} +div.document h1 { + margin: 0.8rem 0 0.5rem 0; +} +div.document h2 { + margin: 0.8rem 0 0.5rem 0; +} +div.document h3, div.document h4 { + margin: 1rem 0 0.5rem 0; +} +div.document h1:hover a.headerlink, +div.document h2:hover a.headerlink, +div.document h3:hover a.headerlink, +div.document h4:hover a.headerlink { + display: inline-block; +} +div.document p, +div.document li { + font-size: 1rem; + line-height: 1.5; +} +div.document li p { + margin: 0 0 0.5rem 0; +} +div.document ul, div.document ol { + padding-left: 2rem; +} +div.document ol.loweralpha { + list-style: lower-alpha; +} +div.document ol.arabic { + list-style: decimal; +} +div.document ol.lowerroman { + list-style: lower-roman; +} +div.document ol.upperalpha { + list-style: upper-alpha; +} +div.document ol.upperroman { + list-style: upper-roman; +} +div.document dd { + margin-left: 1.5rem; +} +div.document hr { + border: none; + height: 1px; + background-color: var(--dividerColor); + margin: 2rem 0; +} +div.document table.docutils { + border-collapse: collapse; +} +div.document table.docutils th, div.document table.docutils td { + border: 1px solid var(--dividerColor); + box-sizing: border-box; + padding: 0.5rem 1rem; +} +div.document table.docutils th p, div.document table.docutils th ul, div.document table.docutils td p, div.document table.docutils td ul { + margin: 0.3rem 0; +} +div.document table.docutils th ul, div.document table.docutils td ul { + padding-left: 1rem; +} +div.document form input { + padding: 0.5rem; +} +div.document form input[type=submit], div.document form button { + border: none; + background-color: var(--mainNavColor); + color: white; + padding: 0.5rem 1rem; + border-radius: 0.2rem; +} +div.document span.highlighted { + background-color: var(--searchHighlightColor); + padding: 0 0.1em; +} +div.document div#search-results { + padding-top: 2rem; +} +div.document div#search-results p.search-summary { + font-size: 0.8em; +} +div.document div#search-results ul.search { + list-style: none; + padding-left: 0; +} +div.document div#search-results ul.search li { + border-bottom: 1px solid var(--dividerColor); + margin: 0; + padding: 2rem 0; +} +div.document div#search-results ul.search li > a:first-child { + font-size: 1.2rem; +} +div.document dd ul, div.document dd ol { + padding-left: 1rem; +} +div.document dl.py { + margin-bottom: 2rem; +} +div.document dl.py dt.sig { + background-color: var(--codeBackgroundColor); + color: var(--fontColor); + box-sizing: border-box; + font-family: "Roboto Mono", monospace, Monaco, Consolas, Andale Mono; + font-size: 0.9rem; + padding: 1rem; + border-left: 5px solid rgba(0, 0, 0, 0.1); + border-radius: 0.2rem; +} +div.document dl.py em.property { + color: var(--sidebarColor); + font-weight: bold; +} +div.document dl.py span.sig-name { + color: var(--codeBlue); + font-weight: bold; +} +div.document dl.py em.property { + color: var(--codeGreen); +} +div.document dl.py em.sig-param { + margin-left: 2rem; +} +div.document dl.py em.sig-param span.default_value { + color: var(--codeGreen); +} +div.document dl.py span.sig-return span.sig-return-typehint { + color: var(--fontColor); +} +div.document dl.py span.sig-return span.sig-return-typehint pre { + color: var(--fontColor); +} +div.document dl.py em.sig-param > span:first-child { + font-weight: bold; +} +div.document dl.cpp, div.document dl.c { + margin-bottom: 1rem; +} +div.document dl.cpp dt.sig, div.document dl.c dt.sig { + background-color: var(--codeBackgroundColor); + color: var(--fontColor); + box-sizing: border-box; + font-family: "Roboto Mono", monospace, Monaco, Consolas, Andale Mono; + font-size: 0.9rem; + padding: 1rem; + border-left: 5px solid rgba(0, 0, 0, 0.1); + border-radius: 0.2rem; + line-height: 1.4; +} +div.document dl.cpp span.sig-name, div.document dl.c span.sig-name { + color: var(--codeBlue); + font-weight: bold; +} +div.document dl.cpp span.sig-indent, div.document dl.c span.sig-indent { + margin-left: 2rem; +} +div.document dl.cpp span.target + span, div.document dl.c span.target + span { + color: var(--codeGreen); +} +div.document dl.cpp span.sig-param > span:first-child, div.document dl.c span.sig-param > span:first-child { + font-weight: bold; +} +div.document div.admonition { + box-shadow: 0px 0px 0px 1px var(--dividerColor); + border-radius: 0.2rem; + margin: 1rem 0; + overflow: hidden; +} +div.document div.admonition p { + box-sizing: border-box; + font-size: 0.9rem; + padding: 0.5rem; + margin: 0; +} +div.document div.admonition p:first-child { + padding-bottom: 0; + margin-bottom: 0; +} +div.document div.admonition p + p { + padding-top: 0.2rem; +} +div.document div.admonition p.admonition-title { + font-weight: bolder; + letter-spacing: 0.01rem; +} +div.document div.admonition.hint, div.document div.admonition.important, div.document div.admonition.tip { + border-left: 5px solid #56b79c; +} +div.document div.admonition.hint p.admonition-title, div.document div.admonition.important p.admonition-title, div.document div.admonition.tip p.admonition-title { + color: #56b79c; +} +div.document div.admonition.note { + border-left: 5px solid #587f9f; +} +div.document div.admonition.note p.admonition-title { + color: #587f9f; +} +div.document div.admonition.danger, div.document div.admonition.error { + border-left: 5px solid #e6a39a; +} +div.document div.admonition.danger p.admonition-title, div.document div.admonition.error p.admonition-title { + color: #e6a39a; +} +div.document div.admonition.attention, div.document div.admonition.caution, div.document div.admonition.warning { + border-left: 5px solid #e7b486; +} +div.document div.admonition.attention p.admonition-title, div.document div.admonition.caution p.admonition-title, div.document div.admonition.warning p.admonition-title { + color: #e7b486; +} + +/*****************************************************************************/ +/* Sidebar */ +div.sphinxsidebar { + background-color: var(--sidebarColor); + border-right: 1px solid var(--dividerColor); + position: fixed; + left: 0; + top: 0; + bottom: 0; + width: 15rem; + box-sizing: border-box; + padding: var(--navbarHeight) 1rem 1rem; + z-index: 50; +} +@media (max-width: 50rem) { + div.sphinxsidebar { + display: none; + } +} +div.sphinxsidebar div.sphinxsidebarwrapper { + height: 100%; + overflow-y: auto; +} +div.sphinxsidebar ul { + padding-left: 0rem; + list-style: none; +} +div.sphinxsidebar ul li { + font-size: 0.9rem; + line-height: 1.2; +} +div.sphinxsidebar ul li a { + display: block; + box-sizing: border-box; + padding: 0 0.2rem 0.6rem; + color: var(--fontColor); + text-decoration: none; +} +div.sphinxsidebar ul li a.current { + color: var(--linkColor); +} +div.sphinxsidebar ul li a:hover { + color: var(--linkColor); +} +div.sphinxsidebar ul li > ul { + padding-left: 1rem; +} +div.sphinxsidebar p { + color: var(--faintFontColor); +} + +/*****************************************************************************/ +/* The right sidebar, showing the table of contents for the current page. */ +div#show_right_sidebar { + position: fixed; + right: 0; + top: 0; + z-index: 20; + background-color: var(--sidebarColor); + border-left: 1px solid var(--dividerColor); + border-bottom: 1px solid var(--dividerColor); + padding: var(--navbarHeight) 1rem 0rem; +} +div#show_right_sidebar p { + font-size: 0.9em; +} +div#show_right_sidebar p span { + color: var(--faintFontColor); + vertical-align: middle; +} +div#show_right_sidebar p span.icon { + color: var(--linkColor); + font-size: 0.9em; + padding-right: 0.2rem; +} + +div#right_sidebar { + position: fixed; + right: 0; + top: 0; + z-index: 50; + background-color: var(--sidebarColor); + width: 15rem; + border-left: 1px solid var(--dividerColor); + box-sizing: border-box; + padding: var(--navbarHeight) 1rem 1rem; + height: 100%; + overflow-y: auto; +} +div#right_sidebar p span { + color: var(--faintFontColor); + vertical-align: middle; +} +div#right_sidebar p span.icon { + color: var(--linkColor); + font-size: 0.9em; + padding-right: 0.2rem; +} +div#right_sidebar ul { + padding-left: 0rem; + list-style: none; +} +div#right_sidebar ul li { + font-size: 0.9rem; + line-height: 1.2; +} +div#right_sidebar ul li a { + display: block; + box-sizing: border-box; + padding: 0 0.2rem 0.6rem; + color: var(--fontColor); + text-decoration: none; +} +div#right_sidebar ul li a.current { + color: var(--linkColor); +} +div#right_sidebar ul li a:hover { + color: var(--linkColor); +} +div#right_sidebar ul li > ul { + padding-left: 1rem; +} +div#right_sidebar p { + color: var(--faintFontColor); +} +@media (max-width: 50rem) { + div#right_sidebar { + display: none; + } +} + +/*****************************************************************************/ +/* Footer */ +div.footer { + box-sizing: border-box; + padding-top: 2rem; + font-size: 0.7rem; + text-align: center; + text-transform: uppercase; + color: var(--faintFontColor); +} + +p#theme_credit { + font-size: 0.6rem; + text-transform: uppercase; + text-align: center; + color: var(--faintFontColor); +} + +/*****************************************************************************/ +/* Buttons */ +div.button_nav_wrapper { + margin-left: 15rem; + margin-right: 15rem; +} +@media (max-width: 50rem) { + div.button_nav_wrapper { + margin-left: 0px; + margin-right: 0px; + } +} +div.button_nav_wrapper div.button_nav { + max-width: 45rem; + margin: 0 auto; + display: flex; + flex-direction: row; + width: 100%; +} +div.button_nav_wrapper div.button_nav div { + box-sizing: border-box; + padding: 1rem; + flex: 50%; +} +div.button_nav_wrapper div.button_nav div a { + display: block; +} +div.button_nav_wrapper div.button_nav div a span { + vertical-align: middle; +} +div.button_nav_wrapper div.button_nav div a span.icon { + font-weight: bold; + font-size: 0.8em; +} +div.button_nav_wrapper div.button_nav div.left a { + text-align: left; +} +div.button_nav_wrapper div.button_nav div.left a span.icon { + padding-right: 0.4rem; +} +div.button_nav_wrapper div.button_nav div.right a { + text-align: right; +} +div.button_nav_wrapper div.button_nav div.right a span.icon { + padding-left: 0.4rem; +} + +/*****************************************************************************/ +/* Pygments overrides in dark mode */ +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight { + --black: #000000; + --red: #ff9393; + --darkBlue: #6b83fe; + --grey: #a8a8a8; + --pink: #ff99d8; + --torquoise: #68e9e9; + --brown: #d48a00; + --purple: #ce04e9; + --paleYellow: #454534; + background: var(--codeBackgroundColor); + color: var(--fontColor); + /* Comment */ + /* Error */ + /* Keyword */ + /* Operator */ + /* Comment.Hashbang */ + /* Comment.Multiline */ + /* Comment.Preproc */ + /* Comment.PreprocFile */ + /* Comment.Single */ + /* Comment.Special */ + /* Generic.Deleted */ + /* Generic.Emph */ + /* Generic.Error */ + /* Generic.Heading */ + /* Generic.Inserted */ + /* Generic.Output */ + /* Generic.Prompt */ + /* Generic.Strong */ + /* Generic.Subheading */ + /* Generic.Traceback */ + /* Keyword.Constant */ + /* Keyword.Declaration */ + /* Keyword.Namespace */ + /* Keyword.Pseudo */ + /* Keyword.Reserved */ + /* Keyword.Type */ + /* Literal.Number */ + /* Literal.String */ + /* Name.Attribute */ + /* Name.Builtin */ + /* Name.Class */ + /* Name.Constant */ + /* Name.Decorator */ + /* Name.Entity */ + /* Name.Exception */ + /* Name.Function */ + /* Name.Label */ + /* Name.Namespace */ + /* Name.Tag */ + /* Name.Variable */ + /* Operator.Word */ + /* Text.Whitespace */ + /* Literal.Number.Bin */ + /* Literal.Number.Float */ + /* Literal.Number.Hex */ + /* Literal.Number.Integer */ + /* Literal.Number.Oct */ + /* Literal.String.Affix */ + /* Literal.String.Backtick */ + /* Literal.String.Char */ + /* Literal.String.Delimiter */ + /* Literal.String.Doc */ + /* Literal.String.Double */ + /* Literal.String.Escape */ + /* Literal.String.Heredoc */ + /* Literal.String.Interpol */ + /* Literal.String.Other */ + /* Literal.String.Regex */ + /* Literal.String.Single */ + /* Literal.String.Symbol */ + /* Name.Builtin.Pseudo */ + /* Name.Function.Magic */ + /* Name.Variable.Class */ + /* Name.Variable.Global */ + /* Name.Variable.Instance */ + /* Name.Variable.Magic */ + /* Literal.Number.Integer.Long */ +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight pre, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight pre { + line-height: 125%; +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight td.linenos .normal, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight td.linenos .normal { + color: inherit; + background-color: transparent; + padding-left: 5px; + padding-right: 5px; +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight span.linenos, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight span.linenos { + color: inherit; + background-color: transparent; + padding-left: 5px; + padding-right: 5px; +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight td.linenos .special, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight td.linenos .special { + color: var(--black); + background-color: var(--paleYellow); + padding-left: 5px; + padding-right: 5px; +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight span.linenos.special, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight span.linenos.special { + color: var(--black); + background-color: var(--paleYellow); + padding-left: 5px; + padding-right: 5px; +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight .hll, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight .hll { + background-color: var(--paleYellow); +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight .c, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight .c { + color: var(--torquoise); + font-style: italic; +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight .err, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight .err { + border: 1px solid var(--red); +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight .k, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight .k { + color: var(--codeGreen); + font-weight: bold; +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight .o, +:root[data-mode=darkest] body[data-dark_mode_code_blocks=true] .highlight .o { + color: var(--grey); +} +:root[data-mode=dark] body[data-dark_mode_code_blocks=true] .highlight .ch, +:root[data-mode=darkest] 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. 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- - Hosted by Read the Docs - -
-
- `; - - // Inject the generated flyout into the body HTML element. - document.body.insertAdjacentHTML("beforeend", flyout); - - // Trigger the Read the Docs Addons Search modal when clicking on the "Search docs" input from inside the flyout. - document - .querySelector("#flyout-search-form") - .addEventListener("focusin", () => { - const event = new CustomEvent("readthedocs-search-show"); - document.dispatchEvent(event); - }); - }) -} - -if (themeLanguageSelector || themeVersionSelector) { - function onSelectorSwitch(event) { - const option = event.target.selectedIndex; - const item = event.target.options[option]; - window.location.href = item.dataset.url; - } - - document.addEventListener("readthedocs-addons-data-ready", function (event) { - const config = event.detail.data(); - - const versionSwitch = document.querySelector( - "div.switch-menus > div.version-switch", - ); - if (themeVersionSelector) { - let versions = config.versions.active; - if (config.versions.current.hidden || config.versions.current.type === "external") { - versions.unshift(config.versions.current); - } - const versionSelect = ` - - `; - - versionSwitch.innerHTML = versionSelect; - versionSwitch.firstElementChild.addEventListener("change", onSelectorSwitch); - } - - const languageSwitch = document.querySelector( - "div.switch-menus > div.language-switch", - ); - - if (themeLanguageSelector) { - if (config.projects.translations.length) { - // Add the current language to the options on the selector - let languages = config.projects.translations.concat( - config.projects.current, - ); - languages = languages.sort((a, b) => - a.language.name.localeCompare(b.language.name), - ); - - const languageSelect = ` - - `; - - languageSwitch.innerHTML = languageSelect; - languageSwitch.firstElementChild.addEventListener("change", onSelectorSwitch); - } - else { - languageSwitch.remove(); - } - } - }); -} - -document.addEventListener("readthedocs-addons-data-ready", function (event) { - // Trigger the Read the Docs Addons Search modal when clicking on "Search docs" input from the topnav. - document - .querySelector("[role='search'] input") - .addEventListener("focusin", () => { - const event = new CustomEvent("readthedocs-search-show"); - document.dispatchEvent(event); - }); -}); \ No newline at end of file diff --git a/devel/app-minimal.html b/devel/app-minimal.html index 3869a1d0e..50d43c423 100644 --- a/devel/app-minimal.html +++ b/devel/app-minimal.html @@ -1,56 +1,136 @@ - - - - - - - Minimal NDK application — NDK-FPGA Docs documentation - - + + + + - - - - - - + Minimal NDK application — NDK-FPGA documentation + + + + + + - - - + + + + + - -
- - -
+
-
-
-
- -
-
-
-
- +
+
+
+
+
-

Minimal NDK application

+

Minimal NDK application

The NDK-based Minimal application is a simple example of how to build an FPGA application using the NDK. It can also be a starting point for your NDK-based application. The NDK-based Minimal application does not process network packets in any way; it only sends and receives them. If the DMA IP is enabled (see the DMA Module chapter), then it forwards the network packets to and from the computer memory.

The top-level application provides the Ethernet, DMA, and MI configuration bus connections to the individual APP subcore. One independent APP subcore is instantiated for each Ethernet stream. The Ethernet and DMA streams are implemented using the MFB buses and the MVB buses. The block diagram below shows the connection of the Minimal application.

_images/app_core.drawio.svg @@ -125,7 +199,7 @@

In each subcore in the TX direction (DMA to ETH) the DMA channels are statically mapped to Ethernet channels (if there is more than one) according to the MSBs of the DMA channel number. For example, if there are 4 Ethernet channels and 32 DMA channels, the ETH channel number (2 bits) is taken from bits 4 and 3 of the DMA channel number. So packets from DMA channels 0-7 would all be routed to ETH channel 0, packets from DMA channels 8-15 would all be routed to ETH channel 1, etc.

In the RX direction (again, for each subcore), the mapping of Ethernet channels to DMA channels is configurable by the user. The mapping is performed by the MVB Channel Router. By default, each Ethernet channel has a portion of the available DMA channels to which it can send packets. And in the default state, it sends packets to the available DMA channels in the round-robin mode.```

-

The Memory Testers

+

The Memory Testers

The NDK-based Minimal application also contains Memory Tester modules connected to external memory controllers. These modules make it easy to test the operation of external memories and measure their properties (throughput, latency). The Avalon-MM bus is used to access the external memory, see Avalon Interface Specifications.

How to run Memory Tester:

    @@ -188,7 +262,7 @@

    The Memory Testers -

    The application MI offsets

    +

    The application MI offsets

    In this case, the MI address space for the entire application core is divided between the individual application subcores and the wrapper of the memory testers. The whole MI address space is described using DevTree. And its overview can be obtained by reading it from the card using the nfb-bus -l command. For MI offsets of application core see /firmware/mi_bus0/application/* paths in example output of the command:

    @@ -263,34 +337,76 @@

    The application MI offsets

-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <Frequently Asked Questions + +
- +
+ + Basic Tools> + +
-
- -
- +
+ + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/async.html b/devel/async.html index f45b59aff..0ecb33848 100644 --- a/devel/async.html +++ b/devel/async.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Asynchronous modules — NDK-FPGA Docs documentation - - - - - - - - - + Asynchronous modules — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

Asynchronous modules

+

Asynchronous modules

ASYNC_BUS_HANDSHAKE - General asynchronous/clock domain crossing for multi-bit signals and buses. It uses a handshake mechanism and has significantly lower throughput (one transfer per ~10 clock cycles) than the dual clock FIFOs.

ASYNC_GENERAL - General asynchronous/clock domain crossing for single-bit signals only. Detection mode can be configured (rising edge, falling edge).

ASYNC_OPEN_LOOP - Simpler asynchronous/clock domain crossing for single-bit signals, which require specific clock frequency ratio.

@@ -135,40 +210,81 @@

Asynchronous modules

-

References

+

References

For more detailed description refer to Jakub Cabal’s bachelor thesis (2014/2015).

-
+
-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <Basic Tools + +
- +
+ + Memory modules> + +
-
- - - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/base.html b/devel/base.html index 25cfc1bcf..4fe658adb 100644 --- a/devel/base.html +++ b/devel/base.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Basic Tools — NDK-FPGA Docs documentation - - - - - - - - - + Basic Tools — NDK-FPGA documentation + + + + + + - - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

Basic Tools

+

Basic Tools

This chapter describes the basic components such as FIFOs, RAMs, multiplexers, encoders, decoders, etc. -The basic components are typically located in the comp/base/ directory in the OFM repository.

+The basic components are typically located in the comp/base/ directory in the NDK-FPGA repository.

Content:

@@ -136,34 +212,52 @@

Basic Tools

-
+
+
+
+
+ + + <Minimal NDK application + +
-
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
+ + Asynchronous modules> + +
-
-
-
- - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/dsp/dsp_comparator/readme.html b/devel/comp/base/dsp/dsp_comparator/readme.html index cbe7af85a..68f87bb12 100644 --- a/devel/comp/base/dsp/dsp_comparator/readme.html +++ b/devel/comp/base/dsp/dsp_comparator/readme.html @@ -1,52 +1,136 @@ - - - - - - - DSP Comparator — NDK-FPGA Docs documentation - - + + + + - - - - - - + DSP Comparator — NDK-FPGA documentation + + + + + + - + - + + + - -
- - -
+
-
-
-
- -
-
-
-
- +
+
+
+
+
-

DSP Comparator

+

DSP Comparator

-ENTITY DSP_COMPARATOR IS
+ENTITY DSP_COMPARATOR IS

This is a comparator that can use DSP bloks on different Devices but can also be implemented in common logic.

@@ -239,34 +314,52 @@
-
+
-
+
+
+
+
+ + + <DSP components + +
-
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
+ + Basic logic elements> + +
-
- -
- +
+ + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/fifo/asfifox/readme.html b/devel/comp/base/fifo/asfifox/readme.html index 0db440d4a..1357f48aa 100644 --- a/devel/comp/base/fifo/asfifox/readme.html +++ b/devel/comp/base/fifo/asfifox/readme.html @@ -1,52 +1,136 @@ - - - - - - - ASFIFOX — NDK-FPGA Docs documentation - - + + + + - - - - - - + ASFIFOX — NDK-FPGA documentation + + + + + + - + + + - -
- +
-
- -
-
-
- -
-
-
-
- +
+
+
+
+
-

ASFIFOX

+

ASFIFOX

-ENTITY ASFIFOX IS
+ENTITY ASFIFOX IS

A universal asynchronous (dual clock) FIFO, suitable both for Xilinx and Intel (Altera) FPGA. Can be parametrically implemented in BRAM or LUTRAM (MLAB on Intel FPGA = 32 items, distributed memory in Xilinx FPGA = 64 items).

@@ -312,41 +384,82 @@
-

Block diagram

+

Block diagram

../../../../_images/asfifox.svg
-
+
-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <FIFO components + +
- +
+ + FIFOX> + +
-
-
-
- +
+ + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/fifo/fifox/readme.html b/devel/comp/base/fifo/fifox/readme.html index f62ddc448..20fc4fad4 100644 --- a/devel/comp/base/fifo/fifox/readme.html +++ b/devel/comp/base/fifo/fifox/readme.html @@ -1,52 +1,136 @@ - - - - - - - FIFOX — NDK-FPGA Docs documentation - - + + + + - - - - - - + FIFOX — NDK-FPGA documentation + + + + + + - + + + - -
- +
-
- -
-
-
- -
-
-
-
- +
+
+
+
+
-

FIFOX

+

FIFOX

-ENTITY FIFOX IS
+ENTITY FIFOX IS

A universal FIFO, capable of implementation in multiple types of memories. Both DATA_WIDTH and ITEMS may be set to any value; however ITEMS has an implicit lower limit of 2 that will be automatically used if required.

@@ -204,7 +275,7 @@
-TYPE FIFOX_RAM_TYPE IS
+TYPE FIFOX_RAM_TYPE IS

Represents the type of memory implementation used by FIFOX. Should be chosen based on the target FPGA and required size of the FIFOX

Note: this type is for documentation only; string representations of the @@ -330,15 +401,15 @@

-

Block diagram

+

Block diagram

TODO- Přidat blokový diagram komponenty FIFOX

-

Verification

+

Verification

Verification is coverage oriented. There is code coverage turned on. The code coverage report can be generated by uncommenting one line in top_level.fdo. Both input and output interfaces of component are connected by MVB interfaces to the verification environment. The scoreboard checks that the data that are written into component are readed in correct order at output interface.

-

Verification block diagram

+

Verification block diagram

../../../../_images/fifox_ver.svg

There are 3 tests. The first 2 are most random and are designed to verify correct functionality in classic use. The 3th one is designed to check functionality when data are more often written and less often readed.

@@ -346,34 +417,77 @@

Verification block diagram

-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <ASFIFOX + +
- +
+ + FIFOX Multi> + +
-
-
- - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/fifo/fifox_multi/readme.html b/devel/comp/base/fifo/fifox_multi/readme.html index 0c77360a5..77ccc6db6 100644 --- a/devel/comp/base/fifo/fifox_multi/readme.html +++ b/devel/comp/base/fifo/fifox_multi/readme.html @@ -1,52 +1,136 @@ - - - - - - - FIFOX Multi — NDK-FPGA Docs documentation - - + + + + - - - - - - + FIFOX Multi — NDK-FPGA documentation + + + + + + - + + + - -
- +
-
- -
-
-
- -
-
-
-
- +
+
+
+
+
-

FIFOX Multi

+

FIFOX Multi

-ENTITY FIFOX_MULTI IS
+ENTITY FIFOX_MULTI IS

Synchronous FIFO queue, allowing for multiple write and read requests in each cycle. With N write ports and M read ports it can perform 0 to N writes and 0 to M reads simultaneously. Uses FIFOX @@ -291,18 +362,18 @@

-

Block diagram

+

Block diagram

-

Write interface behavior

+

Write interface behavior

The write interface allows you to write 0 to WRITE_PORTS items in each clock cycle. Valid input items are marked by setting the corresponding bit of WR to '1'.

The write requests are only performed when signal FULL has value '0'. When FULL is '0', no items can be written.

In case of multiple simultaneous writes the item on port 0 will be placed as the first in the FIFO and the item on port WRITE_PORTS-1 as the last.

-

Read interface behavior

+

Read interface behavior

The read interface allows you to read 0 to READ_PORTS items in each clock cycle. Simultaneous read requests must be continuous from index 0 up. You cannot read items out-of-order.

@@ -317,34 +388,77 @@

Read interface behavior -

+
-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <FIFOX + +
- +
+ + DSP components> + +
-
-
- - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/fifo/reg_fifo/readme.html b/devel/comp/base/fifo/reg_fifo/readme.html index 608597153..331f2f603 100644 --- a/devel/comp/base/fifo/reg_fifo/readme.html +++ b/devel/comp/base/fifo/reg_fifo/readme.html @@ -1,50 +1,134 @@ + + + + + - - - - - - - Register FIFO — NDK-FPGA Docs documentation - - - - - - - - - + Register FIFO — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

Register FIFO

+

Register FIFO

-ENTITY REG_FIFO IS
+ENTITY REG_FIFO IS

This component is the most primitive FIFO here which is made of registers that buffers data also when the output TX_DST_RDY is deasserted. In that case, the buffer keeps an output RX_DST_RDY asserted unless the FIFO is full. If the TX_DST_RDY is asserted, the buffer behaves as a set of register @@ -204,31 +282,42 @@

-
+
-
- -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - +
+
+
+
+
+
+
+ +
- +
+ +
-
-
-
- - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/logic/barrel_shifter/readme.html b/devel/comp/base/logic/barrel_shifter/readme.html index 61968edf3..c5cd2b935 100644 --- a/devel/comp/base/logic/barrel_shifter/readme.html +++ b/devel/comp/base/logic/barrel_shifter/readme.html @@ -1,52 +1,136 @@ - - - - - - - Barrel Shifter — NDK-FPGA Docs documentation - - + + + + - - - - - - + Barrel Shifter — NDK-FPGA documentation + + + + + + - + + + - -
- - -
+
-
-
-
- -
-
-
-
- +
+
+
+
+
-

Barrel Shifter

+

Barrel Shifter

-ENTITY BARREL_SHIFTER_GEN IS
+ENTITY BARREL_SHIFTER_GEN IS

Generically adjustable barrel shifter where single bits as well as whole blocks can be shifted. The direction can also be set.

Generics @@ -189,7 +264,7 @@
-ENTITY BARREL_SHIFTER_GEN_PIPED IS
+ENTITY BARREL_SHIFTER_GEN_PIPED IS
Generics
@@ -308,34 +383,52 @@ - +
- +
+ + Multi MEMx Counter> + +
- - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/logic/cnt_multi_memx/readme.html b/devel/comp/base/logic/cnt_multi_memx/readme.html index 6b7f12f96..b1b833c79 100644 --- a/devel/comp/base/logic/cnt_multi_memx/readme.html +++ b/devel/comp/base/logic/cnt_multi_memx/readme.html @@ -1,52 +1,136 @@ - - - - - - - Multi MEMx Counter — NDK-FPGA Docs documentation - - + + + + - - - - - - + Multi MEMx Counter — NDK-FPGA documentation + + + + + + - + + + - -
- - -
+
-
-
-
- -
-
-
-
- +
+
+
+
+
-

Multi MEMx Counter

+

Multi MEMx Counter

-ENTITY CNT_MULTI_MEMX IS
+ENTITY CNT_MULTI_MEMX IS

Implements statistics counters for multiple Channels using MEMX.

Generics

Generic
@@ -251,34 +326,52 @@ - +
- +
+ + H3 Class Hash> + +
- - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/logic/h3hash/readme.html b/devel/comp/base/logic/h3hash/readme.html index 99433570b..41e731049 100644 --- a/devel/comp/base/logic/h3hash/readme.html +++ b/devel/comp/base/logic/h3hash/readme.html @@ -1,52 +1,136 @@ - - - - - - - H3 Class Hash — NDK-FPGA Docs documentation - - + + + + - - - - - - + H3 Class Hash — NDK-FPGA documentation + + + + + + - + + + - -
- - -
+
-
-
-
- -
-
-
-
- +
+
+
+
+
-

H3 Class Hash

+

H3 Class Hash

-ENTITY H3_HASH IS
+ENTITY H3_HASH IS

Component for computing any hash function from universal H3 class. Universal hash functions have some interesting properties, for reference, check out this paper: https://www.cs.princeton.edu/courses/archive/fall09/cos521/Handouts/universalclasses.pdf. @@ -240,34 +315,52 @@

-
+
-
+
+
+
+
+ + + <Multi MEMx Counter + +
-
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
+ + Miscellaneous> + +
-
- -
- +
+ + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/logic/n_loop_op/readme.html b/devel/comp/base/logic/n_loop_op/readme.html index 4973f6ae2..85ffa402d 100644 --- a/devel/comp/base/logic/n_loop_op/readme.html +++ b/devel/comp/base/logic/n_loop_op/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - N_LOOP_OP — NDK-FPGA Docs documentation - - - - - - - - - + N_LOOP_OP — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

N_LOOP_OP

+

N_LOOP_OP

The N_LOOP_OP (N-loop operator) is a unit for performing multiple parallel read-modify-write operations over an multi-port memory. The user defines the number of read-modify-write interfaces (operators) and the number of read-only interfaces (these have simpler architecture) and the unit provides user-friendly interfaces for this to be done. There are 2 main reasons why this is easier compared to solving the problem yourself:

@@ -151,16 +221,16 @@ Try to keep this number as low as possible to avoid problems with timing and resource consumption.

-

Block diagram

+

Block diagram

-

Operator flow

+

Operator flow

Here is an example of how the N_LOOP_OP can be used when working with items stored in a memory. This example demonstrates how to use the unit’s interfaces and the overall flow of operators.

-

Situation

+

Situation

Lets say you have a memory with statistic 64 counters. Your design is connected to 3 independent interfaces (I0, I1 and I2). Each of the interfaces can send you a request to increment or decrement the a counter on a specific address (0 - 63) by 1. @@ -170,7 +240,7 @@

Situation -

Solution

+

Solution

To implement this example using the N_LOOP_OP you need to define the following:

  1. Number of operators.

    @@ -254,9 +324,9 @@

    Solution

-

Additional Features

+

Additional Features

-

Quick reset

+

Quick reset

Generics: QUICK_RESET_EN and RESET_VAL

The quick reset feature allows you to reset all values in the internal memory to a specific value by activating the RESET. This feature adds additional logic.

@@ -265,34 +335,84 @@

Quick reset

-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <Basic logic elements + +
- +
+ + Synchronous SR latch> + +
-
-
-
- - - +
+ + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/logic/sr_sync_latch/readme.html b/devel/comp/base/logic/sr_sync_latch/readme.html index e8aced0f4..9f6aa1906 100644 --- a/devel/comp/base/logic/sr_sync_latch/readme.html +++ b/devel/comp/base/logic/sr_sync_latch/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Synchronous SR latch — NDK-FPGA Docs documentation - - - - - - - - - + Synchronous SR latch — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

Synchronous SR latch

+

Synchronous SR latch

-ENTITY SR_SYNC_LATCH IS
+ENTITY SR_SYNC_LATCH IS

This component provides synchrnous SR latch behavior with some enhancements:

1. The forbidden state when both SET and RESET are asserted has been removed. @@ -203,34 +278,52 @@

-
+
-
+
+
+
+
+ + + <N_LOOP_OP + +
-
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
+ + Barrel Shifter> + +
-
-
-
- - - +
+ + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/mem/lvt_mem/readme.html b/devel/comp/base/mem/lvt_mem/readme.html index 1a46a7313..0c5481037 100644 --- a/devel/comp/base/mem/lvt_mem/readme.html +++ b/devel/comp/base/mem/lvt_mem/readme.html @@ -1,52 +1,136 @@ - - - - - - - Live value table memory — NDK-FPGA Docs documentation - - + + + + - - - - - - + Live value table memory — NDK-FPGA documentation + + + + + + - + + + - -
- - -
+
-
-
-
- -
-
-
-
- +
+
+
+
+
-

Live value table memory

+

Live value table memory

-ENTITY LVT_MEM IS
+ENTITY LVT_MEM IS

Multiported memory implementation inspired by https://dl.acm.org/doi/abs/10.1145/2629629 This approach is suitable for shallow memories since it implements smaller true multiported memories using registers. Thus underlying memories are @@ -241,34 +315,52 @@

-
+
-
+
+
+
+
+ + + <Multi-port BRAM + +
-
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
+ + FIFO components> + +
-
- -
- +
+ + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/mem/mp_bram/readme.html b/devel/comp/base/mem/mp_bram/readme.html index fca4d9b58..2e4a8b009 100644 --- a/devel/comp/base/mem/mp_bram/readme.html +++ b/devel/comp/base/mem/mp_bram/readme.html @@ -1,52 +1,136 @@ - - - - - - - Multi-port BRAM — NDK-FPGA Docs documentation - - + + + + - - - - - - + Multi-port BRAM — NDK-FPGA documentation + + + + + + - + + + - -
- - -
+
-
-
-
- -
-
-
-
- +
+
+
+
+
-

Multi-port BRAM

+

Multi-port BRAM

-ENTITY MP_BRAM IS
+ENTITY MP_BRAM IS

Multi-port BRAM. Currently supports only one write port. This will change in future. Amount of read ports is not restricted.

Generics
@@ -304,34 +378,52 @@ - +
- +
+ + Live value table memory> + +
- - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/mem/np_lutram/readme.html b/devel/comp/base/mem/np_lutram/readme.html index bbe5508dd..8de16422b 100644 --- a/devel/comp/base/mem/np_lutram/readme.html +++ b/devel/comp/base/mem/np_lutram/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - NP LUT RAM — NDK-FPGA Docs documentation - - - - - - - - - + NP LUT RAM — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

NP LUT RAM

+

NP LUT RAM

-ENTITY np_lutram IS
+ENTITY np_lutram IS

Generic N-port distributed LUT memory

Generics
@@ -215,34 +289,52 @@ - +
- +
+ + Simple dual-port BRAM> + +
- - - - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/mem/sdp_bram/readme.html b/devel/comp/base/mem/sdp_bram/readme.html index 868d974f1..1c54579e6 100644 --- a/devel/comp/base/mem/sdp_bram/readme.html +++ b/devel/comp/base/mem/sdp_bram/readme.html @@ -1,52 +1,136 @@ - - - - - - - Simple dual-port BRAM — NDK-FPGA Docs documentation - - + + + + - - - - - - + Simple dual-port BRAM — NDK-FPGA documentation + + + + + + - + + + - -
- +
-
- -
-
-
- -
-
-
-
- +
+
+
+
+
-

Simple dual-port BRAM

+

Simple dual-port BRAM

-ENTITY SDP_BRAM IS
+ENTITY SDP_BRAM IS
Generics
@@ -304,10 +378,10 @@
-

Simple dual-port BRAM with Byte Enable

+

Simple dual-port BRAM with Byte Enable

-ENTITY SDP_BRAM_BE IS
+ENTITY SDP_BRAM_BE IS

A wrapper for SDP_BRAM to abstract Block Enable signal. (Byte Enable with arbitrary width.)

Generics

Generic
@@ -463,34 +537,73 @@

Simple dual-port BRAM with Byte Enable - +
+ + Multi-port BRAM> + +
- - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/misc/crossbarx/readme.html b/devel/comp/base/misc/crossbarx/readme.html index 4c2dc48d4..0e7196dbe 100644 --- a/devel/comp/base/misc/crossbarx/readme.html +++ b/devel/comp/base/misc/crossbarx/readme.html @@ -1,52 +1,136 @@ - - - - - - - CrossbarX — NDK-FPGA Docs documentation - - + + + + - - - - - - + CrossbarX — NDK-FPGA documentation + + + + + + - + + + - -
- +
-
- -
-
-
- -
-
-
-
- +
+
+
+
+
-

CrossbarX

+

CrossbarX

This unit performs data transfer between two buffers connected on SRC_BUF and DST_BUF interfaces based on Transactions passed on the TRANS interface. Transactions can be passed on multiple independent Streams. Different Streams must have different Buffer A but common Buffer B. @@ -144,12 +212,12 @@ The unit propagates Completed signal for each done Transaction together with its Metadata. These Completed signals have the same order as the input Transactions (within each Stream).

-

Block diagram

+

Block diagram

-

Generics

+

Generics

@@ -252,7 +320,7 @@

Block diagram -

Ports

+

Ports

Name
@@ -388,7 +456,7 @@

Block diagram -

Architecture

+

Architecture

The internal architecture of CrossbarX can be seen in the above diagram. The main advantage of the CrossbarX is its scalability when performing parallel data transfers on a very wide data bus. For this reason, the component allows to setup multiple independent Streams od Transactions. @@ -421,40 +489,85 @@

Architecture -

References

+

References

For more detailed description refer to Jan Kubalek’s thesis 2019/20.

- +
- +
+ + Transaction Sorter> + +
- - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/misc/event_counter/readme.html b/devel/comp/base/misc/event_counter/readme.html index 1a5b549b7..d366a476c 100644 --- a/devel/comp/base/misc/event_counter/readme.html +++ b/devel/comp/base/misc/event_counter/readme.html @@ -1,52 +1,136 @@ - - - - - - - Event Counter — NDK-FPGA Docs documentation - - + + + + - - - - - - + Event Counter — NDK-FPGA documentation + + + + + + - + + + - -
- +
-
- -
-
-
- -
-
-
-
- +
+
+
+
+
-

Event Counter

+

Event Counter

The Event Counter is a debuging unit for receiving statistics of occurence frequency of a certain event. It is made accessible through MI interface using the Event Counter MI Wrapper. The MI address space consists of 4 addresses which are configured by the user as generics.

@@ -144,12 +215,12 @@

Once a whole interval has been counted, the events counter and the cycles counter are reset and the counting automatically continues to the next interval. From the view of the user this means, that the values read from the output register can change all the time.

-

Architecture

+

Architecture

-

Capture feature

+

Capture feature

Sometimes it is useful to be able to see the evolution of the event’s occurence across time. The user can read the output counter register to get the rough idea. (e.g. NOW events are occuring a lot. A second later there are none.) @@ -192,7 +263,7 @@

Capture feature
-ENTITY EVENT_COUNTER_MI_WRAPPER IS
+ENTITY EVENT_COUNTER_MI_WRAPPER IS
Generics

Name
@@ -294,34 +365,76 @@

Capture feature - +
+ + Pulse short> + +
- - - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/misc/packet_planner/readme.html b/devel/comp/base/misc/packet_planner/readme.html index 122ad8295..8d2bc54cd 100644 --- a/devel/comp/base/misc/packet_planner/readme.html +++ b/devel/comp/base/misc/packet_planner/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Packet Planner — NDK-FPGA Docs documentation - - - - - - - - - + Packet Planner — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

Packet Planner

+

Packet Planner

The Packet Planner processes input MVB packet headers by assigning addresses to an outside buffer space to each packet, so that they are placed one after another with the needed inter-packet gaps and alignment. With the help from the input read pointer from the outside buffer it also checks space availability and stops the header input before the buffer overflows.

The user specifies:

@@ -152,7 +222,7 @@ This is meant mainly for debug purposes. You can also use it to simulate an infinite target buffer space by connecting it directly back as the read pointer.

-

Architecture

+

Architecture

The Packet Planner receives multiple input packet headers from multiple independent interfaces (Streams). @@ -194,7 +264,7 @@

Architecture -

Additional features

+

Additional features

Because the component has FIFOX Multis on its input and outputs, the number of parallel headers processed in the internal pipeline can be set independently with generic PLANNED_PKTS. This may allow the user to reduce internal logic complexity at the cost of throughput for small packets.

The internal pipeline is enabled by Almost Full signals from the output FIFOs. @@ -202,40 +272,83 @@

Additional features -

References

+

References

For more detailed description refer to Jan Kubalek’s thesis 2019/20.

-
+
-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <Transaction Sorter + +
- +
+ + Event Counter> + +
-
-
-
- - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/misc/pulse_short/readme.html b/devel/comp/base/misc/pulse_short/readme.html index e89dce1ea..9c32c37cf 100644 --- a/devel/comp/base/misc/pulse_short/readme.html +++ b/devel/comp/base/misc/pulse_short/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Pulse short — NDK-FPGA Docs documentation - - - - - - - - - + Pulse short — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

Pulse short

+

Pulse short

-ENTITY PULSE_SHORT IS
+ENTITY PULSE_SHORT IS

This component allows to shorten arbitrary long pulse on the input TRIGGER to only one clock period short pulse (driven by the BCLK). @@ -210,34 +285,52 @@

-
+
-
+
+
+
+
+ + + <Event Counter + +
-
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
+ + Controllers & TSU> + +
-
-
-
- - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/misc/trans_sorter/readme.html b/devel/comp/base/misc/trans_sorter/readme.html index 312571f8f..ac70c0ecc 100644 --- a/devel/comp/base/misc/trans_sorter/readme.html +++ b/devel/comp/base/misc/trans_sorter/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Transaction Sorter — NDK-FPGA Docs documentation - - - - - - - - - + Transaction Sorter — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

Transaction Sorter

+

Transaction Sorter

This unit converts out-of-order confirmations of transactions to the original order of the transactions. The unit has 3 interfaces:

    @@ -152,7 +224,7 @@
-

Architecture

+

Architecture

The main parts of the architecture are the confirmation memory register array and the transaction sorage FIFO. @@ -177,34 +249,75 @@

Architecture

-
+ -
- -
-

© Copyright 2024, CESNET z.s.p.o..

-
- - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
+
+
+
+
+ + + <CrossbarX + +
- +
+ + Packet Planner> + +
-
-
-
- - - + + + +
+ Git branch: devel
Git hash: ea2302fb +
+ +

+ +

+ \ No newline at end of file diff --git a/devel/comp/base/pkg/readme.html b/devel/comp/base/pkg/readme.html index eea33f69e..1c46b5b2f 100644 --- a/devel/comp/base/pkg/readme.html +++ b/devel/comp/base/pkg/readme.html @@ -1,50 +1,134 @@ - - - - - - - Packages — NDK-FPGA Docs documentation - - + + + + - - - - - - + Packages — NDK-FPGA documentation + + + + + + - + + + - -
- +
-
- -
-
-
- -
-
-
-
- +
+
+
+
+
-

Packages

+

Packages

PACKAGE eth_hdr_pack IS
@@ -250,31 +328,42 @@

Packages

-
+
-
+
+
+
+
+
+
+ +
- +
+ +
-
-
- - + + + +
+ Git branch: devel
Git hash: ea2302fb +
- +

+ +

+ \ No newline at end of file diff --git a/devel/comp/ctrls/sdm_client/readme.html b/devel/comp/ctrls/sdm_client/readme.html index bad685b56..9e525adf0 100644 --- a/devel/comp/ctrls/sdm_client/readme.html +++ b/devel/comp/ctrls/sdm_client/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - SDM CLIENT — NDK-FPGA Docs documentation - - - - - - - - - + SDM CLIENT — NDK-FPGA documentation + + + + + + - - - -
- - -
- -
-
-
- -
-
-
-
- +
+ +
+
+
+
+
-

SDM CLIENT

+

SDM CLIENT

This component acts as a bridge between a host and the SDM (Secure Device Manager) on Intel FPGAs (Stratix 10, Agilex). It converts MI to Avalon-MM interface and uses Mailbox Client FPGA IP to send commands and obtain status information from the SDM peripheral clients. There are multiple pre-defined functions available:

@@ -131,7 +203,7 @@

  • Performing RSU (Remote System Update)

    • -

    Specification

    +

    Specification

    Avalon-MM and Mailbox Client IP use 32bit word addressing. In order to avoid working with unaligned addresses, MI addresses are shifted 2 bits to the right (word align) and after that 4 lowest bits are used for Mailbox Client’s OFFSET (spans from 0 to 10). Mailbox Client IP uses a command fifo on OFFSET[0] where you should direct the commands and their arguments in a sequence.

    @@ -144,12 +216,12 @@

    SpecificationMailbox Client Intel FPGA IP User Guide for more detailed information.

    -

    Block diagram

    +

    Block diagram

    ../../../_images/sdm_client_arch.svg
    -

    More references

    +

    More references

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Controllers & TSU + +
    - +
    + + TSU GEN> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/data_logger/mem_logger/readme.html b/devel/comp/debug/data_logger/mem_logger/readme.html index 95b94d74c..7a03e0677 100644 --- a/devel/comp/debug/data_logger/mem_logger/readme.html +++ b/devel/comp/debug/data_logger/mem_logger/readme.html @@ -1,52 +1,136 @@ - - - - - - - Mem logger — NDK-FPGA Docs documentation - - + + + + - - - - - - + Mem logger — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Mem logger

    +

    Mem logger

    Mem logger is wrap around DATA_LOGGER that is able to log common statistics about memory interface. Example usage can be found in MEM_TESTER component.

    -

    Key features

    +

    Key features

    Generic

    @@ -355,7 +422,7 @@

    Component port and generics description -

    Instance template (simple usage)

    +

    Instance template (simple usage)

    mem_logger_i : entity work.MEM_LOGGER
 generic map (
     MEM_DATA_WIDTH          => MEM_DATA_WIDTH       ,
@@ -392,7 +459,7 @@ 
    Instance template (simple usage)
-
    Control SW
    
+
    Control SW
    
 
    First install DATA_LOGGER package
    
 
      
 
    • You also need to install python nfb package
      • 
@@ -409,34 +476,78 @@ 
      Control SW
    - +
    + + JTAG-over-protocol Client> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/data_logger/readme.html b/devel/comp/debug/data_logger/readme.html index 250be4358..dd13f69cb 100644 --- a/devel/comp/debug/data_logger/readme.html +++ b/devel/comp/debug/data_logger/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Data logger — NDK-FPGA Docs documentation - - - - - - - - - + Data logger — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Data logger

    +

    Data logger

    Data logger is used to log statistics about a specific events and make them available on the MI bus. Simple usage can be seen in MEM_LOGGER component.

    -

    Key features

    +

    Key features

    Generic
    @@ -419,7 +487,7 @@

    Component port and generics description -

    Instance template (simple usage)

    +

    Instance template (simple usage)

    data_logger_i : entity work.DATA_LOGGER
 generic map (
     MI_DATA_WIDTH       => MI_DATA_WIDTH  ,
@@ -451,7 +519,7 @@ 
    Instance template (simple usage)
-
    Instance template (full usage)
    
+
    Instance template (full usage)
    
 
    data_logger_i : entity work.DATA_LOGGER
 generic map (
     MI_DATA_WIDTH       => MI_DATA_WIDTH  ,
@@ -524,7 +592,7 @@ 
    Instance template (full usage)
-
    Control SW
    
+
    Control SW
    
 
    Folder data_logger/sw/ contains Python3 package that provides:
    
 
      
 
    • Module for basic interaction with DATA_LOGGER
      • 
@@ -543,7 +611,7 @@ 
      Control SW
-
      MI address space
      
+
      MI address space
      
 
      0x0000: CTRL REG
         0: sw rst
         1: rst done
@@ -604,34 +672,81 @@ 
      MI address space
      
           
      
-          
     
+    
 
-  
    
-
-  
    
-    
    © Copyright 2024, CESNET z.s.p.o..
    
-  
    
-
-  Built with Sphinx using a
-    theme
-    provided by Read the Docs.
-   
+    
+     
+      
    
+    
    
+    
    
+        
    
+            
    
+                
+                
+                    <Latency meter
+                
+            
    
 
-
+            
    
+                
+                Mem logger>
+                
+            
    
         
    
-      
    
-    
-
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/histogramer/readme.html b/devel/comp/debug/histogramer/readme.html index 6d2dc62ea..199ed3cf6 100644 --- a/devel/comp/debug/histogramer/readme.html +++ b/devel/comp/debug/histogramer/readme.html @@ -1,52 +1,136 @@ - - - - - - - Histogramer — NDK-FPGA Docs documentation - - + + + + - - - - - - + Histogramer — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Histogramer

    +

    Histogramer

    Histogramer is used to manage a histogram.

    -

    Key features

    +

    Key features

    • Histogram boxes are stored inside Block RAM

    • Each box will be sequentially cleared after the reset

      • @@ -138,10 +210,10 @@

      Key features -

      Component port and generics description

      +

      Component port and generics description

      -ENTITY HISTOGRAMER IS
      +ENTITY HISTOGRAMER IS
      Generics

    Generic
    @@ -254,7 +326,7 @@

    Component port and generics description -

    Instance template

    +

    Instance template

    histogrammer_i : entity work.HISTOGRAMER
 generic map(
     INPUT_WIDTH             => INPUT_WIDTH,
@@ -283,34 +355,77 @@ 
    Instance template
    - +
    + + Latency meter> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/jtag_op_client/readme.html b/devel/comp/debug/jtag_op_client/readme.html index fdf703838..a6ea7b523 100644 --- a/devel/comp/debug/jtag_op_client/readme.html +++ b/devel/comp/debug/jtag_op_client/readme.html @@ -1,52 +1,136 @@ - - - - - - - JTAG-over-protocol Client — NDK-FPGA Docs documentation - - + + + + - - - - - - + JTAG-over-protocol Client — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    JTAG-over-protocol Client

    +

    JTAG-over-protocol Client

    This component is used for software communication with internal debug hardware present on Intel FPGAs. It acts as MI wrapper of the JTAG-over-protocol IP core and provides the capability of debugging card designs via e. g. SignalTap over PCIe without the need of connecting a JTAG cable. The debugging is done via a running instance of etherlink application which translates the traffic between JTAG server (communicating with SignalTap) and nfb driver.

    -

    Address space size

    +

    Address space size

    Size of the JTAG-over-protocol IP address space depends on the configuration given while generating the IP core. The total memory occupied by the component consists of three distinct memory blocks for each subpart (as mentioned in the documentation of the IP core).

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Mem logger + +
    - +
    + + UVM Verification> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/latency_meter/readme.html b/devel/comp/debug/latency_meter/readme.html index 92e3adbc4..34912e609 100644 --- a/devel/comp/debug/latency_meter/readme.html +++ b/devel/comp/debug/latency_meter/readme.html @@ -1,52 +1,136 @@ - - - - - - - Latency meter — NDK-FPGA Docs documentation - - + + + + - - - - - - + Latency meter — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Latency meter

    +

    Latency meter

    Latency meter is used to measure the duration of a specific event.

    -

    Key features

    +

    Key features

    • Measures the number of ticks between the start and the end of a given event

    • Multiple parallel events can be measured

      • @@ -133,10 +205,10 @@

      Key features -

      Component port and generics description

      +

      Component port and generics description

      -ENTITY LATENCY_METER IS
      +ENTITY LATENCY_METER IS
      Generics

    Generic
    @@ -218,7 +290,7 @@

    Component port and generics description -

    Instance template

    +

    Instance template

    latency_meter_i : entity work.LATENCY_METER
 generic map (
     DATA_WIDTH              => DATA_WIDTH,
@@ -239,34 +311,77 @@ 
    Instance template
    - +
    + + Data logger> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/mem_tester/amm_gen/readme.html b/devel/comp/debug/mem_tester/amm_gen/readme.html index 91f1393ff..1be1ee908 100644 --- a/devel/comp/debug/mem_tester/amm_gen/readme.html +++ b/devel/comp/debug/mem_tester/amm_gen/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - AMM_GEN — NDK-FPGA Docs documentation - - - - - - - - - + AMM_GEN — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    AMM_GEN

    +

    AMM_GEN

    This component is used to manually read or write to the external memory from the MI bus via the AMM bus. It has to be connected to EMIF Hard IP.

    -

    Internal Architecture

    +

    Internal Architecture

    AMM data bus width is significantly larger than MI data bus width and all data words in the burst have to be sent/received in one continuous request. Therefore there is a buffer that can be first filled with MI bus transactions and then sent to EMIF. @@ -169,7 +234,7 @@

    Internal Architecture

    -

    MI Bus Control

    +

    MI Bus Control

    MI Address Space Definition

    BASE + 0x00 -- ctrl
               1. bit -- memory write
@@ -207,34 +272,76 @@ 
    MI Bus Control
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <DDR4 Memory Tester + +
    - +
    + + AMM_PROBE> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/mem_tester/amm_probe/readme.html b/devel/comp/debug/mem_tester/amm_probe/readme.html index 4e0394613..2c781e921 100644 --- a/devel/comp/debug/mem_tester/amm_probe/readme.html +++ b/devel/comp/debug/mem_tester/amm_probe/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - AMM_PROBE — NDK-FPGA Docs documentation - - - - - - - - - + AMM_PROBE — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    AMM_PROBE

    +

    AMM_PROBE

    Warning

    AMM_PROBE is now depreciated and MEM_LOGGER should be used!

    @@ -148,7 +213,7 @@

  • Latency histogram of read requests

    • -

    MI Bus Control

    +

    MI Bus Control

    MI Address Space Definition

    BASE + 0x00 -- ctrl
               0. bit -- reset
@@ -187,34 +252,75 @@ 
    MI Bus Control
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <AMM_GEN + +
    - +
    + + MEM_TESTER Software> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/debug/mem_tester/readme.html b/devel/comp/debug/mem_tester/readme.html index 9019f64eb..28e48d65c 100644 --- a/devel/comp/debug/mem_tester/readme.html +++ b/devel/comp/debug/mem_tester/readme.html @@ -1,52 +1,136 @@ - - - - - - - DDR4 Memory Tester — NDK-FPGA Docs documentation - - + + + + - - - - - - + DDR4 Memory Tester — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    DDR4 Memory Tester

    +

    DDR4 Memory Tester

    MEM_TESTER is used to test external DDR memory to detect failures and overal performance of the memory.

    -

    Key features

    +

    Key features

    • Memory interface is compatible with AMM (Avalon-Memory-Mapped) interface and Intel EMIF Hard IP

    • Basic test workflow:

      @@ -185,10 +251,10 @@

      Key features -

      Component port and generics description

      +

      Component port and generics description

      -ENTITY MEM_TESTER IS
      +ENTITY MEM_TESTER IS
      Generics

    Generic
    @@ -478,7 +544,7 @@

    Component port and generics description -

    Control SW

    +

    Control SW

    Because the measurement is handled by MEM_LOGGER (DATA_LOGGER wrap) you need to install its package:

    Generic
    @@ -280,34 +358,52 @@ - +
    - +
    + + Header Insertor> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/comp/rx/readme.html b/devel/comp/dma/dma_calypte/comp/rx/readme.html index 0333b1d03..12899e682 100644 --- a/devel/comp/dma/dma_calypte/comp/rx/readme.html +++ b/devel/comp/dma/dma_calypte/comp/rx/readme.html @@ -1,52 +1,136 @@ - - - - - - - RX DMA Calypte — NDK-FPGA Docs documentation - - + + + + - - - - - - + RX DMA Calypte — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    RX DMA Calypte

    +

    RX DMA Calypte

    This is receiving part of the DMA Calypte core. Simple block scheme is provided in the following figure:

    @@ -139,7 +218,7 @@
    -ENTITY RX_DMA_CALYPTE IS
    +ENTITY RX_DMA_CALYPTE IS
    Generics
    @@ -416,7 +495,7 @@
    -

    Control/Status Registers

    +

    Control/Status Registers

    In order for the controller to be controlled by the software, an address space with configuration/status (C/S) registers is initialized. Currently, each channel contains its own set of registers with the overall size of 128 B. The @@ -425,7 +504,7 @@

    Control/Status Registers -

    + @@ -617,18 +696,18 @@

    Control/Status Registers -

    UVM Verification

    +

    UVM Verification

    ../../../../../_images/uvm_ver.jpg
    -

    Verification Plan

    +

    Verification Plan

    TBD

    -

    Local Subcomponents

    +

    Local Subcomponents

    - +
    + + Input Buffer> + +
    - -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/comp/tx/comp/chan_start_stop_ctrl/readme.html b/devel/comp/dma/dma_calypte/comp/tx/comp/chan_start_stop_ctrl/readme.html index e7cf3dcb0..895a48156 100644 --- a/devel/comp/dma/dma_calypte/comp/tx/comp/chan_start_stop_ctrl/readme.html +++ b/devel/comp/dma/dma_calypte/comp/tx/comp/chan_start_stop_ctrl/readme.html @@ -1,52 +1,136 @@ - - - - - - - Channel Start/stop control — NDK-FPGA Docs documentation - - + + + + - - - - - - + Channel Start/stop control — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Channel Start/stop control

    +

    Channel Start/stop control

    -ENTITY TX_DMA_CHAN_START_STOP_CTRL IS
    +ENTITY TX_DMA_CHAN_START_STOP_CTRL IS

    This component controls the acception of incoming frames according to the running state of a specific DMA channel. When channel is stopped, all incoming frames to that channel are dropped. When channel is running, all incoming frames on that channel are accepted and reach the @@ -390,7 +468,7 @@

    -

    General subcomponents

    +

    General subcomponents

    @@ -398,34 +476,75 @@

    General subcomponents -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Metadata Extractor + +
    - +
    + + Packet Dispatcher> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/comp/tx/comp/metadata_extractor/readme.html b/devel/comp/dma/dma_calypte/comp/tx/comp/metadata_extractor/readme.html index 2bfef633c..c15b12279 100644 --- a/devel/comp/dma/dma_calypte/comp/tx/comp/metadata_extractor/readme.html +++ b/devel/comp/dma/dma_calypte/comp/tx/comp/metadata_extractor/readme.html @@ -1,52 +1,136 @@ - - - - - - - Metadata Extractor — NDK-FPGA Docs documentation - - + + + + - - - - - - + Metadata Extractor — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Metadata Extractor

    +

    Metadata Extractor

    -ENTITY TX_DMA_METADATA_EXTRACTOR IS
    +ENTITY TX_DMA_METADATA_EXTRACTOR IS

    This component processes the incoming PCIe transactions. This does not care about whole DMA frames delimited by the DMA header but processes all frames in general. The metadata on the output are chosen according their usefullness later in the design.

    @@ -298,7 +376,7 @@
    -

    General subcomponents

    +

    General subcomponents

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <TX DMA Calypte + +
    - +
    + + Channel Start/stop control> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/comp/tx/comp/packet_dispatcher/readme.html b/devel/comp/dma/dma_calypte/comp/tx/comp/packet_dispatcher/readme.html index f5a5a0c61..3ce166d1c 100644 --- a/devel/comp/dma/dma_calypte/comp/tx/comp/packet_dispatcher/readme.html +++ b/devel/comp/dma/dma_calypte/comp/tx/comp/packet_dispatcher/readme.html @@ -1,52 +1,136 @@ - - - - - - - Packet Dispatcher — NDK-FPGA Docs documentation - - + + + + - - - - - - + Packet Dispatcher — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Packet Dispatcher

    +

    Packet Dispatcher

    -ENTITY TX_DMA_PKT_DISPATCHER IS
    +ENTITY TX_DMA_PKT_DISPATCHER IS

    This component dispatches the frames from data buffers according to available DMA Headers. Frames are dispatched from all channels in order in which DMA headers came from the PCI Express. After dispatching a frame, the component issues an update of header and data pointers. If a channel @@ -419,34 +497,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <Channel Start/stop control + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + Transaction buffer> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/comp/tx/comp/pcie_trans_buffer/readme.html b/devel/comp/dma/dma_calypte/comp/tx/comp/pcie_trans_buffer/readme.html index 9fae4508e..476c60686 100644 --- a/devel/comp/dma/dma_calypte/comp/tx/comp/pcie_trans_buffer/readme.html +++ b/devel/comp/dma/dma_calypte/comp/tx/comp/pcie_trans_buffer/readme.html @@ -1,52 +1,136 @@ - - - - - - - Transaction buffer — NDK-FPGA Docs documentation - - + + + + - - - - - - + Transaction buffer — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Transaction buffer

    +

    Transaction buffer

    -ENTITY TX_DMA_PCIE_TRANS_BUFFER IS
    +ENTITY TX_DMA_PCIE_TRANS_BUFFER IS

    This component instantiaties data buffers for all channels. Internally, the component constists of Block RAMs. This component has the largest footprint since data are stored by bytes for every channel. The component behaves as quasi buffer to which data can by written with the resolution @@ -270,7 +348,7 @@

    -

    General subcomponents

    +

    General subcomponents

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Packet Dispatcher + +
    - +
    + + Software Manager> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/comp/tx/comp/software_manager/readme.html b/devel/comp/dma/dma_calypte/comp/tx/comp/software_manager/readme.html index a667116f7..f5962ccee 100644 --- a/devel/comp/dma/dma_calypte/comp/tx/comp/software_manager/readme.html +++ b/devel/comp/dma/dma_calypte/comp/tx/comp/software_manager/readme.html @@ -1,52 +1,136 @@ - - - - - - - Software Manager — NDK-FPGA Docs documentation - - + + + + - - - - - - + Software Manager — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Software Manager

    +

    Software Manager

    -ENTITY TX_DMA_SW_MANAGER IS
    +ENTITY TX_DMA_SW_MANAGER IS

    This component provides control interface for TX DMA Calypte controller. It contains MI configuration registers which allows acces from the SW to control some behavior of the controller or to read status information. Each channel has its own set of registers. The component serves as @@ -385,7 +463,7 @@

    -

    General components

    +

    General components

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Transaction buffer + +
    - +
    + + Debug Tools> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/comp/tx/readme.html b/devel/comp/dma/dma_calypte/comp/tx/readme.html index 0a192a0e4..e66cf5538 100644 --- a/devel/comp/dma/dma_calypte/comp/tx/readme.html +++ b/devel/comp/dma/dma_calypte/comp/tx/readme.html @@ -1,52 +1,136 @@ - - - - - - - TX DMA Calypte — NDK-FPGA Docs documentation - - + + + + - - - - - - + TX DMA Calypte — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    TX DMA Calypte

    +

    TX DMA Calypte

    This is the transmitting part of the DMA Calypte core. TX direction behaves similarly to the RX DMA Calypte. Data buffers are provided in the hardware to which the data can be stored. The frames are output on the USR_TX_ side and @@ -149,7 +228,7 @@

    -ENTITY TX_DMA_CALYPTE IS
    +ENTITY TX_DMA_CALYPTE IS
    Generics

    Generic
    Tab. 1Tab. 1

    Address

    Name
    @@ -452,7 +531,7 @@
    -

    Control/Status Registers

    +

    Control/Status Registers

    In order for the controller to be controlled by the software, an address space with configuration/status (C/S) registers is initialized. Currently, each channel contains its own set of registers with the overall size of 128 B. The @@ -462,7 +541,7 @@

    Control/Status Registers -

    + @@ -654,7 +733,7 @@

    Control/Status Registers -

    UVM Verification

    +

    UVM Verification

    ../../../../../_images/uvm_ver1.jpg @@ -662,11 +741,11 @@

    UVM Verification -

    Verification Plan

    +

    Verification Plan

    All of these tests were checked in a verification with a random seed. The verification files are located in the uvm/ directory

    Generic
    Tab. 1Tab. 1

    Address

    Name
    - +@@ -730,7 +809,7 @@

    Verification Plan -

    Local Subcomponents

    +

    Local Subcomponents

    +
    -     +
    + + Metadata Extractor> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/dma/dma_calypte/readme.html b/devel/comp/dma/dma_calypte/readme.html index f13fe8f1b..9e387f9f1 100644 --- a/devel/comp/dma/dma_calypte/readme.html +++ b/devel/comp/dma/dma_calypte/readme.html @@ -1,52 +1,136 @@ - - - - - - - DMA Calypte — NDK-FPGA Docs documentation - - + + + + - - - - - - + DMA Calypte — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    DMA Calypte

    +

    DMA Calypte

    This core provides simple DMA functionality for both RX and TX directions. The design was primary focused on the lowest latency possible for the transaction from the input of the DMA core to reach its output. The block scheme @@ -140,7 +213,7 @@

    -ENTITY DMA_CALYPTE IS
    +ENTITY DMA_CALYPTE IS
    Generics
    Tab. 2Tab. 2
    @@ -596,7 +669,7 @@
    -

    Supported PCIe Configurations

    +

    Supported PCIe Configurations

    The design can be configured for various bus widths and PCIe IP core configurations.

      @@ -617,7 +690,7 @@

      Supported PCIe Configurations -

      Local Subcomponents

      +

      Local Subcomponents

      - +
      + + RX DMA Calypte> + +
      - -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/flu_tools/readme.html b/devel/comp/flu_tools/readme.html index 087ee52f7..f6ed25aec 100644 --- a/devel/comp/flu_tools/readme.html +++ b/devel/comp/flu_tools/readme.html @@ -1,50 +1,134 @@ - - - - - - - FLU bus specification — NDK-FPGA Docs documentation - - + + + + - - - - - - + FLU bus specification — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    FLU bus specification

    +

    FLU bus specification

    This page describes the FrameLinkUnaligned (FLU) protocol, which is a successor of the FrameLink protocol. FrameLinkUnaligned (or FLU) is designed for wide data busses (256 bits and above) without wasting as much bandwidth as with FrameLink. Main differences:

    • Adds support for unaligned start of packet. Fineness of the alignment is a protocol parameter (width of the SOP_POS signal).

      • @@ -115,7 +193,7 @@

    • Uses positive logic. No _N suffixes.

    -

    Table of generics

    +

    Table of generics

    These are generics of the modules using the FLU protocol.

    Generic
    @@ -137,7 +215,7 @@

    Table of generics -

    Table of signals

    +

    Table of signals

    @@ -186,7 +264,7 @@

    Table of signals -

    Usage guidelines

    +

    Usage guidelines

    Signal name
    @@ -315,34 +391,52 @@ - +
    - +
    + + Metadata Insertor> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/enabler/readme.html b/devel/comp/mfb_tools/flow/enabler/readme.html index 53f6e0519..7c5c20fc3 100644 --- a/devel/comp/mfb_tools/flow/enabler/readme.html +++ b/devel/comp/mfb_tools/flow/enabler/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Enabler — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Enabler — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Enabler

    +

    MFB Enabler

    -ENTITY MFB_ENABLER IS
    +ENTITY MFB_ENABLER IS

    This component enables sending of MFB frames to the output. For this purpose, it uses the TX_ENABLE port. Enabling starts from the first SOF. @@ -334,34 +410,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MFB Splitter + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + Rate Limiter> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/frame_masker/readme.html b/devel/comp/mfb_tools/flow/frame_masker/readme.html index 45780e2d0..0bfeca42a 100644 --- a/devel/comp/mfb_tools/flow/frame_masker/readme.html +++ b/devel/comp/mfb_tools/flow/frame_masker/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Frame Masker — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Frame Masker — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Frame Masker

    +

    MFB Frame Masker

    -ENTITY MFB_FRAME_MASKER IS
    +ENTITY MFB_FRAME_MASKER IS
    Generics
    @@ -389,7 +460,7 @@
    -

    Component specification

    +

    Component specification

    The Frame Masker 2 outputs one or more frames according to the user’s specification through the TX_MASK port. This Mask (set by the user/verification) is valid with TX_DST_RDY and also with SOFs in the output word. The TX SOF and EOF ports with the suffix “MASKED” are part of the standard output MFB interface that contains the masked frames. @@ -412,7 +483,7 @@

    Component specification

    -

    Examples

    +

    Examples

    Example 1 demonstates a common reading of 2 packets in one clock cycle. Note that the values of Mask can be arbitrary in Regions without SOF (SOF_UNMASKED). So instead of Mask 1 0 1 0, it could be also written as 1 x 1 x. @@ -600,9 +671,9 @@

    Examples

    -

    Verification plan

    +

    Verification plan

    Generic
    - +@@ -662,34 +733,77 @@

    Verification plan - +
    + + MFB FRAME TRIMMER> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/frame_packer/readme.html b/devel/comp/mfb_tools/flow/frame_packer/readme.html index 01b5bc1a7..83d420b11 100644 --- a/devel/comp/mfb_tools/flow/frame_packer/readme.html +++ b/devel/comp/mfb_tools/flow/frame_packer/readme.html @@ -1,52 +1,136 @@ - - - - - - - Frame Packer — NDK-FPGA Docs documentation - - + + + + - - - - - - + Frame Packer — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Frame Packer

    +

    Frame Packer

    -ENTITY FRAME_PACKER IS
    +ENTITY FRAME_PACKER IS

    The FRAME_PACKER module is used to create Super-Packets. The incoming packets are aligned to the BLOCKs so that the space between them is minimal (ranges from 0 to 7 items per each packet). The size of the Super-Packet is set by the parameter SPKT_SIZE_MIN. This value is used for length @@ -402,7 +474,7 @@

    -

    Architecture

    +

    Architecture

    The Frame Packer operates in the following way. The MFB and MVB has to be synchronized as the channel ID of each packet is used to sort incoming packets. This is done at the input using a Metadata Insertor.

    @@ -446,40 +518,82 @@

    ArchitectureMVB_FIFO which is directly connected to the output MVB interface.

    -

    References

    +

    References

    For more detailed description refer to David Beneš’s master thesis (2023/2024)

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MFB Reconfigurator + +
    - +
    + + Frame Unpacker> + +
    -
    -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/frame_unpacker/readme.html b/devel/comp/mfb_tools/flow/frame_unpacker/readme.html index 9679e2666..6e5070d56 100644 --- a/devel/comp/mfb_tools/flow/frame_unpacker/readme.html +++ b/devel/comp/mfb_tools/flow/frame_unpacker/readme.html @@ -1,52 +1,136 @@ - - - - - - - Frame Unpacker — NDK-FPGA Docs documentation - - + + + + - - - - - - + Frame Unpacker — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Frame Unpacker

    +

    Frame Unpacker

    -ENTITY FRAME_UNPACKER IS
    +ENTITY FRAME_UNPACKER IS

    This unit accepts and processes SuperPackets. SuperPackets consist of one or more MFB frames. Each of these individual frames has a special header:

    @@ -420,7 +491,7 @@
    -

    Arcitecture

    +

    Arcitecture

    The Frame Unpacker operates in the following way. First, it extracts the length of the first individual frame of the SuperPacket from the first header (located immediately behind SOF). To get the offset of the SOF of the following individual frame, it makes a sum of the length (from the header), length of the header (a constant), and the SOF POS (which is offset by the region it is located in). @@ -448,18 +519,18 @@

    Arcitecture -

    Block diagram

    +

    Block diagram

    -

    Subcomponents

    +

    Subcomponents

    The Frame Unpacker has two dedicated subcomponents: the Offset Processor and the SOF Creator. They are illustrated at the bottom of the diagram above and documented below.

    Offset Processor

    -ENTITY OFFSET_PROCESSOR IS
    +ENTITY OFFSET_PROCESSOR IS

    The Offset Processor (OP) receives the offset from the OP in the previous stage along with its SOF (the Old SOF). From the SOF Creator (also in the previous stage), it receives the extracted Length and its own SOF (the New SOF). Based on the Old SOF, it propagates either the received offset (when Old SOF = 1) or “creates” a new offset by rounding up the received offset to the next Block and adding the received length to it. @@ -662,7 +733,7 @@

    Subcomponents
    -ENTITY SOF_CREATOR IS
    +ENTITY SOF_CREATOR IS

    The SOF Creator accepts the “new” offset from the Offset Processor and rounds it up to the nearest Block. Then it evaluates it to determine whether it points to this Word and this Region, and if it does, it asserts (creates) SOF. Lastly, with the help of the rounded offset, it extracts the Length field of the header of the following individual frame in the SuperPacket.

    @@ -839,34 +910,77 @@

    Subcomponents

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Frame Packer + +
    - +
    + + MFB Splitter Simple> + +
    -
    -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/loopback/readme.html b/devel/comp/mfb_tools/flow/loopback/readme.html index f16aae14b..db0af2742 100644 --- a/devel/comp/mfb_tools/flow/loopback/readme.html +++ b/devel/comp/mfb_tools/flow/loopback/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Loopback — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Loopback — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Loopback

    +

    MFB Loopback

    -ENTITY MFB_LOOPBACK IS
    +ENTITY MFB_LOOPBACK IS

    This component provides the capability to set loopback on MFB interfaces. Both near-end and far-end type is possible. The module is controlled by the MI interface where address space is set as follows:

    @@ -477,34 +553,52 @@
    -
    +
    -
    +
    +
    +
    +
    + + + <Timestamp Limiter + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + CROSSBARX STREAM2> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/merger/readme.html b/devel/comp/mfb_tools/flow/merger/readme.html index 6bcc97461..4b7728267 100644 --- a/devel/comp/mfb_tools/flow/merger/readme.html +++ b/devel/comp/mfb_tools/flow/merger/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Merger — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Merger — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Merger

    +

    MFB Merger

    -ENTITY MFB_MERGER IS
    +ENTITY MFB_MERGER IS

    Merges two input MVB+MFB interfaces in one output interface Contains input FIFOs and output PIPEs.

    Generics

    Tab. 1Tab. 1
    @@ -524,34 +600,52 @@ - +
    - +
    + + MFB Splitter> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/merger_simple/readme.html b/devel/comp/mfb_tools/flow/merger_simple/readme.html index 87242d7eb..8fafa5e91 100644 --- a/devel/comp/mfb_tools/flow/merger_simple/readme.html +++ b/devel/comp/mfb_tools/flow/merger_simple/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Merger Simple — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Merger Simple — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Merger Simple

    +

    MFB Merger Simple

    -ENTITY MFB_MERGER_SIMPLE IS
    +ENTITY MFB_MERGER_SIMPLE IS

    This component merges two MFB streams into a single one. It starts merging from Input 0. After CNT_MAX clock cycles, @@ -368,10 +444,10 @@

    -

    MFB Merger Simple GEN

    +

    MFB Merger Simple GEN

    -ENTITY MFB_MERGER_SIMPLE_GEN IS
    +ENTITY MFB_MERGER_SIMPLE_GEN IS

    This is a generic implementation of the MFB Merger when the number of input interfaces can be set to arbitrary large number.

    Generics
    @@ -546,34 +622,73 @@

    MFB Merger Simple GEN - +
    + + MFB Cutter Simple> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/metadata_insertor/readme.html b/devel/comp/mfb_tools/flow/metadata_insertor/readme.html index 00a36b130..bdbc1e152 100644 --- a/devel/comp/mfb_tools/flow/metadata_insertor/readme.html +++ b/devel/comp/mfb_tools/flow/metadata_insertor/readme.html @@ -1,52 +1,136 @@ - - - - - - - Metadata Insertor — NDK-FPGA Docs documentation - - + + + + - - - - - - + Metadata Insertor — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Metadata Insertor

    +

    Metadata Insertor

    -ENTITY METADATA_INSERTOR IS
    +ENTITY METADATA_INSERTOR IS

    Takes items from input MVB stream and inserts them to MFB stream as metadata without affecting the MFB flow in any other way.

    Generics

    @@ -402,34 +478,52 @@ - +
    - +
    + + MFB Trasformer> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/packet_delayer/readme.html b/devel/comp/mfb_tools/flow/packet_delayer/readme.html index 36124fd9d..008eb0064 100644 --- a/devel/comp/mfb_tools/flow/packet_delayer/readme.html +++ b/devel/comp/mfb_tools/flow/packet_delayer/readme.html @@ -1,52 +1,136 @@ - - - - - - - Packet Delayer — NDK-FPGA Docs documentation - - + + + + - - - - - - + Packet Delayer — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Packet Delayer

    +

    Packet Delayer

    -ENTITY MFB_PACKET_DELAYER IS
    +ENTITY MFB_PACKET_DELAYER IS

    Incoming packets with Timestamps [ns] are stored in the RX FIFO. From there each packet is read when the Stored time value reaches the packet’s Timestamp value. There are 2 Timestamp formats that are currently supported (see the TS_FORMAT generic). @@ -373,41 +446,82 @@

    -

    Block diagram

    +

    Block diagram

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Rate Limiter + +
    - +
    + + Timestamp Limiter> + +
    -
    -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/pipe/readme.html b/devel/comp/mfb_tools/flow/pipe/readme.html index e469af992..20b1fff34 100644 --- a/devel/comp/mfb_tools/flow/pipe/readme.html +++ b/devel/comp/mfb_tools/flow/pipe/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB PIPE — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB PIPE — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB PIPE

    +

    MFB PIPE

    -ENTITY MFB_PIPE IS
    +ENTITY MFB_PIPE IS

    Component for pipelining MFB data paths with source and destination ready signals. Compatible with Xilinx and Intel FPGAs.

    Generics
    @@ -340,34 +416,52 @@ - +
    - +
    + + MFB Merger> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/rate_limiter/readme.html b/devel/comp/mfb_tools/flow/rate_limiter/readme.html index ab7b3d803..074e741d8 100644 --- a/devel/comp/mfb_tools/flow/rate_limiter/readme.html +++ b/devel/comp/mfb_tools/flow/rate_limiter/readme.html @@ -1,52 +1,136 @@ - - - - - - - Rate Limiter — NDK-FPGA Docs documentation - - + + + + - - - - - - + Rate Limiter — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Rate Limiter

    +

    Rate Limiter

    The Rate limiter modifies the output speed according to the given configuration. The user can set the speed to anything, from a constant rate to complex patterns, as needed for the specific application.

    -

    Operation

    +

    Operation

    The component forwards the incoming data unchanged. Based on the values loaded to the configuration registers, it either lets the traffic flow through at full speed or slows the traffic down when the limit of the configured rate is reached. The user configures the output speed per each Interval (see the picture below). @@ -172,7 +242,7 @@

    OperationUsage section).

    +Unfortunately, this approach is not ideal, and some configuration restrictions must be met for the component to function correctly (see the Usage section).

    ../../../../_images/timespace.svg @@ -190,7 +260,7 @@

    Operation
    -ENTITY RATE_LIMITER IS
    +ENTITY RATE_LIMITER IS
    Generics

    @@ -414,7 +484,7 @@

    Operation -

    Address space and configuration

    +

    Address space and configuration

    The component has several registers accessible through the MI interface that are used for its configuration.

    Generic
    @@ -482,7 +552,7 @@

    Address space and configuration -

    Usage

    +

    Usage

    Intro

    The status register is also used as a control register. By setting its bits (flags), the user can change the working modes of the Rate Limiter and its settings. @@ -573,7 +643,7 @@

    Address space and configuration -

    Notes

    +

    Notes

    @@ -360,7 +429,7 @@

    Architecture
    -ENTITY MFB_BLOCK_RECONFIGURATOR IS
    +ENTITY MFB_BLOCK_RECONFIGURATOR IS
    Generics

    Generic

    @@ -578,7 +647,7 @@

    Architecture
    -ENTITY MFB_REGION_RECONFIGURATOR IS
    +ENTITY MFB_REGION_RECONFIGURATOR IS
    Generics

    Generic

    @@ -813,7 +882,7 @@

    Architecture -

    Constraints and side-effects

    +

    Constraints and side-effects

    The MFB Reconfigurator has a few constraints and side-effects concerning secondary MFB bus characteristics.

    First there are side-effects caused by the very nature of the MFB bus:

    If you are increasing the value ITEM_WIDTH, you are reducing the resolution of the EOF_POS value. @@ -821,7 +890,7 @@

    Constraints and side-effectsEOF_POS up, which will lead to invalid data appearing at the end of each previously unaligned frame. (e.g.: If there is a frame with the size of 1 MFB Item and we are doubling the ITEM_WIDTH, then the output frame will also have the size of 1 MFB Item, but it will be a larger MFB Item and only the beginig will contain valid data.)

    -

    Data shifting

    +

    Data shifting

    Some reconfigurations will require shifting of frame data within the data word. Data shifting is the most resource-consuming action of the MFB Reconfigurator. It also raises the component latency and, in case of a complicated MFB configuration, may lead to timing problems. @@ -843,34 +912,79 @@

    Data shifting - +
    + + Frame Packer> + +
    - -

    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/splitter/readme.html b/devel/comp/mfb_tools/flow/splitter/readme.html index 9e7914f86..fb35ea087 100644 --- a/devel/comp/mfb_tools/flow/splitter/readme.html +++ b/devel/comp/mfb_tools/flow/splitter/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Splitter — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Splitter — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Splitter

    +

    MFB Splitter

    -ENTITY MFB_SPLITTER IS
    +ENTITY MFB_SPLITTER IS

    Splits RX MFB+MVB interface to two intefaces. Switches packets based on one bit SWITCH for each MVB header.

    Generics

    Generic
    @@ -476,10 +552,10 @@
    -

    MFB Splitter Gen

    +

    MFB Splitter Gen

    -ENTITY MFB_SPLITTER_GEN IS
    +ENTITY MFB_SPLITTER_GEN IS

    MFB+MVB bus splitter with generic number of outputs

    Generics
    @@ -724,34 +800,73 @@

    MFB Splitter Gen - +
    + + MFB Enabler> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/splitter_simple/readme.html b/devel/comp/mfb_tools/flow/splitter_simple/readme.html index 47ba9c85d..6f44b5187 100644 --- a/devel/comp/mfb_tools/flow/splitter_simple/readme.html +++ b/devel/comp/mfb_tools/flow/splitter_simple/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Splitter Simple — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Splitter Simple — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Splitter Simple

    +

    MFB Splitter Simple

    -ENTITY MFB_SPLITTER_SIMPLE IS
    +ENTITY MFB_SPLITTER_SIMPLE IS

    This component transmits received packets on one interface to one out of the two outputs according to the select bit.

    Generics

    @@ -353,10 +429,10 @@
    -

    MFB Splitter Simple Gen

    +

    MFB Splitter Simple Gen

    -ENTITY MFB_SPLITTER_SIMPLE_GEN IS
    +ENTITY MFB_SPLITTER_SIMPLE_GEN IS

    This is a 1:N MFB splitter. It consists of numerous 1:2 MFB splitters in log2(SPLITTER_OUTPUTS) stages.

    Generics
    @@ -532,34 +608,73 @@

    MFB Splitter Simple Gen - +
    + + MFB Merger Simple> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/timestamp_limiter/readme.html b/devel/comp/mfb_tools/flow/timestamp_limiter/readme.html index 666d5d42a..ba50a14a4 100644 --- a/devel/comp/mfb_tools/flow/timestamp_limiter/readme.html +++ b/devel/comp/mfb_tools/flow/timestamp_limiter/readme.html @@ -1,52 +1,136 @@ - - - - - - - Timestamp Limiter — NDK-FPGA Docs documentation - - + + + + - - - - - - + Timestamp Limiter — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Timestamp Limiter

    +

    Timestamp Limiter

    -ENTITY MFB_TIMESTAMP_LIMITER IS
    +ENTITY MFB_TIMESTAMP_LIMITER IS

    This component limits output speed according to given Timestamps via the RX_MFB_TIMESTAMP port. There are 2 Timestamp formats that are currently supported (see the TIMESTAMP_FORMAT generic). The incoming packets are split into queues (e.g., per each DMA Channel), where the order of packets is kept the same. @@ -489,41 +562,82 @@

    -

    Block diagram

    +

    Block diagram

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Packet Delayer + +
    - +
    + + MFB Loopback> + +
    -
    -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/flow/transformer/readme.html b/devel/comp/mfb_tools/flow/transformer/readme.html index c0be4325a..348b43ced 100644 --- a/devel/comp/mfb_tools/flow/transformer/readme.html +++ b/devel/comp/mfb_tools/flow/transformer/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Trasformer — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Trasformer — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Trasformer

    +

    MFB Trasformer

    -ENTITY MFB_TRANSFORMER IS
    +ENTITY MFB_TRANSFORMER IS

    This component performs changing MFB word size by increasing or decreasing the number of Regions on RX to TX.

    There are two possible solutions:
      @@ -326,34 +402,52 @@
    -
    +
    -
    +
    +
    +
    +
    + + + <Metadata Insertor + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MFB PIPE> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/logic/auxiliary_signals/readme.html b/devel/comp/mfb_tools/logic/auxiliary_signals/readme.html index 9398be890..f222f5d91 100644 --- a/devel/comp/mfb_tools/logic/auxiliary_signals/readme.html +++ b/devel/comp/mfb_tools/logic/auxiliary_signals/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Auxiliary Signals — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Auxiliary Signals — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Auxiliary Signals

    +

    MFB Auxiliary Signals

    -ENTITY MFB_AUXILIARY_SIGNALS IS
    +ENTITY MFB_AUXILIARY_SIGNALS IS
    Generics

    @@ -358,34 +434,52 @@ - +
    - +
    + + MFB Packet Discard ASFIFO> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/logic/checksum_calculator/readme.html b/devel/comp/mfb_tools/logic/checksum_calculator/readme.html index 3b2276269..2e8f4ee6b 100644 --- a/devel/comp/mfb_tools/logic/checksum_calculator/readme.html +++ b/devel/comp/mfb_tools/logic/checksum_calculator/readme.html @@ -1,52 +1,136 @@ - - - - - - - Checksum Calculator — NDK-FPGA Docs documentation - - + + + + - - - - - - + Checksum Calculator — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Checksum Calculator

    +

    Checksum Calculator

    -ENTITY CHECKSUM_CALCULATOR IS
    +ENTITY CHECKSUM_CALCULATOR IS

    This component calculates checksum from the Section of each frame specified by the Offset and Length. The IPv4(=TCP=UDP) checksum algorithm is used. The calculation can be “disabled” per each frame by setting the RX_CHSUM_EN to 0. @@ -347,34 +423,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <CrossbarX Stream + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MFB Auxiliary Signals> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/logic/crossbarx_stream/readme.html b/devel/comp/mfb_tools/logic/crossbarx_stream/readme.html index 551959bc6..08fb214bc 100644 --- a/devel/comp/mfb_tools/logic/crossbarx_stream/readme.html +++ b/devel/comp/mfb_tools/logic/crossbarx_stream/readme.html @@ -1,52 +1,136 @@ - - - - - - - CrossbarX Stream — NDK-FPGA Docs documentation - - + + + + - - - - - - + CrossbarX Stream — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    CrossbarX Stream

    +

    CrossbarX Stream

    -ENTITY CROSSBARX_STREAM IS
    +ENTITY CROSSBARX_STREAM IS

    This unit can:

    • discard packets,

      • @@ -442,12 +514,12 @@
    -

    Block diagram

    +

    Block diagram

    -

    Operations

    +

    Operations

    1. Discarding : discards come with EOFs. Therefore, they are first transferred from the RX Buffer through the CX Stream to the TX Buffer, where they are overwritten by the next transaction.

    2. Gap insertion : the Packet Planner component (PP) takes care of this.

      3. @@ -464,34 +536,76 @@

      Operations

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MFB FRAME EXTENDER + +
    - +
    + + Checksum Calculator> + +
    -
    -
    -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/readme.html b/devel/comp/mfb_tools/readme.html index 6981f5cd7..1916d622e 100644 --- a/devel/comp/mfb_tools/readme.html +++ b/devel/comp/mfb_tools/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB specification — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB specification — NDK-FPGA documentation + + + + + + - - - + + + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB specification

    +

    MFB specification

    The Multi-Frame Bus (MFB) has been created on the basis of need to process multiple small frames in one clock cycle as well as frames of virtually any length. MFB features great versatility and is being used in the majority of our internal communication channels.

    -

    Operation

    +

    Operation

    Transmitted data are organized into units called words. Each word is divided into regions where each region contains a specified number of blocks which are then composed of single items. Items are the smallest part of the word @@ -188,14 +213,14 @@

    Operation../../_images/mfb_maxframes.svg
    -

    Four whole frames aligned in a single word

    +

    Four whole frames aligned in a single word

    ../../_images/mfb_abs_maxframes.svg
    -

    Five frames aligned in a single word, not all are complete though

    +

    Five frames aligned in a single word, not all are complete though

    Figure “Five frames aligned in a single word, not all are complete though” shows that the total amount of frames being @@ -205,7 +230,7 @@

    Operation -

    Generic parameters

    +

    Generic parameters

    Generic
    @@ -267,7 +292,7 @@

    Generic parameters -

    Port description

    +

    Port description

    Name
    @@ -361,7 +386,7 @@

    Port description
    -

    Example of function of the SOF_POS index

    +

    Example of function of the SOF_POS index

    Index length can be calculated from the given configuration as SOF_POS_WIDTH = 4 * log2( 8 ) = 4 * 3, that is a three-bit index of a block in a region which is finally multiplied by the amount of regions. Those are 12 bits in total to @@ -376,7 +401,7 @@

    Example of function of the SOF_POS index -

    Example of function of the EOF_POS index

    +

    Example of function of the EOF_POS index

    According to the configuration parameters given earlier, the EOF_POS_WIDTH can be calculated as 4 * log2( 8 * 8 ) = 4 * 6, i.e. six-bit index for addressing an item in a region multiplied by the amount of regions. Altogether, that is 24 bits @@ -408,7 +433,7 @@

    Example of function of the EOF_POS index -

    Timing diagrams

    +

    Timing diagrams

    For the sake of simplicity, the function in the following diagrams will be demonstrated using bus configuration MFB#(4,4,2,8). The first figure describes the indexation of each part of the word.

    @@ -423,20 +448,20 @@

    Timing diagrams../../_images/MFB_numbering.svg
    -

    Indexation of specific parts of the word.

    +

    Indexation of specific parts of the word.

    ../../_images/MFB_transaction.svg
    -

    Example of five consecutive MFB transactions.

    +

    Example of five consecutive MFB transactions.

    Next, two scenarios will be provided showing how these transactions can be transferred.

    -

    Scenario 1

    +

    Scenario 1

    ../../_images/mfb_waveform_scenario_1.svg @@ -445,7 +470,7 @@

    Scenario 1 -

    Scenario 2

    +

    Scenario 2

    ../../_images/mfb_waveform_scenario_2.svg @@ -457,7 +482,7 @@

    Scenario 2 -

    Example configurations

    +

    Example configurations

    Here are examples of some MFB configurations being used.

    1. 400G NDK -> MFB#(4,8,8,8)

      2. @@ -483,34 +508,87 @@

      Example configurations - +
      -       +
      + + ReflexCES XpressSX AGI-FH400G> + +
      - -

    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/storage/asfifox/readme.html b/devel/comp/mfb_tools/storage/asfifox/readme.html index 585f5a6d2..a681ba153 100644 --- a/devel/comp/mfb_tools/storage/asfifox/readme.html +++ b/devel/comp/mfb_tools/storage/asfifox/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB ASFIFOX — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB ASFIFOX — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB ASFIFOX

    +

    MFB ASFIFOX

    -ENTITY MFB_ASFIFOX IS
    +ENTITY MFB_ASFIFOX IS

    This component provides the transition between the clock domains of the two MFB interfaces through the ASFIFOX component. For more information about ASFIFOX see the documentation

    Generics

    Port name

    @@ -387,34 +463,52 @@ - +
    - +
    + + MFB FIFOX> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/storage/crossbarx_output_buffer/readme.html b/devel/comp/mfb_tools/storage/crossbarx_output_buffer/readme.html index 572d189cd..b9e530c86 100644 --- a/devel/comp/mfb_tools/storage/crossbarx_output_buffer/readme.html +++ b/devel/comp/mfb_tools/storage/crossbarx_output_buffer/readme.html @@ -1,52 +1,136 @@ - - - - - - - Crossbarx Output Buffer — NDK-FPGA Docs documentation - - + + + + - - - - - - + Crossbarx Output Buffer — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Crossbarx Output Buffer

    +

    Crossbarx Output Buffer

    -ENTITY MFB_CROSSBARX_OUTPUT_BUFFER IS
    +ENTITY MFB_CROSSBARX_OUTPUT_BUFFER IS

    This component receives data through a buffer write interface. It also receives informations about Packets contained in that data and based on these informations automaticly sends the written data to output @@ -537,34 +613,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MFB FIFOX + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + Gen Loop Switch (GLS)> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/storage/fifox/readme.html b/devel/comp/mfb_tools/storage/fifox/readme.html index cd8e0bc5c..53b8eda48 100644 --- a/devel/comp/mfb_tools/storage/fifox/readme.html +++ b/devel/comp/mfb_tools/storage/fifox/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB FIFOX — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB FIFOX — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB FIFOX

    +

    MFB FIFOX

    -ENTITY MFB_FIFOX IS
    +ENTITY MFB_FIFOX IS

    This component implements the FIFO memory for the MFB interface using the FIFOX component. For more information about the FIFOX component, see the documentation

    Generics
    @@ -386,34 +462,52 @@ - +
    - +
    + + Crossbarx Output Buffer> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/storage/pd_asfifo/readme.html b/devel/comp/mfb_tools/storage/pd_asfifo/readme.html index 643811400..73b22bb05 100644 --- a/devel/comp/mfb_tools/storage/pd_asfifo/readme.html +++ b/devel/comp/mfb_tools/storage/pd_asfifo/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - MFB Packet Discard ASFIFO — NDK-FPGA Docs documentation - - - - - - - - - + MFB Packet Discard ASFIFO — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    MFB Packet Discard ASFIFO

    +

    MFB Packet Discard ASFIFO

    The Packet Discard ASFIFO is an asynchronous FIFO with the ability to erase (discard) MFB frames (packets). For each packet put inside, the user specifies if the packet is to be discarded (information valid with EOF). If so, the packet will not appear on the ASFIFO output. Because the information about discarding is only available with the EOF, the unit works in store-and-forward mode (each packet has to be stored completely before we can decide whether to propagate it further).

    -

    Architecture

    +

    Architecture

    The internal architecture of the unit consists of multipe stages.

    @@ -178,9 +247,9 @@

    Architecture -

    Additional Features

    +

    Additional Features

    -

    Force Discard

    +

    Force Discard

    The Force Discard feature can be used to immidiately start discarding packets. When Force Discard is active, the currently processed packet is discarded as well as all following packets as long as the signal is active. Once the signal falls to 0, the next valid word must start with a SOF. @@ -192,34 +261,79 @@

    Force Discard

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MFB Auxiliary Signals + +
    - +
    + + MFB PD ASFIFO SIMPLE> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mfb_tools/storage/pd_asfifo_simple/readme.html b/devel/comp/mfb_tools/storage/pd_asfifo_simple/readme.html index 88b9c07e9..23dd9fd5d 100644 --- a/devel/comp/mfb_tools/storage/pd_asfifo_simple/readme.html +++ b/devel/comp/mfb_tools/storage/pd_asfifo_simple/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB PD ASFIFO SIMPLE — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB PD ASFIFO SIMPLE — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB PD ASFIFO SIMPLE

    +

    MFB PD ASFIFO SIMPLE

    -ENTITY MFB_PD_ASFIFO_SIMPLE IS
    +ENTITY MFB_PD_ASFIFO_SIMPLE IS
    Generics
    @@ -354,34 +430,52 @@ - +
    - +
    + + MFB ASFIFOX> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/async/readme.html b/devel/comp/mi_tools/async/readme.html index c07444a5e..fb9f889ff 100644 --- a/devel/comp/mi_tools/async/readme.html +++ b/devel/comp/mi_tools/async/readme.html @@ -1,52 +1,136 @@ - - - - - - - MI ASYNC — NDK-FPGA Docs documentation - - + + + + - - - - - - + MI ASYNC — NDK-FPGA documentation + + + + + + - - + + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MI ASYNC

    +

    MI ASYNC

    -ENTITY MI_ASYNC IS
    +ENTITY MI_ASYNC IS

    The MI_ASYNC implements the MI bus transition between two clock domains. Asynchronous FIFO memory is used to implement the cross-domain crossing. The MI_ASYNC component also contains logic that can ensure the correct @@ -298,34 +374,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MI Tools + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MI Pipe> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/converters/mi2avmm/readme.html b/devel/comp/mi_tools/converters/mi2avmm/readme.html index e84b522d4..84094f8aa 100644 --- a/devel/comp/mi_tools/converters/mi2avmm/readme.html +++ b/devel/comp/mi_tools/converters/mi2avmm/readme.html @@ -1,52 +1,136 @@ - - - - - - - MI2AVMM — NDK-FPGA Docs documentation - - + + + + - - - - - - + MI2AVMM — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MI2AVMM

    +

    MI2AVMM

    -ENTITY MI2AVMM IS
    +ENTITY MI2AVMM IS

    This component converts MI interface to Avalon Memory-Mapped (Avalon-MM) interface. In the current implementation these are just directly connected wires and one not gate.

    Generics

    Generic
    @@ -270,7 +343,7 @@

    Read MI bus specification for more information on the MI bus.

    -

    Specification

    +

    Specification

    Both interfaces use common clock and reset signals. AVMM interface does not support debugaccess, optional signals (response, writeresponsevalid), lock for multiple hosts and burst mode signals (burstcount, beginbursttransfer). Pipelined read transfers are possible with readdatavalid signal. @@ -290,34 +363,75 @@

    Specification - +
    + + MI2AXI4> + +
    - -

    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/converters/mi2axi4/readme.html b/devel/comp/mi_tools/converters/mi2axi4/readme.html index 5b5043633..44faf7e8b 100644 --- a/devel/comp/mi_tools/converters/mi2axi4/readme.html +++ b/devel/comp/mi_tools/converters/mi2axi4/readme.html @@ -1,52 +1,136 @@ - - - - - - - MI2AXI4 — NDK-FPGA Docs documentation - - + + + + - - - - - - + MI2AXI4 — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MI2AXI4

    +

    MI2AXI4

    -ENTITY MI2AXI4 IS
    +ENTITY MI2AXI4 IS

    This component converts MI interface (slave) to AXI4 interface (master).

    Generics
    @@ -392,34 +468,52 @@ - +
    - +
    + + MFB Tools> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/indirect_access/readme.html b/devel/comp/mi_tools/indirect_access/readme.html index d92810e43..1d46fff96 100644 --- a/devel/comp/mi_tools/indirect_access/readme.html +++ b/devel/comp/mi_tools/indirect_access/readme.html @@ -1,52 +1,136 @@ - - - - - - - MI indirect access — NDK-FPGA Docs documentation - - + + + + - - - - - - + MI indirect access — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MI indirect access

    +

    MI indirect access

    Through this component it is possible to send MI transactions indirectly to one or more output interfaces. That means you have to set the parameters of the MI transaction (by sending Write requests) to a set of registers, which are also accessed by MI.

    -ENTITY MI_INDIRECT_ACCESS IS
    +ENTITY MI_INDIRECT_ACCESS IS
    Generics
    @@ -273,7 +345,7 @@ MI indirect access block scheme
    -

    Usage

    +

    Usage

    Set the ID of the desired output interface, Address , Data to be written (in case it’s a Write reqest), and the Command of the indirect request. Set LSB of the Command register (cmd(0)) to ‘1’ to send indirect Write request or set cmd(1) to ‘1’ to send indirect Read request.

    @@ -282,9 +354,9 @@

    Usage

    -

    Address space

    +

    Address space

    Generic
    - +@@ -319,34 +391,76 @@

    Address space - +
    + + MI Reconfigurator> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/pipe/readme.html b/devel/comp/mi_tools/pipe/readme.html index e67633aa5..1e0b810d6 100644 --- a/devel/comp/mi_tools/pipe/readme.html +++ b/devel/comp/mi_tools/pipe/readme.html @@ -1,52 +1,136 @@ - - - - - - - MI Pipe — NDK-FPGA Docs documentation - - + + + + - - - - - - + MI Pipe — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MI Pipe

    +

    MI Pipe

    -ENTITY MI_PIPE IS
    +ENTITY MI_PIPE IS

    Wrapper over generic Pipe (comp/base/misc/pipe) for MI interface.

    Generics

    Tab. 1Tab. 1
    @@ -311,34 +387,52 @@ - +
    - +
    + + MI indirect access> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/readme.html b/devel/comp/mi_tools/readme.html index 31f340e25..a287657fd 100644 --- a/devel/comp/mi_tools/readme.html +++ b/devel/comp/mi_tools/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - MI bus specification — NDK-FPGA Docs documentation - - - - - - - - - + MI bus specification — NDK-FPGA documentation + + + + + + - - - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    MI bus specification

    +

    MI bus specification

    MI (Memory Interface) bus realizes software access to firmware components. These components (usually some control, state or statistics registers) can be either configured by write requests, or their current data can be determined by read requests. These components are accessed by their addresses that are sent along with the requests. The default width used in this project is 32 bits for both, data and addresses. That is why the name MI32 is often used for this bus.

    -

    MI bus description

    +

    MI bus description

    MI bus has these 8 ports + 1 port optional divided into two channels (the port directions in example are valid for slave MI components):

    -- ===========================================================================
 -- Ports of MI bus request channel (master to slave):
@@ -158,7 +221,7 @@ 
    MI bus descriptionBE is there to define which bytes of the transferred data (DWR or DRD) are valid and should be worked with and which bytes should be ignored. Each bit validates one byte of the data, that is why it is DATA_WIDTH/8 bits wide. Usually, it is used in write transactions, but it may also be used in read transactions.
    -

    A few timing diagrams

    +

    A few timing diagrams

    to make sure you really understand, how the MI bus works. The optional MWR signal is not used in these examples.

    A) Simple write transaction & the ARDY occurrences

    A simple write transaction and ARDY @@ -189,34 +252,76 @@

    A few timing diagrams -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <LOGIC VECTOR ARRAY LBUS Environment + +
    - +
    + + MVB Specification> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/reconf/readme.html b/devel/comp/mi_tools/reconf/readme.html index 249c98ea0..1069d9b59 100644 --- a/devel/comp/mi_tools/reconf/readme.html +++ b/devel/comp/mi_tools/reconf/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - MI Reconfigurator — NDK-FPGA Docs documentation - - - - - - - - - + MI Reconfigurator — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    MI Reconfigurator

    +

    MI Reconfigurator

    The MI Reconfigurator can be used to modify the width of the MI interface. Both RX and TX data width has to be a power of 2 and at least 8 bits.

    -

    Architecture

    +

    Architecture

    The architecture has 3 different shapes depending on the configuration:

    1. RX width == TX width

      @@ -176,34 +249,75 @@

      Architecture

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MI indirect access + +
    - +
    + + MI Splitter Plus Gen> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mi_tools/splitter_plus_gen/readme.html b/devel/comp/mi_tools/splitter_plus_gen/readme.html index 76c42a7a6..99eb4c9fe 100644 --- a/devel/comp/mi_tools/splitter_plus_gen/readme.html +++ b/devel/comp/mi_tools/splitter_plus_gen/readme.html @@ -1,52 +1,136 @@ - - - - - - - MI Splitter Plus Gen — NDK-FPGA Docs documentation - - + + + + - - - - - - + MI Splitter Plus Gen — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MI Splitter Plus Gen

    +

    MI Splitter Plus Gen

    -ENTITY MI_SPLITTER_PLUS_GEN IS
    +ENTITY MI_SPLITTER_PLUS_GEN IS

    This is another splitter for the MI bus. MI transactions are routed out of a certain port, depending on how the splitter is set and on the transaction’s address.

    @@ -352,7 +419,7 @@
    -

    Architecture

    +

    Architecture

    The splitter accepts standard MI transactions at its input. Output ports have a range(s) of addresses assigned and transactions addressed to this range are sent out of the according port. As was said before, the address ranges are defined by ABs. @@ -366,7 +433,7 @@

    Architecture -

    Examples of use

    +

    Examples of use

    The next 3 examples explain how to:

    • set up ABs,

      • @@ -374,13 +441,13 @@

      Examples of use -

      Example 1 - setting up ADDR_BASE

      +

      Example 1 - setting up ADDR_BASE

      Perhaps we want to use the MI splitter with 7 outputs (as is in the figure above). We want transactions with addresses in range from 0x0 up to 0x3 to be routed out of port 0, addresses in range from 0x4 up to 0x7 to be routed out of port 1 an so on, just like the first 2 columns of table 1 show. Then we should set ABs like in the 3rd column of this table. Side note: generally, the ranges don’t have to be the same, but let’s keep it simple for now.

    - +@@ -430,7 +497,7 @@

    Example 1 - setting up ADDR_BASE -

    Example 2 - masking irrelevant bits of the address

    +

    Example 2 - masking irrelevant bits of the address

    In this case, we want to choose the output port according to only a part of MI transaction’s address. If we want the port with highest associated AB to act as a default port (one that will carry all transactions that don’t fall into any other range), we have to set ADDR_MASK to (others => ‘1’), because we want to use all bits of the address. If we leave the mask in default state, all ABs are ORed together and interleaving ‘0’s are replaced by ‘1’s. @@ -445,7 +512,7 @@

    Example 2 - masking irrelevant bits of the address

    Tab. 1Tab. 1
    - +@@ -507,7 +574,7 @@

    Example 2 - masking irrelevant bits of the address1 11111100.

    -

    Example 3 - mapping ports to differnt ABs

    +

    Example 3 - mapping ports to differnt ABs

    In this advanced example, we would like to assign more ABs (i.e. more address ranges) to a single port. For that we’re gonna need to use PORT_MAPPING. Let’s take the first example we had. @@ -539,7 +606,7 @@

    Example 3 - mapping ports to differnt ABs -

    +@@ -578,34 +645,81 @@

    Example 3 - mapping ports to differnt ABs - +
    + + MI2AVMM> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/channel_router/readme.html b/devel/comp/mvb_tools/flow/channel_router/readme.html index c58fea73e..30802dbd6 100644 --- a/devel/comp/mvb_tools/flow/channel_router/readme.html +++ b/devel/comp/mvb_tools/flow/channel_router/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Channel Router — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Channel Router — NDK-FPGA documentation + + + + + + - - + + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Channel Router

    +

    MVB Channel Router

    -ENTITY MVB_CHANNEL_ROUTER_MI IS
    +ENTITY MVB_CHANNEL_ROUTER_MI IS

    This component works as a simple configurable routing table. It is primarily used for basic routing of Ethernet frames to selected DMA channels. You can use generics to set three modes of default behavior (see DEFAULT_MODE generic). @@ -380,34 +456,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Components + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB DISCARD> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/demux/readme.html b/devel/comp/mvb_tools/flow/demux/readme.html index ca7efd6f5..50fb997df 100644 --- a/devel/comp/mvb_tools/flow/demux/readme.html +++ b/devel/comp/mvb_tools/flow/demux/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB DEMUX — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB DEMUX — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB DEMUX

    +

    MVB DEMUX

    Multi-value bus item demultiplexer. For each item, there is a select signal, which determines to which TX port the item will be transmitted.

    Transaction on RX MVB is executed, when all ports, to which at least one item will be transmitted, have DST_RDY asserted. Ports, which will not receive any item, do not have to have DST_RDY asserted.

    -ENTITY GEN_MVB_DEMUX IS
    +ENTITY GEN_MVB_DEMUX IS

    Multi-value bus item demultiplexer. For each item, there is a select signal, which determines to which TX port the item will be transmitted. Transaction on RX MVB is executed, when all ports, to which at least one item will be transmitted, @@ -263,34 +339,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Merge Streams + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB MUX> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/discard/readme.html b/devel/comp/mvb_tools/flow/discard/readme.html index 8eacafc22..1c8599982 100644 --- a/devel/comp/mvb_tools/flow/discard/readme.html +++ b/devel/comp/mvb_tools/flow/discard/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB DISCARD — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB DISCARD — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB DISCARD

    +

    MVB DISCARD

    -ENTITY MVB_DISCARD IS
    +ENTITY MVB_DISCARD IS

    The MVB_DISCARD component allows to discard selected items. The item marked with the discard flag will be discarded (masked) in the internal logic. There is a built-in optional output register.

    @@ -232,34 +308,52 @@
    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Channel Router + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB Item Collision Resolver> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/item_collision_resolver/readme.html b/devel/comp/mvb_tools/flow/item_collision_resolver/readme.html index 39f10d102..cd1391636 100644 --- a/devel/comp/mvb_tools/flow/item_collision_resolver/readme.html +++ b/devel/comp/mvb_tools/flow/item_collision_resolver/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Item Collision Resolver — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Item Collision Resolver — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Item Collision Resolver

    +

    MVB Item Collision Resolver

    -ENTITY MVB_ITEM_COLLISION_RESOLVER IS
    +ENTITY MVB_ITEM_COLLISION_RESOLVER IS

    The component MVB_ITEM_COLLISION_RESOLVER ensures that only Items with different data are valid at the output in each clock cycle. When the data at the output are the same, they are invalidated (all but one).

    The data are stored in a FIFO and await to be read. @@ -244,34 +320,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB DISCARD + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB Merge Items> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/merge_items/readme.html b/devel/comp/mvb_tools/flow/merge_items/readme.html index 76b7570de..398ef27e8 100644 --- a/devel/comp/mvb_tools/flow/merge_items/readme.html +++ b/devel/comp/mvb_tools/flow/merge_items/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Merge Items — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Merge Items — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Merge Items

    +

    MVB Merge Items

    -ENTITY MVB_MERGE_ITEMS IS
    +ENTITY MVB_MERGE_ITEMS IS

    This MVB_MERGE_ITEMS component allows to merge two different MVB streams by merging items from both streams into one item. Both input MVB streams must receive the same number of items in the same order, but they can be aligned @@ -288,34 +364,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Item Collision Resolver + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB Merge Streams> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/merge_n_to_m/readme.html b/devel/comp/mvb_tools/flow/merge_n_to_m/readme.html index a47a6e29d..bb40baa1d 100644 --- a/devel/comp/mvb_tools/flow/merge_n_to_m/readme.html +++ b/devel/comp/mvb_tools/flow/merge_n_to_m/readme.html @@ -1,52 +1,136 @@ - - - - - - - SHAKEDOWN — NDK-FPGA Docs documentation - - + + + + - - - - - - + SHAKEDOWN — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    SHAKEDOWN

    +

    SHAKEDOWN

    -ENTITY SHAKEDOWN IS
    +ENTITY SHAKEDOWN IS

    Merges input MVB of N items to output MVB of M items. There can be at most M items valid on input MVB, otherwise, items might get lost, if you . Can be used as combinational logic with @@ -241,10 +317,10 @@

    -

    MERGE_N_TO_M

    +

    MERGE_N_TO_M

    -ENTITY MERGE_N_TO_M IS
    +ENTITY MERGE_N_TO_M IS

    OBSOLETE!!! Use at your own risk. This component is used by SHAKEDOWN. Merges N item MVB into M item MVB, on RX interface, there must be at most M items marked as valid, otherwise, they will be lost!. @@ -336,34 +412,73 @@

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MVB MUX + +
    - +
    + + MVB Shakedown> + +
    -
    -
    -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/merge_streams/readme.html b/devel/comp/mvb_tools/flow/merge_streams/readme.html index 5d1ccd855..95fd3268c 100644 --- a/devel/comp/mvb_tools/flow/merge_streams/readme.html +++ b/devel/comp/mvb_tools/flow/merge_streams/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Merge Streams — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Merge Streams — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Merge Streams

    +

    MVB Merge Streams

    -ENTITY MVB_MERGE_STREAMS IS
    +ENTITY MVB_MERGE_STREAMS IS

    The MVB_MERGE_STREAMS component is used to merge two or more independent MVB streams into one. The order of merging items is random. The speed of switching between input streams can be influenced by the width of the timeout @@ -245,34 +321,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Merge Items + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB DEMUX> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/merge_streams/uvm/readme.html b/devel/comp/mvb_tools/flow/merge_streams/uvm/readme.html index 7d2b6931f..a13c25ed1 100644 --- a/devel/comp/mvb_tools/flow/merge_streams/uvm/readme.html +++ b/devel/comp/mvb_tools/flow/merge_streams/uvm/readme.html @@ -1,50 +1,134 @@ - - - - - - - - The verification of this component will be designed and implemented as part of the bachelor’s thesis. — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + The verification of this component will be designed and implemented as part of the bachelor’s thesis. — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    -
      -
      • -
    • The verification of this component will be designed and implemented as part of the bachelor’s thesis.
      • -
    • - View page source -
      • -
    -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    The verification of this component will be designed and implemented as part of the bachelor’s thesis.

    +

    The verification of this component will be designed and implemented as part of the bachelor’s thesis.

    -
    +
    -
    - -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - -
    -
    -
    -
    - - - +
    +
    +
    +
    +
    +
    + +
    + +
    + +
    +
    +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/merge_streams_ordered/readme.html b/devel/comp/mvb_tools/flow/merge_streams_ordered/readme.html index b86f424d2..bb1749097 100644 --- a/devel/comp/mvb_tools/flow/merge_streams_ordered/readme.html +++ b/devel/comp/mvb_tools/flow/merge_streams_ordered/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Merge Streams Ordered — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Merge Streams Ordered — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Merge Streams Ordered

    +

    MVB Merge Streams Ordered

    -ENTITY MVB_MERGE_STREAMS_ORDERED IS
    +ENTITY MVB_MERGE_STREAMS_ORDERED IS

    Merges multiple MVB streams to one big streams in defined order. Order is defined by RX_SEL interface. Each word on this interface tells from which interface next word should be transmitted. @@ -279,34 +355,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Operation + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB2MFB> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/mux/readme.html b/devel/comp/mvb_tools/flow/mux/readme.html index 931a058a6..d629bb233 100644 --- a/devel/comp/mvb_tools/flow/mux/readme.html +++ b/devel/comp/mvb_tools/flow/mux/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB MUX — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB MUX — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB MUX

    +

    MVB MUX

    Multi-value bus multiplexer. Selects, which input MVB will be transmitting to output MVB.

    The selection is done base on received select transactions. For each RX transaction, there must be exactly one select transaction. If there is none, the component will wait until one is received.

    -ENTITY GEN_MVB_MUX IS
    +ENTITY GEN_MVB_MUX IS

    Multi-value bus multiplexer. Selects, which input MVB interface will be transmitting to output MVB. The selection is done base on received select transactions. For each RX transaction, there must be exactly one select transaction. If there is none, the component will wait until one is received.

    @@ -260,34 +336,52 @@
    -
    +
    -
    +
    +
    +
    +
    + + + <MVB DEMUX + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + SHAKEDOWN> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/mvb2mfb/readme.html b/devel/comp/mvb_tools/flow/mvb2mfb/readme.html index 60040aeaf..b3363531c 100644 --- a/devel/comp/mvb_tools/flow/mvb2mfb/readme.html +++ b/devel/comp/mvb_tools/flow/mvb2mfb/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB2MFB — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB2MFB — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB2MFB

    +

    MVB2MFB

    -ENTITY MVB2MFB IS
    +ENTITY MVB2MFB IS

    Component MVB2MFB converts MVB ITEMs to MFB transactions. It is possible to set different parameters for the input MVB bus and the output MFB bus. However, there are several limiting conditions, see the description of @@ -289,34 +365,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Merge Streams Ordered + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB Lookup Table> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/operation/readme.html b/devel/comp/mvb_tools/flow/operation/readme.html index 35735b155..50da1522a 100644 --- a/devel/comp/mvb_tools/flow/operation/readme.html +++ b/devel/comp/mvb_tools/flow/operation/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Operation — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Operation — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Operation

    +

    MVB Operation

    -ENTITY MVB_OPERATION IS
    +ENTITY MVB_OPERATION IS

    This component enables optional transaction forking and response receiving based on RX_OP_EN. Optionally forked data are sent to TX Operation Interface and responses are received from RX Operation Interface. @@ -379,34 +455,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB Shakedown + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB Merge Streams Ordered> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/shakedown/readme.html b/devel/comp/mvb_tools/flow/shakedown/readme.html index f64e9ef97..fc21df873 100644 --- a/devel/comp/mvb_tools/flow/shakedown/readme.html +++ b/devel/comp/mvb_tools/flow/shakedown/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Shakedown — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Shakedown — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Shakedown

    +

    MVB Shakedown

    -ENTITY MVB_SHAKEDOWN IS
    +ENTITY MVB_SHAKEDOWN IS

    Converts RX_ITEMS item input MVB to TX_ITEMS amount of single item MVB interfaces. Items can be read independetly and in order (out of order is not tested, UVM verification needed).

    Generics

    Tab. 2Tab. 2 Tab. 3Tab. 3
    @@ -256,34 +332,52 @@ - +
    - +
    + + MVB Operation> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/flow/shakedown/uvm/readme.html b/devel/comp/mvb_tools/flow/shakedown/uvm/readme.html index aabf65b58..a13c25ed1 100644 --- a/devel/comp/mvb_tools/flow/shakedown/uvm/readme.html +++ b/devel/comp/mvb_tools/flow/shakedown/uvm/readme.html @@ -1,50 +1,134 @@ - - - - - - - - The verification of this component will be designed and implemented as part of the bachelor’s thesis. — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + The verification of this component will be designed and implemented as part of the bachelor’s thesis. — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    -
      -
      • -
    • The verification of this component will be designed and implemented as part of the bachelor’s thesis.
      • -
    • - View page source -
      • -
    -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    The verification of this component will be designed and implemented as part of the bachelor’s thesis.

    +

    The verification of this component will be designed and implemented as part of the bachelor’s thesis.

    -
    +
    -
    - -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - -
    -
    -
    -
    - - - + +
    + +
    +
    +
    + +
    + +
    + +
    +
    +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/readme.html b/devel/comp/mvb_tools/readme.html index 7f5243c99..9ad2bcff9 100644 --- a/devel/comp/mvb_tools/readme.html +++ b/devel/comp/mvb_tools/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Specification — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Specification — NDK-FPGA documentation + + + + + + - - - + + + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Specification

    +

    MVB Specification

    Multi-Value Bus (MVB) has been created as a communication channel able to process multiple data in one clock cycle. This bus is often used as a separate channel to transfer fixed length meta-data for the data transmitted on the MFB bus. Therefore both of these buses are often used together as one communication channel.

    -

    Operation

    +

    Operation

    Data are transmitted in units called words which consist of the specified amount of items. The maximum amount of items, which can be transmitted in one clock cycle, is set during the creation of the bus. Not all items have to @@ -160,7 +206,7 @@

    Operation -

    Generic parameters

    +

    Generic parameters

    @@ -194,12 +240,12 @@

    Generic parameters../../_images/mvb_item_alignment.svg
    -

    Example of the item arrangement within a word

    +

    Example of the item arrangement within a word

    -

    Port description

    +

    Port description

    Name

    @@ -238,7 +284,7 @@

    Port description -

    Examples of various VLD signal values

    +

    Examples of various VLD signal values

    1. The value of VLD = 1110 means, that three valid items are transmitted in current word. Their indexes are 3, 2 and 1.

      2. @@ -254,7 +300,7 @@

      Examples of various VLD signal values -

      Timing diagrams

      +

      Timing diagrams

      Two timing diagrams will be shown in this section. These diagrams describe how a MVB transmission is performed in terms of waveforms. Example of MVB transactions are shown in the following figure:

      @@ -262,13 +308,13 @@

      Timing diagrams../../_images/mvb_transactions.svg
      -

      Examples of MVB transactions

      +

      Examples of MVB transactions

      In next sections, two scenarios will be provided showing how these transactions can be transferred.

      -

      Scenario 1

      +

      Scenario 1

      ../../_images/mvb_tim_uninterrupted.svg @@ -280,7 +326,7 @@

      Scenario 1 -

      Scenario 2

      +

      Scenario 2

      ../../_images/mvb_tim_interrupted.svg @@ -306,34 +352,85 @@

      Scenario 2 - +
      + + MFB specification> + +
      - -

      - - + + + +
      + Git branch: devel
      Git hash: ea2302fb +
      - +

      + +

      + \ No newline at end of file diff --git a/devel/comp/mvb_tools/storage/fifox/readme.html b/devel/comp/mvb_tools/storage/fifox/readme.html index 0b296c655..0cd1a2cd9 100644 --- a/devel/comp/mvb_tools/storage/fifox/readme.html +++ b/devel/comp/mvb_tools/storage/fifox/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB FIFOX — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB FIFOX — NDK-FPGA documentation + + + + + + - + + + - -
      - - -
      +
      -
      -
      -
      - -
      -
      -
      -
      - +
      +
      +
      +
      +
      -

      MVB FIFOX

      +

      MVB FIFOX

      -ENTITY MVB_FIFOX IS
      +ENTITY MVB_FIFOX IS
      Generics

    Port name
    @@ -289,7 +362,7 @@
    -

    General subcomponents

    +

    General subcomponents

    @@ -297,34 +370,75 @@

    General subcomponents - +
    -     +
    + + Network Tools> + +
    - -

    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/mvb_tools/storage/lookup_table/readme.html b/devel/comp/mvb_tools/storage/lookup_table/readme.html index 31f04a9e0..ff89b59ae 100644 --- a/devel/comp/mvb_tools/storage/lookup_table/readme.html +++ b/devel/comp/mvb_tools/storage/lookup_table/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB Lookup Table — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB Lookup Table — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB Lookup Table

    +

    MVB Lookup Table

    -ENTITY MVB_LOOKUP_TABLE IS
    +ENTITY MVB_LOOKUP_TABLE IS

    Component MVB_LOOKUP_TABLE allows to read values from the lookup table using the MVB bus. The input MVB transaction must contain the address of an entry in the lookup table. This MVB transaction will be transferred to the output @@ -311,34 +387,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <MVB2MFB + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB FIFOX> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/nic/eth_phy/40ge/readme.html b/devel/comp/nic/eth_phy/40ge/readme.html index d3aecb82c..20767a567 100644 --- a/devel/comp/nic/eth_phy/40ge/readme.html +++ b/devel/comp/nic/eth_phy/40ge/readme.html @@ -1,52 +1,136 @@ - - - - - - - 40GE Ethernet PHY for Ultrascale+ FPGAs — NDK-FPGA Docs documentation - - + + + + - - - - - - + 40GE Ethernet PHY for Ultrascale+ FPGAs — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    40GE Ethernet PHY for Ultrascale+ FPGAs

    +

    40GE Ethernet PHY for Ultrascale+ FPGAs

    The phy_40ge component implements 40G Ethernet Physical Layers (GBASE-R PCS + PMA) according to IEEE 802.3 clauses 82 and 83, intended for Xilinx Ultrascale FPGAs with GTY transceivers forming the PMA layer. Via the serial data ports RXP TXP, it can directly connect QSFP optical or CR-type transceivers. Ethernet data are passed to/from FPGA fabric via the standard MII interface. The component also includes management registers similar to 802.3 clauses 45.2.1 (PMA/PMD registers) and 42.2.3 (PCS registers) - see Address space.

    -

    Interface

    +

    Interface

    -ENTITY phy_40ge IS
    +ENTITY phy_40ge IS
    Ports

    Generic
    @@ -316,12 +382,12 @@

    InterfaceMI bus specification

    -

    Architecture

    +

    Architecture

    The main building blocks are the TX PCS tx_path_40ge, RX PCS rx_path_40ge, the PMA pma_xlaui_gty and the management mgmt

    ../../../../_images/bd.svg
    -

    TX PCS

    +

    TX PCS

    The transmit side of the PCS layer performs functions defined in 802.3 clause 82.2: data coming from the XLGMII are encoded into 66-bit blocks, scrambled, distributed on 4 lanes, and then on each lane, the alignment marker block is periodically inserted.

    The main building components are as follows:

      @@ -332,7 +398,7 @@

      TX PCS<

    -

    RX PCS

    +

    RX PCS

    The receive side of the PCS layer performs functions defined in 802.3 clause 82.2. The main building blocks are as follows:

    • Decoder gbaser_decode performs GBASE-R block decoding and conversion to XLGMII

      • @@ -343,16 +409,16 @@

      RX PCS<

    -

    PMA

    +

    PMA

    The PMA’s main task is to serialize and deserialize the data stream, provide TX, and recover RX clocks. The component’s core is the Xilinx GT IP gty_40ge, configured in 4 lane mode, with a bitrate of 10.3125 Gbps each. Each lane uses an async gearbox to simplify design logic and clocking (provided clocks match XLGMII frequency of 156.25 MHz in such configuration). Moreover, the PMA includes block lock component block_lock to perform GBASE-R boundaries search on link startup, pipeline registers on the data path to simplify FPGA place & route, and logic to perform GTY reset sequence.

    -

    Management

    +

    Management

    The management component collects PCS and PMA statistics and makes them available to software via the MI32 bus. It also provides some control registers to allow a reset of the PMA and PCS or to turn the loopback on/off. For more details, see the MI bus specification and Address space sections.

    -

    Address space

    +

    Address space

    Port

    @@ -456,34 +522,83 @@

    Management - +
    + + PCIe Tools> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/nic/mac_lite/rx_mac_lite/comp/buffer/uvm/readme.html b/devel/comp/nic/mac_lite/rx_mac_lite/comp/buffer/uvm/readme.html index 0db0f25c4..1470a8bcf 100644 --- a/devel/comp/nic/mac_lite/rx_mac_lite/comp/buffer/uvm/readme.html +++ b/devel/comp/nic/mac_lite/rx_mac_lite/comp/buffer/uvm/readme.html @@ -1,50 +1,134 @@ + + + + + - - - - - - - BUFFER — NDK-FPGA Docs documentation - - - - - - - - - + BUFFER — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    BUFFER

    +

    BUFFER

    -

    Verification Plan

    +

    Verification Plan

    Offset

    @@ -135,31 +213,65 @@

    Verification Plan - +
    + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/nic/mac_lite/rx_mac_lite/readme.html b/devel/comp/nic/mac_lite/rx_mac_lite/readme.html index 7211c493d..cd362a3d2 100644 --- a/devel/comp/nic/mac_lite/rx_mac_lite/readme.html +++ b/devel/comp/nic/mac_lite/rx_mac_lite/readme.html @@ -1,52 +1,136 @@ - - - - - - - RX MAC LITE — NDK-FPGA Docs documentation - - + + + + - - - - - - + RX MAC LITE — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    RX MAC LITE

    +

    RX MAC LITE

    This component is used to implement the Ethernet MAC layer on the receiving side. Thanks to the modular architecture (RX MAC LITE + Adapter), it can be connected to a supported ETH Hard IP block or implement the MAC layer separately. The implementation may include differences from the Ethernet standard.

    -

    Architecture

    +

    Architecture

    RX MAC LITE contains several components that analyze the received frame (CRC, MAC address, length) and check for errors. The Ethernet frame is stored in the buffer (store and forward), if it does not contain errors, it is sent to the output interface along with the metadata, otherwise the frame is discarded. Some of these components are optional. The whole module can be controlled by SW using MI registers (see chapter Register Map).

    ../../../../_images/rx_mac_lite_arch.svg @@ -146,7 +217,7 @@

    Architecture -

    Adapter

    +

    Adapter

    The adapter allows you to connect the RX MAC LITE to various variants of the PCS/PMA layer of the Ethernet or various Ethernet Hard IPs. The main task of the adapter is to convert the selected input bus to the MFB bus. Currently, several variants of the adapter are implemented:

    @@ -158,7 +229,7 @@

    Adapter

    -

    Register Map

    +

    Register Map

    It is possible to configure RX MAC LITE on the fly, but if you want to make changes atomically, you should disable RX MAC LITE first. You can set MAC check mode, RX MAC LITE error mask, minimal and maximal frame length. After you are done you can enable RX MAC LITE. @@ -733,10 +804,10 @@

    Register Map -

    Ports and Generics

    +

    Ports and Generics

    -ENTITY RX_MAC_LITE IS
    +ENTITY RX_MAC_LITE IS
    Generics

    ID

    @@ -1102,34 +1173,78 @@

    Ports and Generics - +
    + + TX MAC LITE> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/nic/mac_lite/tx_mac_lite/comp/adapters/lbus/reconf/readme.html b/devel/comp/nic/mac_lite/tx_mac_lite/comp/adapters/lbus/reconf/readme.html index 2c1ed6ebd..5942ac0a0 100644 --- a/devel/comp/nic/mac_lite/tx_mac_lite/comp/adapters/lbus/reconf/readme.html +++ b/devel/comp/nic/mac_lite/tx_mac_lite/comp/adapters/lbus/reconf/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB -> LBUS reconfigurator (TX LBUS) — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB -> LBUS reconfigurator (TX LBUS) — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB -> LBUS reconfigurator (TX LBUS)

    +

    MFB -> LBUS reconfigurator (TX LBUS)

    This component converts frames from the input with MFB#(1,8,8,8) configuration to the output with MFB#(1,4,16,8) configuration. The behavior of the output transmission abides also by the LBUS specification. This @@ -146,7 +203,7 @@ requirements.

    -ENTITY MFB_TO_LBUS_RECONF IS
    +ENTITY MFB_TO_LBUS_RECONF IS

    This entity does not have generic paramters alhough it is a MFB to MFB type interface. The generic paremeters are set from input to output in the following manner: MFB#(1,8,8,8) -> MFB#(1,4,16,8).

    @@ -244,7 +301,7 @@
    -

    Operation

    +

    Operation

    The input frame transactions meet the MFB specification while the outgoing meet the LBUS specification. The second one is similar to the first with following differences:

    @@ -265,7 +322,7 @@

    Operation -

    Controlling state machine

    +

    Controlling state machine

    The internal design consists of two BARREL_SHIFTER_GEN components which are controlled by the sh_fsm state machine. The simplified transition diagram looks like the following:

    @@ -275,7 +332,7 @@

    Controlling state machine -

    IDLE

    +

    IDLE

    The state machine is reset into the IDLE state. The FSM waits for a frame to come and sets the proper shift on the output according to the frames RX_SOF_POS value. Two consecutive words are buffered on the input every time and @@ -286,7 +343,7 @@

    IDLE< situation occurs.

    -

    PKT_PROCESS

    +

    PKT_PROCESS

    The PKT_PROCESS state processes the frame after receiving a SOF. The shifting does not change in this state. Sometimes, when there is an EOF in the first register, the shifting can be set to a @@ -295,13 +352,13 @@

    PKT_PROCESS -

    PKT_END

    +

    PKT_END

    The PKT_END state is entered when there is an RX_EOF of a currently processed frame. The output MFB signals are set and the TX_EOF_POS is set according to the value by which the frame has been shifted.

    -

    WORD_REALIGN

    +

    WORD_REALIGN

    The WORD_REALIGN state takes care of the situation when two frames occur in a single word (one frame ends and another begins). The shift of the ending frame remains unchanged. On the output, the beginning frame is shifted to @@ -322,7 +379,7 @@

    WORD_REALIGN -

    PKT_HALT

    +

    PKT_HALT

    The input buffer is stopped because the last block remains in the first word. The shift is set to the usual DOWN direction (to the 0th block) and the processing of the frame continues (see the right half of the picture in @@ -330,7 +387,7 @@

    PKT_HALT

    -

    Examples of realignment

    +

    Examples of realignment

    The following figures show various forms of realignment of an input frame. The resolution of those examples is done with respect to MFB blocks. The input configuration is MFB #(1,8,8,8) and the output is MFB #(1,4,16,8). This is shown @@ -344,7 +401,7 @@

    Examples of realignmentNotice that the input and output words are of the same length.

    -

    Scenario 1

    +

    Scenario 1

    ../../../../../../../../_images/mfb_lbus_reconf_realignment-Simple_real.svg @@ -361,7 +418,7 @@

    Scenario 1 -

    Scenario 2

    +

    Scenario 2

    ../../../../../../../../_images/mfb_lbus_reconf_realignment-Shift_whole.svg @@ -371,7 +428,7 @@

    Scenario 2 -

    Scenario 3

    +

    Scenario 3

    ../../../../../../../../_images/mfb_lbus_reconf_realignment-Two_together.svg @@ -387,7 +444,7 @@

    Scenario 3 -

    Scenario 4

    +

    Scenario 4

    ../../../../../../../../_images/mfb_lbus_reconf_realignment-Two_together_back.svg @@ -405,7 +462,7 @@

    Scenario 3 -

    Scenario 5

    +

    Scenario 5

    ../../../../../../../../_images/mfb_lbus_reconf_realignment-End_to_curr.svg @@ -417,7 +474,7 @@

    Scenario 3 -

    Scenario 6

    +

    Scenario 6

    ../../../../../../../../_images/mfb_lbus_reconf_realignment-End_to_curr_sec.svg @@ -431,34 +488,92 @@

    Scenario 6

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <TX MAC LITE + +
    - +
    + + 40GE Ethernet PHY for Ultrascale+ FPGAs> + +
    -
    -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/nic/mac_lite/tx_mac_lite/readme.html b/devel/comp/nic/mac_lite/tx_mac_lite/readme.html index 3e85d2f83..20f10e0d9 100644 --- a/devel/comp/nic/mac_lite/tx_mac_lite/readme.html +++ b/devel/comp/nic/mac_lite/tx_mac_lite/readme.html @@ -1,52 +1,136 @@ - - - - - - - TX MAC LITE — NDK-FPGA Docs documentation - - + + + + - - - - - - + TX MAC LITE — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    TX MAC LITE

    +

    TX MAC LITE

    This component is used to implement the Ethernet MAC layer on the transmitting side. Thanks to the modular architecture (TX MAC LITE + Adapter), it can be connected to a supported ETH Hard IP block or implement the MAC layer separately. The implementation may include differences from the Ethernet standard.

    -

    Architecture

    +

    Architecture

    The TX MAC LITE checks the length of the input frames, if it is less than 60B, these frames are discarded. TX MAC LITE may optionally contain subcomponents that are used to calculate and insert a CRC into the frame being sent. In cases where the module must insert a CRC or generate inter-packet gaps, the Spacer (CrossbarX Stream) component is used as the main buffer. @@ -147,7 +218,7 @@

    Architecture -

    Adapter

    +

    Adapter

    The adapter allows you to connect the TX MAC LITE to various variants of the PCS/PMA layer of the Ethernet or various Ethernet Hard IPs. The main task of the adapter is to convert the selected input bus to the MFB bus. Currently, several variants of the adapter are implemented:

    @@ -159,7 +230,7 @@

    Adapter

    -

    Register Map

    +

    Register Map

    TX MAC LITE is off by default, it must be turned on (Enable register) to allow Ethernet frames to be sent. There are four statistical counters in the address space. You have to sample the counters first and then you can read their content.

    @@ -477,10 +548,10 @@

    Register Map -

    Ports and Generics

    +

    Ports and Generics

    -ENTITY TX_MAC_LITE IS
    +ENTITY TX_MAC_LITE IS
    Generics

    Generic

    @@ -788,34 +859,78 @@

    Ports and Generics - +
    + + MFB -> LBUS reconfigurator (TX LBUS)> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/common/readme.html b/devel/comp/pcie/common/readme.html index 9a81c41a3..a39437b23 100644 --- a/devel/comp/pcie/common/readme.html +++ b/devel/comp/pcie/common/readme.html @@ -1,52 +1,136 @@ - - - - - - - PCI_EXT_CAP — NDK-FPGA Docs documentation - - + + + + - - - - - - + PCI_EXT_CAP — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    PCI_EXT_CAP

    +

    PCI_EXT_CAP

    PCI Extended Capability unit stores OFM-specific identification mechanisms. It is typically connected to the PCIe core and mapped to the PCI configuration space as a Vendor-Specific Extension Capability (VSEC) with ID 0x0D7B.

    Generic

    - +@@ -190,7 +261,7 @@
    Address spaceAddress space
    - +@@ -213,7 +284,7 @@
    Extra spaceExtra space
    -

    Device Tree

    +

    Device Tree

    The Device Tree with the firmware description is obtained through the dtb_pkg VHDL package.

    Software gets the length of stored DT in bytes by reading the DTB length register and then performs the appropriate number of reads from the dword-sized DTB data register. @@ -221,18 +292,18 @@

    Device Tree -

    Endpoint ID

    +

    Endpoint ID

    For multi-PCIe endpoint firmware, the software must identify a particular PCIe endpoint. For that purpose, it reads the Endpoint ID value (4b) in the Flags register. The Endpoint ID is valid only if the Endpoint ID flag bit is set.

    -

    Extra space

    +

    Extra space

    The Extra data register uses indirect addressing like the DTB data register. Access must be preceded with a write of an index to the Extra address register.

    -

    Card ID

    +

    Card ID

    When more cards are present in the system, the software needs to pair all PCIe endpoints of multi-PCIe cards to the correct parent device (typically based on the primary PCIe endpoint with the Endpoint ID value 0).

    @@ -244,34 +315,78 @@

    Card ID

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <PTC Tag Manager + +
    - +
    + + PCIE Byte Count> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/convertors/readme.html b/devel/comp/pcie/convertors/readme.html index 9af224e85..c60e8feaf 100644 --- a/devel/comp/pcie/convertors/readme.html +++ b/devel/comp/pcie/convertors/readme.html @@ -1,52 +1,136 @@ - - - - - - - PCIE CONVERSION UNITS — NDK-FPGA Docs documentation - - + + + + - - - - - - + PCIE CONVERSION UNITS — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    PCIE CONVERSION UNITS

    +

    PCIE CONVERSION UNITS

    -ENTITY PCIE_CQ_AXI2MFB IS
    +ENTITY PCIE_CQ_AXI2MFB IS

    The Purpose of this component is to convert AXI to MFB bus. Supported are 512b and 256b with and without straddling, but variants with straddling and all 256 variant has not been tested.

    @@ -321,7 +398,7 @@
    -ENTITY PCIE_CC_MFB2AXI IS
    +ENTITY PCIE_CC_MFB2AXI IS

    The Purpose of this component is to convert MFB to AXI bus. Supported is only 512b variant without straddling

    Generics @@ -482,34 +559,52 @@ - +
    - +
    + + DMA Calypte> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/logic/byte_count/readme.html b/devel/comp/pcie/logic/byte_count/readme.html index 6cf374a2a..b164547c8 100644 --- a/devel/comp/pcie/logic/byte_count/readme.html +++ b/devel/comp/pcie/logic/byte_count/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - PCIE Byte Count — NDK-FPGA Docs documentation - - - - - - - - - + PCIE Byte Count — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    PCIE Byte Count

    +

    PCIE Byte Count

    -ENTITY PCIE_BYTE_COUNT IS
    +ENTITY PCIE_BYTE_COUNT IS

    This component calculates the correct number of bytes contained in the payload of the incoming PCIe transaction. The size is calculated using DW_COUNT, FIRST_BE and LAST_BE signals provided by each transaction.

    @@ -200,34 +277,52 @@
    -
    +
    -
    +
    +
    +
    +
    + + + <PCI_EXT_CAP + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + PCIe Byte Enable Decoder> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/logic/byte_en_decoder/readme.html b/devel/comp/pcie/logic/byte_en_decoder/readme.html index 514079393..4f76a41af 100644 --- a/devel/comp/pcie/logic/byte_en_decoder/readme.html +++ b/devel/comp/pcie/logic/byte_en_decoder/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - PCIe Byte Enable Decoder — NDK-FPGA Docs documentation - - - - - - - - - + PCIe Byte Enable Decoder — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    PCIe Byte Enable Decoder

    +

    PCIe Byte Enable Decoder

    -ENTITY PCIE_BYTE_EN_DECODER IS
    +ENTITY PCIE_BYTE_EN_DECODER IS

    This component decodes Last and First Byte Enable signals for the incoming PCI Express transactions. Non-continuous series of ones are replaced by contiuous. For example:

    Input (Last_BE,First_BE) -> Output (Last_BE,First_BE)

    @@ -172,34 +249,52 @@
    -
    +
    -
    +
    +
    +
    +
    + + + <PCIE Byte Count + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + PCIE Header parsing/deparsing> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/mtc/readme.html b/devel/comp/pcie/mtc/readme.html index d942f4ff7..1f55db0ae 100644 --- a/devel/comp/pcie/mtc/readme.html +++ b/devel/comp/pcie/mtc/readme.html @@ -1,52 +1,136 @@ - - - - - - - MTC (MI Transaction Controller) — NDK-FPGA Docs documentation - - + + + + - - - - - - + MTC (MI Transaction Controller) — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MTC (MI Transaction Controller)

    +

    MTC (MI Transaction Controller)

    -ENTITY MTC IS
    +ENTITY MTC IS

    The MI Transaction Controller (MTC) component serves as the MI master endpoint. It provides the conversion of PCIe read and write requests to MI requests. It processes the responses to MI requests and sends them to @@ -424,34 +501,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <PCIe Tools + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + PTC (PCIe Transaction Controller)> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/others/hdr_gen/readme.html b/devel/comp/pcie/others/hdr_gen/readme.html index 3c87a1d48..fca0b02c2 100644 --- a/devel/comp/pcie/others/hdr_gen/readme.html +++ b/devel/comp/pcie/others/hdr_gen/readme.html @@ -1,52 +1,136 @@ - - - - - - - PCIE Header parsing/deparsing — NDK-FPGA Docs documentation - - + + + + - - - - - - + PCIE Header parsing/deparsing — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    PCIE Header parsing/deparsing

    +

    PCIE Header parsing/deparsing

    -ENTITY PCIE_RQ_HDR_GEN IS
    +ENTITY PCIE_RQ_HDR_GEN IS

    The Purpose of this component is to fill PCIE RQ header.

    Generics
    @@ -221,7 +298,7 @@
    -ENTITY PCIE_CC_HDR_GEN IS
    +ENTITY PCIE_CC_HDR_GEN IS

    The Purpose of this component is to fill PCIE CC header.

    Generics
    @@ -331,7 +408,7 @@
    -ENTITY PCIE_RC_HDR_DEPARSER IS
    +ENTITY PCIE_RC_HDR_DEPARSER IS

    The Purpose of this component is to deparse PCIE RC header.

    Generics
    @@ -414,7 +491,7 @@
    -ENTITY PCIE_CQ_HDR_DEPARSER IS
    +ENTITY PCIE_CQ_HDR_DEPARSER IS

    The Purpose of this component is to deparse PCIE CQ header.

    Generics
    @@ -565,34 +642,52 @@ - +
    - +
    + + PCIE CONVERSION UNITS> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/ptc/comp/tag_manager/readme.html b/devel/comp/pcie/ptc/comp/tag_manager/readme.html index c879d67e6..45e73760f 100644 --- a/devel/comp/pcie/ptc/comp/tag_manager/readme.html +++ b/devel/comp/pcie/ptc/comp/tag_manager/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - PTC Tag Manager — NDK-FPGA Docs documentation - - - - - - - - - + PTC Tag Manager — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    PTC Tag Manager

    +

    PTC Tag Manager

    The purpose of the Tag Manager is to convert between the ID tagging space of the DMA transactions and the ID tagging space of the PCIe transactions. The DMA tagging consists of a Unit ID (one for each unit which generates requests) and a Tag. This way, each unit can have its own independent space of transaction Tags. @@ -134,7 +208,7 @@ The Tag Manager is also responsible for freeing of the PCIe Tags, checking of their availability and of the availability of storage space in the downstream MVB+MFB Storage FIFO. (The MVB+MFB Storage FIFO must be kept from overflowing to prevent fall of DST_RDY on the downstream IP core interface.)

    -

    Block diagram

    +

    Block diagram

    The core part of the unit is the Tag mapping N_LOOP_OP. It is a memory, which stores the corresponding DMA Tag and Unit ID for each possible PCIe Tag. Since, this memory can be updated multiple times in each cycle, the N_LOOP_OP is used, which allows parallel memory update.

    @@ -174,34 +248,75 @@

    Block diagram

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <PTC (PCIe Transaction Controller) + +
    - +
    + + PCI_EXT_CAP> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/pcie/ptc/readme.html b/devel/comp/pcie/ptc/readme.html index bcd193abf..fd0586556 100644 --- a/devel/comp/pcie/ptc/readme.html +++ b/devel/comp/pcie/ptc/readme.html @@ -1,52 +1,136 @@ - - - - - - - PTC (PCIe Transaction Controller) — NDK-FPGA Docs documentation - - + + + + - - - - - - + PTC (PCIe Transaction Controller) — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    PTC (PCIe Transaction Controller)

    +

    PTC (PCIe Transaction Controller)

    The PTC unit converts between MVB+MFB bus and an interface of a specific PCIe IP. It enables PCIe Transaction layer support. It only works with the Requester part of PCIe communication (requests from FPGA to host computer and responses for such requests). The unit contains multiple different IP-side interfaces for different IP cores. Only one of these interfaces is used in each design depending on the generics setting.

    -

    Block diagram

    +

    Block diagram

    The PTC unit has 2 main parts: the Upstream Path and the Downstream Path. @@ -153,7 +224,7 @@

    Block diagramdocumentation.

    -

    Other components

    +

    Other components

    Appart from the Tag Manager, the PTC (as shown on the diagram above) contains these components:

    1. MVB ASFIFO, MFB ASFIFO

      @@ -205,7 +276,7 @@

      Other components -

      Architecture configurations

      +

      Architecture configurations

      The PTC architecture changes depending on the type of the connected PCIe IP core. The architecture described in the diagram above is for Xilinx IP core with 1 DMA port and no MFB resizing.

      There are these changes which may occur:

      @@ -249,40 +320,84 @@

      Architecture configurations -

      References

      +

      References

      For more detailed description refer to Jan Kubalek’s thesis 2019/20.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MTC (MI Transaction Controller) + +
    - +
    + + PTC Tag Manager> + +
    -
    -
    - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/tsu/tsu_format_to_ns/readme.html b/devel/comp/tsu/tsu_format_to_ns/readme.html index 24c07fe45..8e435c126 100644 --- a/devel/comp/tsu/tsu_format_to_ns/readme.html +++ b/devel/comp/tsu/tsu_format_to_ns/readme.html @@ -1,50 +1,134 @@ + + + + + - - - - - - - TSU Format to ns Convertor — NDK-FPGA Docs documentation - - - - - - - - - + TSU Format to ns Convertor — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    TSU Format to ns Convertor

    +

    TSU Format to ns Convertor

    -ENTITY TSU_FORMAT_TO_NS IS
    +ENTITY TSU_FORMAT_TO_NS IS

    This component converts the Timestamp format of the TimeStamp Unit (the TS_NS output port) to pure nanosecond format. It does this by multiplying the upper 32 bits (that indicate the number of seconds) of the input by 10**9 and adding it to the lower 32 bits (that indicate the number of nanoseconds). Quartus and Vivado both manage to use DSPs for the multiplication, eventhough this description is behavioral. @@ -177,31 +255,42 @@

    -
    +
    -
    - -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - +
    +
    +
    +
    +
    +
    +
    + +
    - +
    + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/tsu/tsu_gen/readme.html b/devel/comp/tsu/tsu_gen/readme.html index 3792966a9..0a7ded87f 100644 --- a/devel/comp/tsu/tsu_gen/readme.html +++ b/devel/comp/tsu/tsu_gen/readme.html @@ -1,52 +1,136 @@ - - - - - - - TSU GEN — NDK-FPGA Docs documentation - - + + + + - - - - - - + TSU GEN — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    TSU GEN

    +

    TSU GEN

    -ENTITY TSU_GEN IS
    +ENTITY TSU_GEN IS

    The TimeStamp Unit is used to generate accurate 64b timestamps in two different formats (see the description of the TS and TS_NS ports). Conversion to another @@ -355,34 +432,52 @@

    -
    +
    -
    +
    +
    +
    +
    + + + <SDM CLIENT + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MI Tools> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/avmm/readme.html b/devel/comp/uvm/avmm/readme.html index 7b5968af0..a15e1298d 100644 --- a/devel/comp/uvm/avmm/readme.html +++ b/devel/comp/uvm/avmm/readme.html @@ -1,52 +1,136 @@ - - - - - - - AVMM Agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + AVMM Agent — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    AVMM Agent

    +

    AVMM Agent

    This agent is a low-level agent that is responsible for communication through the Intel Avalon Memory Mapped interface. This package uvm_avmm contains two agents. The slave agent sends requests to the DUT. The master agent samples requests from DUT and sends responses from the memory model.

    The agents are configured with three parameters:

    @@ -165,11 +236,11 @@

    AVMM Agent -

    Sequence Items

    +

    Sequence Items

    The following table shows properties in the sequence_items classes. This is a low-level protocol, so if you generate data in sequence, please be careful not to break the AVMM protocol rules.

    -

    sequence_item_request

    +

    sequence_item_request

    rand logic ready;
 rand logic read;
 rand logic write;
@@ -180,7 +251,7 @@ 
    sequence_item_request
    -

    sequence_item_response

    +

    sequence_item_response

    rand logic ready;
 rand logic [DATA_WIDTH-1 : 0] readdata;
 rand logic readdatavalid;
@@ -189,11 +260,11 @@ 
    sequence_item_response
    -

    Response logic

    +

    Response logic

    The master agent is capable of generating responses to input requests. For that reason, the agent contains two other components: request_subscriber and memory_model. These two components use internal items, request_item and response_item.

    -

    request_item

    +

    request_item

    Note :class: note

    @@ -207,18 +278,18 @@

    request_item -

    response_item

    +

    response_item

    logic [DATA_WIDTH-1 : 0] readdata;
 time timestamp;
    -

    request_subscriber

    +

    request_subscriber

    The request_subscriber converts sequence_item_request into request_item.

    -

    memory_model

    +

    memory_model

    The memory_model’s main purpose is to process the input request_item. For READ request_item, the memory_model outputs timestamped request_item with read data, which are used by sequences to send sequence_item_response items. The model uses a file as its memory.

    @@ -231,41 +302,94 @@

    memory_model -

    Sequences

    +

    Sequences

    The sequences use the response_item fifo located in their sequencer to generate sequence_item_response items. There are several sequences that work with response_item’s timestamp and response latency and can be useful for more complex DUT verification.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <FlowTest Sequence + +
    - +
    + + AVST CRDT Agent> + +
    -
    -
    -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/avst_crdt/readme.html b/devel/comp/uvm/avst_crdt/readme.html index 07a4300f8..01ae6a931 100644 --- a/devel/comp/uvm/avst_crdt/readme.html +++ b/devel/comp/uvm/avst_crdt/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - AVST CRDT Agent — NDK-FPGA Docs documentation - - - - - - - - - + AVST CRDT Agent — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    AVST CRDT Agent

    +

    AVST CRDT Agent

    This agent is a low-level agent that is responsible for communication through the Intel Credit Control interface. This package, uvm_avst_crdt, contains 2 generic and 4 predefined agents. The RX agent sends credits to the DUT. The TX agent is responsible for the correct initialization.

    -

    Agents

    +

    Agents

    The package contains RX and TX agents that can be parameterized with the UPDATE_CNT_WIDTH parameter. The generic agents are configured with one parameter:

      @@ -174,7 +245,7 @@

      Agents<

    -

    Sequence Item

    +

    Sequence Item

    The following table shows properties in the sequence_item class.

    rand logic                          init;
 rand logic                          init_ack;
@@ -184,7 +255,7 @@ 
    Sequence Item
-
    Sequences
    
+
    Sequences
    
 
      
 
    • sequence_rx is a common credit-generating sequence.
      • 
 
    • sequence_rx_initializing is responsible for correct initialization on the RX side.
      • 
@@ -195,34 +266,77 @@ 
      Sequences
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <AVMM Agent + +
    - +
    + + probe agent> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/axi/readme.html b/devel/comp/uvm/axi/readme.html index da7304908..2cd34ea33 100644 --- a/devel/comp/uvm/axi/readme.html +++ b/devel/comp/uvm/axi/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - AXI Agent — NDK-FPGA Docs documentation - - - - - - - - - + AXI Agent — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    AXI Agent

    +

    AXI Agent

    This agent is responsible for communication through the AXI interface. This is a low-level agent which generates only simple AXI words. For advanced control use the logic_vector_array_axi.

    The environment is configured by three parameters:

      @@ -162,7 +235,7 @@

    • REGIONS

    -

    sequence_item

    +

    sequence_item

    This package contains two agents. The RX agent sends data to the DUT and the TX agent samples the received data. Sequence run in the RX agent generates TDATA, TUSER, TKEEP, TLAST, and TVALID variables in a sequence_item. One clock cycle later, the driver sets the TREADY variable in the sequence_item as a response. The TX agent receives data from the DUT. It is required to generate TREADY and drive TDATA, TUSER, TKEEP, TLAST, and TVALID as a response one clock cycle later.

    @@ -180,34 +253,75 @@

    sequence_item

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Intel MAC SEG + +
    - +
    + + logic_vector_array_axi environment> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/byte_array/readme.html b/devel/comp/uvm/byte_array/readme.html index dd71a4c1e..73cb7e303 100644 --- a/devel/comp/uvm/byte_array/readme.html +++ b/devel/comp/uvm/byte_array/readme.html @@ -1,52 +1,136 @@ - - - - - - - Byte Array agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + Byte Array agent — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Byte Array agent

    +

    Byte Array agent

    The main task of this agent is to generate field of bytes which can be sent to DUT through the lower level agent. This agents does not contains a driver because it is higher level agent. Agent is used for connecting of all components (driver, monitor,…). Agent has his own configuration object which contains one parameter active (when is up then agent is active in other way is passive). When agent is active then sequencer is created. When is passive then only monitor is created.

    -

    Byte Array sequence item

    +

    Byte Array sequence item

    Sequence item contains only one randomizable item.

    • byte unsigned data[] sequence_item randomizable variable

      • @@ -171,7 +241,7 @@

      Byte Array sequence item -

      Byte Array monitor

      +

      Byte Array monitor

      Byte Array monitor is base class used for monitoring of traffic. This is only simple monitor which creates analysis port and sequence item and must be subclassed to particular lower level interface.

      @@ -180,7 +250,7 @@

      Byte Array monitor -

      Byte Array Sequence

      +

      Byte Array Sequence

      This package contains some interesting predefined sequences. Sequences generate N random transactions. The number of transactions is randomly selected when the sequence is randomized. Transactions contain a randomizable byte array. The major difference between the sequences is the boundary of the randomized size of a byte array. @@ -214,7 +284,7 @@

      Byte Array Sequence -

      Sequence configuration

      +

      Sequence configuration

      Configuration object config_sequence contain one configuration function.

    @@ -242,34 +312,78 @@

    Sequence configuration - +
    -     +
    + + Byte_array_mfb environment> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/byte_array_lii/readme.html b/devel/comp/uvm/byte_array_lii/readme.html index ffbcdc0e7..b79d9168a 100644 --- a/devel/comp/uvm/byte_array_lii/readme.html +++ b/devel/comp/uvm/byte_array_lii/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Byte Array to LII convert enviroment — NDK-FPGA Docs documentation - - - - - - - - - + Byte Array to LII convert enviroment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Byte Array to LII convert enviroment

    +

    Byte Array to LII convert enviroment

    This enviroment serves for preparation of agents (configuration set and creation), their connection to right analysis export and starting sequence on the right sequencer. This enviroment connect Byte Array agent with LII agent in fact.

    -

    Byte Array to LII monitor

    +

    Byte Array to LII monitor

    This monitor take LII specified number (it depends on the Length of Byte Array transaction) of transaction, merge them to one Byte Array transaction and writes it to analysis port. For acumulation of LII transactions is used fifo which only store all those transactions to his own memory.

    -

    Byte Array to LII Sequence

    +

    Byte Array to LII Sequence

    This sequence has one quest and that is cutting of Byte array sequence to bytes and set ports of LII request to right values. SOF will be asserted when first chunk of transaction arrive and EOF will be asserted when the last chunk of transaction arrive. If it is last chunk of transaction then it set to BYTES_VLD number of valid bytes of that chunk. At the end is sequence send to driver. There is also task which send empty sequence when frame is null.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Byte array to MII transitional environment + +
    - +
    + + Byte Array to LII convert enviroment> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/byte_array_lii_rx/readme.html b/devel/comp/uvm/byte_array_lii_rx/readme.html index fefcf9e77..9461eb957 100644 --- a/devel/comp/uvm/byte_array_lii_rx/readme.html +++ b/devel/comp/uvm/byte_array_lii_rx/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Byte Array to LII convert enviroment — NDK-FPGA Docs documentation - - - - - - - - - + Byte Array to LII convert enviroment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Byte Array to LII convert enviroment

    +

    Byte Array to LII convert enviroment

    This enviroment serves for preparation of agents (configuration set and creation), their connection to right analysis export and starting sequence on the right sequencer. This enviroment connect Byte Array agent with LII agent in fact.

    -

    Byte Array to LII monitor

    +

    Byte Array to LII monitor

    This monitor take LII specified number (it depends on the Length of Byte Array transaction) of transaction, merge them to one Byte Array transaction and writes it to analysis port. For acumulation of LII transactions is used fifo which only store all those transactions to his own memory.

    -

    Byte Array to LII Sequence

    +

    Byte Array to LII Sequence

    This sequence has one quest and that is cutting of Byte array sequence to bytes and set ports of LII request to right values. SOF will be asserted when first chunk of transaction arrive and EOF will be asserted when the last chunk of transaction arrive. If it is last chunk of transaction then it set to BYTES_VLD number of valid bytes of that chunk. At the end is sequence send to driver. There is also task which send empty sequence when frame is null.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Byte Array to LII convert enviroment + +
    - +
    + + Common package> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/byte_array_mfb/readme.html b/devel/comp/uvm/byte_array_mfb/readme.html index 5a252fa8d..509609daf 100644 --- a/devel/comp/uvm/byte_array_mfb/readme.html +++ b/devel/comp/uvm/byte_array_mfb/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Byte_array_mfb environment — NDK-FPGA Docs documentation - - - - - - - - - + Byte_array_mfb environment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Byte_array_mfb environment

    +

    Byte_array_mfb environment

    This environment has two high-level agents. The first one is a byte array agent and it works with data. The second one is a logic vector agent which works with metadata. This package contains two environments. Environment RX generates data and metadata and sends them to the DUT. Environment TX generates the DST_RDY signal and observes the TX interface.

    @@ -169,14 +239,14 @@

  • META_WIDTH

    • -

    Top sequencers and sequences

    +

    Top sequencers and sequences

    In the RX direction, there are two sequencers: the first is a Byte Array sequencer that handles MFB_DATA. The second is a Logic Vector sequencer that handles MFB_METADATA. Both sequencers pull the data from sequences together.

    In the TX direction, there is one sequencer of type mfb::sequencer #(), which generates the DST_RDY signal.

    Both directions have two analysis_exports. One export is for the Byte Array transactions, and the second is for the Logic Vector (metadata) transactions.

    -

    Configuration

    +

    Configuration

    The config class has three variables.

    @@ -232,7 +302,7 @@

    Configuration -

    Low sequence configuration

    +

    Low sequence configuration

    configuration object config_sequence contain two function.

    @@ -254,7 +324,7 @@

    Low sequence configuration -

    RX Inner sequences

    +

    RX Inner sequences

    For the RX direction exists one base sequence class “sequence_simple_rx_base” which simplifies creating others sequences. It processes the reset signal and exports virtual function create_sequence_item. In this function can child create mfb::sequence_item what they like. Other important function in “sequence_simple_rx_base” class is try_get() which downloads required data from base array agent. It is also important to note that the base class is state oriented. Following table describes internal states.

    @@ -346,34 +416,78 @@

    RX Inner sequences - +
    + + byte array to MAC SEG> + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/byte_array_mii/readme.html b/devel/comp/uvm/byte_array_mii/readme.html index 8f28d0f6f..82ce830f0 100644 --- a/devel/comp/uvm/byte_array_mii/readme.html +++ b/devel/comp/uvm/byte_array_mii/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Byte array to MII transitional environment — NDK-FPGA Docs documentation - - - - - - - - - + Byte array to MII transitional environment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Byte array to MII transitional environment

    +

    Byte array to MII transitional environment

    The purpose of this environment is to create MII and Byte array agents, set them up correctly, introduce randomness to data generation, and guarantee, that this data will be sent and read as standard defines. This environment allows to use multi-channel xMII bus and one cannot verify components that are using the MII bus, without this high-level environment.

    -

    Usage

    +

    Usage

    There are two types of environment: RX and TX. To use the RX environment, instantiate it, and run byte_array sequence on the high-level agent (if active). To use the TX environment, just instantiate it, no need to run any sequences.

    -

    monitor.sv

    +

    monitor.sv

    The monitor takes low-level xMII transactions and extracts data from them. It creates one byte_array transaction for a frame transmitted.

    -

    sequencer.sv

    +

    sequencer.sv

    This sequencer contains a reference to a high-level sequencer.

    -

    env.sv

    +

    env.sv

    This file contains RX and TX environments. RX environment, if active, takes high-level transactions from the byte_array agent, transforms them to low-level xMII transactions and sends them to the interface. TX environment, if active, drives the CLK_EN signal.

    -

    sequence_rx_base.sv

    +

    sequence_rx_base.sv

    This file contains a base class for all RX sequences. It is recommended for all RX sequences to inherit from them. They can be modified by creating specific instances of classes described below.

    -

    sequence_tx_base.sv

    +

    sequence_tx_base.sv

    This file contains a base class for all TX sequences. It is recommended for all TX sequences to inherit from them. They can be modified by creating specific instances of classes described below.

    -

    ce_generator.sv

    +

    ce_generator.sv

    Classes in this file take care of generating clock enable signal.

    -

    wrapper.sv

    +

    wrapper.sv

    This class takes an array (FIFO, to make implementation easier) of bytes as input and adds the start of frame delimiter and preamble to the beginning of data, and appends the end of frame delimiter to the end. It also creates control logic array for the whole wrapped array of bytes

    -

    ipg_generator.sv

    +

    ipg_generator.sv

    This class appends a random number (between idle_count_min and idle_count_max) of idle octets to the wrapped frame and control array.

    -

    channel_align.sv

    +

    channel_align.sv

    This class appends as many idle octets to the array as needed to make sure, that the next frame starts on lane 0 of any channel. In other words, it fills the remaining free bytes of the current channel with idle octets.

    -

    data_buffer.sv

    +

    data_buffer.sv

    This class accumulates data generated in pipeline (byte array -> wrapper -> ipg_generator -> channel_align -> data_buffer) until low-level transaction can be generated. In case, when more than one low-level transaction can be generated, it informs the user about it and one can retrieve data from it until no low-level transaction can be generated. In case no more high-level transactions will be generated, it can generate idle octets until one, last low-level transaction can be generated (flush).

    As the last step, low-level transactions are distributed accordingly to channels.

    -

    sequence_rx.sv and sequence_tx.sv

    +

    sequence_rx.sv and sequence_tx.sv

    These files contain sequences specific by different speeds (amount of idle octets) and clock enable patterns.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Byte array to pma convert enviroment + +
    - +
    + + Byte Array to LII convert enviroment> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/byte_array_pma/readme.html b/devel/comp/uvm/byte_array_pma/readme.html index 511f2312c..1750686aa 100644 --- a/devel/comp/uvm/byte_array_pma/readme.html +++ b/devel/comp/uvm/byte_array_pma/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Byte array to pma convert enviroment — NDK-FPGA Docs documentation - - - - - - - - - + Byte array to pma convert enviroment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Byte array to pma convert enviroment

    +

    Byte array to pma convert enviroment

    This enviroment serves for preparation of agents (configuration set and creation), their connection to right analysis export and starting sequence on the right sequencer. This environment connect Byte Array agent with PMA agent in fact.

    -

    Byte Array to PMA monitor

    +

    Byte Array to PMA monitor

    Function of this monitor is take PMA transaction descramble it, then choose if it is start, middle or end of high level transaction that depends on type of frame (IDLE, START, …). When the end of transaction occured, high level transaction is writed to analysis port. To accumulation of data is used easy fifo.

    -

    Byte Array to PMA Sequence

    +

    Byte Array to PMA Sequence

    This sequence is used for generation of encoded data in right way and then send it to driver. Ther is state machine, which generate data in the right way. First random amount of idles is generated, after this state is changed to start and start sequence is generated, after second chunk of start sequence is generated, then state is changed to data and after that data from high level sequence are cutted to chunks which has same width as PMA transaction and there are sended to driver. After all data are sended, then terminate sequence is generate, this sequence depends on amount of valid bytes of last two words in high level sequence. To every sequence is generated header which has only valid values and tehre is also generated header valid once per two clocks cycles. There is one constraint in randomization which set percentage of occurrence of the block lock in verification. Every PMA sequence which is generated is scramble by scrambler with polynom 1 + x^39 + x^58.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <byte array to MAC SEG + +
    - +
    + + Byte array to MII transitional environment> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/common/readme.html b/devel/comp/uvm/common/readme.html index db5f803bd..7e3ae7c9d 100644 --- a/devel/comp/uvm/common/readme.html +++ b/devel/comp/uvm/common/readme.html @@ -1,52 +1,136 @@ - - - - - - - - Common package — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + Common package — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Common package

    +

    Common package

    common package contain commonly used small components.

    -

    Random

    +

    Random

    Common randomization is required for generating space between frame and space between packets. For this purpose two classes have been created (rand_rdy, rand_length). Fist class generates rdy signal. Second class generate number reprezenting length.

    @@ -201,12 +272,12 @@

    Random<

    -

    Comparer

    +

    Comparer

    These components compare transactions from the DUT with transactions from the model. There are three major classes. All classes have one required parameter and one optional parameter. The first parameter is the type of model’s transactions. The second parameter is the type of DUT transactions.

    - +@@ -231,7 +302,7 @@

    Comparer

    If the type of the model and DUT transactions are the same, then a predefined comparer component can be used. This component has only one parameter - the transaction type.

    comparer classescomparer classes
    - + @@ -251,7 +322,7 @@

    Comparer

    All comparers contain a watchdog. You can set up the maximum waiting time for the model and DUT transactions. Maximum waiting time for the model transactions may be necessary if the DUT can create results from partial input.

    comparer classescomparer classes
    - +@@ -336,7 +407,7 @@

    Comparer
    -

    fifo

    +

    fifo

    This component has been created for connecting models. The problem is when there is an output value of one model changes before entering another model. A common example is when the same model is used in the verification multiple times, and each time, its input(s) are modified differently. Such a scenario is displayed in the example below.

    ENTITY_i : entity work.ENTITY_A
@@ -499,34 +570,77 @@ 
    fifo<
    - +
    - + + +
    + +
    +
    +
    + + + <Byte Array to LII convert enviroment + +
    + +
    + + LII agent> + +
    -
    - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/componets.html b/devel/comp/uvm/componets.html index b71489f4c..ff836e87b 100644 --- a/devel/comp/uvm/componets.html +++ b/devel/comp/uvm/componets.html @@ -1,52 +1,136 @@ - - - - - - - Components — NDK-FPGA Docs documentation - - + + + + - - - - - - + Components — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Components

    +

    Components

    Library of commonly used agents and enviroments in UVM verification

    Components:

    @@ -335,34 +412,52 @@
    -
    +
    -
    +
    +
    +
    +
    + + + <UVM simulation + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + RESET agent> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/intel_mac_seg/readme.html b/devel/comp/uvm/intel_mac_seg/readme.html index 9f1cb8529..60b26e2ff 100644 --- a/devel/comp/uvm/intel_mac_seg/readme.html +++ b/devel/comp/uvm/intel_mac_seg/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Intel MAC SEG — NDK-FPGA Docs documentation - - - - - - - - - + Intel MAC SEG — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Intel MAC SEG

    +

    Intel MAC SEG

    This agent is a low-level agent that is responsible for communication through Intel MAC SEG. It is commonly used for ethernet communication. The intel_mac_seg_if interface has one parameter, SEGMENTS, which represents a number of segments. There are two agents for Rx and Tx communication. The component is commonly used with the uvm_logic_vector_array when the uvm_logic_vector_array::sequence_item has to be converted to the uvm_intel_mac_seg::sequence_item.

    -

    Sequence item

    +

    Sequence item

    • rand logic [64-1:0] data[SEGMENTS];

      • @@ -175,12 +246,12 @@

      Sequence item -

      Sequence

      +

      Sequence

      There are two sequences. The one for RX is not commonly used. It doesn’t generate truly valid frames. Better is to use the uvm_logic_vector_array_intel_mac_seg::env environment. The Tx one generates a ready signal for the Tx agent.

    -

    Config

    +

    Config

    The config contains two variables. The active decides whether the agent drives the interface or only observes the interface. The interface_name variable represents the name under which is interface stored in a database.

    @@ -193,34 +264,77 @@

    Config<

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <PMA agent + +
    - +
    + + AXI Agent> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/lbus/readme.html b/devel/comp/uvm/lbus/readme.html index f6252b635..a8b6ad25f 100644 --- a/devel/comp/uvm/lbus/readme.html +++ b/devel/comp/uvm/lbus/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - LBUS Agent — NDK-FPGA Docs documentation - - - - - - - - - + LBUS Agent — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    LBUS Agent

    +

    LBUS Agent

    This agent is a low-level agent that is responsible for communication through the Xilinx LBUS interface. This package, uvm_lbus, contains 2 agents. The TX agent sends low-level transactions to the DUT. The RX agent is responsible for correctly receiving low-level transactions sent by the DUT.

    -

    Sequence Item

    +

    Sequence Item

    The following table shows properties in the sequence_item class.

    rand logic [4*128-1 : 0] data;
 rand logic [4    -1 : 0] ena;
@@ -172,7 +243,7 @@ 
    Sequence Item
-
    Sequences
    
+
    Sequences
    
 
      
 
    • sequence_rx is a common ready-generating sequence that internally uses the uvm_common::rand_rdy.
      • 
 
    • sequence_rx_stop is a sequence with an asserted READY signal.
      • 
@@ -180,7 +251,7 @@ 
      Sequences
-
      Sequence Libraries
      
+
      Sequence Libraries
      
 
        
 
      • sequence_library_rx contains: sequence_rx, sequence_rx_stop, sequence_rx_fullspeed.
        • 
 
      • sequence_library_rx_fullspeed contains: sequence_rx_fullspeed.
        • 
@@ -189,34 +260,77 @@ 
        Sequence Libraries
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <probe agent + +
    - +
    + + LOGIC VECTOR ARRAY LBUS Environment> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/lii/readme.html b/devel/comp/uvm/lii/readme.html index 29627491f..1df613272 100644 --- a/devel/comp/uvm/lii/readme.html +++ b/devel/comp/uvm/lii/readme.html @@ -1,52 +1,136 @@ - - - - - - - LII agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + LII agent — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    LII agent

    +

    LII agent

    Agent is used for connecting of all components (driver, monitor,…). Agent has his own configuration object which contains two parameters: active (when is up then agent is active in other way is passive) and interface which say name of the interface that is used. When agent is active then sequencer and driver are created amd connected to interface. When is passive then only monitor is created.

    -

    LII interface

    +

    LII interface

    LII (Media-independent interface) bus is interface which allows communication throught 10g low latency ethernet. There are asserts which check if EEOF is asserted right and if SOF and EOF are coming in right ordder. Link for detailed description of LII bus is here: https://gitlab.liberouter.org/ndk/hft/-/tree/friedl-feat-ethphy/comp/eth_phy/10ge/top

    -

    LII bus description

    +

    LII bus description

    LII bus has these 5 ports + 2 ports optional (EEOF and EDB) which depends on parameter FAST_SOF. In verification interface are asserts which check these events.

    -

    Generics

    +

    Generics

    comparer classescomparer classes
    @@ -191,7 +261,7 @@

    Generics

    Name

    -

    Ports

    +

    Ports

    @@ -241,7 +311,7 @@

    Ports
    -

    LII sequence item

    +

    LII sequence item

    Sequence item contains basic ports from interface, except EEOF and EDB which are only drived to interface by driver. All signals which are in sequence item are randomized. There are three methods:

      @@ -251,44 +321,93 @@

      LII sequence item -

      LII monitor

      +

      LII monitor

      LII monitor is used for monitoring of traffic. There is only easy monitor which write whole transaction to analysis port when reset is not asserted.

    -

    LII driver

    +

    LII driver

    LII driver is used for driving LII transactions to interface. There is used one parameter FAST SOF, when this parameter is asserted then driver driving EEOF and EDB to interface. EEOF and EDB is drived only when in the next transaction is asserted EOF, EDB must be same as BYTES_VLD in next transaction.

    - +
    - +
    + + LII agent> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/lii_rx/readme.html b/devel/comp/uvm/lii_rx/readme.html index d6fef923d..bbe760415 100644 --- a/devel/comp/uvm/lii_rx/readme.html +++ b/devel/comp/uvm/lii_rx/readme.html @@ -1,52 +1,136 @@ - - - - - - - LII agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + LII agent — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    LII agent

    +

    LII agent

    Agent is used for connecting of all components (driver, monitor,…). Agent has his own configuration object which contains two parameters: active (when is up then agent is active in other way is passive) and interface which say name of the interface that is used. When agent is active then sequencer and driver are created amd connected to interface. When is passive then only monitor is created.

    -

    LII interface

    +

    LII interface

    LII (Media-independent interface) bus is interface which allows communication throught 10g low latency ethernet. There are asserts which check if EEOF is asserted right and if SOF and EOF are coming in right ordder. Link for detailed description of LII bus is here: https://gitlab.liberouter.org/ndk/hft/-/tree/friedl-feat-ethphy/comp/eth_phy/10ge/top

    -

    LII bus description

    +

    LII bus description

    LII bus has these 5 ports + 2 ports optional (EEOF and EDB) which depends on parameter FAST_SOF. In verification interface are asserts which check these events.

    -

    Generics

    +

    Generics

    Name

    @@ -191,7 +262,7 @@

    Generics

    Name

    -

    Ports

    +

    Ports

    @@ -241,7 +312,7 @@

    Ports
    -

    LII sequence item

    +

    LII sequence item

    Sequence item contains basic ports from interface, except EEOF and EDB which are only drived to interface by driver. All signals which are in sequence item are randomized. There are three methods:

      @@ -251,43 +322,90 @@

      LII sequence item -

      LII monitor

      +

      LII monitor

      LII monitor is used for monitoring of traffic. There is only easy monitor which write whole transaction to analysis port when reset is not asserted.

    -

    LII driver

    +

    LII driver

    LII driver is used for driving LII transactions to interface. There is used one parameter FAST SOF, when this parameter is asserted then driver driving EEOF and EDB to interface. EEOF and EDB is drived only when in the next transaction is asserted EOF, EDB must be same as BYTES_VLD in next transaction.

    - +
    - +
    + + MVB agent> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/logic_vector/readme.html b/devel/comp/uvm/logic_vector/readme.html index 55f2f68ad..e7ac68083 100644 --- a/devel/comp/uvm/logic_vector/readme.html +++ b/devel/comp/uvm/logic_vector/readme.html @@ -1,52 +1,136 @@ - - - - - - - Logic vector agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + Logic vector agent — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Logic vector agent

    +

    Logic vector agent

    The main task of this agent is to generate field of logic vector[ITEM_WIDTH-1:0] which can be sent to DUT through the lower level agent. This agents does not contains a driver because it is higher level agent. Agent is used for connecting of all components (driver, monitor,…). Agent has his own configuration object which contains one parameter active (when is up then agent is active in other way is passive). When agent is active then sequencer is created. When is passive then only monitor is created.

    -

    Logic Vector Array sequence item

    +

    Logic Vector Array sequence item

    Sequence item contains only one randomizable item.

    • logic [ITEM_WIDTH-1:0] data[] sequence_item randomizable variable

      • @@ -171,7 +241,7 @@

      Logic Vector Array sequence item -

      Logic Vector Array monitor

      +

      Logic Vector Array monitor

      Logic vector array monitor is base class used for monitoring of traffic. This is only simple monitor which creates analysis port and sequence item and must be subclassed to particular lower level interface.

      @@ -180,7 +250,7 @@

      Logic Vector Array monitor -

      Logic Vector Array Sequence

      +

      Logic Vector Array Sequence

      This package contains some interesting predefined sequences. Sequences generate N random transactions. The number of transactions is randomly selected when the sequence is randomized. Transactions contain a randomizable logic_vector array. The major difference between the sequences is the boundary of the randomized size of a logic vector array. @@ -214,7 +284,7 @@

      Logic Vector Array Sequence -

      Sequence configuration

      +

      Sequence configuration

      Configuration object config_sequence contain one configuration function.

    Name

    @@ -242,34 +312,78 @@

    Sequence configuration - +
    -     +
    + + logic_vector_mvb environment> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/logic_vector_array/readme.html b/devel/comp/uvm/logic_vector_array/readme.html index 5f6deca3c..c56dbd45f 100644 --- a/devel/comp/uvm/logic_vector_array/readme.html +++ b/devel/comp/uvm/logic_vector_array/readme.html @@ -1,52 +1,136 @@ - - - - - - - Logic Vector Array agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + Logic Vector Array agent — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Logic Vector Array agent

    +

    Logic Vector Array agent

    The main task of this agent is to generate a field of logic vectors that can be sent to the DUT through a lower-level agent. This agent does not contain a driver because it is a higher-level agent. However, it connects all components like the driver, monitor, etc., together. It has its own configuration object which contains one parameter: active (the agent is active when it is set, else it is passive). When the agent is active, a sequencer is created. When it is passive, only a monitor is created.

    -

    Logic Vector Array sequence item

    +

    Logic Vector Array sequence item

    A sequence item contains only one randomizable item.

    • logic[ITEM_WIDTH-1 : 0] data[] sequence_item randomizable variable

      • @@ -201,7 +271,7 @@

      Logic Vector Array sequence item -

      Logic Vector Array monitor

      +

      Logic Vector Array monitor

      Logic Vector Array monitor is a basic class used to monitor traffic. This is only a simple monitor which creates an analysis port and a sequence item and must be subclassed to a particular lower-level interface.

      @@ -210,7 +280,7 @@

      Logic Vector Array monitor -

      Logic Vector Array Sequence

      +

      Logic Vector Array Sequence

      This package contains some interesting predefined sequences. Sequences generate N random transactions. The number of transactions is randomly selected when the sequence is randomized. Transactions contain a randomizable byte array. The major difference between the sequences is the boundary of the randomized size of a byte array. @@ -244,7 +314,7 @@

      Logic Vector Array Sequence -

      Sequence configuration

      +

      Sequence configuration

      The configuration object config_sequence contains a single configuration function.

    @@ -272,34 +342,78 @@

    Sequence configuration - +
    -     +
    + + logic_vector_array_mfb environment> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/logic_vector_array_axi/readme.html b/devel/comp/uvm/logic_vector_array_axi/readme.html index 561e84282..f6be2fc07 100644 --- a/devel/comp/uvm/logic_vector_array_axi/readme.html +++ b/devel/comp/uvm/logic_vector_array_axi/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - logic_vector_array_axi environment — NDK-FPGA Docs documentation - - - - - - - - - + logic_vector_array_axi environment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    logic_vector_array_axi environment

    +

    logic_vector_array_axi environment

    This environment has one high-level logic vector array agent and it works only with data. This package contains two environments. The RX environment generates and sends data to the DUT. The TX environment generates TREADY and observes the TX interface.

    @@ -170,13 +240,13 @@

  • REGIONS

    • -

    Top sequencers and sequences

    +

    Top sequencers and sequences

    In the RX direction, there is the Logic vector array sequencer that handles the AXI TDATA and the TUSER.

    In the TX direction, there is one sequencer of type axi::sequencer #(DATA_WIDTH, TUSER_WIDTH, REGIONS) which generates the TREADY signal.

    Both directions have an analysis_export for logic vector array transactions.

    -

    Configuration

    +

    Configuration

    The config class has three variables.

    @@ -228,7 +298,7 @@

    Configuration -

    Low-level sequence configuration

    +

    Low-level sequence configuration

    The configuration object config_sequence contains two functions.

    @@ -250,7 +320,7 @@

    Low-level sequence configuration -

    RX Inner sequences

    +

    RX Inner sequences

    For the RX direction, there is one base sequence class “sequence_simple_rx_base” which simplifies the creation of other sequences. It processes the reset signal and exports the create_sequence_item virtual function. In this function, a child can create an axi::sequence_item as they like. Another important function in the “sequence_simple_rx_base” class is try_get() which gets the required data from the base array agent. It is also important to note that the base class is state-oriented. The following table describes the internal states.

    @@ -337,34 +407,78 @@

    RX Inner sequences - +
    + + FlowTest Sequence> + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/logic_vector_array_intel_mac_seg/readme.html b/devel/comp/uvm/logic_vector_array_intel_mac_seg/readme.html index 78c35585a..a085ee2d4 100644 --- a/devel/comp/uvm/logic_vector_array_intel_mac_seg/readme.html +++ b/devel/comp/uvm/logic_vector_array_intel_mac_seg/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - byte array to MAC SEG — NDK-FPGA Docs documentation - - - - - - - - - + byte array to MAC SEG — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    byte array to MAC SEG

    +

    byte array to MAC SEG

    this agent is low level agent for MAC SEG

    -
    +
    -
    +
    +
    +
    +
    + + + <Byte_array_mfb environment + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + Byte array to pma convert enviroment> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/logic_vector_array_lbus/readme.html b/devel/comp/uvm/logic_vector_array_lbus/readme.html index 230c8350c..c7d4cba80 100644 --- a/devel/comp/uvm/logic_vector_array_lbus/readme.html +++ b/devel/comp/uvm/logic_vector_array_lbus/readme.html @@ -1,51 +1,136 @@ + + + + + - - - - - - - LOGIC VECTOR ARRAY LBUS Environment — NDK-FPGA Docs documentation - - - - - - - - - + LOGIC VECTOR ARRAY LBUS Environment — NDK-FPGA documentation + + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    LOGIC VECTOR ARRAY LBUS Environment

    +

    LOGIC VECTOR ARRAY LBUS Environment

    This environment has two high-level agents. The first one is a logic vector array agent that works with packet data. The second one is a logic vector agent that works with error data. This package contains two environments. TX environment generates packet and error data and sends them to the DUT. RX environment generates the RDY signal and observes the RX interface.

    -

    Sequencers

    +

    Sequencers

    -

    TX direction

    +

    TX direction

    • packet is a logic vector array sequencer that handles packet data.

    • error is a logic vector sequencer that handles error data.

      • @@ -167,13 +240,13 @@

      TX direction -

      RX direction

      +

      RX direction

      There is one sequencer of type lbus::sequencer that generates the RDY signal.

      Both directions have two analysis exports. One export is for the logic vector array transactions, and the second is for the logic vector transactions.

    -

    Sequences

    +

    Sequences

    • sequence_tx is a basic converting sequence.

    • sequence_tx_stop is a sequence that generates only empty transactions.

      • @@ -183,33 +256,80 @@

      Sequences

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <LBUS Agent + +
    - +
    + + MI bus specification> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/logic_vector_array_mfb/readme.html b/devel/comp/uvm/logic_vector_array_mfb/readme.html index 9a15bb7a6..2fada5e14 100644 --- a/devel/comp/uvm/logic_vector_array_mfb/readme.html +++ b/devel/comp/uvm/logic_vector_array_mfb/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - logic_vector_array_mfb environment — NDK-FPGA Docs documentation - - - - - - - - - + logic_vector_array_mfb environment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    logic_vector_array_mfb environment

    +

    logic_vector_array_mfb environment

    This environment has two high-level agents. The first one is a logic vector array agent and it works with data. The second one is a logic vector agent which works with metadata. This package contains two environments. Environment RX generates data and metadata and sends them to the DUT. Environment TX generates the DST_RDY signal and observes the TX interface.

    @@ -170,14 +240,14 @@

  • META_WIDTH

    • -

    op sequencers and sequences

    +

    op sequencers and sequences

    In the RX direction, there are two sequencers: the first is a Logic vector array sequencer that handles MFB_DATA. The second is a logic vector sequencer that handles MFB_METADATA. Both sequencers pull the data from sequences together.

    In the TX direction, there is one sequencer of type mfb::sequencer #(), which generates the DST_RDY signal.

    Both directions have two analysis_exports. One export is for the logic vector array transactions, and the second is for the logic vector (metadata) transactions.

    -

    Configuration

    +

    Configuration

    The config class has three variables.

    @@ -233,7 +303,7 @@

    Configuration -

    Low sequence configuration

    +

    Low sequence configuration

    The configuration object config_sequence contains two functions.

    @@ -255,7 +325,7 @@

    Low sequence configuration -

    RX Inner sequences

    +

    RX Inner sequences

    For the RX direction, there is one basic sequence class called the “sequence_simple_rx_base” which simplifies creating other sequences. It processes the reset signal and exports the virtual function create_sequence_item. In this function, a child can create mfb::sequence_items as they like. Another important function in the “sequence_simple_rx_base” class is try_get() which gets the required data from the base array agent. It is also important to note that the base class is state-oriented. The following table describes internal states.

    @@ -347,34 +417,78 @@

    RX Inner sequences - +
    + + Byte Array agent> + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/logic_vector_mvb/readme.html b/devel/comp/uvm/logic_vector_mvb/readme.html index 163f43152..51cea4322 100644 --- a/devel/comp/uvm/logic_vector_mvb/readme.html +++ b/devel/comp/uvm/logic_vector_mvb/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - logic_vector_mvb environment — NDK-FPGA Docs documentation - - - - - - - - - + logic_vector_mvb environment — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    logic_vector_mvb environment

    +

    logic_vector_mvb environment

    This environment convert logic_vector transaction to mvb transactions.

    The environment is configured by these four parameters: For more information see mvb documentation.

      @@ -164,13 +234,13 @@

    • ITEMS_WIDTH

    -

    Top sequencers and sequences

    +

    Top sequencers and sequences

    In the RX direction, there is one sequencer that generates logic_vector transactions. The generated transactions will be randomly ordered and then converted to MVB transactions.

    In the TX direction, there is one sequencer of type mvb::sequencer #() which generates the DST_RDY signal.

    Both environments send logic_vector transactions through the analysis_export.

    -

    Configuration

    +

    Configuration

    The config class has three variables.

    @@ -223,7 +293,7 @@

    Configuration -

    Low sequence configuration

    +

    Low sequence configuration

    The configuration object config_sequence contains one function.

    @@ -241,7 +311,7 @@

    Low sequence configuration -

    RX Inner sequences

    +

    RX Inner sequences

    For the RX direction, there is one basic sequence class called “sequence_simple_rx_base”, which simplifies creating other sequences. It processes the reset signal and exports the create_sequence_item virtual function. In this function, a child can create a mvb::sequence_item as they like.

    The environment has three sequences. The table below describes them. In the default state, the RX env runs sequence_lib_rx.

    @@ -311,34 +381,78 @@

    RX Inner sequences - +
    + + Logic Vector Array agent> + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/manual.html b/devel/comp/uvm/manual.html index dcb036898..0f735f6a3 100644 --- a/devel/comp/uvm/manual.html +++ b/devel/comp/uvm/manual.html @@ -1,52 +1,136 @@ - - - - - - - - SystemVerilog and UVM tutorial — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + SystemVerilog and UVM tutorial — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    SystemVerilog and UVM tutorial

    +

    SystemVerilog and UVM tutorial

    This is manual describes how the UVM verification in our environment should be written.

    -

    Other tutorials

    +

    Other tutorials

    This document does not serve as a general UVM or a SystemVerilog manual. Various tutorials can be found at:

      @@ -193,10 +211,10 @@

      Other tutorials -

      Basic usage of the UVM methodology in the OFM repository

      +

      Basic usage of the UVM methodology in the OFM repository

      This document describes one of the possible solutions for some common verification issues.

      -

      Interface

      +

      Interface

      An Interface creates connections between the Device Under Test(DUT) and the verification environment. If there is no serious reason to do otherwise, use wire logic instead of logic. Wire logic is a net whereas logic @@ -208,7 +226,7 @@

      Interface -

      Properties

      +

      Properties

      The DUT often communicates with its surroundings using a specific protocol which usually has some restrictions. These restrictions can be controlled by the Properties module which can be instantiated and connected to an Interface. The @@ -228,7 +246,7 @@

      Properties -

      Driver

      +

      Driver

      A Driver writes data to an Interface. It is required to use the try_get or try_next_item function to get the next item. Using the get or get_next_item function is not recommended. For example, if a Sequence uses @@ -287,7 +305,7 @@

      Driver<

    -

    Agent

    +

    Agent

    Please stick to the following rules when writing agents, environments or packages:

      @@ -354,7 +372,7 @@

      Agent

    -

    Configuration object

    +

    Configuration object

    Every agent has its own configuration object, which can modify its behavior. There are two most commonly used variables in the configuration object. The first one is the active variable which indicates whether the agent is active @@ -366,7 +384,7 @@

    Configuration objectinterface_name.

    -

    Sequence

    +

    Sequence

    The sequence contains three functions that can change the randomization output (pre_do, mid_do, post_do). Function pre_do is called before the randomization. It is suitable for changing the randomization rules. Function @@ -401,7 +419,7 @@

    Sequence

    -

    Sequence library

    +

    Sequence library

    For all agents, it is recommended to create a Sequence library that contains multiple sequences. More sequences help to uncover more bugs and it also improves coverage with small effort. The Sequence library randomly selects a @@ -514,7 +532,7 @@

    Sequence library -

    Package

    +

    Package

    In all registration macros (those are `uvm_components_* and `uvm_object_*), it is required to use a class name together with a package name, for example: `uvm_components_utils(pkg::class)

    @@ -528,7 +546,7 @@

    Package you can use it is to import the uvm_package.

    -

    Layered agents

    +

    Layered agents

    Most of the verification tests do not need to generate low-level data (i.e. individual signals). That is why there are high-level generators that can create whole packets. This allows for a packet approach and separates it from a @@ -538,7 +556,7 @@

    Layered agents -

    Environment

    +

    Environment

    The environment groups together other environments and agents in logical order. In this case, the environment groups high- and low-level agents. Required steps are:

    @@ -607,7 +625,7 @@

    Environment -

    Low-level sequence

    +

    Low-level sequence

    The purpose of the low-level sequence is to create low-level sequence_items from a high-level sequence_item. For example, we use byte_array as the high-level sequence_item and 32bit word as the low-level transaction. The following example shows @@ -647,7 +665,7 @@

    Low-level sequence -

    High-level monitor

    +

    High-level monitor

    The purpose of the high-level monitor is to create a high-level sequence_item from low-level sequence_items. Unfortunately, the general high-level monitor cannot cooperate with the low-level transaction. Therefore, the common approach @@ -688,7 +706,7 @@

    High-level monitor -

    Configuration object

    +

    Configuration object

    The environment creates one or multiple configuration objects for its subenvironments or internal agents. The following example shows how to create two configuration objects for agents which are instantiated in the current @@ -730,7 +748,7 @@

    Configuration object

    -

    Sequence library

    +

    Sequence library

    It is recommended to use a sequence library as the lower sequence. This is going to improve the coverage.

    class sequence_library extends uvm_sequence_library;
@@ -762,7 +780,7 @@ 
    Sequence library
-
    Run of a specific sequence
    
+
    Run of a specific sequence
    
 
    This example shows how to run a specific sequence on the lower sequencer in the
 environment from the Test.
    
 
    class sequence_lib extends byte_array_mfb::sequence_library;
@@ -811,7 +829,7 @@ 
    Run of a specific sequence
-
    Common environment
    
+
    Common environment
    
 
    Environment (uvm_env) puts agents, subenvironments, and other components into a
 logical unit. A common use of the environment is to connect the high-level agent
 with the low-level one. The picture below shows an Environment with two agents,
@@ -819,7 +837,7 @@ 
    Common environment
 
    
-
    Virtual sequencer
    
+
    Virtual sequencer
    
 
    A virtual sequencer connects all highest-level sequencers into one which runs a
 virtual sequence. It serves to synchronize all highest-level sequencers (so the
 agents start sending data at the same time). If the environment contains
@@ -866,11 +884,11 @@ 
    Virtual sequencer
-
    Virtual sequence and synchronization
    
+
    Virtual sequence and synchronization
    
 
    TODO
    
 
    
 
    
-
    Scoreboard
    
+
    Scoreboard
    
 
    A Scoreboard is connected to the DUT, receives transactions from it, and
 compares them with transactions received from a Model. Operations performed in a
 Model (there can be more than one) are according to the DUT’s specified
@@ -948,7 +966,7 @@ 
    Scoreboard
-
    Request-response Agents
    
+
    Request-response Agents
    
 
    Some agents may require bidirectional communications. For this purpose, the UVM
 has the Request-Response mechanism.
    
 
    For example, the read request on MI has two transactions. The first transaction
@@ -957,7 +975,7 @@ 
    Request-response Agents
 
    
 
    
-
    Reset
    
+
    Reset
    
 
    One possible solution to the problem when a reset is generated in the middle of
 the verification (not only at its start) is to use the wait task to wait for all
 required inputs. An example is provided below showing this type of the solution.
@@ -965,7 +983,7 @@ 
    Reset
 
    
 
    
-
    Scoreboard
    
+
    Scoreboard
    
 
    class scoreboard extends uvm_scoreboard;
     `uvm_component_utils(env::scoreboard)
 
@@ -990,7 +1008,7 @@ 
    Scoreboard
    
 
    
 
    
-
    Coverage
    
+
    Coverage
    
 
    Coverage is one of the essential metrics for checking a verification status.
 Coverage can tell whether the verification of the design has been done properly
 or not. Every verification should check whether its coverage is high enough. If
@@ -1027,7 +1045,7 @@ 
    Coverage
 
    
 
    
 
    
-
    Functional coverage
    
+
    Functional coverage
    
 
    Every model should contain a functional coverage to check if all of its
 functionalities have been tested (if all instances/states that could occur have
 occurred). Functional coverage can be measured in the model.
    
@@ -1056,7 +1074,7 @@ 
    Functional coverage
-
    Code coverage
    
+
    Code coverage
    
 
    In contrast to the functional coverage, code coverage reports how many lines,
 conditional jumps and expressions were checked during the verification.
    
 
    A simple metric is usually generated by the verification tool. In the OFM
@@ -1064,7 +1082,7 @@ 
    Code coverage
-
    Generating coverage reports
    
+
    Generating coverage reports
    
 
    ModelSim can generate coverage reports in the HTML format:
    
 
    coverage report -html -output cov_html -instance=/testbench/DUT_U -annotate -details -assert -directive -cvg -code bcefst -verbose -threshL 50 -threshH 90
 
    
@@ -1086,7 +1104,7 @@ 
    Generating coverage reports
-
    Verification example
    
+
    Verification example
    
 
    In this example, we introduce the MFB splitter component which divides a single
 MFB input stream into N MFB output streams. With every incoming packet on the
 MFB comes also information about the output port. That information is received
@@ -1096,7 +1114,7 @@ 
    Verification exampleThe following image shows the connections between the blocks of such verification:
    
 Verification connection
 
    
-
    Byte_array_port environment
    
+
    Byte_array_port environment
    
 
    The environment is used for grouping the byte_array and the port. The advantage of this
 approach lies in generating data for the MVB and the MFB in one roll.
    
 
    
@@ -1252,7 +1270,7 @@ 
    Byte_array_port environment
-
    Model
    
+
    Model
    
 
    Inputs and outputs of the model are implemented by the Transaction Level Model
 (TLM) in the UVM where the uvm_analysis_*, uvm_tlm_analysis_* macros are used.
    
 
    The model can have a slightly different output and input than the DUT. The reason for this
@@ -1328,7 +1346,7 @@ 
    Model
 
    
 
    
-
    Create model input fifo
    
+
    Create model input fifo
    
 
    `uvm_analysis_imp_decl(_data)
 `uvm_analysis_imp_decl(_meta)
 
@@ -1393,7 +1411,7 @@ 
    Create model input fifo
 
    
 
    
-
    Scoreboard
    
+
    Scoreboard
    
 
    class comparer_meta #(ITEM_WIDTH, META_WIDTH) extends uvm_common::comparer_base_tagged#(model_data#(ITEM_WIDTH, META_WIDTH), uvm_logic_vector::sequence_item#(META_WIDTH));
     `uvm_component_param_utils(net_mod_logic_env::comparer_meta#(ITEM_WIDTH, META_WIDTH))
 
@@ -1569,7 +1587,7 @@ 
    Scoreboard
    
 
    
 
    
-
    Test environment
    
+
    Test environment
    
 
    After creating the model and the scoreboard, we can assemble a test environment
 env. We use the byte_array_port environment, which we have created earlier,
 and the byte_array_mfb environment, which is located in the OFM repository in
@@ -1620,7 +1638,7 @@ 
    Test environment
-
    Test
    
+
    Test
    
 
    The test runs the highest level sequence and creates specific adjustments to the
 verification environment. For some tests, we want to generate a full-speed
 traffic for the MFB without any inter-frame gaps or gaps between the frames.
@@ -1682,7 +1700,7 @@ 
    Test<
 
    
 
    
 
    
-
    Properties
    
+
    Properties
    
 
    Properties contain interfacing protocol rules to which the DUT must adhere
 as well as other DUT properties.
    
 
    module mfb_splitter_properties #(OUTPUTS) (logic CLK, reset_if RESET, mfb_if RX_MFB, mvb_if RX_MFB, mfb_if TX_MFB[OUTPUTS]);
@@ -1706,7 +1724,7 @@ 
    Properties
    
 
    
 
    
-
    Testbench
    
+
    Testbench
    
 
    It is required to put the $stop() command after the run_test command. If you
 do not want to quit ModelSim after drop_objection, you must set the
 finish_on_completion variable to zero. If you set the variable
@@ -1784,13 +1802,13 @@ 
    Testbench
-
    NOTES
    
+
    NOTES
    
 
    
-
    UVM_info
    
+
    UVM_info
    
 
    Please use this macro to print information about the verification. The following table
 lists the available log levels in the UVM and the specific information they provide

    - +@@ -1823,7 +1841,7 @@

    UVM_info

    uvm_infouvm_info
    -

    UVM_error vs UVM_fatal

    +

    UVM_error vs UVM_fatal

    The difference between the UVM_error and the UVM_fatal macros is in the meaning. The UVM_fatal macro represents an error in the verification environment. For example, when an agent cannot find an interface. The @@ -1840,7 +1858,7 @@

    UVM_error vs UVM_fatal

    -

    Parametrized object

    +

    Parametrized object

    If you need a parametrized uvm_object or uvm_component, use registration macros uvm_component_param_utils and uvm_object_param_utils. Parametrized object can be required when an interface uses a signal with parametrized width.

    @@ -1864,7 +1882,7 @@

    Parametrized object -

    Synchronization

    +

    Synchronization

    The UVM provides the uvm_event class to achieve synchronization. This class offers even more functionalities, such as the standard barrier in SystemVerilog. There is also the uvm_pool, which provides access to the uvm_barrier using a @@ -1872,7 +1890,7 @@

    Synchronization -

    OFM verification environment

    +

    OFM verification environment

    When you need to create a new agent, you can get inspiration from: MVB agent. You should place all classes related to one agent or an environment into one directory. A package (pkg.sv) includes all files in that directory. It should also contain an @@ -1884,7 +1902,7 @@

    OFM verification environment
    -

    Modules.tcl

    +

    Modules.tcl

    Written in TCL language, this file contains the required components and dependencies for the package. The following command adds a package that will be compiled first. One of the commonly used packages is math_pkg.sv which @@ -1907,7 +1925,7 @@

    Modules.tcl -

    Main .fdo script for running the verification

    +

    Main .fdo script for running the verification

    This file is typically named top_level.fdo and contains the COMPONENT variable which typically holds two items:

      @@ -1954,34 +1972,131 @@

      Main .fdo script for running the verification

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - + + +
    +
    +
    +
    +
    + + + <UVM Verification + +
    + +
    + + UVM simulation> + +
    -
    - -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/mfb/readme.html b/devel/comp/uvm/mfb/readme.html index 7f0a8e7b9..1e23bbfda 100644 --- a/devel/comp/uvm/mfb/readme.html +++ b/devel/comp/uvm/mfb/readme.html @@ -1,52 +1,136 @@ - - - - - - - MFB Agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + MFB Agent — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MFB Agent

    +

    MFB Agent

    This agent is responsible for the communication through the MFB interface. This is a low level agent which generates only simple MFB words. For advanced control use the byte_array_mfb.

    The environment is configured by five parameters: For more information see mfb documentation.

    @@ -181,7 +254,7 @@
    -

    sequence_item

    +

    sequence_item

    This package containst two agents. RX agents send data to DUT. Sequence run in RX agent generate ITEMS, META, SOF_POS, EOF_POS, EOF, SOF, SRC_RDY variables in sequence_item. Driver after clock cycle set DST_RDY variable in sequence_item as response. TX agent is reciving data from DUT. There is required to generate DST_RDY and driver after clock cycle set ITEMS, META, SOF_POS, EOF_POS, EOF, SOF, SRC_RDY as response.

    @@ -224,34 +297,75 @@

    sequence_item

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MVB agent + +
    - +
    + + MI agent> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/mi/readme.html b/devel/comp/uvm/mi/readme.html index ce6257ca7..e2f13b1f3 100644 --- a/devel/comp/uvm/mi/readme.html +++ b/devel/comp/uvm/mi/readme.html @@ -1,52 +1,136 @@ - - - - - - - MI agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + MI agent — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MI agent

    +

    MI agent

    This package contains two UVM verification agents which generate transactions to the :ref:MI<mi_bus> interface. The slave agent is connected to the slave DUT port but acts as the master of this communication (the slave agent generates the requests for the DUT). The master agent is connected to the master DUT port but acts as the slave of this communication (it accepts the requests from the DUT). Both agents have three class parameters. DATA_WIDTH , ADDR_WIDTH and META_WIDTH. META_WIDTH has default value set to 0.

    ../../../_images/MI_agent.svg
    -

    Sequence_item

    +

    Sequence_item

    There are two sequence items. The sequence_item_request is for generating requests, and the sequence_item_response is for responses.

    Sequence_item_request

    @@ -288,34 +361,75 @@

    Sequence_item - +
    + + PMA agent> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/mvb/readme.html b/devel/comp/uvm/mvb/readme.html index 50f27f950..42e95b3ad 100644 --- a/devel/comp/uvm/mvb/readme.html +++ b/devel/comp/uvm/mvb/readme.html @@ -1,52 +1,136 @@ - - - - - - - MVB agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + MVB agent — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    MVB agent

    +

    MVB agent

    -

    Interface

    +

    Interface

    MVB interface is simple interface which is composed of signals below.

    @@ -196,13 +263,13 @@

    Interface -

    Sequence item

    +

    Sequence item

    Sequence item have same signals as interface accept for DATA. In the DATA is saved all items in the array. There is ITEMS’s logic vector items with width of ITEM_WIDTH.

    All of those signals are randomized. There also are overridden UVM functions(“do_compare”, “do_copy” and “convert2string”).

    -

    Sequence

    +

    Sequence

    There is req which is instance of sequence_item. There are 2 unsigned integers max_transaction_count and min_transaction_count. Last variable is randomized transaction_count. This variable is randomized in range of <max_transaction_count, min_transaction_count>.

    There are 2 sequences. One for RX and one for TX. This is because TX, and RX behave differently. @@ -210,53 +277,100 @@

    Sequence

    Because of this there is one bit variable next_action. This bit decide on contents of actual req based on previous sequence item.

    -

    Driver

    +

    Driver

    The driver gets sequence_item from sequence and assign corresponding signals to interface.

    Because of behaviour described above there are also 2 drivers. One for RX and one for TX. The RX driver have to also create response and sand it back to sequence.

    -

    Monitor

    +

    Monitor

    Monitor just waiting for monitor clocking block and than sample values at interface. And at the end he write this sample to the analysis port.

    -

    Config

    +

    Config

    In the config 2 variables. First is active that decides if the driver and sequencer will be created. And the second one is interface_name.

    -

    Agent

    +

    Agent

    There are also 2 agents. Agent only connect everything together.

    - +
    - +
    + + MFB Agent> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/packet_generators/flowtest/readme.html b/devel/comp/uvm/packet_generators/flowtest/readme.html index 1df6d433d..50057f320 100644 --- a/devel/comp/uvm/packet_generators/flowtest/readme.html +++ b/devel/comp/uvm/packet_generators/flowtest/readme.html @@ -1,52 +1,136 @@ - - - - - - - FlowTest Sequence — NDK-FPGA Docs documentation - - + + + + - - - - - - + FlowTest Sequence — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    FlowTest Sequence

    +

    FlowTest Sequence

    FlowTest Sequence uses FlowTest ft-generator to generate and run a PCAP file based on configuration and profile. The configuration and profile are described in the FlowTest ft-generator repository.

    -

    Sequence parameters

    +

    Sequence parameters

    -

    Configuration generation

    +

    Configuration generation

    • generated_config is an on/off switch determining whether the sequence will generate a new configuration file located at config_filepath or use a user-provided file at config_filepath.

    @@ -210,7 +282,7 @@

    Configuration generation -

    Profile generation

    +

    Profile generation

    • generated_profile is an on/off switch determining whether the sequence will generate a new profile file located at profile_filepath or use a user-provided file at profile_filepath.

    @@ -249,13 +321,13 @@

    Profile generation -

    Example configurations

    +

    Example configurations

    Note

    Parameters in a JSON configuration are case-insensitive and can be provided in any order.

    -

    Configuration generator configuration

    +

    Configuration generator configuration

    {
   "MANDATORY_IPv4_ADDRESS_RANGES": [
     "1.1.1.1/1",
@@ -271,7 +343,7 @@ 
    Configuration generator configuration
-
    Profile generator configuration
    
+
    Profile generator configuration
    
 
    {
   "START_TIME_MIN": 412,
   "PACKETS_REV_MIN_NUMBER": 10,
@@ -285,34 +357,84 @@ 
    Profile generator configuration
    
           
    
-
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <logic_vector_array_axi environment + +
    - +
    + + AVMM Agent> + +
    -
    -
    -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/pma/readme.html b/devel/comp/uvm/pma/readme.html index 0d9f282cc..0c8c53965 100644 --- a/devel/comp/uvm/pma/readme.html +++ b/devel/comp/uvm/pma/readme.html @@ -1,52 +1,136 @@ - - - - - - - PMA agent — NDK-FPGA Docs documentation - - + + + + - - - - - - + PMA agent — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    PMA agent

    +

    PMA agent

    Agent is used for connecting of all components (driver, monitor,…). Agent has his own configuration object which contains two parameters: active (when is up then agent is active in other way is passive) and interface which say name of the interface that is used. When agent is active then sequencer and driver are created amd connected to interface. When is passive then only monitor is created.

    -

    PMA interface

    +

    PMA interface

    PMA (Physical Medium Attachment) bus is proprietary interface which is connected to tranascievers. Main task of this interface is took data from encoder, scramble them and send it to tranasciever. There could be two types of data (depends on header), control data or usable data. On this interface are encoded data from encoder, this data could have this formats:

    -

    PMA bus description

    +

    PMA bus description

    PMA bus has these 5 ports which will be described below.

    -

    Generics

    +

    Generics

    @@ -192,7 +262,7 @@

    Generics

    Name

    -

    Ports

    +

    Ports

    @@ -232,7 +302,7 @@

    Ports
    -

    PMA sequence item

    +

    PMA sequence item

    Sequence item contains basic ports from interface. All signals which are in sequence item are randomized. There are three methods:

      @@ -242,44 +312,93 @@

      PMA sequence item -

      PMA monitor

      +

      PMA monitor

      PMA monitor is used for monitoring of traffic. There is only easy monitor which write whole transaction to analysis port.

    -

    PMA driver

    +

    PMA driver

    PMA driver is used for driving PMA transactions to interface.

    - +
    - +
    + + Intel MAC SEG> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/probe/readme.html b/devel/comp/uvm/probe/readme.html index 0c0da6169..22bbfe2bc 100644 --- a/devel/comp/uvm/probe/readme.html +++ b/devel/comp/uvm/probe/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - probe agent — NDK-FPGA Docs documentation - - - - - - - - - + probe agent — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    probe agent

    +

    probe agent

    The purpose of this agent is to get information from the tested design. That information is commonly used in models to correct generated output. For example, to check the correct time when some pipelines in DUT are disabled or to change some rules for dropping packets.

    -

    Interface

    +

    Interface

    The interface has one parameter and three signals. The parameter defines the width of the data signal. Signal event_signal is connected to a trigger. Signal event_data is connected to collected data. The last signal CLK is a clock. The trigger is evaluated when there is a rising edge of the clock.

    interface probe_inf #(int unsigned DATA_WIDTH) (
     input wire logic event_signal,
@@ -171,7 +242,7 @@ 
    Interface
-
    Bind
    
+
    Bind
    
 
    The bind command creates an instance of an interface directly in a component. The bind command is divided into several parts. The first is a component name. The second is a path to the component. probe_inf is an interface name. probe_status is a bind name. The interface has three parameters. The first is a trigger. The second is sampled data. When the trigger is fired, data is sampled. The last parameter is a clock. All parameters are connected to the internal signals in a bound component.
    
 
    // entity name : path to entity  probe_if #(DATA_WIDTH) ( trigger , data , CLOCK)
 bind FIFOX : VHDL_DUT_U probe_inf #(2) probe_status((RESET === 1'b0), { wr_en, rd_en }, CLK);
@@ -179,7 +250,7 @@ 
    Bind<
    -

    Callback

    +

    Callback

    The callback is called when there is a rising edge of the clock and the trigger is activated. The data is sampled at this point.

    Callback class definition

    class cbs_simple #(int unsigned DATA_WIDTH) extends uvm_event_callback;
@@ -249,34 +320,77 @@ 
    Callback
    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <AVST CRDT Agent + +
    - +
    + + LBUS Agent> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/reset/readme.html b/devel/comp/uvm/reset/readme.html index 4bae0b6bd..7c678d788 100644 --- a/devel/comp/uvm/reset/readme.html +++ b/devel/comp/uvm/reset/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - RESET agent — NDK-FPGA Docs documentation - - - - - - - - - + RESET agent — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    RESET agent

    +

    RESET agent

    This agent generate one bit signal which is never have undefined value. Primary use of this agent is generating reset signal in verification.

    Package containt two major sequences.

    sequence_simple - fist n random cicles generate reset and next m random cicles generates no reset. This pattern is repeating until end of simulation. @@ -204,7 +277,7 @@

    -

    simple sychronous RESET agents

    +

    simple sychronous RESET agents

    enviroment env#(RESETS) contain RESETS number of reset agents which generate synchronous reset for asynchronous clock domain. Synchronization mechanism is realy simple and cannot be used everyvhere. All resets agent read one value which is change ones per specified time. Time is specified in class env_config_item#(RESETS) in variable driver_delay. User have to setup up time to two times maximum of slowest reset time multiple of slowest clock. 2*max(CLK[it]*RESET_TIME[it]). Enviroment work as agent. You can run any sequence on enviroment seqeuencer which can be ran on agent sequencer

    @@ -213,34 +286,75 @@

    simple sychronous RESET agents

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Components + +
    - +
    + + Logic vector agent> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/comp/uvm/sim_manual.html b/devel/comp/uvm/sim_manual.html index 4d20e400f..f6cf8cbd2 100644 --- a/devel/comp/uvm/sim_manual.html +++ b/devel/comp/uvm/sim_manual.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - UVM simulation — NDK-FPGA Docs documentation - - - - - - - - - + UVM simulation — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    UVM simulation

    +

    UVM simulation

    UVM simulation is a tool that can be used by FW developers to create baseline tests for their components. This section will explain how to create a UVM simulation.

    -

    Examples

    +

    Examples

    This section contains examples of the UVM simulation. Every example is located in the uvm_sim folder. All examples contain only the most necessary files (UVM components). @@ -139,7 +207,7 @@

    Examples The following three examples are for the most commonly used combinations of interfaces: MFB + MI, MVB + MI, and MFB + META/MVB. The following subsections will describe what the sequences look like and how to modify them to use them for another component.

    -

    MFB + MI

    +

    MFB + MI

    The first example is a simulation of the Speed Meter component that uses MFB and MI interfaces. There are two sequences in the sequence_tb.sv file, sequence_mi.sv for the MI interface and sequence_mfb_data.sv for the MFB interface. The first one inherits from the sequence_mi_sim, which is located in the uvm_mi pkg (for more information see, the UVM MI documentation). @@ -231,7 +299,7 @@

    MFB + MI

    -

    MFB + META/MVB

    +

    MFB + META/MVB

    The second example is a simulation of the Dropper component that uses the MFB interface with metadata. There are two sequences in the sequence_tb.sv file, sequence_mfb_data.sv for the MFB interface and sequence_meta.sv for metadata. The first one is the same as in the previous example, and the second one generates random metadata and drop signal. @@ -272,7 +340,7 @@

    MFB + META/MVB -

    MVB + MI

    +

    MVB + MI

    The last example is a simulation of the Lookup Table component that uses MVB interface with MI. There are two sequences in the sequence_tb.sv file, sequence_mvb_data.sv for the MVB interface and sequence_mi.sv for the MI interface. The first one generates data for MVB transactions. @@ -322,7 +390,7 @@

    MVB + MI

    -

    How to use the UVM simulation

    +

    How to use the UVM simulation

    So that was a brief description with a few examples. Now, if you want to use these examples for a component of your choice, here is a list of steps you have to do:

      @@ -346,34 +414,81 @@

      How to use the UVM simulation - +
      + + Components> + +
      - -

    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ctrls.html b/devel/ctrls.html index 2167349c3..f0e7dfea3 100644 --- a/devel/ctrls.html +++ b/devel/ctrls.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Controllers & TSU — NDK-FPGA Docs documentation - - - - - - - - - + Controllers & TSU — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
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    - -
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    -
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    - +
    + +
    +
    +
    +
    +
    -

    Controllers & TSU

    +

    Controllers & TSU

    This chapter describes the different variants of controllers and TimeStamp Unit (TSU). The controllers are typically located in the comp/ctrls/ directory in the OFM repository. The TSU modules are typically located in the comp/tsu/ directory in the OFM repository.

    @@ -127,34 +205,52 @@

    Controllers & TSU

    -
    +
    +
    +
    +
    + + + <Pulse short + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + SDM CLIENT> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/debug.html b/devel/debug.html index dd4058173..35bff56d1 100644 --- a/devel/debug.html +++ b/devel/debug.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Debug Tools — NDK-FPGA Docs documentation - - - - - - - - - + Debug Tools — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Debug Tools

    +

    Debug Tools

    This chapter describes the general components for debugging and testing. For example, here is a description of a component that allows you to test external DDR4 memory on an Intel FPGA. The components are typically located in the comp/debug/ directory in the OFM repository.

    @@ -133,34 +211,52 @@

    Debug Tools

    -
    +
    +
    +
    +
    + + + <Software Manager + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + DDR4 Memory Tester> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/dsp.html b/devel/dsp.html index be5f335c3..f7650d6c1 100644 --- a/devel/dsp.html +++ b/devel/dsp.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - DSP components — NDK-FPGA Docs documentation - - - - - - - - - + DSP components — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
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    DSP components

    +

    DSP components

    This page provides overview of components using DSP as a accelerating element.

    -
    +
    -
    +
    +
    +
    +
    + + + <FIFOX Multi + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + DSP Comparator> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/fifo.html b/devel/fifo.html index 336c23779..5ad17aab4 100644 --- a/devel/fifo.html +++ b/devel/fifo.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - FIFO components — NDK-FPGA Docs documentation - - - - - - - - - + FIFO components — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
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    -
    - -
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    + +
    +
    +
    +
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    FIFO components

    +

    FIFO components

    -

    Dual clock (asynchronous) FIFOs

    -

    ASFIFO - Behavioral dual clock FIFO implementation based on LUTMEMs and optimized for Xilinx only. Include status signal. OBSOLETE, use ASFIFOX!

    -

    ASFIFO_BRAM - Behavioral dual clock FIFO implementation based on BRAMs and optimized for Xilinx only. Include status signal. OBSOLETE, use ASFIFOX!

    +

    Dual clock (asynchronous) FIFOs

    +

    ASFIFO - Behavioral dual clock FIFO implementation, based on LUTMEMs and optimized for Xilinx only. Includes status signal.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use ASFIFOX instead.

    +
    +
    +

    ASFIFO_BRAM - Behavioral dual clock FIFO implementation, based on BRAMs and optimized for Xilinx only. Includes status signal.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use ASFIFOX instead.

    +
    +

    ASFIFO_BRAM_BLOCK - Similar to ASFIFO_BRAM but with extra signal to mark end of input data block, output remains in empty state until such mark is received. Located in the same folder as ASFIFO_BRAM.

    ASFIFO_BRAM_RELEASE - Similar to ASFIFO_BRAM but contains two extra signals, one (MARK) is used for detecting end of input data blocks and second (DRELEASE) says that there is possibility of releasing the last data block. @@ -148,22 +229,46 @@

    FIFO components -

    Single clock FIFOs

    -

    FIFO - Behavioral FIFO implementation based on LUTMEMs and optimized for Xilinx only. Include status signal. OBSOLETE, use FIFOX!

    -

    FIFO_BRAM - Behavioral FIFO implementation based on BRAMs and optimized for Xilinx only. Include status signal. OBSOLETE, use FIFOX!

    +

    Single clock FIFOs

    +

    FIFO - Behavioral FIFO implementation, based on LUTMEMs and optimized for Xilinx only. Includes status signal.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use FIFOX instead.

    +
    +
    +

    FIFO_BRAM - Behavioral FIFO implementation, based on BRAMs and optimized for Xilinx only. Includes status signal.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use FIFOX instead.

    +
    +

    FIFO_BRAM_XILINX - Structural implementation of FIFO based on Xilinx specific BRAM FIFO primitives (no extra logic). Include almost full and almost empty signal.

    -

    FIFO_N1 - Behavioral implementation of FIFO with multiple write ports, it based on LUTMEMs and optimized for Xilinx only. OBSOLETE, use FIFOX_MULTI!

    +

    FIFO_N1 - Behavioral implementation of FIFO with multiple write ports, it is based on LUTMEMs and optimized for Xilinx only.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use FIFOX instead.

    +
    +

    FIFOX - Universal FIFO for Xilinx and Intel FPGAs. It support various memory implementation: LUTMEMs, BRAMs, URAMs (Xilinx only) and shift-registers in LUT slices (effective on Xilinx only). Include almost full, almost empty and status signal. Possible automatic selection of a suitable memory implementation. Detailed documentation can be found here.

    FIFOX_MULTI - Universal FIFO based on FIFOX, which allows multiple write and read requests in each cycle. Detailed documentation can be found here.

    MULTI_FIFO - Behavioral implementation of FIFO for Xilinx and Intel FPGAs with multiple independent channels. It support various memory implementation: LUTMEMs, BRAMs, URAMs (Xilinx only). The memory type is selected automatically.

    -

    SH_FIFO - Behavioral FIFO implementation based on shift-registers in LUT slices and optimized for Xilinx only. OBSOLETE, use FIFOX!

    +

    SH_FIFO - Behavioral FIFO implementation, based on shift-registers in LUT slices and optimized for Xilinx only.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use FIFOX instead.

    +
    +
    -

    References

    +

    References

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Live value table memory + +
    - +
    + + ASFIFOX> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/fl.html b/devel/fl.html index c3645650d..9a73df2c3 100644 --- a/devel/fl.html +++ b/devel/fl.html @@ -1,50 +1,134 @@ - - - - - - - - FL Tools — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + FL Tools — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    FL Tools

    +

    FL Tools

    This chapter contains the specifications of the FL bus and a description of the components that use FL bus. Components using the FL bus are typically located in the comp/fl_tools/ directory in the OFM repository.

    @@ -115,31 +193,42 @@

    FL Tools

    -
    +
    -
    -
    -
    -
    - - - + +
    + +
    +
    +
    + +
    + +
    + +
    +
    +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/flu.html b/devel/flu.html index 48469fcad..0768313e9 100644 --- a/devel/flu.html +++ b/devel/flu.html @@ -1,50 +1,134 @@ - - - - - - - - FLU Tools — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + FLU Tools — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    FLU Tools

    +

    FLU Tools

    This chapter contains the specifications of the FLU bus and a description of the components that use FLU bus. Components using the FLU bus are typically located in the comp/flu_tools/ directory in the OFM repository.

    @@ -119,31 +197,42 @@

    FLU Tools

    -
    -
    -
    -
    - - - + +
    + +
    +
    +
    + +
    + +
    + +
    +
    +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/genindex.html b/devel/genindex.html index 2f935acd7..e8ec30daf 100644 --- a/devel/genindex.html +++ b/devel/genindex.html @@ -1,49 +1,133 @@ - - - - - - - Index — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + Index — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    -
      -
      • -
    • Index
      • -
    • -
      • -
    -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +

    Index

    @@ -112,31 +191,42 @@

    Index

    -
    +
    -
    - -
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    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - -
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    - - - + +
    + +
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    +
    + +
    + +
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    +
    +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/index.html b/devel/index.html index b3180c884..23835bae4 100644 --- a/devel/index.html +++ b/devel/index.html @@ -1,51 +1,135 @@ + + + + + - - - - - - - Documentation of Minimal NDK Application — NDK-FPGA Docs documentation - - - - - - - - - + Overview — NDK-FPGA documentation + + + + + + - - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - -
    -

    Documentation of Minimal NDK Application

    -

    Welcome to documentation of Minimal NDK Application!

    -

    The NDK-APP-Minimal is a reference application based on the Network Development Kit (NDK) for FPGAs. The NDK allows users to quickly and easily develop FPGA-accelerated network applications. The NDK is optimized for high throughput and scalability to support up to 400 Gigabit Ethernet.

    -_images/liberouter_logo.svg - -

    The NDK-based Minimal application is a simple example of how to build an FPGA application using the NDK. It can also be a starting point for your NDK-based application. The NDK-based Minimal application does not process network packets in any way; it only sends and receives them. If the DMA IP is enabled (see the DMA Module chapter), then it forwards the network packets to and from the computer memory.

    -
    -

    Warning

    -

    The DMA Medusa IP is not part of the open-source NDK. You can get the NDK, including the DMA Medusa IP and professional support, through our partner BrnoLogic.

    -
    -
    +
    +

    Bus Specifications

    +
    +
    +

    The NDK supports a wide range of FPGA cards, providing access to features such as DDR and HBM +memories, PCIe, and Ethernet in your applications. However, different applications may only +support a subset of these cards. A complete list of supported FPGA cards can be found below +(minimal app supports all of them).

    +

    Supported Cards

    +
    -
    +
    +

    NDK provides two implementations of DMA IPs:

    +
      +

    • DMA Medusa

      • +

    • DMA Calypte

      • +
    +

    DMA Medusa is a state-of-the-art DMA module that supports up to 400Gbps of throughput to +host memory. DMA Calypte is an open-source low-latency DMA supporting throughput up +to tens of Gigabits per second. However, the DMA Calypte is still under development +and is not yet officially released (stay tuned).

    +
    +

    Warning

    +

    The DMA Medusa IP is not included in the open-source version of the NDK. You can obtain the full NDK package, including DMA Medusa IP and professional support, from our partner BrnoLogic.

    +_images/liberouter_logo.svg +
    -
    +
    -
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    +
    + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + How to start> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/logic.html b/devel/logic.html index 8df84c316..c5af7e281 100644 --- a/devel/logic.html +++ b/devel/logic.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Basic logic elements — NDK-FPGA Docs documentation - - - - - - - - - + Basic logic elements — NDK-FPGA documentation + + + + + + - - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Basic logic elements

    +

    Basic logic elements

    AFTER_ONE - The unit sets all output bits to high if they have a higher index than the first one in the input vector. Example: DI=”00100000” => DO=”11000000”.

    ALU - ALU implementation based on Xilinx 7-Series DSP slices.

    AND - Behavioral implementation of generic AND.

    @@ -179,34 +255,52 @@

    Basic logic elements -

    +
    -
    +
    +
    +
    +
    + + + <DSP Comparator + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + N_LOOP_OP> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/memory.html b/devel/memory.html index ac9a2a084..fd0b73705 100644 --- a/devel/memory.html +++ b/devel/memory.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Memory modules — NDK-FPGA Docs documentation - - - - - - - - - + Memory modules — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Memory modules

    +

    Memory modules

    CAM - Ternary content addressable memory implemented in memory LUTs, optimized for Xilinx only. Also there is light variant implemented using register array, simpler but less effective.

    -

    DP_BMEM - Behavioral implementation of dual clock BRAM memory with two read/write port. OBSOLETE, use DP_BRAM or DP_BRAM_XILINX!

    -

    DP_BMEM_V7 - Structural implementation of dual clock BRAM memory based on Virtex 7 specific primitives with two read/write ports. OBSOLETE, use DP_BRAM or DP_BRAM_XILINX!

    +

    DP_BMEM - Behavioral implementation of dual clock BRAM memory with two read/write ports.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use DP_BRAM or DP_BRAM_XILINX instead.

    +
    +
    +

    DP_BMEM_V7 - Structural implementation of dual clock BRAM memory based on Virtex 7 specific primitives with two read/write ports.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use DP_BRAM or DP_BRAM_XILINX instead.

    +
    +

    DP_BRAM - Behavioral implementation of single clock BRAM memory with two read/write port. Optimized for Xilinx and Intel FPGAs.

    DP_BRAM_XILINX - Structural implementation of dual clock BRAM memory based on Xilinx specific primitives with two read/write ports. Only for Xilinx FPGAs.

    DP_URAM_XILINX - Structural implementation of single clock URAM memory based on Xilinx specific primitives with two read/write ports. Only for Xilinx UltraScale+ FPGAs.

    @@ -142,28 +229,45 @@

    Memory modulesOBSOLETE, use DP_BRAM or DP_BRAM_XILINX!

    +

    SDP_BMEM - Behavioral implementation of dual clock BRAM memory with one read port and one write port. Located in the same folder as DP_BMEM.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use DP_BRAM or DP_BRAM_XILINX instead.

    +
    +

    SDP_BMEM_V7 - Structural implementation of dual clock BRAM memory based on Virtex 7 specific primitives with one read port and one write port. -Located in the same folder as DP_BMEM_V7. OBSOLETE, use SDP_BRAM or SDP_BRAM_XILINX!

    +Located in the same folder as DP_BMEM_V7.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use DP_BRAM or DP_BRAM_XILINX instead.

    +
    +

    SDP_BRAM - Structural implementation of dual clock BRAM memory based on Xilinx and Intel specific primitives (xpm_memory_sdpram, altera_syncram) with one read port and one write port. It supports the byte enable feature!

    -

    MP_BRAM - Generic multiported single clock BRAM memory based on SDP_BRAM. Currently supports only 1 write port. Amount of read ports is not restricted. Also supports byte enable -feature.

    -

    LVT_MEM - Multiported memory implemented suitable for shallow memories, supports generic amount of write/read ports and has customizable read during write behaviour.

    +

    MP_BRAM - Generic multi-port single-clock BRAM memory based on SDP_BRAM.

    +

    LVT_MEM - Multi-port memory is suitable for shallow memories, supports a generic amount of write/read ports, and has customizable read during write behavior.

    SDP_BRAM_BEHAV - Another behavioral implementation of dual clock BRAM memory with one read port and one write port. -Located in the same folder as SDP_BRAM. OBSOLETE, use DP_BRAM or DP_BRAM_XILINX!

    +Located in the same folder as SDP_BRAM.

    SDP_BRAM_XILINX - Structural implementation of dual clock BRAM memory based on Xilinx specific primitives with one read port and one write port. Only for Xilinx FPGAs.

    SDP_MEMX - Universal behavioral implementation of single clock memory with one read port and one write port. Allows setting type of memory (LUT, BRAM, URAM) or automatic mode. Optimized for Xilinx and Intel FPGAs.

    SDP_URAM_XILINX - Structural implementation of single clock URAM memory based on Xilinx specific primitives with one read port and one write port. Only for Xilinx UltraScale+ FPGAs.

    -

    SP_BMEM - Old behavioral implementation of single clock BRAM memory with one read/write port. OBSOLETE, use SP_BRAM or SP_BRAM_XILINX!

    +

    SP_BMEM - Old behavioral implementation of a single-clock BRAM memory with one read/write port.

    +
    +

    Warning

    +
    +

    Deprecated since version 0.7.0: This component is obsolete and is a candidate for removal, use SP_BRAM or SP_BRAM_XILINX instead.

    +
    +

    SP_BRAM - Behavioral implementation of single clock BRAM memory with one read/write port. Optimized for Xilinx and Intel FPGAs.

    SP_BRAM_XILINX - Structural implementation of single clock BRAM memory based on Xilinx specific primitives with one read/write port. Only for Xilinx FPGAs.

    SP_URAM_XILINX - Structural implementation of single clock URAM memory based on Xilinx specific primitives with one read/write port. Only for Xilinx UltraScale+ FPGAs.

    -

    References

    +

    References

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Asynchronous modules + +
    - +
    + + NP LUT RAM> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/mfb.html b/devel/mfb.html index c18df476c..4d4f271a3 100644 --- a/devel/mfb.html +++ b/devel/mfb.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - MFB Tools — NDK-FPGA Docs documentation - - - - - - - - - + MFB Tools — NDK-FPGA documentation + + + + + + - + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    MFB Tools

    +

    MFB Tools

    This chapter contains the specifications of the MFB bus and a description of the components that use MFB bus. The MFB bus was developed to support multiple packets in one clock cycle. Components using the MFB bus are typically located in the comp/mfb_tools/ directory in the OFM repository.

    Content:

    -
    +
    +
    +
    +
    + + + <MI2AXI4 + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MFB Reconfigurator> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/mi.html b/devel/mi.html index 3e95bc5da..0edbddfb0 100644 --- a/devel/mi.html +++ b/devel/mi.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - MI Tools — NDK-FPGA Docs documentation - - - - - - - - - + MI Tools — NDK-FPGA documentation + + + + + + - + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    MI Tools

    +

    MI Tools

    This chapter contains the specifications of the MI bus and a description of the components that use MI bus. Components using the MI bus are typically located in the comp/mi_tools/ directory in the OFM repository.

    Content:

    -
    +
    -
    +
    +
    +
    +
    + + + <TSU GEN + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MI ASYNC> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/misc.html b/devel/misc.html index ca9ac11ae..569acd78b 100644 --- a/devel/misc.html +++ b/devel/misc.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Miscellaneous — NDK-FPGA Docs documentation - - - - - - - - - + Miscellaneous — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Miscellaneous

    +

    Miscellaneous

    ADC_SENSORS - Controller of the Temperature and Voltage ADC IPs for Intel Stratix 10 FPGA. It is controlled via the MI bus. CANDIDATE FOR MOVE to CTRLs folder!

    CLK_GEN - Old clock generator, is used in some simulation only. CANDIDATE FOR REMOVAL!

    CROSSBARX - This unit performs data transfer between two buffers connected on SRC_BUF and DST_BUF interfaces based on Transactions passed on the TRANS interface. @@ -154,34 +230,52 @@

    Miscellaneous

    -
    +
    +
    +
    +
    + + + <H3 Class Hash + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + CrossbarX> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/mvb.html b/devel/mvb.html index d7f83e0bb..a924bd5e5 100644 --- a/devel/mvb.html +++ b/devel/mvb.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - MVB Tools — NDK-FPGA Docs documentation - - - - - - - - - + MVB Components — NDK-FPGA documentation + + + + + + - + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - -
    -

    MVB Tools

    +
    + +
    +
    +
    +
    + +
    +

    MVB Components

    This chapter contains the specifications of the MVB bus and a description of the components that use MVB bus. The MVB bus was developed to support multiple items/values in one clock cycle. Components using the MFB bus are typically located in the comp/mvb_tools/ directory in the OFM repository.

    Content:

    -
    +
    +
    +
    +
    + + + <MFB Generator + +
    -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + MVB Channel Router> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_build/readme.html b/devel/ndk_build/readme.html index 076afd69c..8428dd0b1 100644 --- a/devel/ndk_build/readme.html +++ b/devel/ndk_build/readme.html @@ -1,102 +1,169 @@ - - - - - - - Build System — NDK-FPGA Docs documentation - - + + + + - - - - - - + Build System — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Build System

    +

    Build System

    This build system has been developed for easier implementation and simulation of the large projects and individual components as well. The main idea is based on the uniform definition of components hierarchy, @@ -157,7 +196,7 @@ The Tcl language is independent of target operation system and it is supported in the most of tools dedicated for hardware developement.

    -

    Hierarchy description in Modules.tcl

    +

    Hierarchy description in Modules.tcl

    The objective of hierarchy description is to define a structure of complex projects. Generally, a project is composed of several components and a component is recursively composed of several subcomponents and @@ -175,7 +214,7 @@

    Hierarchy description in Modules.tclCOMPONENTS variable specifies the subcomponent list of the component.

    -

    Variables in Modules.tcl obtained by the build system

    +

    Variables in Modules.tcl obtained by the build system

    • PACKAGES defines the list of VHDL files, which serve as packages. These packages are usually used at the begining of VHDL files using command @@ -223,7 +262,7 @@

      Variables in Modules.tcl obtained by the build system

    -

    PLATFORM_TAGS

    +

    PLATFORM_TAGS

    In the situation, when a platform (build tool: Quartus, Vivado, simulator: Questa Sim, etc.) supports various architectures / implementation schemes, the PLATFORM_TAGS list variable can be used to distinguish, which source file should be included into project.

    List of available platforms:

    @@ -238,7 +277,7 @@

    PLATFORM_TAGS -

    Priority for PLATFORM_TAGS

    +

    Priority for PLATFORM_TAGS

    The PLATFORM_TAGS list can be potentially used also for specifying preference/priority (latter position in list means higher priority): set PLATFORM_TAGS "xilinx:bram:behav xilinx:bram:macro" The priority can be easily overriden simply by appending item to the list. @@ -253,7 +292,7 @@

    Priority for PLATFORM_TAGS -

    List of properties used in MOD variables

    +

    List of properties used in MOD variables

    For translation, it is often required to specify more of the details about items (files) present in MOD and PACKAGES variables. In this case the translation system can get a list with property name and value pairs instead of a single item, e.g.:

    @@ -277,7 +316,7 @@

    Priority for PLATFORM_TAGSvsim -L extra_library testbench

    -

    Example of using properties

    +

    Example of using properties

    lappend MOD [list $ENTITY_BASE/dp_bmem_behav.vhd VIVADO_SET_PROPERTY [list -quiet FILE_TYPE {VHDL}]] ;# set the VHDL98 standard for this file
 lappend MOD [list "$ENTITY_BASE/bus_handshake.xdc" TYPE "CONSTR_VIVADO" SCOPED_TO_REF "ASYNC_BUS_HANDSHAKE" PROCESSING_ORDER "LATE"]
    @@ -285,13 +324,13 @@

    Example of using properties -

    List of properties used in SV_LIBS

    +

    List of properties used in SV_LIBS

    • MAKE_PARAMS - value will be passed to make command as the parameters

    -

    Example of using Modules.tcl variables

    +

    Example of using Modules.tcl variables

    # HFE top level entity
 if {$ENTITY == "HFE_TOP"} {
    if {$ARCHGRP == "FULL"} {
@@ -326,14 +365,14 @@ 
    Example of using Modules.tcl variables
-
    Component synthesis
    
+
    Component synthesis
    
 
    Synthesis of the component is typically handled by a simple user-created Makefile.
 It can be located anywhere, but the recommendation is to use the synth subdirectory of the synthesized component.
 The Makefile sets the TOP_LEVEL_ENT variable and calls the comp target
 from global Makefile located in $OFM_PATH/build/Makefile, which must be included.
 After calling make the synthesis will be performed.
    
 
    
-
    Advanced synthesis configuration
    
+
    Advanced synthesis configuration
    
 
    User can specify those variables in Makefile:
    
 
 
    
-
    Example of Makefile for component synthesis
    
+
    Example of Makefile for component synthesis
    
 
    TOP_LEVEL_ENT=RX_MAC_LITE
 TOP_LEVEL_PATH=../../mac/rx
 
@@ -371,7 +410,7 @@ 
    Example of Makefile for component synthesis
-
    The comp target in Makefile
    
+
    The comp target in Makefile
    
 
    The make comp runs the comp_$(SYNTH).tcl script located in $OFM_PATH/build/targets/ with the synthesis tool.
 Script sets some default values for mandatory variables and fetches environment variables listed above.
 The script also tries to source Vivado.inc.tcl / Quartust.inc.tcl file (if it exists) in a current directory.
@@ -384,7 +423,7 @@ 
    Example of Makefile for component synthesis
-
    Chip design synthesis and implementation
    
+
    Chip design synthesis and implementation
    
 
    It is a good practice to split common functionality from application specific functionality:
    
 
      
 
    1. top-level entity of card together with main constraints and build scripts,
      2. 
@@ -398,36 +437,36 @@ 
      Chip design synthesis and implementationnb_main procedure, which passes to SynthesizeProject procedure within target_default similarly as in the comp target.
      
 
    
 
    
-
    SynthesizeProject
    
+
    SynthesizeProject
    
 
    
-
    1. Init phase (SetupDesign)
    
+
    1. Init phase (SetupDesign)
    
 
    This creates a project within synthesis tool, sets the FPGA device type and does the necessary project setup before adding any source files.
    
 
    
 
    
-
    2. File add phase (AddInputFiles)
    
+
    2. File add phase (AddInputFiles)
    
 
    In this stage, files and components are processed from HIERARCHY array and passed to procedure EvalFile.
 EvalFile is called for each entry in PACKAGES/MOD variables and should instruct the synthesis tool to compile source file including fine-tunnig of additional properties based on extra file properties
    
 
    
 
    
-
    3. Synthesis and Implemenation (SynthetizeDesign, ImplementDesign)
    
+
    3. Synthesis and Implemenation (SynthetizeDesign, ImplementDesign)
    
 
    Procedures configure rest of parameters of the project and run the main process: the synthesis and the implementation.
    
 
    
 
    
-
    4. Final phase (SaveDesign)
    
+
    4. Final phase (SaveDesign)
    
 
    In this step, the binary programming file is generated.
    
 
    
 
    
 
    
-
    Other features of the build system
    
+
    Other features of the build system
    
 
    
-
    EvalFile
    
+
    EvalFile
    
 
    EvalFile procedure is specific for each synthesis tool and is being used as callback
 when the common code goes through hierarchy of modules. Procedure usually adds
 source files into the project and sets additional properties based on extra file
 properties.
    
 
    
 
    
-
    Batch feature in EvalFile
    
+
    Batch feature in EvalFile
    
 
    Although the EvalFile procedure receives one file for processing in each call,
 it can use the lazy evaluation mechanism, which processes a batch of source
 files in one command run. This mechanism is enabled in the simulation environment
@@ -438,7 +477,7 @@ 
    Batch feature in EvalFile
-
    Makefile
    
+
    Makefile
    
 
    There are few mechanisms in the global Makefile which deserve an explanation.
    
 
    Some targets in the Makefile are aware of unchanged files. If none of the source files
 for such target has been modified and the target already exists, it will not be remade.
@@ -464,7 +503,7 @@ 
    Makefile
 Common used files are DevTree.dts/dtb/vhd and user_const.vhd.
    
 
    
 
    
-
    The (incomplete) list of SYNTH_FLAGS array items
    
+
    The (incomplete) list of SYNTH_FLAGS array items
    
 
      
 
    • PROJ_ONLY {false, true}: Only the project file will be created. Neither synthesis nor implementation will be run.
      • 
 
    • SYNTH_ONLY {false, true}: Only the synthesis will be run, the implementation will be skipped.
      • 
@@ -485,34 +524,111 @@ 
      The (incomplete) list of SYNTH_FLAGS array items
    -

    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <NDK testing + +
    - +
    + + Device Tree> + +
    -
    - -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/amd/alveo-u200/readme.html b/devel/ndk_cards/amd/alveo-u200/readme.html index 883784902..95153fffe 100644 --- a/devel/ndk_cards/amd/alveo-u200/readme.html +++ b/devel/ndk_cards/amd/alveo-u200/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - AMD Alveo U200 — NDK-FPGA Docs documentation - - - - - - - - - + AMD Alveo U200 — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    AMD Alveo U200

    +

    AMD Alveo U200

    • Card information:
        @@ -137,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -172,7 +246,7 @@

          NDK firmware support

      -

      Programming the device

      +

      Programming the device

      1. Buld the firmware using make as described above (“Generate bitstream” using Vivado GUI flow)

      2. Connect USB cable to the JTAG interface of the card

        3. @@ -193,34 +267,76 @@

        Programming the device -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Bittware IA-420F + +
    - +
    + + AMD Alveo U55C> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/amd/alveo-u55c/readme.html b/devel/ndk_cards/amd/alveo-u55c/readme.html index b303e2545..e6bfc2f15 100644 --- a/devel/ndk_cards/amd/alveo-u55c/readme.html +++ b/devel/ndk_cards/amd/alveo-u55c/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - AMD Alveo U55C — NDK-FPGA Docs documentation - - - - - - - - - + AMD Alveo U55C — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    AMD Alveo U55C

    +

    AMD Alveo U55C

    • Card information:
        @@ -137,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -171,7 +245,7 @@

          NDK firmware support

      -

      Programming the device

      +

      Programming the device

      1. Buld the firmware using make as described above (“Generate bitstream” using Vivado GUI flow)

      2. Connect USB cable to the JTAG interface of the card

        3. @@ -192,34 +266,76 @@

        Programming the device -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <AMD Alveo U200 + +
    - +
    + + AMD VCU118@VU9P> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/amd/vcu118/readme.html b/devel/ndk_cards/amd/vcu118/readme.html index 93453bb56..bbbb05ef6 100644 --- a/devel/ndk_cards/amd/vcu118/readme.html +++ b/devel/ndk_cards/amd/vcu118/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - AMD VCU118@VU9P — NDK-FPGA Docs documentation - - - - - - - - - + AMD VCU118@VU9P — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    AMD VCU118@VU9P

    +

    AMD VCU118@VU9P

    • Card information:
        @@ -137,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -172,7 +246,7 @@

          NDK firmware support

      -

      Programming the device

      +

      Programming the device

      1. Buld the firmware using make as described above (“Generate bitstream” using Vivado GUI flow)

      2. Connect USB cable to the JTAG interface of the card

        3. @@ -193,34 +267,76 @@

        Programming the device -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <AMD Alveo U55C + +
    - +
    + + PRO DESIGN Falcon> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/bittware/ia-420f/readme.html b/devel/ndk_cards/bittware/ia-420f/readme.html index 4264fd6de..15938f9fa 100644 --- a/devel/ndk_cards/bittware/ia-420f/readme.html +++ b/devel/ndk_cards/bittware/ia-420f/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Bittware IA-420F — NDK-FPGA Docs documentation - - - - - - - - - + Bittware IA-420F — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Bittware IA-420F

    +

    Bittware IA-420F

    • Card information:
        @@ -137,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -177,7 +251,7 @@

          NDK firmware support

      -

      Boot instructions (initial)

      +

      Boot instructions (initial)

      Before you can use the nfb-boot tool, you must write the initial NDK firmware to flash memory using a regular JTAG programmer.

      • After the NDK firmware build is complete, you will have a bitstream file called my_bitstream.sof.

        • @@ -193,34 +267,76 @@

        Boot instructions (initial)

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Silicom N6010 + +
    - +
    + + AMD Alveo U200> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/intel/dk-dev-1sdx-p/readme.html b/devel/ndk_cards/intel/dk-dev-1sdx-p/readme.html index 8c7f936ef..544321505 100644 --- a/devel/ndk_cards/intel/dk-dev-1sdx-p/readme.html +++ b/devel/ndk_cards/intel/dk-dev-1sdx-p/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Intel Stratix 10 DX FPGA DK — NDK-FPGA Docs documentation - - - - - - - - - + Intel Stratix 10 DX FPGA DK — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Intel Stratix 10 DX FPGA DK

    +

    Intel Stratix 10 DX FPGA DK

    • Card information:
        @@ -139,7 +213,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -179,7 +253,7 @@

          NDK firmware support

      -

      Boot instructions

      +

      Boot instructions

      • After the NDK firmware build is complete, you will have a bitstream file called my_bitstream.sof.

      • Use the <NDK-APP_root_directory>/ndk/cards/dk-dev-1sdx-p/scripts/generate_pof.sh my_bitstream.sof command to convert the bitstream file to .pof format for flash memory.

        • @@ -194,34 +268,76 @@

        Boot instructions

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <ReflexCES XpressSX AGI-FH400G + +
    - +
    + + Intel Agilex I-Series FPGA DK> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/intel/dk-dev-agi027res/readme.html b/devel/ndk_cards/intel/dk-dev-agi027res/readme.html index 63a730fe6..edd87650c 100644 --- a/devel/ndk_cards/intel/dk-dev-agi027res/readme.html +++ b/devel/ndk_cards/intel/dk-dev-agi027res/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Intel Agilex I-Series FPGA DK — NDK-FPGA Docs documentation - - - - - - - - - + Intel Agilex I-Series FPGA DK — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Intel Agilex I-Series FPGA DK

    +

    Intel Agilex I-Series FPGA DK

    • Card information:
        @@ -139,7 +213,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -183,7 +257,7 @@

          NDK firmware support

      -

      Boot instructions

      +

      Boot instructions

      • After the NDK firmware build is complete, you will have a bitstream file called my_bitstream.sof.

      • Use the <NDK-APP_root_directory>/ndk/cards/dk-dev-agi027res/scripts/generate_pof.sh my_bitstream.sof command to convert the bitstream file to .pof format for flash memory.

        • @@ -198,34 +272,76 @@

        Boot instructions

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Intel Stratix 10 DX FPGA DK + +
    - +
    + + Silicom fb4CGg3@VU9P> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/prodesign/pd-falcon/readme.html b/devel/ndk_cards/prodesign/pd-falcon/readme.html index 2171c6f8b..73036e499 100644 --- a/devel/ndk_cards/prodesign/pd-falcon/readme.html +++ b/devel/ndk_cards/prodesign/pd-falcon/readme.html @@ -1,52 +1,135 @@ + + + + + - - - - - - - PRO DESIGN Falcon — NDK-FPGA Docs documentation - - - - - - - - - + PRO DESIGN Falcon — NDK-FPGA documentation + + + + + + - - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    PRO DESIGN Falcon

    +

    PRO DESIGN Falcon

    • Card Information:
        @@ -138,7 +211,7 @@

        PRO DESIGN Falcon -

        NDK Firmware Support

        +

        NDK Firmware Support

        • Supported Ethernet Cores in the NDK Firmware:
            @@ -176,7 +249,7 @@

            NDK Firmware Support

    -

    Boot Instructions

    +

    Boot Instructions

    • First, build the NDK firmware. Note that the first build will fail—this is expected.

    • After the first failed implementation, run the <NDK-APP_root_directory>/ndk/cards/prodesign/pd-falcon/src/ip/htile_pcie_fix.sh script to fix the generated H-Tile IP core.

      • @@ -190,34 +263,71 @@

      Boot Instructions

    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <AMD VCU118@VU9P + +
    - +
    + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/reflexces/agi-fh400g/readme.html b/devel/ndk_cards/reflexces/agi-fh400g/readme.html index 9fa70f461..1cf1530de 100644 --- a/devel/ndk_cards/reflexces/agi-fh400g/readme.html +++ b/devel/ndk_cards/reflexces/agi-fh400g/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - ReflexCES XpressSX AGI-FH400G — NDK-FPGA Docs documentation - - - - - - - - - + ReflexCES XpressSX AGI-FH400G — NDK-FPGA documentation + + + + + + - - - - -
    - - -
    - -
    -
    -
    - -
    -
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    -
    - +
    + +
    +
    +
    +
    +
    -

    ReflexCES XpressSX AGI-FH400G

    +

    ReflexCES XpressSX AGI-FH400G

    • Card information:
        @@ -138,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -182,7 +255,7 @@

          NDK firmware support

      -

      Board Revision

      +

      Board Revision

      This card exists in multiple revisions. The default revision for the firmware build is BOARD_REV=0. The correct revision for the firmware build can be selected using the Makefile parameter BOARD_REV, for example as follows:

      $ cd <NDK-APP_root_directory>/build/agi-fh400g
@@ -196,7 +269,7 @@ 
      Board Revision
-
      Board Test Scripts
      
+
      Board Test Scripts
      
 
      The NDK firmware enables easy testing of the FPGA card. The firmware includes several generators and switchable loopback paths (usually part of the the Gen Loop Switch (GLS) module). A simplified diagram showing the testing capabilities can be found below.
      
 ../../../_images/ndk_loopback.drawio.svg
 
@@ -221,34 +294,77 @@ 
      Board Test Scripts
      -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <MFB specification + +
    - +
    + + Intel Stratix 10 DX FPGA DK> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/silicom/fb2cghh/readme.html b/devel/ndk_cards/silicom/fb2cghh/readme.html index bcd70b13b..b7bff423b 100644 --- a/devel/ndk_cards/silicom/fb2cghh/readme.html +++ b/devel/ndk_cards/silicom/fb2cghh/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Silicom fb2CGhh@KU15P — NDK-FPGA Docs documentation - - - - - - - - - + Silicom fb2CGhh@KU15P — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Silicom fb2CGhh@KU15P

    +

    Silicom fb2CGhh@KU15P

    • Card information:
        @@ -136,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -176,34 +251,75 @@

          NDK firmware support -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Silicom fb4CGg3@VU9P + +
    - +
    + + Silicom N6010> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/silicom/fb4cgg3/readme.html b/devel/ndk_cards/silicom/fb4cgg3/readme.html index 343ca9124..57cd4776b 100644 --- a/devel/ndk_cards/silicom/fb4cgg3/readme.html +++ b/devel/ndk_cards/silicom/fb4cgg3/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Silicom fb4CGg3@VU9P — NDK-FPGA Docs documentation - - - - - - - - - + Silicom fb4CGg3@VU9P — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Silicom fb4CGg3@VU9P

    +

    Silicom fb4CGg3@VU9P

    • Card information:
        @@ -136,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -177,34 +252,75 @@

          NDK firmware support -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Intel Agilex I-Series FPGA DK + +
    - +
    + + Silicom fb2CGhh@KU15P> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_cards/silicom/n6010/readme.html b/devel/ndk_cards/silicom/n6010/readme.html index 25b1fdda7..ecfd350c4 100644 --- a/devel/ndk_cards/silicom/n6010/readme.html +++ b/devel/ndk_cards/silicom/n6010/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Silicom N6010 — NDK-FPGA Docs documentation - - - - - - - - - + Silicom N6010 — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Silicom N6010

    +

    Silicom N6010

    • Card information:
        @@ -136,7 +211,7 @@
      -

      NDK firmware support

      +

      NDK firmware support

      • Ethernet cores that are supported in the NDK firmware:
          @@ -177,34 +252,75 @@

          NDK firmware support -

    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Silicom fb2CGhh@KU15P + +
    - +
    + + Bittware IA-420F> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/cocotb/README.html b/devel/ndk_core/cocotb/README.html index c527079aa..4a717dacf 100644 --- a/devel/ndk_core/cocotb/README.html +++ b/devel/ndk_core/cocotb/README.html @@ -1,50 +1,134 @@ + + + + + - - - - - - - Cocotb toplevel simulation core — NDK-FPGA Docs documentation - - - - - - - - - + Cocotb toplevel simulation core — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Cocotb toplevel simulation core

    +

    Cocotb toplevel simulation core

    -

    Quick start

    +

    Quick start

    1. Install python packages with ‘pip install -r requirements.txt’

    2. Copy example files to your project card build directory

      3. @@ -120,31 +198,65 @@

      Quick start

    -
    - -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    +
    +
    + - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + +
    - +
    + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.html b/devel/ndk_core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.html index e8da6ad3f..73919d319 100644 --- a/devel/ndk_core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.html +++ b/devel/ndk_core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.html @@ -1,50 +1,134 @@ + + + + + - - - - - - - F-Tile Multirate IP — NDK-FPGA Docs documentation - - - - - - - - - + F-Tile Multirate IP — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    F-Tile Multirate IP

    +

    F-Tile Multirate IP

    -

    Implemented IP cores

    +

    Implemented IP cores

    Right now, you can use two designs with Multirate IP. These designs have optimized parameters, so you do not need to change anything. These designs are 100GE and 25GE, the individual profiles that can be set are listed in Tab. 1. If you want to make a build with Multirate IP, check the Makefile file for agi-fh400g, there are pseudo names for each Multirate IP core.

    -

    Build tips

    +

    Build tips

    The first step is to make a build. If an error during the build occurs, here are a few tips to help you to fix them. If you have a problem during the build with Timing analysis and it seems that it could be because of asynchronous clk signals, look into the timing.sdc file. There is the declaration of asynchronous clocks for both Multirate IP cores. If you have a problem with the Profile ID setup for Dynamic Reconfiguration, look into multirate.qsf. There is the declaration of profiles for both types of IP cores (100G and 25G) and it is set by its setup (the order of profiles when the IP was generated). These assignments allow you to set the order of all profiles (from 0 to …) for all IP cores. If you have other problems, look into Intel’s documentation: Intel F-Tile Ethernet Multirate Intel FPGA IP User Guide and Intel F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide.

    Name

    - +@@ -173,7 +251,7 @@

    Build tips -

    Switching profiles

    +

    Switching profiles

    Python script named profile_swap.py was made for swapping profiles. It is located in the ndk-core/intel/src/comp/network_mod/sw/ directory. There are five parameters, which have to be set to change the speed or type of FEC. These parameters are:

    @@ -189,31 +267,67 @@

    Switching profiles - +
    + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/comp/eth/network_mod/readme.html b/devel/ndk_core/comp/eth/network_mod/readme.html index 7068eb9f8..c3cf0c79c 100644 --- a/devel/ndk_core/comp/eth/network_mod/readme.html +++ b/devel/ndk_core/comp/eth/network_mod/readme.html @@ -1,50 +1,134 @@ - - - - - - - NETWORK MODULE — NDK-FPGA Docs documentation - - + + + + - - - - - - + NETWORK MODULE — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    NETWORK MODULE

    +

    NETWORK MODULE

    -

    Typical Configurations

    +

    Typical Configurations

    Tab. 1 F-Tile_Multirate IPs variantsTab. 1 F-Tile_Multirate IPs variants
    @@ -143,7 +221,7 @@

    Typical Configurations
    -

    Verification Plan

    +

    Verification Plan

    It is necessary to test all supported Ethernet IP architectures (E-Tile, CMAC,…) and their supported speeds/channels.

    ETH_CORE_ARCH

    @@ -195,10 +273,10 @@

    Verification Plan -

    Entity Docs

    +

    Entity Docs

    -ENTITY NETWORK_MOD IS
    +ENTITY NETWORK_MOD IS
    Generics
    @@ -880,31 +958,67 @@

    Entity Docs - +
    + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/comp/eth/network_mod/uvm/readme.html b/devel/ndk_core/comp/eth/network_mod/uvm/readme.html index 4047d462f..1f371e229 100644 --- a/devel/ndk_core/comp/eth/network_mod/uvm/readme.html +++ b/devel/ndk_core/comp/eth/network_mod/uvm/readme.html @@ -1,50 +1,134 @@ + + + + + - - - - - - - BUFFER — NDK-FPGA Docs documentation - - - - - - - - - + BUFFER — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    BUFFER

    +

    BUFFER

    -

    Verification Plan

    +

    Verification Plan

    Generic

    - + @@ -142,31 +220,65 @@

    Verification Plan - +
    + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/readme.html b/devel/ndk_core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/readme.html index a2b1c88d2..3251b3543 100644 --- a/devel/ndk_core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/readme.html +++ b/devel/ndk_core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/readme.html @@ -1,50 +1,134 @@ - - - - - - - - CRDT Agent — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + CRDT Agent — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    CRDT Agent

    +

    CRDT Agent

    This agent substitutes the PCIE_CRDT_LOGIC component.

    -
    +
    -
    - -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - -
    -
    -
    -
    - - - + +
    + +
    +
    +
    + +
    + +
    + +
    +
    +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/app.html b/devel/ndk_core/doc/app.html index 0ed10ba26..c1b7da8a3 100644 --- a/devel/ndk_core/doc/app.html +++ b/devel/ndk_core/doc/app.html @@ -1,68 +1,141 @@ - - - - - - - The Application — NDK-FPGA Docs documentation - - + + + + - - - - - - + The Application — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    The Application

    +

    The Application

    The NDK is designed for creating new network applications for packet processing in a deep pipeline. The NDK provides space for your application and defines several interfaces for communication with devices on the network, with software (control and data), or with external memory. We refer to this space in the NDK as the Application.

    Depending on the selected FPGA card, there are several ETH streams for communication over an Ethernet network and several DMA streams for communication with the host CPU through the DMA module. There are also several Avalon-MM interfaces for access to external memory (typically DDR4) and an MI interface for access to the CSR implemented in the application. ETH and DMA streams use a combination of MFB (for packet data) and MVB (for packet headers and metadata) buses to transfer Ethernet packets. The Application allows you to assign the selected user clock to individual parts of the design. A typical connection of the Application is shown in the block diagram below:

    ../../_images/ndk_app.drawio.svg

    We recommend splitting the Application into several parts that we call Application cores. Typically, an Application core is instantiated for each Ethernet stream. Depending on the selected FPGA card, the number of ETH streams is equal to the number of DMA streams, or there are multiple ETH streams and only one DMA stream. For such cases, the NDK has prepared modules (see the Application implementation in NDK-APP-Minimal) to ensure that each Application Core is correctly connected to the available DMA interfaces. They also ensure proper distribution of the available DMA channels among the Application cores.

    -

    How to use the Application interfaces

    +

    How to use the Application interfaces

    The following sections describe how to work with each of the Application interfaces. You will also learn in which formats you can receive data and in which you must send it. We also strongly recommend that you read the MFB bus specification, MVB bus specification and MI bus specification. The MTU of packets transferred via DMA or Ethernet can be set using configuration parameters, see chapter “Configuration files and parameters”. The set MTU values are then available in the DeviceTree description of the NDK firmware.

    -

    Receiving packets from Ethernet

    +

    Receiving packets from Ethernet

    Ethernet packets enter the application over two buses (ETH_RX_*). The MVB bus carries the packet metadata, and the MFB bus carries the actual packet data. Both buses have independent flow control.

    Warning

    @@ -244,11 +310,11 @@

    Receiving packets from Ethernet -

    Transmitting packets to the Ethernet

    +

    Transmitting packets to the Ethernet

    The packets are sent to the Ethernet only through the MFB bus (ETH_TX_MFB_*). In this case, the metadata is transferred in a special signal: ETH_TX_MFB_HDR. This signal is valid for each MFB Region where an Ethernet packet starts. The packet data must contain an Ethernet frame without the CRC, which is calculated and inserted further in the design. The minimum allowed length of the packet data is 60B, if necessary, the application must add padding to the packet. The metadata format is also defined in the eth_hdr_pack package (see the previous section).

    -

    Receiving packets from the DMA module

    +

    Receiving packets from the DMA module

    The application receives packets from the DMA module over two buses, MVB and MFB (DMA_TX_*). As before, MVB carries the metadata, and MFB carries the actual packet data. Both buses have independent flow control.

    Warning

    @@ -282,7 +348,7 @@

    Receiving packets from the DMA module -

    Transmitting packets to the DMA module

    +

    Transmitting packets to the DMA module

    The application sends packets to the DMA module over two buses, MVB and MFB (DMA_RX_*), which have the same roles as stated in previous sections. As before, MVB carries the metadata, and MFB carries the actual packet data. Again, the MVB bus does not use a single MVB_DATA signal but multiple data signals instead:

    • MVB_LEN - the length of the packet in bytes

      • @@ -299,17 +365,17 @@

      Transmitting packets to the DMA module -

      Read/write access to the Application registers from SW

      +

      Read/write access to the Application registers from SW

      The application is typically controlled by a software tool. The NDK provides the nfb-bus tool and an API for generating read/write memory requests. These are transferred via the MI bus in the NDK firmware. This memory-oriented bus is wired throughout the NDK firmware, and each part, including the application, has its own allocated address space. You can find more about the MI and the available address space in the MI bus interconnect chapter.

      The description of the components with a specific address space is implemented in the NDK using a DeviceTree. Also, the Application must have its own DeviceTree description, which can further refer to the internal components and their address spaces. It is a good idea to take inspiration from the NDK-APP-Minimal application DeviceTree file when creating a DeviceTree file for your application.

    -

    Ports and generics of the Application

    +

    Ports and generics of the Application

    In the tables below, you can see a detailed description of the Application interface, i.e., a description of all its generics and ports.

    -ENTITY APPLICATION_CORE IS
    +ENTITY APPLICATION_CORE IS
    Generics

    Verification PlanVerification Plan

    ID

    Description

    @@ -1330,34 +1396,83 @@

    Ports and generics of the Application - +
    + + The MI bus interconnect> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/configuration.html b/devel/ndk_core/doc/configuration.html index 2504520f7..930b57f76 100644 --- a/devel/ndk_core/doc/configuration.html +++ b/devel/ndk_core/doc/configuration.html @@ -1,114 +1,169 @@ - - - - - - - Configuration files and parameters — NDK-FPGA Docs documentation - - + + + + - - - - - - + Configuration files and parameters — NDK-FPGA documentation + + + + + + - + + + - -
    - - -
    +
    -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    Configuration files and parameters

    +

    Configuration files and parameters

    This chapter describes the NDK configuration files and parameters. The configuration has three levels: the CORE, the card, and the user application. A detailed description of each level is below (the abreviated version is provided via the following link).

    -

    Build system files

    +

    Build system files

    The following table provides an overview of files used for building a project/design.

    Note

    @@ -174,7 +201,7 @@ The placeholder {TOOL} refers to the tool-specific filename, for example: Vivado, Quartus.

    Generic

    - +@@ -255,7 +282,7 @@
    Configuration filesConfiguration files
    -

    Parametrizing NDK-CORE design

    +

    Parametrizing NDK-CORE design

    The files in the <NDK-CORE_root_directory>/intel/config directory and the <NDK-CORE_root_directory>/intel/core.mk file contain CORE parameters. Some of these parameters are configurable (more info below). The sourcing of @@ -267,7 +294,7 @@ ../../_images/const_hierarchy.svg

    -

    Hierarchy diagram

    +

    Hierarchy diagram

    Numbers show the order in which these parameter files are sourced. Sourcing takes place in the core_boostrap.tcl file.

    @@ -275,9 +302,9 @@
    -

    File description

    +

    File description

    -

    core_conf.tcl

    +

    core_conf.tcl

    This file provides a listing of all parameters that can be changed by the user. Each parameter contains a comment with allowed values and the meaning of these values. Because the NDK-CORE design is independent of the underlying @@ -287,7 +314,7 @@

    File description -

    core_const.tcl

    +

    core_const.tcl

    Warning

    This file contains parameters that should not be changed deliberately by the @@ -318,13 +345,13 @@

    File description -

    core.mk

    +

    core.mk

    This file contains default values for the parameters specified in the Makefile. The allowed values of each parameter are provided in the comments. The user of the design can change these values freely.

    -

    core_bootstrap.tcl

    +

    core_bootstrap.tcl

    Warning

    The features in this file are for development and should not be changed.

    @@ -336,7 +363,7 @@

    core_bootstrap.tcl -

    Further work with parameters

    +

    Further work with parameters

    Warning

    These features are for development and should not be used in regular @@ -347,7 +374,7 @@

    Further work with parameters -

    Passing through Modules.tcl

    +

    Passing through Modules.tcl

    As described in the Build System section, the Modules.tcl files allow for modular and hierarchical organization of VHDL source files. The Modules.tcl files provide an ARCHGRP list to pass specific constants across the source file hierarchy. Each @@ -366,7 +393,7 @@

    Passing through Modules.tcl<NDK-CORE_root_directory>/intel/Modules.tcl file.

    -

    Adding constants to the VHDL package

    +

    Adding constants to the VHDL package

    A dynamic VHDL package is generated each time a user starts building a new design. The package is called combo_user_const and contains all parameters which were added in the core_const.tcl file described @@ -396,16 +423,16 @@

    Passing through Modules.tcl -

    Parametrizing a specific card type

    +

    Parametrizing a specific card type

    The final design of the NDK application depends on the underlying platform, e.g., the card type on which the design should run. The system provides mechanism to configure card specific parameters.

    -

    File description

    +

    File description

    The file structure is similar to the one described in the configuration of the NDK-CORE design.

    -

    card_conf.tcl

    +

    card_conf.tcl

    This file lists user-configurable parameters and their possible values in the comments. The file contains parameters relevant to a specific card. Those parameters are mostly tied to the underlying hardware, like the number of Ethernet @@ -414,7 +441,7 @@

    card_conf.tcl -

    card_const.tcl

    +

    card_const.tcl

    Warning

    This file contains features for development. It is not recommended for the user to change @@ -433,7 +460,7 @@

    card_conf.tcl -

    card.mk

    +

    card.mk

    Warning

    This file contains features for development. It is not recommended for the user to change @@ -447,7 +474,7 @@

    card.mk

    -

    Further work with parameters

    +

    Further work with parameters

    Warning

    These features are for development and should not be used in regular @@ -456,7 +483,7 @@

    Further work with parameters -

    Passing through Modules.tcl

    +

    Passing through Modules.tcl

    The card-specific parameters are passed to the Modules.tcl file of the top-level entity using the CARD_ARCHGRP associative array. This array is initialized in the <card_root_directory>/src/Vivado.inc.tcl file for Xilinx-based cards and @@ -468,7 +495,7 @@

    Passing through Modules.tcl -

    Adding constants to the VHDL package

    +

    Adding constants to the VHDL package

    It is recommended to add card-specific constants to the combo_user_const VHDL package in card_const.tcl file. The way of adding these constants was described in the Adding constants to the VHDL package section in the documentation of NDK-CORE @@ -477,19 +504,19 @@

    Adding constants to the VHDL package

    -

    Parametrizing the user application

    +

    Parametrizing the user application

    The user application can also be parametrized using specific configuration files. Configuration parameters can be handed to the subcomponents of the APPLICATION_CORE design entity. It also allows the user to choose one of, sometimes, multiple configurations for a specific card before launching the build process.

    -

    Configuration files

    +

    Configuration files

    The configuration of the application is less constrained than NDK-CORE and card configuration. The application repository provides three files in which the user application is or can be configured.

    -

    build/<card_name>/Makefile

    +

    build/<card_name>/Makefile

    Warning

    This file contains features for development. It is not recommended for the user to change @@ -516,7 +543,7 @@

    Configuration files -

    build/<card_name>/{Vivado,Quartus}.tcl

    +

    build/<card_name>/{Vivado,Quartus}.tcl

    This file adds the APPLICATION_CORE architecture where a logic of a user application is. The APP_ARCHGRP associative array is initialized in this file and allows the user to pass one or more user-specified @@ -525,7 +552,7 @@

    build/<card_name>/{Vivado,Quartus}.tcl -

    build/<card_name>/app_conf.tcl

    +

    build/<card_name>/app_conf.tcl

    This file has the highest priority of all user-configurable constants (for more details, refer to the Hierarchy diagram). The user can change the parameters specified in this file or add others according to @@ -535,10 +562,10 @@

    build/<card_name>/{Vivado,Quartus}.tcl -

    TL;DR

    +

    TL;DR

    This section contains specific recipes for achieving specific goals.

    -

    I need to include specific component in CORE depending on a given parameter value

    +

    I need to include specific component in CORE depending on a given parameter value

    1. First, you should write your parameter to the core/intel/config/core_conf.tcl with a specific value (if the parameter @@ -598,7 +625,7 @@

      I need to include specific component in CORE depending on a given parameter

    -

    What can I do with the core_conf.tcl file

    +

    What can I do with the core_conf.tcl file

    • You can declare new configuration parameters (and assign their default values) so they would be visible across all supported cards. These default @@ -608,7 +635,7 @@

      What can I do with the core_conf.tcl file

    -

    What can I do with the core_const.tcl file

    +

    What can I do with the core_const.tcl file

    • You can add a dependent parameter (the value of such a parameter depends on the value of another parameter). The developer should add CORE-specific @@ -644,13 +671,13 @@

      What can I do with the core_const.tcl file

    -

    What can I do with the card_conf.tcl file

    +

    What can I do with the card_conf.tcl file

    You can change parameters specified in the core_conf.tcl file for a specific card type (because some parameters are directly dependent on an underlying hardware), e.g., the number of Ethernet ports or Ethernet channels.

    -

    What can I do with the card_const.tcl file

    +

    What can I do with the card_const.tcl file

    • You can add a dependent parameter when a card requiers it. CORE specific parameters belong to the core_const.tcl.

      • @@ -660,7 +687,7 @@

      What can I do with the card_const.tcl file

    -

    What can I do with the app_conf.tcl file

    +

    What can I do with the app_conf.tcl file

    • You can add parameters for the given application (component application_core.vhd).

      • @@ -673,41 +700,130 @@

      What can I do with the app_conf.tcl file

    -

    Contact for author

    +

    Contact for author

    Send suggestions regarding missing information or unanswered questions to valekv@cesnet.cz.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Time Stamp Unit + +
    - +
    + + NDK testing> + +
    -
    -
    -
    - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/devtree.html b/devel/ndk_core/doc/devtree.html index 022878a65..22a7cf75a 100644 --- a/devel/ndk_core/doc/devtree.html +++ b/devel/ndk_core/doc/devtree.html @@ -1,52 +1,136 @@ - - - - - - - - Device Tree — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + Device Tree — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Device Tree

    +

    Device Tree

    Using the Device Tree (DT), we describe the contents of the firmware for the utility software: base addresses, versions and features of the individual components. To a certain extent, the Device Tree communicates to the user basic information about the HW platform, firmware version, etc. The Device Tree structure will be closely linked to a specific firmware - integrated inside.

    -

    DT integration in build system

    +

    DT integration in build system

    There are scripts in the translation system that go through components using Modules.tcl. The top-level DevTree.tcl script (in ofm/build) first inserts general information in the form of DT-properties into the DTS framework (build time, current repository revision, author of the firmware build, etc.). Then, if it exists, it calls a function called dts_build_project, and it calls the dts_build_netcope function, which should be included in each base of the card project (typically a top-level directory with fpga_common.vhd). Here, the card project already ensures the insertion of specific information (eg card type) itself, including the instancing of its subcomponents (typically dts_boot_controller, dts_dma_module, dts_application…) and passing generics to these functions.

    After running make (for compiling the firmware of the selected card) a file DevTree.dts (generated by passing TCL scripts DevTree.tcl) and VHDL package DevTree.vhd are created, which contains std_logic_vector DTB_DATA (which is a binary representation of compiled (dtc) and compressed (xz) input DevTree.dts file). This package is used by the PCI_EXT_CAP component, see the next chapter.

    Because constants in packages cannot be accessed directly in TCL, the user_const.vhd package files are generated by the TCL script user_const.tcl. This is the only way to ensure consistency in top-level generations and Device Tree descriptions. Translation scripts need the dtc compiler for their operation.

    -

    Location of DTB in the firmware

    +

    Location of DTB in the firmware

    The DT blob is located in the PCI configuration space. A custom extension (PCIe VSEC - Vendor-Specific Extended Capability) has been created. Because the configuration space is relatively small, there are only a few control registers that make the entire DTB stored in BRAM accessible. In this way, the DTB does not load the MI bus and cannot be easily or accidentally removed from the design. You can use the dtc tool to read the complete Device Tree from the FPGA card:

    # dtc -I dtb /dev/nfb0
    -

    Example of DTS of one component

    +

    Example of DTS of one component

    /*
  * ref_name:   instance name, typically populated by the parent module when needed
  *             get reference to the installed component (can be empty)
@@ -163,7 +234,7 @@ 
    Example of DTS of one component
-
    Example of generated DTS for FPGA card
    
+
    Example of generated DTS for FPGA card
    
 
    /dts-v1/;
 
 / {
@@ -744,7 +815,7 @@ 
    Example of generated DTS for FPGA card
-
    Requirements for developers
    
+
    Requirements for developers
    
 
      
 
    • 
 
      Requirements for SW developers:
        
@@ -773,34 +844,79 @@ 
        Requirements for developers
    
           
    
-
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - + + +
    +
    +
    +
    +
    + + + <Build System + +
    + +
    + + Frequently Asked Questions> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/dma.html b/devel/ndk_core/doc/dma.html index 1859d3ddc..ea2b2a397 100644 --- a/devel/ndk_core/doc/dma.html +++ b/devel/ndk_core/doc/dma.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - The DMA module — NDK-FPGA Docs documentation - - - - - - - - - + The DMA module — NDK-FPGA documentation + + + + + + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    The DMA module

    +

    The DMA module

    The DMA module is a wrapper containing the DMA controller (DMA IP), auxiliary, and debug logic. The connection of the DMA module is shown in the block diagram below. The DMA module is parametric and handles different numbers of DMA streams. The number of DMA streams corresponds to the number of instantiated DMA controllers. The currently supported DMA controllers in NDK are:

    • DMA Medusa IP – Closed-source DMA controller optimized for high throughput (up to 400 Gbps) and support for multiple PCIe endpoints. See the DMA Medusa IP documentation for a detailed description.

      • @@ -138,7 +211,7 @@ ../../_images/dma_module.drawio.svg
      -

      Selecting a DMA controller

      +

      Selecting a DMA controller

      Before running the FPGA firmware compilation, the desired DMA controller can be selected using the makefile parameter DMA_TYPE. Without this parameter, the default DMA controller is automatically selected. These are the allowed values:

      • DMA_TYPE=0 – No DMA IP is instantiated. DMA IP is replaced by a loopback.

        • @@ -151,40 +224,82 @@

        Selecting a DMA controller -

        DMA Medusa IP notes

        +

        DMA Medusa IP notes

        The DMA Medusa IP has an internal architecture divided into several DMA endpoints, each rated for 100 Gbps throughput. See the DMA Medusa documentation for a detailed description. Individual DMA endpoints are statically mapped to a physical PCIe endpoint (mapping is implemented in the PCIe module). The current implementation allows one or two DMA endpoints to be mapped to one PCIe endpoint. Individual DMA channels of the DMA Medusa IP are controlled through MI requests, therefore, the MI bus is also mapped to the DMA Medusa from individual PCIe endpoints.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <The Network Module + +
    - +
    + + The PCIe module> + +
    -
    -
    -
    - - - +
    + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/eth.html b/devel/ndk_core/doc/eth.html index cb3e57831..a2f40439d 100644 --- a/devel/ndk_core/doc/eth.html +++ b/devel/ndk_core/doc/eth.html @@ -1,75 +1,143 @@ - - - - - - - The Network Module — NDK-FPGA Docs documentation - - + + + + - - - - - - + The Network Module — NDK-FPGA documentation + + + + + + - + + + - -
    - +
    -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    +
    +
    +
    +
    -

    The Network Module

    +

    The Network Module

    Network Module enables connection of the NDK platform to an Ethernet interface(s). The basic architecture is displayed below.

    ../../_images/network_module_arch.svg @@ -172,7 +233,7 @@ The MI Splitter forwards requests to one or more instances of Network Module Logic. The main blocks and their connection between address spaces are in the table below:

    - +@@ -208,13 +269,13 @@

    -

    How to use the Network Module interfaces

    +

    How to use the Network Module interfaces

    In the following two subsections, you will learn how to work with the interfaces of the Network Module that connect to the Application (left side of the diagram above). That includes the format in which data should be sent to and received from the Application. The Ethernet packets are sent over the MFB bus, some additional info is sent over the MVB bus, and access to the CSR registers is provided over the MI bus. We strongly recommend reading their specifications before trying to use them.

    -

    Receiving packets from the Application

    +

    Receiving packets from the Application

    Ethernet packets enter the Network Module through the MFB bus (RX_MFB_*) along with its metadata (RX_MFB_HDR). MFB bus carries the actual packet data, and metadata data contain the Ethernet header. The packet data is an Ethernet frame without CRC. @@ -316,7 +377,7 @@

    Receiving packets from the Application -

    Transmitting packets to the Application

    +

    Transmitting packets to the Application

    Ethernet packets are sent to the Application over two buses: the MFB (TX_MFB_*) and the MVB (TX_MVB_*). The MFB bus carries the actual packet data, and the MVB bus carries the packet’s metadata. Both buses have independent flow control.

    @@ -333,7 +394,7 @@

    Transmitting packets to the Application -

    SW access to the Network Module Cores and Network Module Logics

    +

    SW access to the Network Module Cores and Network Module Logics

    The Network Module Core(s) is/are accessed over the MI PHY bus. Each Core has its own address space offset from each other by 0x00200000. According to this offset, the MI PHY Splitter forwards the MI transactions to the target Core(s). @@ -349,7 +410,7 @@

    SW access to the Network Module Cores and Network Module Logics -

    +@@ -384,7 +445,7 @@

    SW access to the Network Module Cores and Network Module Logics

    Tab. 1Tab. 1 Tab. 2Tab. 2
    - +@@ -420,7 +481,7 @@

    SW access to the Network Module Cores and Network Module Logics -

    Network Module Core

    +

    Network Module Core

    The so-called Network Module Core is a subcomponent of the Network Module. It contains the required hard IP(s), appropriate adapters, and an MI component for reconfiguring the hard IP(s). Right now, the Network Module can use three different Ethernet hard IPs: for Intel FPGA, it is the E-Tile or the F-Tile, and for the Xilinx FPGA, it is the CMAC. @@ -474,7 +535,7 @@

    SW access to the Network Module Cores and Network Module Logicsnfb-eth tool documentation for instructions on how to turn the loopback on/off.

    -

    SW access to the reconfiguration interfaces

    +

    SW access to the reconfiguration interfaces

    Software access is provided via the management unit (MGMT), which is instantiated per channel. This component employs an MDIO (Management Data Input/Output) interface. Its main task is to provide access to the reconfiguration interfaces of the hard IP(s). @@ -494,7 +555,7 @@

    SW access to the Network Module Cores and Network Module Logics -

    Network Module Logic

    +

    Network Module Logic

    The Network Module Core is connected to Network Module Logic which contains TX and RX MAC Lites. There is one MAC Lite pair (TX + RX) for each Ethernet channel, and they are connected one-on-one to appropriate adapters located in the Network Module Core. On the other side, TX MAC Lites receive data from the MFB Splitter, which splits the incoming stream of MFB data into channels (according to the PORT item of the header, see the eth_hdr_pack above). @@ -510,7 +571,7 @@

    SW access to the Network Module Cores and Network Module LogicsTSU), which generates timestamps. The timestamps are inserted per frame into their header (the TIMESTAMP and TIMESTAMPVLD items of the header).

    -

    SW access to the MAC Lites

    +

    SW access to the MAC Lites

    The MI splitting logic block shown in the diagram below is a virtual block that exists only to explain the Network Module (it is not an actual component). The purpose of this subsection is to describe the access to the MAC Lites for multi-channel configurations. The diagram below shows how the MAC Lites are connected to the MI bus.

    @@ -529,7 +590,7 @@

    SW access to the Network Module Cores and Network Module Logics -

    +@@ -646,34 +707,88 @@

    SW access to the Network Module Cores and Network Module Logics - +
    + + The DMA module> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/faq.html b/devel/ndk_core/doc/faq.html index 0bafb0d3e..4ae89fd90 100644 --- a/devel/ndk_core/doc/faq.html +++ b/devel/ndk_core/doc/faq.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Frequently Asked Questions — NDK-FPGA Docs documentation - - - - - - - - - + Frequently Asked Questions — NDK-FPGA documentation + + + + + + - + - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    Frequently Asked Questions

    +

    Frequently Asked Questions

    -

    What is a Network Development Kit (NDK)?

    +

    What is a Network Development Kit (NDK)?

    The NDK is a generic FPGA framework for easy development of your own high-speed network FPGA application. CESNET (an association of universities of the Czech Republic and the Czech Academy of Sciences) develops and uses NDK primarily to implement own FPGA probes for monitoring CESNET high-speed backbone networks.

    -

    What SW do I need to build the NDK firmware?

    +

    What SW do I need to build the NDK firmware?

    Intel Quartus Prime Pro tool is required to build FW with target FPGA from Intel. Xilinx Vivado tool is needed to build FW with target FPGA from Xilinx (AMD). You also need to have the corresponding licenses for these tools. The specific required versions of these tools are listed for each NDK application in the main README.md file.

    -

    What FPGA chips and cards does NDK support?

    +

    What FPGA chips and cards does NDK support?

    The NDK supports FPGA chips from both major manufacturers Intel and Xilinx (AMD). Specifically, these are Intel Agilex, Stratix 10 and Xilinx UltraScale+ FPGA chips. A list of specific supported FPGA cards is available for each NDK application in the main README.md file.

    -

    What communication interfaces can a NDK applications have available?

    +

    What communication interfaces can a NDK applications have available?

    A NDK application can use the interface for communication with external memories, for network communication (Ethernet), for software configuration (write and read 32b words) and for high-speed data transfers between the FPGA and the host memory (DMA).

    -

    What Ethernet standards does NDK support?

    +

    What Ethernet standards does NDK support?

    The specific support of Ethernet standards is always dependent on the target FPGA card or on the Ethernet IP used. NDK currently supports Intel E-Tile, F-Tile or Xilinx CMAC Ethernet IP. All listed IPs support the 100GBASE standard; E-Tile, F-Tile also handle 10GBASE and 25GBASE; and F-Tile then supports even more Ethernet standards.

    -

    Does NDK implement ISO/OSI protocol support?

    +

    Does NDK implement ISO/OSI protocol support?

    No, the user application in the NDK must work on the line layer (L2), i.e. with Ethernet frames without CRC (it is removed/added in the Ethernet IP). If necessary, support for ISO/OSI protocols must be implemented within the user application.

    -

    Does NDK support Jumbo packets?

    +

    Does NDK support Jumbo packets?

    Yes, the NDK firmware supports packets up to 16383 B by default, which is the maximum possible value. However, the RX MAC by default discards received Ethernet frames larger than 1522 B (including CRC), but this limit can be changed dynamically through the SW tool (nfb-eth).

    -

    Is there also an open-source DMA controller available?

    +

    Is there also an open-source DMA controller available?

    Not currently, but a low-latency DMA controller (DMA Calypte) is currently under development, which will be available as an open-source component of the NDK.

    -

    What clock frequencies are available for the user application?

    +

    What clock frequencies are available for the user application?

    The user application in the NDK has available four clock signals from the same source with frequencies: 100, 200, 300 and 400 MHz. A 100MHz clock is typically used for the configuration interface and the default is 200MHz for the data path. Using a slower clock may degrade the overall throughput of the NDK.

    -

    Is there a SW stack also available for the NDK?

    +

    Is there a SW stack also available for the NDK?

    Yes, a Linux driver, a library with a simple API for developing your own SW application and a set of useful tools are available in a separate repository.

    -

    What is the difference between NDK and NetFPGA?

    +

    What is the difference between NDK and NetFPGA?

    NetFPGA is a general framework for developing your own FPGA application same as the NDK. Unfortunately NetFPGA only supports Xilinx UltraScale+ FPGA chips and does not support Ethernet and data rates higher than 100 Gbps.

    -

    What is the difference between NDK and Corundum?

    +

    What is the difference between NDK and Corundum?

    Rather, Corundum is also trying to create a general FPGA network, but it also enables the expansion of its own RTL application. Corundum also supports various FPGA cards with chips from both Xilinx and Intel. Unfortunately it does not support Ethernet and data transfer rates higher than 100 Gbps.

    -

    What is the difference between NDK and OpenNIC?

    +

    What is the difference between NDK and OpenNIC?

    OpenNIC is a general framework for developing your own FPGA application same as the NDK. Unfortunately OpenNIC only supports Xilinx UltraScale+ FPGA chips and does not support Ethernet and data transfer speeds higher than 100 Gbps.

    -
    +
    -
    + -
    - -
    -

    © Copyright 2024, CESNET z.s.p.o..

    -
    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
    +
    +
    +
    +
    + + + <Device Tree + +
    - +
    + + Minimal NDK application> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/how_to_start.html b/devel/ndk_core/doc/how_to_start.html index d5cfa4d29..fcabe4919 100644 --- a/devel/ndk_core/doc/how_to_start.html +++ b/devel/ndk_core/doc/how_to_start.html @@ -1,65 +1,138 @@ + + + + + - - - - - - - How to start — NDK-FPGA Docs documentation - - - - - - - - - + How to start — NDK-FPGA documentation + + + + + + - - - - -
    - - -
    - -
    -
    -
    - -
    -
    -
    -
    - +
    + +
    +
    +
    +
    +
    -

    How to start

    +

    How to start

    This chapter describes steps for building the FPGA firmware, loading it into the FPGA card, and using it.

    -

    What dependencies are needed to build an FPGA firmware

    +

    What dependencies are needed to build an FPGA firmware

    • The NDK build system is for Linux operating systems only. We recommend using any RHEL-compatible OS, for example, Rocky Linux 8+.

    • The dtc/libfdt package is required. On RHEL-compatible OS, you can use the following command: sudo dnf install dtc.

      • @@ -132,7 +199,7 @@

      What dependencies are needed to build an FPGA firmware

    -

    How to build an FPGA firmware with an NDK-based application

    +

    How to build an FPGA firmware with an NDK-based application

    +
    +
    +
    + + + <Overview + +
    - +
    + + NDK Terminology> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/mem.html b/devel/ndk_core/doc/mem.html index 4cccb2804..1f57f9e60 100644 --- a/devel/ndk_core/doc/mem.html +++ b/devel/ndk_core/doc/mem.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - The Memory Controller — NDK-FPGA Docs documentation - - - - - - - - - + The Memory Controller — NDK-FPGA documentation + + + + + + - - - -
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    The Memory Controller

    +

    The Memory Controller

    Many FPGA cards include external memory (very often DDR4) and the NDK is ready to support them. Depending on the FPGA type and the specific FPGA card, an external memory controller is instantiated in the top-level of the NDK firmware. Currently, three memory controller IPs are supported in the NDK:

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    + + + <The PCIe module + +
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    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + Time Stamp Unit> + +
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    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/mi.html b/devel/ndk_core/doc/mi.html index 67bbc86c6..fc7abdaa4 100644 --- a/devel/ndk_core/doc/mi.html +++ b/devel/ndk_core/doc/mi.html @@ -1,61 +1,142 @@ + + + + + - - - - - - - The MI bus interconnect — NDK-FPGA Docs documentation - - - - - - - - - + The MI bus interconnect — NDK-FPGA documentation + + + + + + - - - -
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    The MI bus interconnect

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    The MI bus interconnect

    The NDK provides the nfb-bus tool and an API for generating read/write memory requests. These requests are transferred via the MI bus in the NDK firmware. This memory-oriented bus is wired throughout the NDK firmware and each part has an allocated address space. The components accessible over the MI bus and their specific address spaces are described in the NDK using a DeviceTree.

    The MI bus interconnection allows easy access to implemented Control/Status Registers (CSR). Communication via the MI bus is always initiated by the software via direct memory access to the PCIe device (FPGA card) memory space. The software sends a read or write PCIe transaction, which is then processed by the MTC module implemented in the FPGA. The MTC module acts as a Master point on the MI bus. It translates requests from the PCIe bus to the MI bus and handles their execution.

    @@ -130,7 +204,7 @@

    A read request to a non-existent/non-implemented memory space in the FPGA can deadlock the NDK firmware or the entire PCIe communication.

    -

    The main allocation of the MI address space

    +

    The main allocation of the MI address space

    An address range of 26 bits is available for the whole NDK firmware. It is divided between the individual parts of the design. The main allocation of the MI address space must be identically described in the VHDL package <NDK-APP-XXX_root_directory>/ndk/core/intel/src/mi_addr_space_pkg.vhd and in the DeviceTree file of the NDK-CORE <NDK-APP-XXX_root_directory>/ndk/core/intel/src/DevTree.tcl. This allocation can also be found below:

    0x00000000-0x000000FF -- Test space (debug R/W registers)
 0x00000100-0x00000FFF -- Reserved space
@@ -158,34 +232,75 @@ 
    The main allocation of the MI address space
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    + -
    - -
    -

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    - - Built with Sphinx using a - theme - provided by Read the Docs. - + + +
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    +
    +
    +
    + + + <The Application + +
    - +
    + + The Network Module> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/pcie.html b/devel/ndk_core/doc/pcie.html index 564f9e7c9..c68fa390e 100644 --- a/devel/ndk_core/doc/pcie.html +++ b/devel/ndk_core/doc/pcie.html @@ -1,52 +1,136 @@ - - - - - - - The PCIe module — NDK-FPGA Docs documentation - - + + + + - - - - - - + The PCIe module — NDK-FPGA documentation + + + + + + - + + + - -
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    The PCIe module

    +

    The PCIe module

    The PCIe module handles all PCIe communication. Its task is to forward/transform PCIe transactions for the DMA controller and the MI bus. The architecture of the PCIe module is divided into two main parts: PCIE_CORE and PCIE_CTRL. Its diagram is shown below.

    ../../_images/pcie_module_arch.drawio.svg @@ -137,7 +205,7 @@

    The PCIe module can support more than one PCIe endpoint. In this case, the individual parts of the PCIe module are appropriately duplicated for each PCIe endpoint. There is also bifurcation support for some PCIe HARD IPs.

    -

    Selecting a PCIe configuration

    +

    Selecting a PCIe configuration

    Before running the FPGA firmware compilation, the target PCIe configuration can be selected using the makefile parameter PCIE_CONF. Without this parameter, the card default configuration is automatically selected. Only some FPGA cards support multiple PCIe configurations. If you enter an unsupported value (for example: PCIE_CONF=1xGen1x16), the console will list the supported configurations on the target FPGA card.

    Examples of some allowed configurations:

      @@ -148,10 +216,10 @@

      Selecting a PCIe configuration -

      The PCIe Core (PCIE_CORE)

      +

      The PCIe Core (PCIE_CORE)

      The PCIe Core varies according to the PCIe Hard IP or FPGA used. The PCIe Core contains the instance(s) of the used PCIe Hard IP, an adapter for converting the AXI/Avalon-ST buses to the MFB buses, the Vendor-Specific Extension Capability (VSEC) registers (implemented in the PCI_EXT_CAP module) containing mainly the DeviceTree firmware description and additional configuration logic. Thus, the main purpose of the PCIe Core is to unify the buses and provide the necessary information about the active PCIe link.

      -

      Supported PCIe Hard IP

      +

      Supported PCIe Hard IP

      A list of the supported PCIe Hard IPs is below. You can select the target architecture by setting the NDK parameter PCIE_MOD_ARCH. According to this parameter, the correct PCIE_CORE module variant is used and the VHDL generic PCIE_ENDPOINT_TYPE is set appropriately.

      -

      The PCIe Control unit (PCIE_CTRL)

      +

      The PCIe Control unit (PCIE_CTRL)

      The PCIe Control unit always includes the MI Transaction Controller (MTC), which transforms the associated PCIe memory transactions into read or write requests on the MI bus. In the case of a read request, the MI response is also transformed back into a PCIe completition transaction and sent back to the host PC. PCIe transactions from the BAR0 address space are allocated to the MTC module. If the NDK uses a DMA controller that requires its own BAR, the PCIe transactions from the DMA-BAR address space (BAR2) are routed directly to the DMA module. This functionality must be enabled via the DMA_BAR_ENABLE parameter.

      Note

      @@ -170,10 +238,10 @@

      The PCIe Control unit (PCIE_CTRL)PTC module, which transforms memory requests (in a simplified format) coming from the DMA into the desired PCIe format and vice versa. The PTC module also implements a completion buffer and handles the allocation of the PCIe TAGs, etc. The PTC can be disabled using the PTC_DISABLE parameter, in which case the DMA requests (in the PCIe transaction format) are directly forwarded to the PCIe Hard IP and vice versa.

      -

      The PCIe module entity

      +

      The PCIe module entity

      -ENTITY PCIE IS
      +ENTITY PCIE IS
      Generics

    Tab. 3Tab. 3 Tab. 4Tab. 4
    @@ -837,34 +905,81 @@

    The PCIe module entity - +
    -     +
    + + The Memory Controller> + +
    - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    - +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/readme.html b/devel/ndk_core/doc/readme.html index 259091aea..40e08a912 100644 --- a/devel/ndk_core/doc/readme.html +++ b/devel/ndk_core/doc/readme.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - NDK Architecture — NDK-FPGA Docs documentation - - - - - - - - - + NDK Architecture — NDK-FPGA documentation + + + + + + - - - -
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    NDK Architecture

    +

    NDK Architecture

    The Network Development Kit (NDK) is available for the selected card based on FPGA. The NDK allows users to quickly and easily develop new network appliances based on FPGA acceleration cards. The NDK is optimized for high throughput and scalable to support 10, 100 and 400 Gigabit Ethernet.

    ../../_images/card_with_ndk.drawio.svg @@ -143,34 +221,52 @@
    -
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    +
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    +
    + + + <NDK Terminology + +
    -
    - -
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    © Copyright 2024, CESNET z.s.p.o..

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    - - Built with Sphinx using a - theme - provided by Read the Docs. - - - +
    + + The Application> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/terminology.html b/devel/ndk_core/doc/terminology.html index c1d75c2a6..7b6d0ccce 100644 --- a/devel/ndk_core/doc/terminology.html +++ b/devel/ndk_core/doc/terminology.html @@ -1,63 +1,139 @@ + + + + + - - - - - - - NDK Terminology — NDK-FPGA Docs documentation - - - - - - - - - + NDK Terminology — NDK-FPGA documentation + + + + + + - - - -
    - - -
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    NDK Terminology

    +

    NDK Terminology

    This chapter explains frequently used terms.

    -

    Ethernet Port

    +

    Ethernet Port

    In our terminology, the Ethernet Port corresponds to one physical network port, typically one optical cage (for example, QSFP28 or QSFP-DD).

    -

    Ethernet Lanes

    +

    Ethernet Lanes

    The term Ethernet Lanes refer to high-speed serial lines used in the physical layer of the Ethernet protocol. Each type of Ethernet Port can use a different number of Ethernet Lanes (for example, QSFP28 uses 4, and QSFP-DD uses 8).

    -

    Ethernet Channel

    +

    Ethernet Channel

    Each Ethernet Port can use a different number of high-speed serial lines (Ethernet Lanes), typically 4 or 8. Different Ethernet standards (like 100 GbE, 25 GbE,…) require one or more of these lanes. For port QSFP28, where there are 4 lanes running at 28 Gbps, 100 GbE standard would take up all 4 lanes together forming one Ethernet channel. For another Ethernet standard like 25 GbE, one lane is enough. Using all 4 lanes, we would get 4 separate 25 Gigabit Ethernet channels.

    -

    Ethernet Stream

    +

    Ethernet Stream

    An Ethernet Stream is a group of data interfaces (RX and TX) that transmits Ethernet packets from/to a selected number of Ethernet Channels. In our platform, the number of Ethernet Streams typically corresponds to the number of Ethernet Ports.

    -

    DMA Stream

    +

    DMA Stream

    An DMA Stream is a group of data interfaces (RX and TX) that transmits DMA packets from/to DMA module. In our platform, the number of DMA Streams typically corresponds to the number of Ethernet Streams (and therefore Ethernet Ports).

    -

    DMA Channel

    +

    DMA Channel

    The DMA controller supports data transmission in each direction (RX and TX) in multiple independent queues, which in our terminology we refer to as DMA channels.

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    -
    + -
    - -
    -

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    + + + <How to start + +
    - +
    + + NDK Architecture> + +
    -
    -
    -
    - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/ndk_core/doc/testing.html b/devel/ndk_core/doc/testing.html index 1a65021c7..5313d6461 100644 --- a/devel/ndk_core/doc/testing.html +++ b/devel/ndk_core/doc/testing.html @@ -1,67 +1,169 @@ + + + + + - - - - - - - NDK testing — NDK-FPGA Docs documentation - - - - - - - - - + NDK testing — NDK-FPGA documentation + + + + + + - - - -
    - - -
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    NDK testing

    +

    NDK testing

    This chapter describes how the NDK firmware and its HDL components can be tested:

    -

    Testing R/W access to the scratch registers

    +

    Testing R/W access to the scratch registers

    The NDK firmware implements 64 32-bit scratch registers for testing purposes. Like other parts of the firmware, they are accessible via the MI bus. This address space is (among other things) stored in the DeviceTree. The nfb-bus tool can be used for easy R/W access to any register in the firmware that is mapped to the MI bus. The following example shows how to:

    • read the first scratch register (the offset is 0x0 in the byte format) in the MI TEST SPACE component (selected using the DeviceTree path),

      • @@ -139,7 +213,7 @@

      You can test R/W requests to the NDK firmware address space of these scratch registers however you want. Similarly, in the future, you can access the registers in your own application that you build on the NDK platform.

    -

    GLS module tutorial

    +

    GLS module tutorial

    The NDK firmware may include a GLS module that is instantiated in each DMA stream between the application core and the DMA controller. The GLS module is used for testing purposes and contains HW packet generators, speed meters, and datapath switches. Please refer to the GLS module documentation for a more information.

    The GLS module also comes with a Python script (<NDK-APP-XXX_root_directory>/ndk/ofm/comp/mfb_tools/debug/gen_loop_switch/sw/gls_mod.py) that can be used to quickly perform several basic tests (modes). For example, you can measure the throughput of the NDK firmware. A list of tests can be obtained by running this script without parameters:

    $ python3 gls_mod.py
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    + Git branch: devel
    Git hash: ea2302fb +
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    + \ No newline at end of file diff --git a/devel/ndk_core/doc/tsu.html b/devel/ndk_core/doc/tsu.html index cde14250e..e5d3733d0 100644 --- a/devel/ndk_core/doc/tsu.html +++ b/devel/ndk_core/doc/tsu.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Time Stamp Unit — NDK-FPGA Docs documentation - - - - - - - - - + Time Stamp Unit — NDK-FPGA documentation + + + + + + - - - -
    - - -
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    Time Stamp Unit

    +

    Time Stamp Unit

    The Time Stamp Unit (TSU) is used to generate accurate timestamps. The Time Stamp Unit is implemented by the TSU_GEN component. This can be generated by the Ethernet clock signal or can be from an external source such as the pulse per second (PPS) signal (this feature is not yet implemented). The TSU is disabled by default and must first be enabled using the nfb-tsu tool. @@ -131,7 +204,7 @@

    The timestamps are transmitted to the Network Module and the Application. The Network Module uses timestamps to mark the reception of each packet. This information is then available in the packet’s metadata.

    -

    Timestamp signals

    +

    Timestamp signals

    Generic

    @@ -161,7 +234,7 @@

    Timestamp signals -

    Timestamp format

    +

    Timestamp format

    The TSU_TS_NS signal contains a timestamp in the Nanoseconds format described below. Time is counted in the Unix Time epoch.

    Name
    @@ -182,34 +255,76 @@

    Timestamp format - +
    + + Configuration files and parameters> + +
    - - - - - - + + + +
    + Git branch: devel
    Git hash: ea2302fb +
    + +

    + +

    + \ No newline at end of file diff --git a/devel/nic.html b/devel/nic.html index 78a53bea7..a64788edc 100644 --- a/devel/nic.html +++ b/devel/nic.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - Network Tools — NDK-FPGA Docs documentation - - - - - - - - - + Network Tools — NDK-FPGA documentation + + + + + + - - - -
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    Network Tools

    +

    Network Tools

    This chapter describes the components that are used to receive and transmit Ethernet packets. The network components are typically located in the comp/nic/ directory in the OFM repository.

    @@ -130,34 +208,52 @@

    Network Tools

    -
    +
    +
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    + \ No newline at end of file diff --git a/devel/objects.inv b/devel/objects.inv index 739c9f364..eda16a7a1 100644 Binary files a/devel/objects.inv and b/devel/objects.inv differ diff --git a/devel/pcie.html b/devel/pcie.html index 710c970a8..d44e009ed 100644 --- a/devel/pcie.html +++ b/devel/pcie.html @@ -1,52 +1,136 @@ + + + + + - - - - - - - PCIe Tools — NDK-FPGA Docs documentation - - - - - - - - - + PCIe Tools — NDK-FPGA documentation + + + + + + - - - -
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    PCIe Tools

    +

    PCIe Tools

    This chapter describes the components that are used for communication via the PCIe interface. A description of DMA controllers is also included. The PCIe components are typically located in the comp/pcie/ directory in the OFM repository. DMA Calypte is located in the comp/dma/ directory. Closed-source DMA Medusa IP is located in a separate submodule.

    Content:

    @@ -139,34 +217,52 @@

    PCIe Tools

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    + + + <40GE Ethernet PHY for Ultrascale+ FPGAs + +
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    © Copyright 2024, CESNET z.s.p.o..

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Final phase (SaveDesign)": [[166, "final-phase-savedesign"]], "40GE Ethernet PHY for Ultrascale+ FPGAs": [[107, null]], "A few timing diagrams": [[87, "a-few-timing-diagrams"]], "AMD Alveo U200": [[167, null]], "AMD Alveo U55C": [[168, null]], "AMD VCU118@VU9P": [[169, null]], "AMM_GEN": [[29, null]], "AMM_PROBE": [[30, null]], "ASFIFOX": [[4, null]], "AVMM Agent": [[122, null]], "AVST CRDT Agent": [[123, null]], "AXI Agent": [[124, null]], "Adapter": [[109, "adapter"], [111, "adapter"]], "Adding constants to the VHDL package": [[184, "adding-constants-to-the-vhdl-package"], [184, "id4"]], "Additional Features": [[11, "additional-features"], [80, "additional-features"]], "Additional features": [[19, "additional-features"]], "Address Manager": [[34, null]], "Address space": [[85, "address-space"], [107, "address-space"], [112, "id2"]], "Address space and configuration": [[67, "address-space-and-configuration"]], "Address space size": [[27, "address-space-size"]], "Advanced synthesis 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"block-diagram"], [6, "block-diagram"], [11, "block-diagram"], [17, "block-diagram"], [23, "block-diagram"], [60, "block-diagram"], [65, "block-diagram"], [71, "block-diagram"], [75, "block-diagram"], [118, "block-diagram"], [119, "block-diagram"]], "Board Revision": [[174, "board-revision"]], "Board Test Scripts": [[174, "board-test-scripts"]], "Boot Instructions": [[173, "boot-instructions"]], "Boot instructions": [[171, "boot-instructions"], [172, "boot-instructions"]], "Boot instructions (initial)": [[170, "boot-instructions-initial"]], "Build System": [[166, null]], "Build system files": [[184, "build-system-files"]], "Build tips": [[179, "build-tips"]], "Byte Array Sequence": [[125, "byte-array-sequence"]], "Byte Array agent": [[125, null]], "Byte Array monitor": [[125, "byte-array-monitor"]], "Byte Array sequence item": [[125, "byte-array-sequence-item"]], "Byte Array to LII Sequence": [[126, "byte-array-to-lii-sequence"], [127, "byte-array-to-lii-sequence"]], "Byte Array to LII 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42, 43, 44, 46, 47, 48, 49, 50, 54, 55, 56, 58, 59, 60, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 74, 75, 77, 78, 81, 82, 83, 84, 86, 87, 88, 90, 91, 96, 98, 99, 102, 107, 108, 109, 111, 113, 114, 116, 117, 119, 120, 121, 123, 133, 134, 135, 136, 144, 147, 149, 150, 151, 160, 161, 167, 169, 175, 176, 179, 180, 181, 183, 184, 189, 192, 195], "20": [17, 19, 31, 60, 107, 119, 131, 144], "200": [18, 67, 107, 146, 180, 188], "2000": 144, "20000": 108, "200000": 144, "200000000": 71, "200g2": [172, 174], "200mhz": 188, "201": 107, "2014": 1, "2015": 1, "2019": [17, 19, 119], "20208": [156, 161], "2022": [167, 169, 185, 189], "2023": 59, "2024": [59, 166, 189], "2048": [27, 65, 71], "2048b": [67, 180], "21": 109, "218": 107, "219": 107, "21st": 76, "22": [31, 109, 185, 189], "23": [0, 22, 90, 109, 183, 187], "24": [18, 22, 31, 35, 39, 42, 45, 46, 61, 75, 76, 101, 144, 183, 187], "241581": 31, "248": 47, "25": [3, 22, 107, 180, 183, 187, 194], "250": [31, 46], "255": [24, 47, 107, 148], "256": [7, 8, 10, 31, 46, 47, 90, 113, 116, 152, 183], "256b": 113, "2570": 31, "25g": 179, "25g8": [170, 171, 172, 174, 177], "25gbase": 188, "25ge": 179, "25mhz": 107, "26": [22, 24, 31, 183, 187, 191], "2629629": 13, "265549": 0, "265625": 107, "266660": [31, 183], "26b": 112, "27": [22, 109, 183, 187], "27238": 0, "28": [22, 109, 148, 183, 187, 194], "288": 5, "288000": [79, 101, 105], "29": [22, 183, 187], "2b": 121, "2hz": 121, "2l": 168, "2nd": [3, 67, 76], "2x": [30, 109, 167, 168, 169, 171, 172, 175, 176, 177], "2x100gbe": [167, 168, 169, 175, 176], "2x100ge": [170, 171, 173, 177], "2x200gbe": [172, 174], "2x200ge": 187, "2x40gbe": [172, 174], "2x40ge": 187, "2xgen4x8x8": 192, "2xgen5x8x8": 192, "3": [0, 5, 11, 12, 15, 18, 21, 25, 27, 29, 30, 31, 33, 35, 47, 49, 58, 67, 68, 76, 83, 84, 85, 87, 88, 98, 102, 104, 107, 109, 111, 112, 115, 116, 117, 121, 133, 174, 179, 180, 183, 184, 186, 192, 195], "30": [22, 148, 183, 187], "300": 188, "300000": 24, "31": [22, 47, 49, 90, 107, 109, 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"400": [46, 75, 107, 109, 111, 159, 180, 186, 188, 193], "400g": [59, 67, 76, 172, 174], "400g1": [172, 174, 180], "401": 107, "4096": [14, 27, 59], "40g": 107, "40g2": [172, 174], "40ge": 197, "41": 31, "412": 148, "418": 107, "419": 107, "42": [0, 107], "425": 0, "427": 0, "4294967295": 0, "43": 195, "4321": 87, "435": 31, "44": 107, "441": 31, "45": [107, 189], "453": 31, "459": 31, "46": 0, "465": 31, "47": 109, "471": 31, "477": 31, "48": [47, 65, 71, 109, 180, 183], "483": 31, "489": 31, "48th": 76, "49": 107, "495": 31, "4b": [22, 112], "4n": 144, "4x": [173, 176], "4x100gbe": [172, 174, 176], "4x100ge": 187, "4x10ge": 187, "4x25": 187, "4x25ge": 187, "5": [0, 19, 23, 25, 30, 31, 49, 58, 67, 75, 89, 90, 107, 109, 116, 135, 136, 149, 166, 180, 185, 187, 189, 195], "50": [107, 144, 148, 152, 180], "500": [146, 152, 166], "501": 31, "50118": 31, "503": 0, "50g8": [172, 174], "50gb": 67, "50th": 76, "51": 107, "511": [47, 110], "512": [4, 6, 9, 16, 24, 31, 46, 47, 48, 59, 77, 78, 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"74899": 0, "75": 31, "75gb": 67, "78": [0, 195], "79": 195, "7seri": [3, 4, 5, 14, 15, 16, 58, 62, 64, 66, 69, 79, 86, 101, 105, 117], "8": [0, 9, 14, 16, 23, 24, 25, 30, 31, 33, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 81, 82, 83, 84, 86, 87, 88, 89, 90, 100, 104, 105, 106, 107, 109, 110, 111, 113, 116, 117, 121, 135, 136, 144, 146, 152, 180, 183, 184, 185, 187, 189, 192, 194, 195], "80": [31, 47], "802": 107, "81": [107, 113], "82": 107, "83": [0, 107, 195], "85": [108, 113, 117], "852": 0, "87": 31, "88": [113, 117], "88513": 0, "8x10gbe": [172, 174], "8x10ge": [170, 171, 177, 187], "8x25gbe": [172, 174], "8x25ge": [170, 171, 177, 187], "8x50gbe": [172, 174], "8x50ge": 187, "9": [16, 25, 30, 42, 44, 74, 89, 107, 120, 121], "90": [108, 144], "91": 179, "93": [0, 31], "94": [185, 189], "95415f0": 185, "96": [0, 47, 117, 195], "96b": 121, "97": 31, "98": 87, "98xx": 87, "99": 31, "999": [121, 196], "A": [4, 5, 11, 16, 17, 18, 21, 26, 39, 40, 45, 47, 58, 65, 67, 76, 110, 118, 128, 131, 138, 139, 142, 143, 144, 146, 174, 183, 184, 185, 187, 188, 191, 192, 195, 198], "AND": [34, 55, 56, 57, 73, 79, 89, 90, 102, 109, 160, 180, 183, 192], "And": [0, 33, 58, 68, 147, 184], "As": [67, 76, 87, 89, 109, 111, 129, 183, 184, 187], "At": [17, 21, 59, 60, 67, 68, 80, 87, 118, 126, 127, 144, 166], "BE": [22, 67, 87, 88, 152], "BY": 183, "Be": [27, 148], "But": [11, 19, 67, 76, 87, 146], "By": [0, 48, 67, 111, 192], "FOR": [34, 164], "For": [0, 1, 6, 7, 11, 14, 17, 18, 19, 31, 32, 41, 42, 45, 55, 57, 59, 67, 68, 76, 77, 79, 80, 87, 89, 91, 99, 107, 109, 110, 111, 112, 113, 115, 117, 118, 119, 122, 124, 126, 127, 128, 131, 139, 142, 143, 144, 145, 147, 150, 151, 152, 154, 166, 167, 168, 169, 183, 184, 187, 189, 193, 194, 195], "IN": [17, 135, 136, 149], "If": [0, 4, 7, 14, 16, 18, 19, 21, 25, 31, 42, 57, 58, 63, 67, 68, 75, 77, 80, 87, 88, 89, 99, 102, 109, 111, 116, 118, 126, 127, 131, 144, 146, 147, 148, 159, 166, 179, 183, 185, 186, 187, 188, 189, 192, 195], "In": [0, 6, 7, 11, 12, 17, 23, 31, 35, 39, 45, 58, 59, 67, 68, 71, 75, 76, 83, 87, 88, 89, 90, 91, 104, 110, 111, 118, 119, 128, 129, 131, 135, 136, 139, 142, 143, 144, 147, 151, 152, 166, 183, 185, 187, 190, 192, 194, 195], "It": [0, 1, 7, 18, 23, 27, 29, 37, 44, 48, 50, 54, 58, 60, 63, 65, 67, 68, 70, 77, 78, 87, 89, 90, 100, 107, 109, 112, 116, 118, 119, 120, 122, 124, 128, 129, 133, 138, 139, 142, 143, 144, 146, 152, 156, 159, 160, 161, 164, 166, 179, 180, 183, 184, 185, 187, 191, 193], "Its": [31, 37, 59, 110, 187, 192], "NO": [146, 167, 168, 169, 171, 172, 179], "NOT": [68, 109], "No": [47, 101, 118, 128, 139, 142, 186, 188], "Not": [48, 59, 71, 76, 104, 113, 173, 188], "OF": 57, "ON": 71, "OR": [22, 89, 160, 183, 187], "ORed": 89, "Of": [60, 109, 111, 113, 183], "On": [19, 88, 104, 108, 110, 118, 119, 135, 136, 149, 170, 171, 172, 187, 189], "One": [0, 10, 29, 68, 70, 99, 101, 105, 124, 128, 141, 142, 144, 147, 160, 166], "Or": 67, "Such": [11, 21, 58, 131, 185], "That": [60, 76, 85, 87, 89, 144, 150, 187], "The": [1, 2, 3, 4, 5, 6, 8, 11, 12, 14, 16, 17, 18, 19, 21, 25, 26, 27, 29, 31, 33, 34, 35, 36, 38, 39, 40, 41, 43, 44, 45, 46, 49, 50, 52, 54, 55, 57, 58, 59, 60, 61, 65, 67, 68, 69, 71, 74, 75, 76, 77, 80, 82, 83, 85, 87, 88, 89, 90, 92, 93, 96, 99, 104, 106, 107, 109, 110, 111, 112, 113, 114, 116, 117, 118, 119, 121, 122, 123, 124, 125, 128, 129, 131, 133, 134, 137, 138, 139, 141, 142, 143, 144, 145, 146, 147, 148, 150, 152, 153, 154, 156, 159, 160, 161, 162, 164, 165, 173, 174, 179, 180, 184, 185, 188, 189, 193, 194, 195, 196, 197, 198], "Their": [104, 166], "Then": [0, 24, 29, 31, 60, 67, 71, 76, 87, 89, 119, 144, 146, 151, 184, 185, 187], "There": [4, 5, 11, 23, 25, 31, 38, 47, 59, 62, 65, 67, 71, 72, 87, 89, 92, 95, 98, 109, 110, 111, 119, 122, 126, 127, 128, 129, 130, 131, 133, 135, 136, 141, 142, 143, 144, 145, 146, 147, 149, 152, 160, 166, 179, 180, 183, 184, 185, 187, 192, 195], "These": [0, 17, 47, 48, 58, 60, 67, 68, 76, 83, 87, 89, 104, 113, 119, 122, 129, 131, 144, 166, 179, 183, 184, 186, 187, 191, 196], "To": [11, 12, 17, 18, 19, 21, 29, 31, 34, 60, 67, 68, 71, 80, 88, 89, 104, 109, 111, 118, 129, 130, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 185, 187, 189], "WITH": [55, 56, 57], "Will": 31, "With": [6, 19, 31, 58, 87, 144, 160, 185], "_conf": 184, "_const": 184, "_data": [47, 123, 144], "_det": 107, "_dst_rdy": [47, 183, 187], "_eop": 47, "_eop_po": 47, "_hdr": 123, "_help_": 179, "_meta": 144, "_n": 47, "_range_max_numb": 148, "_rx": 144, "_sop": 47, "_sop_po": 47, "_src_rdy": 47, "_tx": 144, "a0": 87, "a1": [87, 110], "a2": [87, 110], "a3": 87, "a5": 87, "ab": 13, "abcdef0123456789": 184, "abid": 110, "abil": [18, 76, 80, 107, 187], "abl": [18, 19, 23, 24, 56, 80, 87, 104, 109, 111, 118, 144, 164], "abnorm": 89, "about": [11, 17, 23, 24, 25, 35, 41, 77, 78, 79, 80, 89, 109, 113, 129, 144, 166, 183, 184, 185, 187, 189, 192], "abov": [3, 17, 47, 60, 67, 68, 76, 89, 104, 119, 121, 125, 128, 137, 138, 142, 143, 147, 166, 167, 168, 169, 184, 187, 193], "abrevi": 184, "abstract": [16, 144], "academi": 188, "acc": 44, "acceler": [155, 159, 193], "accept": [4, 17, 23, 33, 36, 40, 45, 47, 60, 76, 83, 87, 89, 102, 104, 146, 147], "access": [0, 11, 18, 23, 26, 27, 31, 37, 39, 44, 45, 46, 49, 67, 87, 88, 109, 111, 112, 121, 144, 163, 164, 184, 185, 190, 191, 193], "accident": 185, "accord": [0, 4, 14, 16, 35, 40, 41, 42, 58, 59, 60, 67, 70, 71, 75, 76, 82, 83, 87, 89, 90, 104, 107, 109, 110, 111, 144, 164, 173, 180, 184, 185, 187, 192], "accordingli": [67, 89, 110, 129], "account": [19, 58, 185], "accross": [118, 119], "accumul": [18, 19, 59, 60, 65, 67, 71, 98, 129, 130], "accumult": 18, "accur": [121, 193, 196], "achiev": [3, 17, 96, 144, 184, 187], "ack": 183, "aclk": 20, "acm": 13, "across": [18, 58, 184], "act": [23, 27, 89, 146, 191], "action": [35, 68], "activ": [1, 11, 31, 44, 62, 80, 87, 95, 96, 109, 111, 119, 121, 125, 128, 129, 133, 135, 136, 137, 138, 139, 142, 143, 144, 147, 149, 150, 151, 183, 187, 192], "activity_rx": 180, "activity_tx": 180, "actual": [5, 6, 11, 17, 18, 37, 39, 44, 60, 67, 89, 109, 111, 121, 144, 146, 147, 183, 187], "actuali": 68, "acumul": [126, 127], "ad": [10, 27, 31, 46, 50, 60, 67, 109, 110, 120, 144, 166, 188], "adapt": [187, 192], "adapter_error": 109, "adapter_link_up": 109, "adc": 164, "adc_sensor": 164, "add": [8, 10, 11, 21, 25, 27, 38, 47, 68, 121, 129, 144, 146, 152, 160, 174, 183, 184, 187], "add_callback": 150, "add_sequ": [128, 139, 142, 143, 144], "adder": 160, "addit": [8, 46, 47, 82, 160, 161, 166, 185, 187, 192], "addition": [31, 106, 187], "additionali": 59, "addr": [31, 32, 34, 39, 42, 87, 88, 111, 144, 146, 152, 185], "addr_bas": 34, "addr_channel": 34, "addr_data_bas": 35, "addr_data_channel": 35, "addr_data_mask": 35, "addr_data_sw_point": 35, "addr_header_bas": 35, "addr_header_channel": 35, "addr_header_mask": 35, "addr_header_sw_point": 35, "addr_mask": [34, 84, 89], "addr_sw_point": 34, "addr_vld": 34, "addr_width": [34, 35, 82, 83, 84, 85, 86, 87, 89, 144, 146], "addra": 15, "addrb": 15, "address": [0, 11, 13, 14, 16, 17, 18, 19, 22, 23, 29, 30, 31, 32, 35, 37, 39, 41, 42, 43, 45, 48, 49, 61, 71, 75, 76, 80, 82, 83, 84, 87, 88, 90, 106, 109, 111, 116, 117, 121, 122, 144, 146, 148, 161, 164, 180, 183, 185, 187, 192, 195], "address_width": 122, "adher": [110, 144, 184], "adjac": 187, "adjust": [8, 58, 67, 75, 144, 184], "adn": 31, "adress": [26, 45, 83], "advanc": [89, 124, 145, 161], "advantag": [12, 17, 89, 144], "advis": 7, "aempti": [5, 6, 105], "affect": [4, 17, 37, 39, 46, 64, 65, 67, 184], "after": [3, 17, 18, 19, 23, 26, 27, 31, 32, 33, 34, 42, 44, 45, 52, 57, 58, 59, 60, 63, 67, 68, 71, 75, 83, 85, 87, 89, 93, 109, 110, 118, 130, 131, 144, 145, 150, 164, 166, 170, 171, 172, 173, 179, 185, 187, 189, 195], "after_on": 160, "afterward": 18, "aful": [5, 6, 105], "afull_offset": 81, "again": [0, 58, 63, 67, 87, 118, 183, 195], "agent": [126, 127, 128, 129, 130, 132, 133, 139, 140, 141, 142, 143, 200], "agent_rx": 144, "agent_rx_data": 123, "agent_rx_hdr": 123, "agent_tx": 144, "agent_tx_data": 123, "agent_tx_hdr": 123, "agfb014r24a2e2v": 177, "agfb014r24b2e2v": 170, "agi": 179, "agi027r": [172, 180], "agib027r29a1e2vr0": [172, 174], "agib027r29a1e2vr3": 174, "agilex": [3, 4, 5, 13, 14, 16, 23, 24, 31, 34, 35, 46, 50, 52, 54, 58, 59, 60, 65, 67, 70, 71, 74, 81, 83, 84, 93, 96, 98, 100, 101, 102, 106, 109, 111, 116, 117, 156, 161, 166, 187, 188, 190], "agreg": 164, "aim": 87, "algorithm": [19, 74, 75, 90, 131, 144, 164], "alhough": 110, "alias": 78, "alig": 94, "align": [19, 23, 33, 36, 38, 47, 59, 60, 68, 76, 88, 94, 100, 104, 107, 110, 117, 144, 164], "all": [0, 6, 11, 17, 18, 19, 21, 22, 25, 27, 29, 31, 32, 40, 41, 42, 43, 44, 45, 47, 48, 49, 57, 58, 60, 61, 64, 67, 68, 69, 71, 75, 76, 80, 87, 88, 89, 90, 91, 93, 98, 104, 107, 109, 111, 112, 113, 118, 119, 120, 122, 123, 125, 126, 127, 128, 129, 130, 131, 135, 136, 137, 138, 139, 142, 144, 146, 147, 149, 150, 151, 152, 160, 166, 179, 180, 183, 184, 185, 187, 188, 189, 192, 194], "alloc": [183, 192], "allow": [3, 4, 6, 11, 14, 16, 17, 18, 19, 20, 21, 35, 37, 39, 42, 44, 46, 48, 49, 50, 52, 56, 58, 67, 68, 76, 77, 82, 92, 94, 104, 106, 107, 109, 110, 111, 116, 118, 129, 135, 136, 144, 154, 156, 159, 160, 161, 174, 179, 180, 183, 184, 186, 187, 189, 191, 192, 193], "allow_single_fifo": 6, "allwai": [62, 68, 108], "almost": [5, 6, 19, 65, 71, 81, 156, 164, 195], "almost_empti": [79, 105], "almost_empty_offset": [4, 5, 6, 77, 79, 105], "almost_ful": [79, 105], "almost_full_offset": [4, 5, 6, 77, 79, 105], "alon": 11, "along": [8, 59, 60, 87, 109, 173, 187], "alow": 31, "alreadi": [19, 27, 42, 58, 110, 119, 166, 184, 185, 189], "also": [0, 3, 4, 6, 7, 8, 11, 13, 16, 19, 24, 25, 27, 31, 35, 36, 37, 47, 58, 59, 60, 67, 68, 75, 78, 82, 85, 87, 89, 104, 107, 109, 110, 118, 119, 126, 127, 128, 129, 130, 131, 139, 142, 144, 147, 148, 159, 160, 161, 166, 170, 171, 172, 176, 179, 183, 184, 185, 186, 187, 191, 192, 193, 195, 198], "altera": [4, 86, 166], "altera_syncram": 161, "altern": [27, 161], "although": [67, 76, 166, 167, 168, 169], "altogeth": [76, 187], "alu": 160, "alwai": [17, 23, 33, 36, 38, 67, 87, 88, 89, 104, 109, 110, 144, 146, 187, 188, 189, 191, 192], "am": 107, "am_in": 107, "amd": [46, 135, 136, 149, 188], "american": 87, "amm": [29, 30, 31, 32, 183], "amm_addr": 31, "amm_addr_width": 31, "amm_address": 31, "amm_burst_count": 31, "amm_burst_count_width": 31, "amm_clk": 31, "amm_data_width": [29, 31], "amm_freq_khz": [24, 31, 183], "amm_gen": [31, 32], "amm_mux": 31, "amm_prob": 31, "amm_probe_en": 31, "amm_read": 31, "amm_read_data": 31, "amm_read_data_valid": 31, "amm_readi": 31, "amm_rst": 31, "amm_writ": 31, "amm_write_data": 31, "among": [183, 187, 191, 195], "amount": [6, 7, 13, 14, 19, 38, 49, 60, 63, 65, 67, 76, 91, 102, 104, 129, 130, 149, 161], "an": [0, 5, 6, 7, 11, 18, 19, 22, 26, 27, 39, 42, 45, 46, 48, 49, 50, 58, 61, 63, 67, 68, 70, 71, 76, 80, 82, 87, 89, 106, 107, 110, 112, 116, 119, 122, 129, 131, 134, 135, 136, 138, 139, 144, 146, 148, 150, 152, 154, 159, 160, 161, 164, 166, 170, 171, 172, 173, 174, 179, 183, 184, 186, 187, 190, 191, 192, 194, 195, 196], "analysi": [125, 126, 127, 130, 131, 135, 136, 137, 138, 141, 147, 149, 179], "analysis_expoert": 131, "analysis_export": [128, 131, 139, 142, 143, 144], "analysis_export_data": 144, "analysis_export_meta": 144, "analysis_export_rx": 144, "analysis_export_rx_packet": 144, "analysis_export_tx": 144, "analysis_export_tx_packet": 144, "analysis_imp": 144, "analysis_imp_dut": [131, 144], "analysis_imp_model": [131, 144], "analysis_imp_reset": 144, "analysis_imp_rx": 144, "analysis_imp_tx": 144, "analysis_port": 144, "analyz": [27, 60, 93, 109], "ancestor": 166, "anew": 93, "ani": [0, 5, 10, 11, 17, 19, 21, 25, 52, 55, 56, 57, 58, 64, 66, 67, 68, 76, 77, 79, 85, 87, 88, 89, 91, 104, 109, 128, 129, 139, 142, 143, 144, 148, 151, 159, 166, 185, 189, 195], "anlysis_export": 144, "annot": 144, "announc": 112, "anot": 44, "anoth": [18, 19, 21, 31, 60, 68, 71, 76, 80, 87, 89, 110, 121, 131, 139, 142, 144, 152, 161, 164, 166, 184, 185, 194], "another_lib": 166, "anotherlib": 166, "answer": 87, "anyhow": 87, "anyth": [21, 65, 67, 89, 131, 179], "anywher": [67, 166], "ap": 173, "apertur": [116, 117], "api": [183, 188, 191], "app": [0, 27, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 180, 183, 185, 189, 190, 191, 195], "app_archgrp": 184, "app_clk": 183, "app_conf": [27, 189], "app_cor": [0, 185], "app_core_minimal_0": [0, 185], "app_core_minimal_1": [0, 185], "app_reset": 183, "app_root_directori": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176], "appart": [19, 68, 119], "appear": [9, 68, 76, 80, 110], "append": [129, 166], "appli": [3, 20, 35, 47, 58, 60, 61, 65, 67, 68, 104, 109, 110, 179], "applianc": 193, "applic": [27, 67, 104, 113, 166, 167, 169, 173, 185, 186, 190, 191, 193, 195, 196], "application_cor": [183, 184], "application_core_entity_onli": 184, "approach": [13, 67, 87, 144, 166], "appropri": [33, 65, 71, 75, 112, 152, 166, 183, 187, 192], "approx": [4, 77], "approxim": 174, "aproxim": 19, "ar": [0, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 16, 17, 18, 19, 21, 22, 23, 24, 26, 27, 29, 33, 34, 35, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 52, 55, 57, 58, 59, 60, 62, 63, 64, 65, 67, 68, 71, 72, 74, 75, 76, 82, 83, 85, 87, 89, 90, 93, 95, 98, 100, 101, 104, 107, 109, 110, 111, 112, 113, 115, 117, 118, 119, 121, 122, 123, 128, 129, 130, 131, 133, 135, 136, 139, 142, 143, 144, 146, 147, 148, 149, 150, 152, 153, 154, 157, 158, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 174, 175, 176, 177, 179, 180, 183, 184, 185, 186, 187, 190, 191, 192, 194, 195, 196, 197, 198], "arbirarili": 20, "arbitr": 164, "arbitrari": [12, 16, 17, 20, 37, 58, 63, 68, 75, 87, 104, 110, 144, 164], "arbitrarili": 87, "arch": 144, "archgrp": [166, 184], "archgrp_arr": 184, "architectur": [5, 6, 11, 14, 49, 62, 79, 101, 105, 118, 144, 156, 161, 166, 180, 184, 186, 187, 189, 190, 192], "archiv": [10, 166], "ardi": [83, 87, 146], "area": [34, 46], "aren": [89, 166], "argument": [23, 31, 32, 144, 148], "arith": 144, "around": [14, 24, 59, 68, 88, 89, 118, 119], "arrai": [21, 59, 73, 118, 128, 132, 139, 142, 144, 147, 152, 160, 161, 184], "arrang": [59, 104, 121], "array_size_set": [125, 137, 138], "arria": 161, "arria10": [4, 5, 14, 16, 79, 101, 105], "arriv": [17, 21, 58, 59, 80, 109, 110, 126, 127, 164], "arrow": 67, "asap": 101, "asfifo": [111, 119, 156, 162], "asfifo_bram": 156, "asfifo_bram_block": 156, "asfifo_bram_datamux": 156, "asfifo_bram_releas": 156, "asfifo_bram_xilinx": 156, "asfifox": [156, 162], "asic": 144, "asid": 11, "assembl": [59, 144], "assembli": 59, "assert": [7, 12, 29, 31, 60, 70, 71, 75, 76, 83, 87, 91, 104, 107, 109, 111, 126, 127, 134, 135, 136, 144, 146, 147, 152], "assign": [17, 19, 89, 109, 118, 119, 147, 164, 179, 183, 184], "associ": [62, 69, 89, 113, 144, 184, 188, 192], "assum": [144, 192], "asx4": 191, "async": [107, 163], "async_bus_handshak": [1, 166], "async_gener": 1, "async_mask": 20, "async_open_loop": 1, "async_open_loop_smd": 1, "async_reset": [1, 164], "asynch": 48, "asynchron": [2, 4, 11, 61, 80, 82, 151, 179], "atom": [17, 109], "attach": [149, 173], "attempt": [6, 67], "attent": 67, "attribut": 68, "author": [185, 189], "auto": [5, 6, 10, 31, 79, 101, 105, 106, 118, 183], "autogener": 122, "autom": 31, "automat": [5, 6, 10, 18, 29, 58, 67, 71, 144, 156, 161, 166, 186, 190, 192], "automaticli": 78, "auxiliari": [41, 58, 59, 67, 113, 116, 162, 186], "avail": [0, 4, 10, 19, 23, 25, 31, 42, 49, 58, 67, 71, 80, 90, 107, 109, 111, 118, 119, 121, 144, 166, 173, 183, 187, 189, 191, 192, 193, 195, 196], "avalon": [0, 23, 31, 83, 122, 183, 187, 190, 192], "averag": [17, 19, 24, 25, 30, 45, 75], "avg": [0, 31, 75], "avmm": [83, 132, 183, 187], "avmm_address": 83, "avmm_byteen": 83, "avmm_read": 83, "avmm_readdata": 83, "avmm_readdatavalid": 83, "avmm_waitrequest": 83, "avmm_writ": 83, "avmm_writedata": 83, "avoid": [11, 19, 23, 58, 67, 71, 85, 183, 184, 187], "avst": [109, 111, 132, 187], "await": [17, 93], "awar": [67, 166], "axi": [84, 113, 117, 119, 132, 139, 183, 192], "axi4": [84, 190], "axi_araddr": 84, "axi_arburst": 84, "axi_arid": 84, "axi_arlen": 84, "axi_arprot": 84, "axi_arreadi": 84, "axi_ars": 84, "axi_arvalid": 84, "axi_awaddr": 84, "axi_awburst": 84, "axi_awid": 84, "axi_awlen": 84, "axi_awprot": 84, "axi_awreadi": 84, "axi_aws": 84, "axi_awvalid": 84, "axi_bid": 84, "axi_breadi": 84, "axi_bresp": 84, "axi_bvalid": 84, "axi_ccuser_width": 113, "axi_cquser_width": 113, "axi_data_width": [84, 113], "axi_if": 139, "axi_lite_interfac": 144, "axi_rdata": 84, "axi_rid": 84, "axi_rlast": 84, "axi_rreadi": 84, "axi_rresp": 84, "axi_rvalid": 84, "axi_rx_spe": 139, "axi_wdata": 84, "axi_wreadi": 84, "axi_wstrb": 84, "axi_wvalid": 84, "b": [17, 21, 31, 39, 45, 47, 60, 87, 110, 131, 144, 150, 188], "b0": [87, 144, 150, 151, 152], "b1": [144, 151, 152], "b_array_t": [25, 89], "bachelor": 1, "back": [19, 67, 71, 75, 80, 144, 147, 166, 184, 186, 187, 192, 195], "backbon": 188, "backpressur": [110, 187], "bandwidth": 47, "bar": [116, 117, 192], "bar0": [116, 185, 192], "bar0_base_addr": [116, 192], "bar1": 116, "bar1_base_addr": [116, 192], "bar2": [116, 192], "bar2_base_addr": [116, 192], "bar3": 116, "bar3_base_addr": [116, 192], "bar4": [116, 192], "bar4_base_addr": [116, 192], "bar5": 116, "bar5_base_addr": [116, 192], "bar_apertur": 117, "bar_id": 117, "bar_shift_lat": 8, "bare": 166, "barrel": [43, 59, 160], "barrel_shift": 160, "barrel_shifter_dsp": 160, "barrel_shifter_gen": [8, 110], "barrel_shifter_gen_pip": 8, "barrier": 144, "base": [0, 2, 5, 17, 25, 26, 29, 30, 31, 34, 37, 39, 45, 59, 60, 67, 69, 76, 78, 86, 88, 89, 99, 101, 107, 110, 112, 116, 117, 118, 119, 121, 122, 125, 128, 129, 137, 139, 142, 143, 144, 147, 148, 156, 159, 160, 161, 164, 166, 184, 185, 187, 190, 192, 193], "base_address": 185, "baseh": 39, "basel": 39, "baselin": 152, "basi": 76, "basic": [25, 31, 32, 67, 71, 90, 110, 128, 135, 136, 138, 139, 141, 142, 143, 149, 166, 167, 185, 187, 189, 190, 195], "bbuild": 27, "bcefst": 144, "bclk": 20, "bear": 17, "becaus": [11, 19, 20, 31, 33, 38, 58, 67, 68, 80, 87, 89, 110, 125, 137, 138, 144, 147, 166, 179, 184, 185, 187], "been": [11, 12, 17, 18, 19, 42, 55, 58, 62, 76, 104, 109, 110, 113, 118, 119, 128, 131, 139, 144, 146, 160, 166, 167, 168, 169, 185], "befor": [5, 9, 17, 18, 19, 22, 49, 58, 63, 67, 68, 71, 75, 76, 80, 85, 87, 89, 91, 101, 109, 111, 118, 119, 128, 131, 139, 142, 144, 146, 150, 166, 170, 180, 183, 184, 186, 187, 192], "before_on": 160, "begener": 49, "begin": [11, 33, 36, 38, 45, 50, 54, 59, 67, 76, 89, 110, 128, 129, 131, 142, 143, 144, 148, 150, 151, 166], "beginbursttransf": 83, "beginig": 68, "behav": [7, 12, 43, 45, 58, 128, 139, 142, 143, 144, 147, 166], "behavior": [11, 12, 44, 82, 87, 90, 110, 120, 141, 144, 147, 156, 160, 161, 164, 187], "behaviour": [13, 58, 101, 147, 161], "behind": [60, 71, 87, 183], "beign": [131, 151], "being": [12, 27, 58, 59, 67, 68, 71, 76, 87, 88, 104, 109, 111, 128, 142, 166], "bellow": [108, 171, 172], "belong": [76, 89, 184, 187], "below": [0, 19, 22, 27, 60, 67, 71, 87, 89, 104, 113, 118, 128, 129, 131, 139, 142, 143, 144, 147, 149, 166, 167, 168, 169, 174, 183, 184, 186, 187, 189, 191, 192, 195, 196], "bene\u0161": 59, "ber": 107, "ber_mon": 107, "besid": [48, 61], "best": [46, 59, 90, 166], "better": [4, 14, 16, 17, 22, 31, 64, 71, 77, 86, 87, 90, 96, 100, 110, 131, 133, 144, 166], "between": [0, 11, 17, 18, 19, 23, 24, 27, 28, 29, 31, 47, 48, 54, 59, 60, 65, 67, 68, 71, 75, 76, 77, 82, 83, 89, 96, 102, 104, 107, 118, 119, 125, 128, 129, 131, 137, 138, 139, 142, 143, 144, 146, 149, 160, 164, 166, 180, 187, 191, 193, 195], "bidirect": 144, "bifurac": 192, "bifurc": 192, "big": [98, 160], "bigger": [68, 104], "bin": [27, 89, 144], "bin2hot": 160, "binari": [18, 59, 76, 89, 160, 166, 185], "bind": [112, 132], "bip": 107, "bit": [0, 1, 3, 4, 5, 6, 7, 8, 11, 12, 14, 16, 17, 18, 20, 21, 22, 23, 25, 27, 29, 30, 31, 32, 35, 39, 45, 46, 47, 48, 49, 50, 54, 55, 59, 60, 61, 62, 63, 65, 67, 68, 69, 70, 71, 74, 75, 76, 82, 83, 84, 85, 87, 88, 90, 92, 94, 95, 96, 98, 100, 104, 107, 109, 111, 112, 113, 116, 117, 120, 121, 122, 135, 136, 144, 147, 149, 150, 151, 160, 164, 183, 187, 189, 191, 192, 195, 196], "bitrat": 107, "bitstream": [167, 168, 169, 170, 171, 172, 173, 189], "bitwis": 160, "black": 195, "blaster": 173, "blob": [112, 185], "block": [0, 3, 8, 14, 16, 26, 27, 36, 38, 39, 43, 45, 46, 48, 49, 50, 54, 59, 61, 62, 63, 67, 68, 69, 70, 73, 74, 76, 101, 107, 109, 110, 111, 113, 116, 130, 138, 144, 147, 149, 156, 160, 183, 184, 186, 187, 192, 193], "block_aux_en": 73, "block_en": [14, 16], "block_lock": [107, 149], "block_siz": [8, 34, 36, 48, 49, 52, 55, 56, 57, 58, 61, 63, 66, 68, 70, 72, 73, 76, 79, 128, 142, 143, 144, 145, 180], "block_width": [8, 14, 16], "blok": 3, "blokov\u00fd": 5, "board": [173, 180, 183, 189, 193], "board_rev": [174, 189], "bock_width": 14, "bodfc": 109, "bodfch": 109, "bodfcl": 109, "bodi": [131, 144], "boolean": [3, 4, 5, 6, 7, 8, 10, 14, 16, 18, 24, 26, 31, 38, 39, 46, 48, 49, 57, 58, 61, 62, 63, 64, 66, 69, 71, 73, 74, 75, 77, 78, 82, 86, 89, 90, 91, 92, 94, 95, 96, 98, 101, 102, 105, 106, 109, 111, 113, 114, 116, 121, 180, 192], "boot": [71, 167, 168, 169, 174, 175, 176, 177, 185, 189, 191], "boot_en": 185, "border": 67, "bot": [68, 151], "both": [3, 4, 5, 11, 12, 17, 19, 24, 26, 43, 46, 48, 61, 67, 68, 76, 80, 82, 83, 87, 88, 89, 94, 101, 104, 107, 110, 117, 119, 120, 128, 139, 141, 142, 143, 144, 146, 147, 179, 183, 184, 187, 188], "bottleneck": 19, "bottom": [60, 174], "bound": [150, 185], "boundari": [107, 125, 137, 138], "box": [25, 26], "box_cnt": 26, "box_width": 26, "bp": 67, "brake": 180, "bram": [4, 5, 13, 26, 43, 59, 77, 79, 80, 82, 101, 105, 106, 156, 161, 166, 185], "branch": 27, "brand": 58, "break": [17, 91, 102, 122, 124, 144, 145], "bridg": [23, 31], "brief": 152, "brnolog": [159, 186], "broadcast": [22, 183, 187], "brodcast": 109, "broken": [27, 116], "bs_calc": 59, "bscn": 67, "bt": 174, "bu": [0, 12, 17, 18, 23, 24, 25, 36, 37, 38, 39, 40, 43, 44, 45, 46, 54, 55, 61, 62, 66, 68, 69, 73, 76, 82, 83, 88, 89, 90, 91, 99, 100, 104, 106, 107, 109, 111, 113, 116, 117, 119, 121, 129, 132, 157, 158, 162, 163, 164, 165, 183, 185, 186, 187, 190, 192, 193, 195], "buf_a_col": 17, "buf_a_sect": 17, "buf_a_stream_row": 17, "buf_b_col": 17, "buf_b_row": 17, "buf_b_sect": 17, "buf_block": 78, "buf_byt": 78, "buf_word": 78, "buff": [29, 31, 32], "buff_rd_addr": 42, "buff_rd_chan": 42, "buff_rd_data": 42, "buff_rd_data_vld": 42, "buff_rd_en": 42, "buffer": [7, 17, 19, 29, 31, 32, 33, 34, 35, 39, 41, 42, 44, 45, 46, 54, 65, 71, 75, 80, 98, 102, 107, 109, 110, 111, 162, 164, 183, 187, 192], "buffer_ae_offset": 71, "buffer_af_offset": 71, "buffer_s": 71, "buffered_data_s": 38, "bug": [59, 144, 185], "build": [0, 27, 67, 107, 144, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 187, 193, 195], "build_phas": [128, 131, 139, 142, 143, 144, 150], "built": [27, 92, 184, 189], "buld": [167, 168, 169], "bundl": 166, "burst": [0, 29, 30, 31, 49, 83, 141, 143, 144, 146, 183], "burst_cnt": [29, 32], "burst_id": 32, "burst_siz": 49, "burst_width": 122, "burstcount": [83, 122], "bus_handshak": 166, "buse": [0, 1, 86, 104, 183, 186, 187, 192], "busi": [67, 85], "buss": 47, "bypass": [14, 71, 74], "byte": [18, 19, 22, 33, 34, 35, 37, 38, 39, 40, 41, 43, 44, 45, 46, 47, 48, 49, 50, 54, 59, 60, 67, 74, 82, 83, 87, 88, 90, 109, 111, 112, 113, 116, 117, 121, 128, 132, 135, 136, 137, 138, 139, 142, 143, 146, 148, 149, 152, 161, 180, 183, 187, 192, 195, 198], "byte_aray_mfb": 144, "byte_arra_mfb": 128, "byte_arrai": [128, 129, 144, 151], "byte_array_ag": 144, "byte_array_cfg": 144, "byte_array_mfb": [125, 132, 144, 145], "byte_array_mfb_cfg": 144, "byte_array_mfb_env": 128, "byte_array_mfb_monitor": 144, "byte_array_mfb_sequ": 144, "byte_array_moinitor": 144, "byte_array_port_env": 144, "bytes_max_numb": 148, "bytes_min_numb": 148, "bytes_per_packet_max_numb": 148, "bytes_per_packet_min_numb": 148, "bytes_per_packet_rev_max_numb": 148, "bytes_per_packet_rev_min_numb": 148, "bytes_rev_max_numb": 148, "bytes_rev_min_numb": 148, "bytes_vld": [126, 127, 135, 136], "bytesh": [39, 45], "bytesl": [39, 45], "c": [10, 31, 39, 45, 87, 144], "c_char_width": 144, "c_data": 150, "c_transact": 144, "ca": 19, "cabal": 1, "cabl": [27, 167, 168, 169, 170, 171, 172, 173], "cage": 194, "calcul": [4, 19, 24, 25, 41, 45, 59, 67, 71, 75, 76, 90, 104, 109, 111, 114, 118, 131, 144, 147, 160, 162, 164, 166, 183, 195], "calibr": [31, 183], "call": [24, 71, 76, 104, 142, 143, 144, 150, 166, 170, 171, 172, 183, 184, 185, 187], "callback": [132, 166], "calucul": 74, "calypt": [37, 44, 186, 188, 198], "cam": [109, 161], "came": [11, 42], "can": [0, 1, 3, 4, 5, 6, 7, 8, 10, 11, 12, 14, 17, 18, 19, 20, 21, 24, 25, 26, 27, 28, 29, 31, 32, 35, 36, 40, 41, 43, 45, 46, 50, 54, 57, 58, 59, 60, 63, 65, 67, 68, 71, 74, 75, 76, 77, 80, 82, 85, 86, 87, 88, 89, 90, 91, 94, 95, 96, 98, 101, 102, 104, 106, 107, 109, 110, 111, 118, 119, 120, 122, 123, 125, 128, 129, 131, 137, 138, 139, 142, 143, 144, 146, 148, 150, 151, 152, 156, 159, 160, 164, 166, 167, 168, 169, 170, 174, 179, 183, 185, 186, 187, 189, 191, 192, 193, 194, 195, 196], "candid": 164, "cannot": [6, 11, 19, 58, 68, 80, 108, 111, 119, 129, 144, 146, 151, 160, 185], "capabl": [5, 27, 61, 112, 122, 174, 185, 192], "capac": [23, 98], "cappabl": 68, "capture_en": 18, "capture_fifo_item": 18, "card": [0, 22, 27, 31, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 183, 187, 190, 191, 192, 193, 195], "card_archgrp": 184, "card_conf": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176], "card_id": 192, "card_id_width": 192, "card_root_directori": 184, "care": [41, 75, 87, 110, 122, 129, 148], "careful": [124, 145], "carefulli": 102, "carri": [87, 89, 160, 183, 187], "carry_chain": 160, "case": [0, 3, 4, 6, 7, 11, 12, 19, 21, 35, 39, 45, 58, 59, 67, 68, 71, 76, 85, 87, 88, 89, 91, 93, 102, 104, 109, 110, 111, 117, 119, 129, 144, 148, 152, 166, 179, 183, 184, 185, 189, 190, 192, 195], "cass": 151, "cast": [131, 144, 150], "caus": [17, 21, 67, 68, 87, 109, 110, 111, 184], "caution": 89, "caveat": 166, "cb": 144, "cbs_simpl": 150, "cc": [113, 116, 117, 192], "cc_axi": 113, "cc_axi_data": 113, "cc_axi_keep": 113, "cc_axi_last": 113, "cc_axi_readi": 113, "cc_axi_us": 113, "cc_axi_valid": 113, "cc_mfb": 113, "cc_mfb_block_siz": 192, "cc_mfb_data": [113, 116], "cc_mfb_dst_rdy": [113, 116], "cc_mfb_eof": [113, 116], "cc_mfb_eof_po": [113, 116], "cc_mfb_item_width": 192, "cc_mfb_meta": 116, "cc_mfb_region": 192, "cc_mfb_region_s": 192, "cc_mfb_sof": [113, 116], "cc_mfb_sof_po": [113, 116], "cc_mfb_src_rdy": [113, 116], "cc_pipe": 116, "cc_user_width": 113, "cd": [0, 24, 25, 27, 31, 174], "cdc": 20, "cdgmii": [109, 111], "ce_gener": 132, "ceil": [35, 67], "cell": 185, "certain": [18, 58, 89, 164, 185], "cesnet": [0, 27, 174, 184, 185, 188], "cfc": 109, "cfch": 109, "cfcl": 109, "cfg": [125, 128, 137, 138, 139, 142, 143, 144], "cgmii": 109, "ch": 179, "ch_cnt": 90, "ch_diff": 90, "ch_max": [49, 90], "ch_min": [49, 90], "ch_next": 90, "ch_out": 90, "chain": [27, 89, 160], "chan": [0, 90], "chang": [14, 17, 18, 29, 49, 58, 64, 67, 68, 72, 87, 88, 89, 90, 109, 110, 111, 113, 116, 119, 128, 130, 131, 139, 142, 143, 144, 148, 150, 151, 152, 179, 184, 185, 188, 189], "channel": [0, 9, 22, 34, 35, 37, 39, 41, 42, 43, 44, 45, 46, 48, 49, 59, 65, 71, 76, 78, 87, 104, 129, 131, 144, 156, 160, 165, 179, 180, 183, 184, 186, 187, 189, 195], "channel_align": 132, "channel_cor": 44, "channel_id": 187, "channel_vld": 34, "channels_width": 49, "chapter": [0, 2, 109, 111, 153, 154, 157, 158, 159, 162, 163, 165, 183, 184, 185, 186, 189, 194, 195, 197, 198], "charact": 144, "characterist": [62, 64, 68, 69], "check": [5, 10, 19, 23, 27, 45, 58, 63, 68, 85, 87, 109, 111, 118, 119, 135, 136, 144, 146, 147, 150, 164, 179, 180, 181, 184, 187], "checker": 119, "checksum": [111, 162], "checksum_calcul": 74, "child": [128, 139, 142, 143], "chip": [23, 160, 183], "choic": [5, 152, 179], "choke": 183, "choos": [3, 5, 89, 128, 130, 139, 142, 143, 184], "chosen": [5, 41, 184], "chunk": [126, 127, 130, 152], "cicl": 151, "circuit": 12, "circumst": 67, "clariti": 184, "class": [45, 117, 123, 124, 125, 128, 129, 134, 137, 138, 139, 142, 143, 144, 145, 146, 150, 151, 160], "class_typ": 131, "classic": 5, "claus": 107, "clb": [156, 161], "clear": [12, 26, 48, 76, 87, 109, 111, 152, 160], "clear_by_read": 26, "clear_by_rst": 26, "client": [153, 154, 187], "clk": [3, 5, 6, 7, 8, 9, 10, 12, 13, 14, 17, 18, 24, 25, 26, 28, 30, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 79, 83, 84, 85, 86, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 110, 114, 116, 120, 121, 131, 144, 150, 151, 166, 179], "clk2": [17, 75, 160], "clk_": 82, "clk_arb": [17, 75], "clk_en": [3, 129], "clk_eth": [180, 183], "clk_freq": 121, "clk_frequenc": 71, "clk_gen": 164, "clk_in": 78, "clk_m": 82, "clk_meta": 78, "clk_out": 78, "clk_period": [144, 152, 166], "clk_port": 166, "clk_sel": 121, "clk_sel_width": 121, "clk_src": 121, "clk_stabl": 107, "clk_user": [180, 183], "clk_user_x2": 183, "clk_user_x3": 183, "clk_user_x4": 183, "clk_x2": 54, "clock": [1, 3, 4, 5, 6, 9, 10, 12, 13, 14, 16, 17, 18, 19, 20, 25, 26, 31, 34, 37, 44, 47, 48, 50, 54, 55, 56, 57, 58, 59, 60, 61, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 82, 83, 84, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 102, 104, 106, 107, 109, 111, 116, 119, 121, 124, 129, 130, 135, 136, 144, 145, 146, 147, 149, 150, 151, 161, 162, 164, 165, 166, 179, 180, 183, 187, 192, 196], "clog2": [131, 145], "clone": [27, 144], "close": [18, 185, 186, 198], "closur": 12, "cmac": [109, 111, 167, 168, 169, 175, 176, 180, 187, 188], "cmake": 27, "cmd": [85, 109, 111], "cmp": 160, "cnt": [11, 25, 30, 31, 160], "cnt_dist": 160, "cnt_max": 63, "cnt_multi_memx": [9, 160], "cnt_next": 11, "cnt_width": 9, "cnter": 25, "cnter_cnt": 25, "cnter_diff_0": 25, "cnter_diff_1": 25, "cnter_diff_2": 25, "cnter_incr_0": 25, "cnter_incr_1": 25, "cnter_incr_2": 25, "cnter_submit_0": 25, "cnter_submit_1": 25, "cnter_submit_2": 25, "cnter_width": 25, "cnters_diff": 25, "cnters_incr": 25, "cnters_submit": 25, "cntr": 49, "cntrs_width": [39, 45], "cocotb": 195, "codapa": 119, "code": [0, 1, 5, 27, 89, 131, 160, 166, 184, 200], "code_archgrp": 184, "code_coverag": 144, "colid": 17, "collect": [107, 150], "collis": [11, 17, 26, 165], "color": [17, 89], "color_conf_delai": 17, "color_timeout_width": 17, "column": [17, 89], "com": [27, 87], "combin": [11, 39, 45, 59, 87, 89, 95, 111, 120, 152, 183, 184], "combinatori": 12, "combo": 189, "combo_user_const": 184, "come": [11, 17, 40, 59, 75, 76, 87, 107, 110, 135, 136, 144, 187, 192, 195], "command": [0, 23, 25, 27, 32, 85, 107, 109, 111, 144, 150, 151, 152, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 189], "comment": [144, 184, 185], "commentari": 184, "common": [3, 16, 17, 24, 25, 31, 47, 58, 62, 69, 83, 85, 86, 89, 95, 107, 123, 132, 134, 166, 184, 200], "common_clock": 16, "commonli": [87, 131, 132, 133, 144, 150, 152, 166], "commun": [27, 30, 76, 104, 116, 119, 122, 123, 124, 133, 134, 135, 136, 144, 145, 146, 183, 185, 186, 190, 191, 192, 193, 198], "comp": [0, 2, 27, 31, 32, 86, 135, 136, 144, 153, 154, 157, 158, 162, 163, 165, 179, 195, 197, 198], "comp_": 166, "comp_with_data": 117, "compar": [11, 31, 44, 62, 89, 119, 125, 132, 135, 136, 137, 138, 144, 149, 160, 192], "comparer_": 144, "comparer_base_ord": 131, "comparer_base_tag": [131, 144], "comparer_base_unord": 131, "comparer_data": 144, "comparer_meta": 144, "comparer_ord": [131, 144], "comparer_tag": 131, "comparer_unord": 131, "comparesr": 144, "comparison": [3, 59, 131, 166], "compat": [11, 31, 32, 59, 66, 164, 184, 185, 189], "compens": 107, "compil": [144, 166, 184, 185, 186, 192], "complet": [11, 17, 22, 32, 45, 46, 57, 67, 76, 80, 113, 116, 117, 118, 144, 166, 170, 171, 172, 173, 185, 187, 189, 192], "completit": [117, 192], "complex": [11, 19, 37, 39, 46, 67, 68, 118, 122, 135, 136, 166], "compli": 17, "complic": [11, 68, 88, 146], "compon": [2, 5, 6, 7, 10, 12, 17, 18, 19, 20, 23, 27, 29, 32, 33, 34, 35, 36, 38, 40, 41, 42, 43, 45, 48, 49, 50, 52, 54, 55, 56, 57, 59, 60, 61, 63, 65, 66, 67, 68, 70, 71, 72, 74, 75, 77, 78, 79, 82, 83, 84, 85, 87, 88, 90, 91, 92, 93, 94, 95, 96, 99, 100, 101, 102, 104, 106, 107, 109, 110, 111, 113, 114, 115, 116, 117, 120, 121, 122, 125, 129, 131, 133, 135, 136, 137, 138, 144, 149, 150, 151, 152, 154, 157, 158, 160, 161, 162, 163, 164, 165, 182, 183, 187, 188, 191, 195, 196, 197, 198, 200], "compos": [76, 121, 147, 166], "compress": [112, 185], "comput": [0, 10, 60, 119, 159], "comun": 151, "concaten": [60, 94, 184], "concern": [68, 166, 187], "concret": 31, "concurr": 18, "condit": [67, 100, 109, 110, 144, 184, 192], "condition": 184, "conduct": [76, 104], "conector": [167, 168, 169, 170, 171, 172, 174, 175, 176, 177], "conenct": 68, "config": [49, 128, 132, 139, 142, 143, 144, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 184], "config_filepath": 148, "config_gener": 148, "config_generator_config_filepath": 148, "config_item": [122, 128, 139, 142, 143], "config_sequ": [125, 128, 137, 138, 139, 142, 143, 144], "configr": 46, "configur": [0, 1, 18, 23, 25, 27, 31, 33, 37, 39, 44, 45, 48, 49, 55, 57, 58, 59, 68, 72, 73, 87, 88, 90, 104, 106, 107, 109, 110, 111, 112, 113, 116, 121, 122, 123, 124, 126, 127, 130, 132, 135, 136, 145, 149, 151, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 183, 185, 187, 188, 189, 196], "configuret": 151, "confirm": [6, 17, 21, 35, 164], "conform": 17, "connect": [0, 4, 5, 7, 11, 12, 17, 19, 20, 27, 29, 31, 37, 39, 45, 46, 47, 48, 58, 59, 68, 71, 83, 87, 88, 89, 91, 107, 109, 111, 112, 119, 125, 126, 127, 128, 130, 131, 135, 136, 137, 138, 139, 142, 143, 144, 146, 147, 149, 150, 151, 160, 164, 167, 168, 169, 170, 171, 172, 174, 183, 185, 186, 187, 189, 192, 193, 195], "connect_phas": [128, 131, 139, 142, 143, 144], "connector": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 192, 193], "consecut": [11, 18, 67, 76, 104, 110, 125, 137, 138], "consequ": 187, "consid": [17, 19, 48, 49, 76, 89, 102, 104, 144, 184, 185, 187, 195], "consist": [18, 27, 40, 60, 67, 68, 70, 75, 80, 89, 104, 110, 118, 119, 144, 185, 186, 193], "consol": 192, "constain": 89, "constant": [20, 46, 59, 60, 67, 76, 83, 89, 104, 109, 111, 148, 160, 185, 195], "constist": [43, 45], "constr_quartu": 166, "constr_text": 166, "constr_vivado": 166, "constrain": 184, "constraint": [1, 98, 130, 144, 166, 184, 187], "construct": 152, "consum": [60, 68, 101, 102], "consume_item_width": 101, "consumpt": [7, 11, 62, 89], "contain": [0, 11, 17, 18, 19, 25, 31, 36, 39, 44, 45, 48, 49, 58, 60, 62, 68, 69, 76, 78, 80, 82, 88, 89, 91, 98, 104, 106, 109, 111, 114, 117, 119, 121, 122, 123, 124, 125, 128, 129, 131, 133, 134, 135, 136, 137, 138, 139, 141, 142, 143, 144, 146, 149, 151, 152, 156, 157, 158, 160, 162, 163, 165, 166, 174, 183, 184, 185, 186, 187, 190, 192, 193, 195, 196, 200], "containst": 145, "containt": [147, 151], "content": [26, 35, 38, 41, 59, 106, 109, 110, 111, 122, 147, 161, 185], "continu": [6, 18, 29, 45, 47, 80, 89, 110, 115, 151, 186, 195, 196], "contiuou": 115, "contol": 38, "contrast": 144, "control": [0, 6, 18, 20, 37, 44, 49, 59, 61, 67, 87, 90, 107, 109, 111, 121, 123, 124, 129, 144, 145, 149, 152, 164, 180, 183, 185, 187, 189, 191, 193, 194, 195, 198], "conv_bscn2gb": 67, "conv_gbs2bscn": 67, "conv_ps2pscn": 67, "conv_pscn2p": 67, "convent": 76, "convers": [48, 67, 107, 111, 116, 121, 125, 137, 138, 198], "convert": [21, 23, 67, 83, 84, 88, 89, 100, 102, 109, 110, 111, 113, 118, 119, 120, 122, 128, 132, 133, 139, 141, 142, 143, 160, 164, 170, 171, 172, 184, 187, 190, 192], "convert2block": 138, "convert2str": [125, 135, 136, 137, 138, 144, 147, 149, 152], "cooper": [144, 174], "copi": [54, 68, 125, 135, 136, 137, 138, 149, 152, 178, 189], "copr": [0, 27], "core": [0, 10, 11, 27, 39, 45, 46, 49, 107, 112, 118, 119, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 180, 183, 191, 193, 195], "core_archgrp": 184, "core_boostrap": 184, "core_func": 184, "core_root_directori": 184, "correct": [4, 5, 14, 16, 18, 35, 45, 82, 88, 109, 112, 113, 114, 116, 123, 144, 147, 150, 174, 180, 189, 192], "correctli": [58, 67, 88, 109, 129, 134, 144, 183, 185, 189], "correspond": [6, 17, 21, 27, 34, 60, 67, 71, 76, 107, 110, 118, 119, 147, 183, 184, 186, 187, 188, 194, 195], "correspons": 21, "cos521": 10, "cost": [19, 93, 98], "could": [11, 12, 17, 19, 20, 58, 59, 76, 89, 104, 144, 149, 179], "count": [0, 6, 18, 19, 24, 25, 29, 30, 31, 55, 67, 75, 91, 102, 109, 111, 160, 164, 183, 196, 198], "counter": [1, 11, 17, 25, 28, 30, 31, 35, 37, 39, 40, 42, 44, 45, 46, 49, 62, 65, 71, 96, 107, 109, 111, 152, 160, 164], "counton": 144, "coupl": [87, 180], "cours": [10, 18, 85], "cov_html": 144, "cov_packet": 144, "cover": [45, 58, 101, 180], "coverag": 5, "coverage_bas": 144, "covergroup": 144, "coverpoint": 144, "cpack": 27, "cpu": 183, "cq": [113, 116, 117, 192], "cq_axi": 113, "cq_axi_data": 113, "cq_axi_keep": 113, "cq_axi_last": 113, "cq_axi_readi": 113, "cq_axi_us": 113, "cq_axi_valid": 113, "cq_fbe": 113, "cq_lbe": 113, "cq_mfb": 113, "cq_mfb_block_siz": 192, "cq_mfb_data": [113, 116], "cq_mfb_dst_rdy": [113, 116], "cq_mfb_eof": [113, 116], "cq_mfb_eof_po": [113, 116], "cq_mfb_item_width": 192, "cq_mfb_meta": 116, "cq_mfb_region": 192, "cq_mfb_region_s": 192, "cq_mfb_sof": [113, 116], "cq_mfb_sof_po": [113, 116], "cq_mfb_src_rdy": [113, 116], "cq_pipe": 116, "cq_tph_present": 113, "cq_tph_st_tag": 113, "cq_tph_type": 113, "cq_user_width": 113, "cquser_width": 117, "cr": 107, "crash": 184, "crc": [22, 109, 111, 183, 187, 188, 195], "crc_check_en": 109, "crc_error": 109, "crc_insert_en": 111, "crc_is_receiv": 109, "crc_remove_en": 109, "crdt": 132, "creat": [17, 27, 34, 37, 48, 59, 60, 62, 68, 69, 76, 86, 104, 119, 125, 128, 129, 131, 135, 136, 137, 138, 139, 142, 143, 146, 147, 149, 150, 152, 160, 166, 173, 178, 183, 185, 187, 188, 189], "create_sequence_item": [128, 139, 142, 143, 146, 152], "creation": [104, 126, 127, 130, 139, 144], "creator": 60, "credit": [118, 123], "critic": 87, "cross": [1, 20, 29, 31, 61, 82, 144, 164], "crossbar": 17, "crossbarx": [21, 111, 162, 164], "crossbarx_stream": 75, "csr": [183, 187, 191, 193], "csv": 148, "ctl_bar_apertur": 116, "ctl_max_payload_s": 116, "ctrl": [25, 29, 30, 31, 109, 153, 164], "ctrl_reg": 121, "ctrli": 25, "ctrli_width": 25, "ctrlo": 25, "ctrlo_default": 25, "ctrlo_width": 25, "curent": 28, "current": [4, 6, 10, 14, 17, 19, 22, 27, 29, 31, 32, 33, 35, 39, 42, 45, 52, 57, 58, 59, 60, 62, 63, 65, 67, 68, 71, 76, 77, 78, 80, 83, 85, 87, 104, 109, 110, 111, 116, 118, 119, 129, 144, 146, 161, 166, 185, 186, 187, 188, 190, 192], "current_tim": 65, "currently_stor": [4, 5, 6], "custom": [25, 146, 152, 184, 185], "customiz": 161, "cut": [55, 60, 109, 119, 126, 127, 130], "cutted_item": 55, "cutter": [41, 109, 119, 162], "cvg": 144, "cx": 75, "cx_clk_arb": 75, "cx_reset_arb": 75, "cx_use_clk2": 75, "cx_use_clk_arb": 75, "cycl": [1, 3, 5, 6, 10, 11, 13, 14, 17, 18, 19, 20, 25, 26, 30, 47, 49, 58, 59, 63, 67, 71, 76, 83, 87, 88, 90, 93, 104, 106, 110, 118, 119, 121, 124, 130, 135, 136, 144, 145, 146, 151, 156, 160, 161, 162, 164, 165, 170, 171, 172], "cz": 184, "czech": 188, "d": [31, 32, 47, 87, 173, 179], "d0": [87, 152], "d1": 87, "d12": 152, "d16": 152, "d2": 87, "d3": 87, "d4": 152, "d512": 152, "d516": 152, "d8": [87, 152], "d9": 87, "damag": 45, "danger": 180, "data": [4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 19, 22, 24, 29, 30, 31, 32, 34, 35, 36, 38, 39, 42, 43, 44, 45, 46, 47, 48, 49, 52, 54, 55, 58, 59, 60, 61, 62, 63, 65, 66, 67, 70, 71, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 87, 88, 89, 90, 92, 93, 94, 95, 96, 98, 101, 102, 104, 105, 107, 109, 111, 112, 113, 116, 117, 119, 121, 122, 124, 125, 128, 129, 130, 131, 133, 134, 135, 136, 137, 138, 139, 141, 142, 143, 144, 145, 146, 147, 149, 150, 151, 152, 154, 156, 160, 161, 164, 180, 183, 186, 187, 188, 189, 192, 193, 194, 195], "data_block_s": 78, "data_block_width": 78, "data_buff": 132, "data_dir": 17, "data_in": [8, 10, 12], "data_in_rdi": 10, "data_in_vld": 10, "data_item": 144, "data_item_width": 78, "data_logg": [0, 24, 25, 31], "data_logger_i": 25, "data_mux_lat": 17, "data_mux_outreg_en": 17, "data_out": [8, 10], "data_out_rdi": 10, "data_out_vld": 10, "data_pcie_hdr": 35, "data_pcie_hdr_dst_rdi": 35, "data_pcie_hdr_s": 35, "data_pcie_hdr_src_rdi": 35, "data_pointer_width": [42, 44, 45], "data_rot_lat": 17, "data_rot_outreg_en": 17, "data_vld": 149, "data_width": [4, 5, 6, 7, 10, 12, 13, 14, 15, 16, 28, 47, 82, 83, 85, 86, 87, 89, 91, 95, 99, 122, 124, 135, 136, 139, 144, 146, 149, 150, 152], "databas": [128, 133, 139, 142, 143, 144], "datapath": 195, "date": 166, "david": 59, "dba_rd_chan": 37, "dba_rd_data": 37, "dbg_gls0": [0, 185], "dbg_gls1": [0, 185], "dbg_signal_width": 40, "dd": [170, 172, 173, 174, 194], "ddr": 31, "ddr4": [154, 183, 190], "ddr_logger_0": 185, "ddr_logger_1": 185, "ddr_logger_2": 185, "ddr_logger_3": 185, "ddr_tester_0": 185, "ddr_tester_1": 185, "ddr_tester_2": 185, "ddr_tester_3": 185, "deactiv": 1, "deadlock": [19, 21, 191], "deafult": 59, "deal": 60, "deassert": [7, 12, 76, 83, 87, 104, 110, 134, 152], "deb": 189, "debug": [0, 18, 19, 31, 40, 45, 46, 109, 144, 164, 167, 168, 169, 173, 174, 186, 191, 192, 195], "debug_rand_addr": 31, "debugaccess": 83, "dec": [3, 111], "dec1fn": 160, "decid": [65, 80, 89, 133, 147], "declar": [47, 68, 76, 104, 166, 179, 184], "decod": [2, 41, 87, 107, 160, 198], "decreas": [68, 72, 75, 125, 137, 138], "decrement": [11, 146], "dedic": [60, 164, 166, 180, 193], "deduc": 11, "deem": 21, "deep": [4, 77, 183], "def_refr_period": 31, "default": [0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 27, 28, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 109, 111, 113, 114, 116, 117, 120, 121, 122, 128, 135, 136, 139, 142, 143, 144, 146, 148, 149, 151, 152, 160, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 180, 183, 184, 185, 186, 188, 192, 196], "default_addr_limit": 31, "default_burst_cnt": 31, "default_mod": 90, "deficit": [19, 75, 111, 164], "deficit_idle_count": 164, "defin": [5, 10, 11, 17, 18, 23, 26, 28, 37, 39, 44, 46, 47, 60, 67, 75, 79, 81, 87, 89, 98, 101, 105, 107, 111, 116, 129, 144, 146, 148, 149, 150, 152, 166, 183, 187], "definit": [11, 29, 30, 31, 109, 111, 150, 166, 183], "degrad": [107, 188], "delai": [5, 14, 17, 20, 58, 67, 87, 131, 146, 151], "delay": [71, 162], "delay_count": 20, "delet": [80, 107, 144, 146], "deliber": 184, "delimit": [40, 41, 45, 129], "demo": [180, 183], "demonst": 58, "demonstr": [11, 58, 76, 104], "demultiplex": [91, 160], "demux": [160, 165], "demux_width": 91, "dens": 98, "depars": [41, 198], "depend": [11, 17, 19, 21, 27, 59, 67, 68, 79, 88, 89, 101, 104, 105, 109, 118, 119, 126, 127, 130, 135, 136, 144, 146, 149, 166, 174, 183, 187, 188, 190], "deprac": 45, "deprec": 183, "depreci": [30, 31, 32], "depth": [4, 5, 13, 14, 16, 27, 44, 48, 50, 59, 77, 79, 81, 94, 99, 101, 105], "deriv": [60, 68, 71, 76, 78], "descend": 184, "descrambl": [107, 130], "descrambler_gen": 107, "describ": [0, 2, 17, 47, 67, 76, 104, 107, 118, 119, 125, 128, 129, 137, 138, 139, 142, 143, 144, 147, 148, 149, 152, 153, 154, 166, 167, 168, 169, 183, 184, 185, 186, 187, 189, 191, 195, 196, 197, 198], "descript": [0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, 20, 22, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 119, 120, 121, 125, 128, 131, 132, 137, 138, 139, 142, 143, 146, 147, 152, 154, 157, 158, 162, 163, 164, 165, 174, 180, 181, 183, 185, 186, 187, 191, 192, 193, 196, 198], "descriptor": [37, 39, 46], "desctin": 17, "deseri": 107, "deserv": 166, "design": [5, 11, 12, 16, 27, 37, 41, 45, 46, 47, 76, 104, 107, 110, 119, 144, 150, 164, 179, 180, 183, 185, 187, 189, 191], "desir": [18, 59, 67, 74, 85, 152, 186, 192], "deskew": 107, "desnt": 14, "despair": 67, "destin": [17, 22, 47, 49, 63, 66, 90, 92, 94, 96, 98, 109, 111, 113, 147, 160, 164, 183, 187, 195], "desynchron": 144, "detail": [0, 1, 16, 17, 19, 23, 59, 75, 104, 107, 113, 119, 135, 136, 144, 156, 160, 164, 166, 174, 183, 184, 186, 187, 189], "detect": [1, 11, 17, 29, 31, 34, 67, 107, 118, 121, 156, 160, 164, 184, 195], "detector": [160, 164], "determin": [4, 5, 6, 25, 39, 43, 45, 54, 60, 62, 67, 76, 79, 87, 89, 91, 96, 105, 109, 111, 113, 122, 148, 183], "dev": [31, 171, 172, 180, 184, 185], "develop": [144, 152, 159, 162, 165, 166, 171, 172, 184, 186, 189, 193], "deviat": 45, "devic": [3, 4, 5, 6, 9, 13, 14, 15, 16, 17, 18, 23, 24, 27, 28, 31, 32, 33, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 58, 59, 60, 61, 62, 64, 65, 66, 67, 68, 69, 70, 71, 74, 75, 77, 78, 79, 81, 82, 83, 84, 86, 89, 90, 93, 94, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 111, 113, 116, 117, 121, 144, 166, 179, 180, 183, 191, 192], "devicetre": [183, 191, 192, 195], "devtre": [0, 27, 31, 166, 185, 191], "dfc": [109, 111], "dfch": [109, 111], "dfcl": [109, 111], "dfifo": 109, "dfifo_ovf": 109, "di": [5, 6, 15, 74, 131, 160], "diagnost": 187, "diagram": [0, 48, 68, 88, 110, 116, 174, 183, 184, 186, 187, 192, 193], "did": 109, "didn": 148, "differ": [3, 11, 17, 18, 21, 25, 27, 31, 43, 47, 67, 68, 75, 87, 88, 90, 93, 94, 100, 109, 110, 111, 113, 118, 119, 121, 125, 129, 131, 137, 138, 144, 146, 147, 152, 153, 166, 184, 186, 187, 190, 194], "difficult": 144, "difficulti": 68, "digit": 18, "dimens": [17, 135, 136, 149], "din": 95, "din_dst_rdi": 95, "din_src_rdi": 95, "din_vld": 95, "dir": [17, 135, 136, 149], "direct": [0, 8, 17, 23, 45, 46, 47, 48, 76, 87, 88, 104, 110, 128, 139, 142, 143, 144, 147, 148, 160, 166, 191, 192, 194], "directli": [7, 14, 16, 19, 21, 24, 27, 58, 59, 67, 83, 89, 107, 121, 144, 150, 166, 184, 185, 187, 192, 195], "directori": [0, 2, 45, 121, 144, 153, 154, 157, 158, 162, 163, 165, 166, 178, 179, 184, 185, 189, 197, 198, 200], "disabl": [3, 5, 6, 14, 25, 27, 39, 45, 48, 49, 57, 61, 74, 86, 90, 95, 105, 107, 109, 111, 121, 144, 148, 150, 167, 169, 180, 189, 192, 196], "disadvantag": 144, "disc_bts_cnt_width": [37, 44], "disc_pkt_cnt_width": [37, 44], "discard": [22, 35, 39, 40, 45, 50, 54, 57, 58, 75, 81, 109, 111, 131, 144, 162, 165, 180, 183, 187, 188], "discart": [37, 44, 111], "discourag": 144, "disect": 17, "disjoint": 87, "dispatch": 45, "displai": [45, 58, 131, 174, 183, 187], "distinct": 27, "distinguish": [47, 67, 76, 166], "distmem": 13, "distr": 90, "distribut": [4, 15, 19, 87, 90, 104, 107, 125, 129, 137, 138, 151, 160, 183], "divid": [0, 31, 67, 68, 76, 87, 90, 138, 144, 150, 152, 186, 191, 192], "divis": [50, 68], "dk": 180, "dl": 13, "dll": 166, "dma": [0, 33, 34, 35, 37, 38, 40, 41, 42, 43, 44, 48, 65, 71, 90, 118, 119, 159, 167, 169, 180, 184, 189, 191, 192, 193, 195, 198], "dma_bar_en": 192, "dma_bus_pack": 22, "dma_calypt": 46, "dma_cc_mfb_data": 192, "dma_cc_mfb_dst_rdi": 192, "dma_cc_mfb_eof": 192, "dma_cc_mfb_eof_po": 192, "dma_cc_mfb_meta": 192, "dma_cc_mfb_sof": 192, "dma_cc_mfb_sof_po": 192, "dma_cc_mfb_src_rdi": 192, "dma_clk": [183, 192], "dma_clk_x2": 183, "dma_cq_mfb_data": 192, "dma_cq_mfb_dst_rdi": 192, "dma_cq_mfb_eof": 192, "dma_cq_mfb_eof_po": 192, "dma_cq_mfb_meta": 192, "dma_cq_mfb_sof": 192, "dma_cq_mfb_sof_po": 192, "dma_cq_mfb_src_rdi": 192, "dma_ctrl_ndp_rx": [0, 185], "dma_ctrl_ndp_rx0": [0, 185], "dma_ctrl_ndp_rx1": [0, 185], "dma_ctrl_ndp_rx10": [0, 185], "dma_ctrl_ndp_rx11": [0, 185], "dma_ctrl_ndp_rx12": [0, 185], "dma_ctrl_ndp_rx13": [0, 185], "dma_ctrl_ndp_rx14": [0, 185], "dma_ctrl_ndp_rx15": [0, 185], "dma_ctrl_ndp_rx2": [0, 185], "dma_ctrl_ndp_rx3": [0, 185], "dma_ctrl_ndp_rx4": [0, 185], "dma_ctrl_ndp_rx5": [0, 185], "dma_ctrl_ndp_rx6": [0, 185], "dma_ctrl_ndp_rx7": [0, 185], "dma_ctrl_ndp_rx8": [0, 185], "dma_ctrl_ndp_rx9": [0, 185], "dma_ctrl_ndp_tx": [0, 185], "dma_ctrl_ndp_tx0": [0, 185], "dma_ctrl_ndp_tx1": [0, 185], "dma_ctrl_ndp_tx10": [0, 185], "dma_ctrl_ndp_tx11": [0, 185], "dma_ctrl_ndp_tx12": [0, 185], "dma_ctrl_ndp_tx13": [0, 185], "dma_ctrl_ndp_tx14": [0, 185], "dma_ctrl_ndp_tx15": [0, 185], "dma_ctrl_ndp_tx2": [0, 185], "dma_ctrl_ndp_tx3": [0, 185], "dma_ctrl_ndp_tx4": [0, 185], "dma_ctrl_ndp_tx5": [0, 185], "dma_ctrl_ndp_tx6": [0, 185], "dma_ctrl_ndp_tx7": [0, 185], "dma_ctrl_ndp_tx8": [0, 185], "dma_ctrl_ndp_tx9": [0, 185], "dma_discard": 35, "dma_downhdr_width": [62, 69, 192], "dma_endpoint": 46, "dma_ep": 192, "dma_hdr": 35, "dma_hdr_dst_rdi": 35, "dma_hdr_meta_width": 183, "dma_hdr_pointer_width": [42, 44, 45], "dma_hdr_src_rdi": 35, "dma_hdr_width": 42, "dma_mfb_region": 183, "dma_mfb_region_s": 183, "dma_modul": [0, 185], "dma_params_rx0": 185, "dma_params_tx0": 185, "dma_pcie_hdr": 35, "dma_pcie_hdr_dst_rdi": 35, "dma_pcie_hdr_s": 35, "dma_pcie_hdr_src_rdi": 35, "dma_port": 192, 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[48, 183], "dma_rx_mvb_discard": [48, 183], "dma_rx_mvb_dst_rdi": [48, 183], "dma_rx_mvb_hdr_meta": [48, 183], "dma_rx_mvb_len": [48, 183], "dma_rx_mvb_src_rdi": [48, 183], "dma_rx_mvb_vld": [48, 183], "dma_stream": 183, "dma_tx": 48, "dma_tx_": 183, "dma_tx_channel": 183, "dma_tx_frame_size_max": 183, "dma_tx_mfb_data": [48, 183], "dma_tx_mfb_dst_rdi": [48, 183], "dma_tx_mfb_eof": [48, 183], "dma_tx_mfb_eof_po": [48, 183], "dma_tx_mfb_sof": [48, 183], "dma_tx_mfb_sof_po": [48, 183], "dma_tx_mfb_src_rdi": [48, 183], "dma_tx_mvb_channel": [48, 183], "dma_tx_mvb_dst_rdi": [48, 183], "dma_tx_mvb_hdr_meta": [48, 183], "dma_tx_mvb_len": [48, 183], "dma_tx_mvb_src_rdi": [48, 183], "dma_tx_mvb_vld": [48, 183], "dma_tx_usr_choke_chan": 183, "dma_typ": [184, 186, 189], "dma_uphdr_width": [62, 69, 192], "dnf": [27, 189], "do": [5, 6, 49, 58, 67, 68, 71, 80, 89, 90, 91, 109, 113, 116, 123, 131, 144, 152, 160, 166, 179, 185, 187, 189, 195], "do_compar": [125, 135, 136, 137, 138, 147, 149], "do_copi": [125, 135, 136, 137, 138, 147, 149], "dob": 15, "doc": [22, 183, 187], "document": [0, 5, 6, 17, 27, 45, 47, 60, 76, 77, 79, 119, 128, 139, 142, 143, 144, 145, 152, 156, 160, 164, 166, 179, 184, 186, 187, 189, 195], "doe": [0, 4, 11, 21, 23, 41, 45, 47, 49, 52, 58, 60, 67, 68, 76, 83, 87, 88, 95, 102, 109, 110, 111, 116, 120, 125, 137, 138, 144, 159, 166, 180, 183, 185, 189, 192], "doesn": [88, 89, 109, 128, 131, 133, 139, 142, 143, 144, 166], "doi": 13, "domain": [1, 20, 31, 77, 82, 151, 187], "don": [11, 17, 20, 31, 87, 89, 109, 144, 148, 149], "done": [11, 17, 18, 25, 27, 31, 44, 59, 60, 67, 68, 88, 99, 109, 110, 118, 119, 131, 144, 151, 183, 184], "dont": [124, 145], "dont_car": 13, "doubl": [17, 68, 75, 109, 111, 118, 119, 156, 160, 183, 187], "doulo": 144, "dout": 95, "dout_dst_rdi": 95, "dout_src_rdi": 95, "dout_vld": 95, "down": [14, 21, 67, 88, 89, 110], "download": [27, 128, 173], "downstream": [46, 118, 119], "downto": [3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 28, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 112, 113, 114, 115, 116, 117, 120, 121, 180, 183, 192], "dp_bmem": 161, "dp_bmem_behav": 166, "dp_bmem_v7": 161, "dp_bram": [29, 161], "dp_bram_xilinx": 161, "dp_uram_xilinx": 161, "dpi": 166, "dpm": [39, 45], "dpm_rd_chan": 37, "dpm_rd_data": 37, "draft": [22, 183, 187, 191], "drc": 187, "drd": [87, 88, 146], "drdy": [83, 87, 146], "dreleas": 156, "drive": [124, 129, 133, 135, 136, 144, 149], "driven": [12, 20], "driver": [27, 31, 37, 124, 125, 126, 127, 130, 132, 137, 138, 145, 146, 151, 174, 185, 188, 189], "driver_delai": 151, "drop": [40, 42, 45, 47, 54, 56, 65, 107, 108, 150, 152, 180], "drop_object": 144, "drope": 45, "dropper": [40, 152, 162], "drp_bridg": 187, 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"entity_bas": [144, 166, 185], "entity_i": 131, "entity_name_1": 184, "entity_name_2": 184, "entri": [45, 106, 166, 184], "enum": 122, "env": [128, 132, 133, 139, 142, 143, 144, 151, 152], "env_config_item": 151, "env_main": 144, "env_rx": [128, 139, 142, 143], "enviro": [132, 151], "environ": [5, 45, 124, 125, 130, 132, 133, 137, 138, 145, 152, 166, 184, 200], "eof": [33, 54, 55, 57, 58, 59, 60, 63, 64, 68, 75, 76, 78, 80, 81, 109, 110, 111, 113, 126, 127, 128, 135, 136, 142, 144, 145, 151, 183], "eof_po": [33, 59, 68, 145], "eof_pos_width": 76, "eop": [47, 134], "eop_empti": 133, "eop_po": 47, "ep": 183, "epoch": 196, "epon": 107, "eq": 131, "equal": [3, 26, 31, 67, 75, 76, 87, 89, 121, 144, 166, 180, 183], "equat": 67, "eras": [26, 80], "err": [31, 134], "error": [0, 22, 31, 85, 87, 107, 108, 109, 131, 133, 141, 144, 179, 180, 183, 184, 187], "error_msg": 131, "errorcrc": [22, 183, 187], "errorfram": [22, 183, 187], "errormac": [22, 183, 187], "errormaxtu": [22, 183, 187], "errormintu": [22, 183, 187], "especi": [184, 185, 195], "essenti": [87, 144], "etc": [0, 2, 39, 45, 47, 67, 87, 102, 138, 144, 166, 184, 185, 187, 192], "eth": [0, 48, 90, 109, 111, 131, 180, 183, 185, 187, 188, 189, 195], "eth0": 185, "eth1": 185, "eth_channel": 183, "eth_core_arch": 180, "eth_hdr_pack": [22, 109, 183, 187], "eth_mac_bypass": 180, "eth_mfb_region": 183, "eth_mfb_region_s": 183, "eth_phi": [135, 136], "eth_port": 180, "eth_port_chan": 180, "eth_port_rx_mtu": 180, "eth_port_spe": 180, "eth_port_tx_mtu": 180, "eth_refclk_n": 180, "eth_refclk_p": 180, "eth_rx": 48, "eth_rx_": 183, "eth_rx_hdr_width": [109, 180, 183], "eth_rx_link_up": 183, "eth_rx_mfb_data": [48, 183], "eth_rx_mfb_dst_rdi": [48, 183], "eth_rx_mfb_eof": [48, 183], "eth_rx_mfb_eof_po": [48, 183], "eth_rx_mfb_sof": [48, 183], "eth_rx_mfb_sof_po": [48, 183], "eth_rx_mfb_src_rdi": [48, 183], "eth_rx_mvb_channel": 48, "eth_rx_mvb_data": 183, "eth_rx_mvb_discard": 48, "eth_rx_mvb_dst_rdi": [48, 183], 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175, 176, 178, 179, 183, 185, 188, 189, 191], "file_to_anotherlib": 166, "file_to_work": 166, "file_typ": 166, "filenam": [166, 184], "fill": [17, 18, 29, 32, 80, 110, 117, 129, 166, 183, 187], "filtr": 59, "final": [3, 54, 71, 76, 87, 89, 144, 152, 184], "find": [31, 128, 139, 142, 143, 144, 148, 183, 184, 189, 192], "fine": [47, 166], "finish": [31, 144, 189], "finish_item": [144, 151, 152], "finish_on_complet": 144, "fire": 150, "firmwar": [0, 67, 87, 112, 183, 186, 190, 191, 192, 193, 195], "firmware_bas": 144, "first": [4, 5, 6, 17, 18, 19, 22, 24, 29, 30, 31, 32, 45, 47, 57, 58, 59, 60, 65, 67, 68, 71, 75, 76, 77, 87, 89, 104, 109, 110, 111, 113, 114, 115, 117, 126, 127, 128, 130, 131, 135, 136, 141, 142, 144, 146, 147, 149, 150, 152, 160, 164, 166, 173, 174, 179, 183, 184, 185, 187, 189, 192, 195, 196], "first_b": [114, 115], "first_on": [160, 164], "first_one_detector": 164, "firstib": 22, "fist": [35, 131, 151], "fit": [6, 11, 18, 19, 59], "five": [67, 76, 139, 145, 152, 179], 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[67, 144, 166, 183], "gp": 121, "grai": 1, "granular": 22, "graph": [18, 25, 31, 32], "great": 76, "greater": [17, 48, 60, 75, 101, 109, 121, 147, 166], "ground": 23, "group": [76, 90, 144, 184, 194], "gt": [107, 189], "gty": [107, 166], "gty_40g": 107, "guarante": 129, "guest": 116, "gui": [144, 167, 168, 169], "guid": [23, 31, 144, 156, 161, 171, 172, 173, 179, 187], "guidelin": 144, "h": [31, 32, 119, 131, 173], "h0": 152, "h02": 152, "h04": 152, "h1": 152, "h1f": 152, "h2474b6ac": 152, "h3": 160, "h3_hash": [10, 160], "h3_pack": 10, "h3_type": 10, "h3c_": 10, "h3c_22x11": 10, "h3c_256x64": 10, "h3c_64x16": 10, "h3c_64x22": 10, "h4": 152, "h4c": 152, "h50": 152, "h6fbaaa52": 152, "h7a": 152, "h8": 152, "ha": [0, 1, 5, 6, 10, 11, 12, 18, 19, 21, 29, 31, 42, 43, 44, 45, 47, 58, 59, 60, 62, 67, 68, 71, 75, 76, 80, 87, 88, 89, 94, 104, 109, 110, 113, 118, 119, 125, 126, 127, 128, 130, 131, 133, 135, 136, 137, 138, 139, 141, 142, 143, 144, 146, 149, 150, 152, 160, 161, 166, 167, 168, 169, 183, 184, 185, 186, 187, 188, 189, 191], "had": [47, 89], "hak": 27, "half": [110, 121, 192], "halt": [67, 119], "hand": [76, 104, 118, 119, 184], "handl": [26, 31, 54, 110, 128, 139, 141, 142, 151, 166, 186, 188, 191, 192], "handout": 10, "handshak": [1, 7, 104, 160], "happen": [21, 26, 57, 60, 80, 101, 144], "hard": [29, 31, 109, 111, 116, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 187, 195], "hardwar": [27, 37, 39, 44, 45, 46, 166, 167, 168, 169, 184], "hash": [144, 160], "hash_width": 10, "have": [6, 10, 11, 14, 17, 18, 19, 25, 29, 31, 39, 45, 48, 55, 58, 60, 67, 68, 76, 80, 85, 87, 88, 89, 91, 104, 108, 109, 110, 111, 118, 119, 123, 128, 131, 139, 141, 142, 144, 146, 147, 149, 151, 152, 160, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 183, 187, 189, 195], "hba_rd_chan": 37, "hba_rd_data": 37, "hbm": 183, "hbm_addr_width": 183, "hbm_axi_araddr": 183, "hbm_axi_arburst": 183, "hbm_axi_arid": 183, "hbm_axi_arlen": 183, "hbm_axi_arprot": 183, "hbm_axi_arqo": 183, "hbm_axi_arreadi": 183, "hbm_axi_ars": 183, "hbm_axi_arus": 183, "hbm_axi_arvalid": 183, "hbm_axi_awaddr": 183, "hbm_axi_awburst": 183, "hbm_axi_awid": 183, "hbm_axi_awlen": 183, "hbm_axi_awprot": 183, "hbm_axi_awqo": 183, "hbm_axi_awreadi": 183, "hbm_axi_aws": 183, "hbm_axi_awus": 183, "hbm_axi_awvalid": 183, "hbm_axi_bid": 183, "hbm_axi_breadi": 183, "hbm_axi_bresp": 183, "hbm_axi_bvalid": 183, "hbm_axi_rdata": 183, "hbm_axi_rdata_par": 183, "hbm_axi_rid": 183, "hbm_axi_rlast": 183, "hbm_axi_rreadi": 183, "hbm_axi_rresp": 183, "hbm_axi_rvalid": 183, "hbm_axi_wdata": 183, "hbm_axi_wdata_par": 183, "hbm_axi_wlast": 183, "hbm_axi_wreadi": 183, "hbm_axi_wstrb": 183, "hbm_axi_wvalid": 183, "hbm_burst_width": 183, "hbm_clk": 183, "hbm_data_width": 183, "hbm_id_width": 183, "hbm_init_don": 183, "hbm_len_width": 183, "hbm_port": 183, "hbm_prot_width": 183, "hbm_qos_width": 183, "hbm_reset": 183, "hbm_resp_width": 183, "hbm_size_width": 183, "hbm_user_width": 183, "hc": 152, "hc4d1ce40": 152, "hda7a5407": 152, "hda7a5411": 152, "hda7a54cc": 152, "hdl": [144, 195], "hdp": [39, 45, 46], "hdp_update_chan": 35, "hdp_update_data": 35, "hdp_update_en": 35, "hdp_wr_chan": [37, 44], "hdp_wr_data": [37, 44], "hdp_wr_en": [37, 44], "hdr": [22, 45, 149, 183, 187], "hdr_buff_addr": 42, "hdr_buff_chan": 42, "hdr_buff_data": 42, "hdr_buff_dst_rdi": 42, "hdr_buff_src_rdi": 42, "hdr_id": 183, "hdr_len": 183, "hdr_length": 60, "hdr_meta_width": [39, 42, 45, 46, 48, 59, 78], "hdr_vld": 149, "hdr_width": [62, 69, 131, 144], "hdrm_data_pcie_hdr": 33, "hdrm_data_pcie_hdr_dst_rdi": 33, "hdrm_data_pcie_hdr_s": 33, "hdrm_data_pcie_hdr_src_rdi": 33, "hdrm_dma_hdr_data": 33, "hdrm_dma_hdr_dst_rdi": 33, "hdrm_dma_hdr_src_rdi": 33, "hdrm_dma_pcie_hdr": 33, "hdrm_dma_pcie_hdr_dst_rdi": 33, "hdrm_dma_pcie_hdr_s": 33, "hdrm_dma_pcie_hdr_src_rdi": 33, "hdrm_pkt_drop": 33, "he": [11, 17, 147, 152, 166], "header": [19, 22, 34, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 59, 60, 62, 69, 74, 78, 107, 112, 114, 119, 130, 131, 144, 149, 152, 164, 183, 187, 198], "header_length": 60, "header_width": 152, "heavili": 19, "heb7ab8cc": 152, "help": [19, 31, 32, 60, 144, 179], "helper": 184, "henc": [58, 67, 87, 166], "here": [1, 6, 7, 11, 17, 18, 19, 21, 58, 59, 67, 71, 76, 88, 109, 110, 135, 136, 152, 154, 156, 160, 164, 179, 184, 185, 187, 189], "hexa": 32, "hexadecim": [76, 87], "hf0": 152, "hf404f404f404f404": 152, "hfe": [152, 166], "hfe_empti": 166, "hfe_ful": 166, "hfe_pars": 166, "hfe_pip": 166, "hfe_top": 166, "hft": [135, 136], "hhp": [39, 45], "hhp_update_chan": 35, "hhp_update_data": 35, "hhp_update_en": 35, "hhp_wr_chan": [37, 44], "hhp_wr_data": [37, 44], "hhp_wr_en": [37, 44], "hi": [125, 126, 127, 135, 136, 137, 149, 185], "hi_ber": 107, "hide": 166, "hierarch": 184, "hierarchi": [122, 184], "high": [17, 19, 31, 49, 73, 76, 85, 90, 107, 109, 111, 121, 128, 129, 130, 139, 141, 142, 147, 151, 159, 160, 186, 188, 193, 194], "higher": [17, 18, 49, 58, 87, 89, 100, 110, 121, 125, 137, 138, 144, 160, 166, 184, 188], "highest": [16, 49, 76, 89, 104, 121, 144, 166, 184], "highli": 200, "highspe": 166, "himself": 80, "hint": 113, "hist": [25, 30], "hist_box_cnt": 25, "hist_box_width": 25, "hist_en": 25, "histogram": [0, 24, 25, 30, 31, 154], "histogram_box": [24, 31], "histogramm": 25, "histogrammer_i": 26, "hit": [22, 183, 187], "hitmac": [22, 183, 187], "hitmacvld": [22, 183, 187], "hl": 144, "hl_item": 144, "hl_sequenc": [131, 144], "hl_tr": 151, "hl_transact": 131, "hold": [76, 109, 111, 144], "hole": [146, 195], "hopefulli": 88, "host": [23, 27, 34, 39, 45, 83, 116, 119, 170, 171, 172, 183, 188, 192, 193], "hot": [59, 160], "how": [0, 4, 5, 6, 11, 18, 20, 22, 25, 58, 67, 76, 79, 87, 89, 104, 105, 128, 131, 139, 142, 143, 144, 159, 186, 195], "howev": [5, 11, 18, 31, 58, 60, 67, 76, 87, 88, 100, 110, 138, 144, 184, 185, 187, 188, 195], "hpm": [39, 45], "hpm_rd_chan": 37, "hpm_rd_data": 37, "hsi": 174, "htile_pcie_fix": 173, "html": [144, 174], "http": [10, 13, 27, 135, 136], "huge": 7, "hw": [34, 35, 185, 195], "hyper": 164, "hyper_pip": 164, "hz": [67, 71], "i": [0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 104, 105, 106, 107, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 154, 156, 159, 160, 161, 164, 166, 169, 170, 171, 173, 174, 176, 179, 180, 183, 185, 186, 187, 189, 190, 191, 192, 193, 194, 195, 196, 198], "i0": 11, "i0_deccr": 11, "i0_incr": 11, "i1": 11, "i1_deccr": 11, "i1_incr": 11, "i2": 11, "i2_deccr": 11, "i2_incr": 11, "i2c": [0, 185, 187], "i2c0": [0, 185], "i2c1": [0, 185], "i_array_t": [25, 89], "i_str": 144, "iclud": 184, "id": [14, 21, 22, 23, 45, 54, 58, 59, 60, 71, 85, 108, 109, 117, 118, 119, 179, 180, 181, 183, 187, 192], "id32": 164, "idea": [18, 60, 144, 166, 183], "ideal": [19, 67, 185], "ident": 191, "identif": [112, 164, 183], "identifi": [87, 107, 112, 144, 185], "idl": [19, 67, 75, 104, 107, 111, 129, 130, 149, 164], "idle_count_max": 129, "idle_count_min": 129, "ie": 185, "ieee": 107, "ier": 23, "iff": 144, "ifg": 109, "ignor": [4, 11, 16, 67, 71, 76, 77, 87, 98, 109, 110, 111], "ii": 173, "illegal_bin": 144, "illegalnam": 144, "illustr": [60, 67, 89, 187], "imag": [144, 173], "immedi": [1, 58, 60, 85, 87, 110, 111, 166, 186], "immidi": [80, 118], "impact": [67, 166], "impement": 144, "implement": [0, 3, 4, 5, 9, 11, 13, 14, 16, 18, 27, 35, 37, 52, 60, 63, 68, 76, 77, 79, 82, 83, 86, 101, 102, 105, 106, 107, 109, 111, 119, 129, 131, 144, 146, 156, 160, 161, 164, 173, 183, 184, 185, 186, 187, 191, 192, 195, 196], "implemet": 102, "impli": 67, "implicit": 5, "import": [58, 68, 128, 139, 142, 144, 166, 185], "important_boolean": 184, "imposs": 144, "improv": [46, 98, 144, 146], "in_a": 131, "in_addr": 86, "in_addr_len": 117, "in_address": 117, "in_address_typ": 117, "in_ardi": 86, "in_attribut": 117, "in_axi_tus": 117, "in_b": [86, 131], "in_bus_num": 117, "in_byte_cnt": 117, "in_comp_st": 117, "in_data": 144, "in_drd": 86, "in_drdi": 86, "in_dw_cnt": 117, "in_dw_count": 114, "in_dwr": 86, "in_fb": 117, "in_first_b": 114, "in_head": 117, "in_intel_meta": 117, "in_last_b": 114, "in_lb": 117, "in_lower_addr": 117, "in_meta_func_id": 117, "in_mwr": 86, "in_pipe_en": 62, "in_rd": 86, "in_req_id": 117, "in_req_typ": 117, "in_stream": 54, "in_tag": 117, "in_tc": 117, "in_vfid": 117, "in_wr": 86, "inact": 87, "inbandfc": 109, "inc": [144, 166, 184], "inc_ch": 9, "inc_fifo_s": 9, "inc_rdi": 9, "inc_val": 9, "inc_vld": 9, "inc_width": 9, "includ": [4, 24, 31, 32, 54, 59, 68, 107, 109, 111, 116, 144, 156, 159, 166, 167, 168, 169, 170, 171, 172, 174, 175, 176, 177, 183, 185, 186, 187, 188, 189, 190, 191, 192, 195, 198], "incom": [17, 35, 36, 40, 41, 55, 56, 59, 65, 67, 71, 76, 80, 87, 89, 109, 114, 115, 119, 144, 183, 187], "incoming_fram": 109, "incompat": 184, "incomplet": 76, "inconsistend": 151, "incr": [49, 90], "incr_val_reg": 121, "increas": [11, 17, 34, 64, 67, 68, 72, 75, 88, 109, 110, 125, 137, 138, 160, 185], "increment": [9, 11, 25, 26, 31, 42, 49, 65, 71, 87, 90, 109, 121, 146, 187, 195], "inculd": 166, "indent": 144, "independ": [0, 11, 16, 17, 19, 60, 63, 67, 90, 96, 102, 118, 119, 135, 136, 144, 156, 166, 183, 184, 187, 194], "independetli": 102, "index": [6, 11, 22, 25, 29, 31, 35, 59, 87, 89, 104, 110, 112, 160, 183, 187], "indic": [4, 31, 57, 60, 67, 76, 85, 87, 89, 104, 113, 120, 144, 179, 185], "indirect": [112, 163], "indirectli": 85, "individu": [0, 1, 60, 62, 65, 71, 87, 109, 144, 166, 179, 183, 185, 186, 187, 191, 192], "ineffici": 68, "inf": [14, 60, 65], "inf_channel": 35, "inf_dst_rdi": 35, "inf_meta": 35, "inf_src_rdi": 35, "infinit": 19, "influenc": [87, 96], "info": [8, 17, 27, 78, 109, 144, 184, 187, 189], "inform": [11, 17, 23, 27, 35, 41, 44, 46, 48, 50, 54, 67, 68, 74, 77, 78, 79, 80, 83, 109, 113, 118, 119, 129, 139, 142, 143, 144, 145, 150, 152, 164, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 185, 187, 189, 192, 195, 196], "infram": [128, 133, 139, 142], "infrastructur": 47, "infrom": 11, "ingor": 102, "inherit": [129, 131, 152], "init": 123, "init_ack": 123, "init_addr_base_downto": 89, "init_addr_mask_downto": 89, "init_done_n": 192, "init_port_mapping_downto": 89, "init_sequ": [128, 139, 142, 143, 144], "init_sequence_librari": [128, 139, 142, 143, 144], "initi": [25, 37, 39, 45, 123, 144, 184, 191], "inner": [132, 144], "inout": 180, "input": [3, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 17, 19, 20, 21, 25, 26, 33, 35, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47, 48, 50, 54, 55, 56, 57, 58, 59, 61, 62, 63, 64, 65, 66, 67, 68, 72, 73, 74, 75, 78, 83, 85, 86, 89, 90, 91, 92, 94, 95, 96, 98, 99, 100, 102, 106, 108, 109, 110, 111, 115, 117, 119, 120, 121, 122, 129, 131, 150, 156, 160, 164, 166, 180, 183, 185, 186, 187], "input_1": 3, "input_2": 3, "input_data": 95, "input_data_width": 3, "input_dst_rdi": 95, "input_eq_output": 78, "input_fifo_s": 62, "input_item": 144, "input_mfb": 144, "input_mvb": 144, "input_reg": [8, 91], "input_regs_en": 3, "input_src_rdi": 95, "input_tim": 144, "input_vld": 26, "input_width": [10, 26], "inrement": 11, "insensit": 148, "insert": [10, 34, 48, 50, 60, 61, 64, 74, 75, 107, 109, 111, 119, 152, 166, 183, 185, 187], "insert_mod": 64, "insertor": [38, 39, 59, 107, 162], "insid": [17, 21, 26, 29, 31, 32, 60, 76, 80, 104, 109, 110, 111, 131, 144, 164, 166, 185, 192, 195], "inspir": [13, 67, 144, 183], "instal": [0, 24, 25, 27, 31, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 185, 189], "instanc": [6, 27, 31, 129, 144, 147, 150, 152, 166, 185, 187, 192], "instant": 47, "instanti": [0, 27, 101, 129, 144, 166, 183, 185, 186, 187, 190, 195], "instantiati": 43, "instead": [5, 6, 50, 58, 62, 68, 71, 76, 89, 98, 128, 139, 142, 143, 144, 166, 183, 189], "instrfac": 25, "instruct": [17, 34, 48, 75, 166, 184, 186, 187, 189], "int": [131, 144, 150, 151], "inta": 121, "intefac": [58, 69], "integ": [8, 11, 14, 15, 16, 24, 25, 26, 28, 31, 34, 35, 36, 38, 58, 62, 63, 64, 66, 68, 69, 70, 72, 74, 75, 77, 86, 87, 89, 95, 121, 144, 147, 166, 183], "integer_vector": 180, "integr": [113, 166, 192], "intel": [4, 5, 23, 27, 31, 46, 59, 66, 79, 83, 86, 101, 105, 109, 111, 113, 116, 117, 119, 122, 123, 132, 154, 156, 161, 164, 166, 170, 173, 174, 177, 179, 180, 184, 187, 188, 189, 190, 191, 192], "intel_jtag_op_control": [0, 185], "intel_jtag_op_ctrl": [0, 185], "intel_mac_seg_if": 133, "intel_sdm_control": [0, 185], "intend": [17, 107], "intensli": 58, "inter": [19, 111, 131, 144, 164], "interact": [25, 67, 87], "interconnect": [61, 183, 193], "interest": [10, 125, 137, 138], "interfac": [0, 4, 5, 9, 11, 17, 18, 19, 21, 23, 24, 25, 26, 29, 31, 33, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 54, 55, 56, 57, 58, 59, 61, 62, 63, 66, 67, 68, 69, 70, 71, 72, 73, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 95, 98, 99, 101, 102, 106, 109, 110, 111, 113, 116, 117, 118, 119, 121, 122, 123, 124, 125, 128, 129, 131, 132, 133, 134, 137, 138, 139, 141, 142, 143, 145, 146, 151, 152, 164, 167, 168, 169, 180, 185, 189, 190, 192, 193, 194, 195, 198], "interface_nam": [128, 133, 139, 142, 143, 144, 147], "interfam": 131, "interleav": 89, "intern": [6, 11, 17, 19, 27, 34, 43, 44, 45, 46, 48, 59, 61, 67, 71, 76, 80, 92, 104, 110, 122, 128, 134, 139, 142, 144, 150, 183, 185, 186, 195], "interpret": [102, 166], "interrupt": [23, 31, 110, 164], "interrupt_manag": 164, "interupt": 183, "interv": [18, 67], "interval_count": 67, "interval_length": 67, "intro": 67, "introduc": [129, 144], "invalid": [6, 22, 59, 60, 67, 68, 87, 93, 104, 114, 146], "invert": [74, 107], "ip": [0, 23, 27, 29, 31, 32, 46, 107, 109, 111, 116, 118, 119, 159, 164, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 180, 184, 185, 187, 188, 189, 190, 191, 195, 198], "ipg": 111, "ipg_gener": 132, "ipg_generate_en": 111, "ipv4": [74, 148], "ipv4_min_packet_size_to_fragment_max": 148, "ipv4_min_packet_size_to_fragment_min": 148, "ipv4_prefix_max": 148, "ipv4_prefix_min": 148, "ipv6": 148, "ipv6_min_packet_size_to_fragment_max": 148, "ipv6_min_packet_size_to_fragment_min": 148, "ipv6_prefix_max": 148, "ipv6_prefix_min": 148, "irq": 23, "is_reset": 151, "iset": 11, "isn": 109, "isnt": 144, "isr": 23, "issu": [11, 27, 39, 42, 45, 71, 87, 144, 184], "isunknown": 144, "it_num": 144, "it_str": 144, "item": [4, 5, 6, 7, 11, 13, 14, 15, 16, 17, 18, 22, 27, 48, 49, 50, 52, 54, 55, 59, 60, 61, 62, 63, 64, 65, 67, 68, 69, 70, 71, 73, 74, 75, 76, 77, 78, 79, 87, 89, 90, 91, 92, 95, 96, 98, 99, 100, 101, 102, 104, 105, 106, 109, 111, 113, 116, 131, 132, 143, 144, 145, 146, 165, 183, 185, 187], "item_aux_en": 73, "item_don": 144, "item_s": [139, 142], "item_width": [17, 36, 48, 49, 52, 55, 56, 57, 58, 61, 63, 66, 68, 70, 72, 73, 76, 79, 90, 92, 93, 101, 102, 104, 105, 128, 137, 138, 139, 142, 143, 144, 145, 147, 152, 180], "items_port": 144, "items_s": 144, "items_width": 143, "itoa": 144, "its": [0, 12, 17, 19, 21, 23, 26, 27, 31, 39, 40, 44, 45, 46, 50, 58, 59, 60, 67, 71, 75, 76, 80, 87, 88, 89, 110, 118, 119, 122, 125, 131, 137, 138, 139, 143, 144, 147, 152, 166, 179, 183, 184, 185, 187, 188, 189, 191, 192, 195], "itself": [11, 19, 46, 118, 166, 173, 185, 187], "jakub": 1, "jan": [17, 19, 119], "jenkin": 144, "jic": 170, "join": [11, 68, 144], "join_ani": 144, "json": [31, 148], "jtag": [154, 167, 168, 169, 170, 171, 172, 191], "jtag_op_cli": 27, "jtag_op_mgmt": 27, "jtagconfig": 27, "jump": 144, "just": [0, 14, 31, 58, 67, 83, 89, 123, 129, 144, 146, 147, 150, 183, 184, 187, 189], "keep": [7, 11, 12, 29, 67, 89, 190], "kei": 187, "kept": [71, 83, 118, 119], "keyword": 166, "khz": [30, 31], "kind": [109, 110], "kintex": 46, "kit": [159, 169, 171, 172, 189, 193], "know": [11, 58, 80, 144, 185], "knowledg": [160, 161], "known": 146, "komponenti": 5, "kubalek": [17, 19, 119], "l": [0, 166], "l2": [188, 195], "lane": [59, 107, 129, 180, 192], "lane_align": 107, "lane_rx_polar": 180, "lane_tx_polar": 180, "languag": [144, 166], "lappend": [144, 166, 184], "larg": [18, 19, 27, 59, 63, 67, 110, 144, 166, 185], "large_vector": 184, "larger": [3, 6, 10, 25, 29, 31, 59, 68, 188], "largest": [40, 43, 45], "last": [6, 19, 22, 24, 30, 47, 57, 58, 60, 67, 76, 80, 85, 87, 89, 110, 113, 114, 115, 117, 118, 125, 126, 127, 129, 130, 135, 136, 137, 138, 144, 147, 149, 150, 151, 152, 156, 160, 166, 179, 184, 187], "last_b": [114, 115], "last_on": 160, "last_vld_impl": 60, "lastib": 22, "lastli": 60, "lat_mea": 45, "latch": 160, "latch_out": 12, "late": 166, "latenc": [0, 3, 6, 8, 9, 10, 11, 13, 17, 24, 30, 31, 45, 46, 58, 59, 68, 83, 87, 101, 122, 135, 136, 154, 160, 161, 186, 188, 190, 192], "latency_fifo_depth": 101, "latency_fifo_en": 101, "latency_fifo_ram_typ": 101, "latency_met": [24, 28], "latency_meter_i": 28, "latency_ticks_width": 24, "latency_vld": 28, "later": [11, 18, 41, 87, 101, 124], "latex": 31, "latter": 166, "launch": [166, 184], "layer": [107, 109, 111, 119, 148, 188, 194], "layer_max_numb": 148, "layer_typ": 148, "layout": 58, "lazi": 166, "lbe_in": 115, "lbe_out": 115, "lbu": [109, 111, 132, 187, 197], "lead": [6, 19, 64, 68, 75], "learn": [144, 183, 187, 189], "least": [5, 19, 31, 57, 83, 88, 91, 108], "leav": [67, 89, 101, 166], "left": [4, 5, 6, 8, 23, 46, 67, 76, 79, 87, 104, 105, 110, 160, 187], "len": 183, "len_width": 52, "lenght": [22, 35], "length": [12, 17, 18, 19, 22, 31, 33, 37, 39, 44, 46, 49, 52, 54, 59, 60, 67, 68, 74, 75, 76, 78, 90, 104, 109, 110, 111, 112, 117, 126, 127, 131, 160, 180, 183, 187, 195], "length_width": [49, 60, 74], "leonardo": 160, "less": [4, 5, 27, 54, 67, 87, 89, 109, 111, 161, 184], "lesser": [62, 160], "let": [11, 19, 67, 68, 87, 89, 178], "letter": 76, "level": [0, 27, 45, 46, 58, 122, 123, 124, 125, 128, 129, 130, 132, 133, 134, 137, 138, 140, 141, 142, 143, 145, 151, 166, 180, 181, 184, 185, 187, 190, 193], "lewer": 151, "lfsr": 160, "lfsr_simple_random_gen": [31, 160], "li": 144, "lib": 166, "liberout": [135, 136, 185, 189], "libfdt": [185, 189], "librari": [25, 132, 166, 185, 188], "licens": [109, 111, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 188, 189], "life": 27, "ligc_vector_array_mfb": 137, "light": 161, "ligic": 137, "lii": 132, "like": [10, 11, 25, 49, 59, 76, 87, 89, 110, 112, 119, 123, 128, 138, 139, 142, 143, 144, 146, 152, 166, 180, 184, 187, 194, 195], "limit": [5, 7, 31, 76, 87, 90, 100, 104, 146, 162, 180, 188], "line": [5, 144, 185, 188, 189, 194], "linear": [19, 30], "link": [47, 107, 109, 111, 135, 136, 180, 183, 184, 185, 187, 189, 192, 195], "link_up": 109, "linux": [174, 188, 189], "list": [1, 27, 32, 39, 45, 59, 125, 137, 138, 144, 148, 152, 179, 184, 187, 188, 192, 195], "listen": 30, "lite": [180, 197], "littl": [60, 67], "ll_transact": 144, "load": [18, 21, 27, 29, 31, 58, 67, 119, 144, 160, 166, 170, 171, 172, 173, 174, 184, 185, 193], "local": [27, 147, 183, 195], "locat": [2, 27, 39, 45, 60, 122, 144, 148, 152, 153, 154, 156, 157, 158, 161, 162, 163, 165, 166, 179, 184, 187, 197, 198], "lock": [83, 107, 130], "log": [24, 25, 33, 144], "log2": [4, 5, 8, 9, 13, 14, 15, 16, 17, 26, 28, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 81, 88, 90, 91, 98, 99, 100, 105, 106, 109, 111, 113, 116, 180, 183, 192], "logarithm": [76, 121], "logger": [31, 154], "logic": [2, 3, 6, 11, 19, 27, 29, 31, 37, 39, 42, 45, 46, 47, 61, 64, 67, 68, 75, 80, 82, 89, 92, 93, 95, 102, 107, 111, 118, 121, 123, 124, 128, 129, 131, 132, 133, 134, 135, 136, 139, 142, 144, 145, 146, 147, 150, 151, 156, 164, 180, 183, 184, 186, 192], "logic_vector": [137, 143], "logic_vector_arrai": [139, 142], "logic_vector_array_axi": [124, 132], "logic_vector_array_axi_env": 139, "logic_vector_array_mfb": [132, 138, 143], "logic_vector_array_mfb_env": 142, "logic_vector_mvb": 132, "logic_vector_mvb_env": 143, "long": [17, 20, 21, 33, 76, 80, 87, 164], "look": [11, 67, 89, 110, 121, 152, 160, 179, 187], "lookup": [152, 165], "loop": [11, 67, 102, 144, 162, 174, 186, 195], "loopback": [48, 107, 162, 174, 186, 187, 189, 195], "lost": 95, "lot": [18, 102, 144, 151], "low": [11, 17, 49, 67, 75, 90, 109, 111, 121, 122, 123, 124, 129, 132, 133, 134, 135, 136, 140, 145, 151, 186, 188, 192], "lower": [1, 5, 6, 14, 17, 18, 21, 39, 45, 49, 55, 58, 62, 68, 75, 87, 89, 93, 100, 109, 110, 117, 120, 121, 125, 137, 138, 144, 160, 187], "lowest": [11, 23, 46, 47, 48, 49, 76, 88, 89, 104, 166, 184], "lsb": [76, 85, 95, 104, 110], "lsearch": 166, "luckili": 11, "lut": [4, 5, 13, 44, 77, 79, 82, 101, 105, 156, 161], "lut_arch": 106, "lut_depth": 106, "lut_width": 106, "lutmem": 156, "lutram": [4, 106], "lvt_mem": [13, 161], "m": [0, 6, 18, 31, 32, 95, 151, 160], "m1_": 131, "m_": 144, "m_agent": 144, "m_byte_arrai": 144, "m_byte_array_ag": 144, "m_byte_array_cfg": 144, "m_cfg": [128, 139, 142, 143], "m_compar": 144, "m_config": [128, 139, 142, 143, 144], "m_config_sequenc": 144, "m_cov": 144, "m_data": 152, "m_driver": 144, "m_env": [128, 139, 142, 143, 144], "m_eth": [128, 142, 143], "m_fifo_input": 131, "m_meta": 152, "m_mfb_agent": 144, "m_mfb_cfg": 144, "m_mfb_sequenc": 144, "m_model": 144, "m_model_a": 131, "m_model_b1": 131, "m_model_b2": 131, "m_monitor": 144, "m_mvb_sequenc": 144, "m_regmodel": 144, "m_reset": [128, 139, 142, 143], "m_root": 144, "m_sequenc": 144, "m_valu": 131, "mac": [22, 49, 107, 132, 148, 166, 180, 183, 188, 191, 195, 197], "mac_check": 109, "mac_check_en": 109, "mac_count": 109, "mac_loopback": 187, "mac_prefix_max": 148, "mac_prefix_min": 148, "machin": [27, 130], "macro": [144, 152, 166], "made": [7, 18, 30, 31, 110, 144, 146, 151, 164, 179, 187], "mai": [4, 5, 6, 19, 21, 47, 58, 67, 68, 76, 87, 95, 104, 109, 111, 116, 118, 119, 131, 144, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 184, 188, 189, 195], "mailbox": [23, 144], "main": [11, 17, 21, 22, 47, 65, 71, 107, 109, 111, 119, 121, 122, 125, 137, 138, 149, 166, 184, 185, 187, 188, 192], "mainli": [19, 166, 192, 195], "maintain": [76, 104, 164], "major": [76, 87, 110, 125, 131, 137, 138, 151, 184, 188], "make": [0, 19, 25, 27, 32, 60, 67, 76, 87, 89, 107, 109, 118, 129, 144, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 184, 185, 187], "make_param": 166, "makefil": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 186, 192], "malfunct": 189, "manag": [23, 26, 33, 39, 42, 45, 119, 120, 167, 168, 169, 187, 198], "mandatori": [60, 166, 185], "mandatory_ipv4_address_rang": 148, "mandatory_ipv6_address_rang": 148, "mandatory_mac_address_rang": 148, "mani": [18, 22, 25, 79, 87, 89, 105, 119, 129, 144, 160, 184, 190], "manipul": [39, 45], "manner": 110, "manual": [27, 29, 31, 32, 67, 144, 167, 168, 169, 173, 195], "manuali": 31, "manufactur": [188, 189], "map": [0, 24, 25, 26, 28, 31, 83, 86, 87, 107, 112, 118, 119, 122, 131, 166, 183, 186, 187, 195], "mark": [6, 47, 80, 92, 95, 156, 196], "markdown": [25, 31], "marker": 107, "mash": 144, "mask": [16, 18, 22, 37, 39, 45, 58, 59, 63, 76, 80, 84, 92, 104, 109, 183, 187], "masker": 162, "masking_en": 63, "master": [44, 59, 82, 84, 87, 90, 107, 109, 111, 116, 121, 122, 144, 146, 183, 191], "master_driv": 146, "master_sequ": 146, "match": [107, 109, 144, 185], "math_pack": 144, "math_pkg": 144, "mathemat": 144, "matplotlib": 25, "matter": [11, 187], "max": [0, 5, 16, 25, 28, 30, 31, 33, 36, 38, 39, 40, 41, 42, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 90, 91, 99, 100, 106, 109, 111, 113, 116, 121, 125, 128, 137, 138, 139, 142, 143, 144, 151, 152, 180, 183, 192], "max_concurrent_ev": 18, "max_en": 25, "max_flow_inter_packet_gap": 148, "max_interval_cycl": 18, "max_paralel_ev": 28, "max_paralel_read": 24, "max_transaction_count": 147, "max_word": 60, "maxim": [25, 30, 31, 59, 109], "maximum": [3, 6, 11, 17, 18, 19, 20, 24, 25, 27, 35, 37, 39, 44, 45, 46, 48, 49, 50, 54, 55, 60, 63, 67, 74, 75, 77, 78, 81, 100, 104, 109, 111, 116, 121, 125, 128, 131, 137, 138, 139, 142, 143, 148, 151, 180, 183, 188, 192, 195, 196], "maxtu": [22, 183, 187], "mb1_in": 131, "mb2_in": 131, "mblock_siz": 60, "mbp": 67, "mcio": 172, "md": [27, 31, 188, 189], "mdio": 187, "mean": [14, 17, 18, 22, 33, 47, 58, 60, 67, 68, 76, 85, 87, 88, 89, 101, 104, 121, 144, 145, 146, 152, 160, 166, 183, 184, 187, 192], "meant": [19, 80, 87], "measur": [0, 18, 24, 28, 30, 31, 45, 144, 180, 190, 195], "mechan": [1, 17, 47, 67, 93, 104, 112, 144, 151, 166, 184, 185], "media": [135, 136], "mediat": 193, "medium": 149, "medusa": [159, 198], "meet": [12, 67, 110], "mem": [0, 25, 183, 190], "mem_addr_width": [24, 183], "mem_address": 24, "mem_async": 24, "mem_avmm_address": [24, 183], "mem_avmm_burstcount": [24, 183], "mem_avmm_read": [24, 183], "mem_avmm_readdata": [24, 183], "mem_avmm_readdatavalid": [24, 183], "mem_avmm_readi": [24, 183], "mem_avmm_writ": [24, 183], "mem_avmm_writedata": [24, 183], "mem_burst_count": 24, "mem_burst_count_width": 24, "mem_burst_width": [24, 183], "mem_clk": [24, 183], "mem_data_width": [24, 183], "mem_def_refr_period": 183, "mem_freq_khz": 24, "mem_logg": [0, 24, 25, 30, 31, 185], "mem_logger_0": [0, 185], "mem_logger_1": [0, 185], "mem_logger_2": [0, 185], "mem_logger_3": [0, 185], "mem_logger_i": 24, "mem_mi_addr": 24, "mem_mi_ardi": 24, "mem_mi_b": 24, "mem_mi_drd": 24, "mem_mi_drdi": 24, "mem_mi_dwr": 24, "mem_mi_rd": 24, "mem_mi_wr": 24, "mem_port": 183, "mem_read": 24, "mem_read_data": 24, "mem_read_data_valid": 24, "mem_readi": 24, "mem_refr_ack": 183, "mem_refr_period": 183, "mem_refr_period_width": 183, "mem_refr_req": 183, "mem_rst": [24, 183], "mem_test": [0, 24, 31, 185], "mem_tester_0": [0, 185], "mem_tester_1": [0, 185], "mem_tester_2": [0, 185], "mem_tester_3": [0, 185], "mem_tester_mi": 31, "mem_tester_report": [31, 32], "mem_typ": 13, "mem_writ": 24, "mem_write_data": 24, "memori": [2, 4, 5, 11, 14, 15, 21, 22, 23, 24, 27, 29, 32, 34, 39, 48, 67, 77, 79, 82, 83, 87, 105, 109, 118, 122, 126, 127, 154, 156, 159, 160, 164, 170, 171, 172, 183, 187, 188, 191, 192, 193], "memory_filepath": 122, "memx": 44, "menawhil": 58, "mention": [27, 67, 76, 89, 166, 187], "merg": [0, 54, 62, 63, 68, 71, 95, 102, 126, 127, 131, 144, 165, 187], "merge_n_to_m": 165, "merger": [0, 119, 162, 187], "merger_input": 63, "messag": [31, 131, 144], "messi": 89, "met": 67, "meta": [59, 69, 74, 82, 83, 89, 104, 117, 131, 144, 145, 146, 183], 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"mfb_auxiliary_sign": [18, 73], "mfb_block_reconfigur": 68, "mfb_block_siz": [42, 43, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 71, 74, 75, 77, 78, 81, 100, 113, 116, 183], "mfb_cfg": 144, "mfb_crossbarx_output_buff": 78, "mfb_crossbarx_stream2": 54, "mfb_cutter_simpl": 55, "mfb_data": [128, 142], "mfb_dropper": 56, "mfb_dst_rdy": 35, "mfb_enabl": 57, "mfb_eof": 35, "mfb_fifo_depth": 50, "mfb_fifox": [65, 79], "mfb_frame_extend": 50, "mfb_frame_mask": 58, "mfb_frame_trimm": 52, "mfb_gen2dma": [0, 185], "mfb_gen2eth": [0, 185], "mfb_gener": [0, 185], "mfb_generator_mi32": [48, 49], "mfb_if": [128, 142, 143, 144], "mfb_item_reconfigur": 68, "mfb_item_width": [42, 43, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 71, 74, 75, 77, 78, 81, 100, 113, 116, 183], "mfb_loopback": 61, "mfb_merger": [59, 62], "mfb_merger_simpl": 63, "mfb_merger_simple_gen": 63, "mfb_meta_width": [60, 62, 63, 64, 65, 67, 71, 74, 75, 78, 81], "mfb_meta_with_sof": 78, "mfb_metadata": [128, 142], "mfb_packet_delay": 65, "mfb_pd_asfifo": 111, "mfb_pd_asfifo_simpl": 81, "mfb_pipe": [58, 66], "mfb_properti": 144, "mfb_reg_siz": [62, 69, 77, 183], "mfb_region": [35, 42, 43, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 71, 74, 75, 77, 78, 81, 100, 113, 116, 183], "mfb_region_reconfigur": 68, "mfb_region_s": [42, 43, 50, 54, 59, 60, 63, 64, 65, 67, 71, 74, 75, 78, 81, 100, 113, 116], "mfb_region_width": [113, 116], "mfb_rx_speed": [128, 142], "mfb_sequenc": 144, "mfb_splitter": 69, "mfb_splitter_gen": 69, "mfb_splitter_properti": 144, "mfb_splitter_simpl": 70, "mfb_splitter_simple_gen": 70, "mfb_src_rdy": 35, "mfb_timestamp_limit": 71, "mfb_to_lbus_reconf": 110, "mfb_tool": [162, 195], "mfb_transform": 72, "mfb_word_width": 67, "mfifo": 109, "mfifo_ovf": 109, "mgmt": [107, 187], "mhz": [18, 46, 67, 107, 188, 192], "mi": [18, 23, 24, 27, 37, 39, 44, 45, 46, 48, 49, 61, 67, 71, 83, 84, 90, 107, 109, 111, 121, 132, 144, 164, 180, 183, 185, 186, 187, 192, 193, 195, 198], "mi0": 185, "mi2avmm": [23, 163], "mi2axi4": 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29, 31, 67, 71, 84, 90, 116, 180, 183], "mi_data_width_phi": 180, "mi_dbg": 192, "mi_dbg_addr": 192, "mi_dbg_ardi": 192, "mi_dbg_b": 192, "mi_dbg_drd": 192, "mi_dbg_drdi": 192, "mi_dbg_dwr": 192, "mi_dbg_rd": 192, "mi_dbg_wr": 192, "mi_debug": 174, "mi_drd": [24, 25, 31, 37, 39, 44, 45, 46, 48, 49, 61, 67, 71, 83, 84, 90, 107, 109, 111, 116, 121, 180, 183, 192], "mi_drd_phi": 180, "mi_drd_pmd": 180, "mi_drdi": [24, 25, 31, 37, 39, 44, 45, 46, 48, 49, 61, 67, 71, 83, 84, 90, 107, 109, 111, 116, 121, 180, 183, 192], "mi_drdy_phi": 180, "mi_drdy_pmd": 180, "mi_dwr": [24, 25, 31, 37, 39, 44, 45, 46, 48, 49, 61, 67, 71, 83, 84, 90, 107, 109, 111, 116, 121, 180, 183, 192], "mi_dwr_phi": 180, "mi_dwr_pmd": 180, "mi_events_addr": 18, "mi_funct": 116, "mi_indirect_access": 85, "mi_interval_addr": 18, "mi_m_addr": 82, "mi_m_ardi": 82, "mi_m_b": 82, "mi_m_drd": 82, "mi_m_drdi": 82, "mi_m_dwr": 82, "mi_m_mwr": 82, "mi_m_rd": 82, "mi_m_wr": 82, "mi_mwr": 83, "mi_pip": [86, 116], "mi_pipe_en": 48, "mi_rd": [24, 25, 31, 37, 39, 44, 45, 46, 48, 49, 61, 67, 71, 83, 84, 90, 107, 109, 111, 116, 121, 180, 183, 192], "mi_rd_phi": 180, "mi_rd_pmd": 180, "mi_read": 146, "mi_reset": [48, 61, 107, 109, 111, 121, 180, 183, 192], "mi_reset_phi": 180, "mi_reset_pmd": 180, "mi_reset_reg": 71, "mi_rst": 31, "mi_s_addr": 82, "mi_s_ardi": 82, "mi_s_b": 82, "mi_s_drd": 82, "mi_s_drdi": 82, "mi_s_dwr": 82, "mi_s_mwr": 82, "mi_s_rd": 82, "mi_s_wr": 82, "mi_sel_queue_reg": 71, "mi_splitter_plus_gen": [31, 87, 89], "mi_test_spac": [0, 185, 195], "mi_tool": 163, "mi_top_speed_reg": 71, "mi_width": [18, 37, 39, 44, 45, 46], "mi_wr": [24, 25, 31, 37, 39, 44, 45, 46, 48, 49, 61, 67, 71, 83, 84, 90, 107, 109, 111, 116, 121, 180, 183, 192], "mi_wr_phi": 180, "mi_wr_pmd": 180, "mi_writ": 146, "mid_do": 144, "middl": [57, 76, 120, 121, 128, 130, 139, 142, 144, 151], "might": [11, 17, 21, 67, 68, 80, 87, 88, 89, 95, 144], "mii": [107, 109, 111, 132], "milisecond": 18, "min": [0, 25, 30, 31, 49, 52, 55, 75, 90, 109, 125, 128, 137, 138, 139, 142, 143], "min_en": 25, "min_packet_size_to_frag": 148, "min_transaction_count": 147, "minim": [25, 30, 31, 59, 109, 111, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 185, 190], "minimalist": [52, 184], "minimum": [4, 19, 24, 27, 45, 46, 49, 60, 62, 67, 69, 77, 90, 100, 109, 111, 125, 137, 138, 148, 151, 166, 180, 183, 187], "minimumspe": 67, "minor": 185, "mintu": [22, 109, 183, 187], "mintu_check": 109, "minu": 21, "minut": 174, "misc": 86, "miscellan": 2, "miss": 184, "mk": 166, "mlab": 4, "mm": [0, 23, 83, 183, 190], "mod": [0, 144, 160, 180, 183], "mod_width": 54, "mode": [0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 28, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 113, 114, 115, 116, 117, 118, 120, 121, 135, 136, 144, 146, 161, 164, 174, 180, 183, 184, 186, 187, 192, 195], "model": [58, 122, 131, 150, 166, 200], "model_a": 131, "model_b": 131, "model_data": 144, "model_entityb": 131, "model_in": 144, "model_input_fifo": 144, "model_item": [131, 144], "model_tr_timeout_set": 131, "model_typ": 131, "modelsim": [89, 144, 166], "modif": [54, 110, 185], "modifi": [11, 26, 54, 67, 68, 88, 129, 131, 144, 152, 160, 166, 189, 195], "modport": 147, "modprob": 174, "modul": [0, 2, 22, 24, 25, 27, 37, 39, 46, 47, 48, 54, 59, 61, 90, 109, 111, 116, 119, 121, 153, 159, 164, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 185, 189, 190, 191, 193, 194, 196], "modular": [109, 111, 184], "modulo": 160, "modulo_lookup": 160, "moment": [17, 67, 109, 111, 128, 142], "mon": 144, "monitor": [18, 59, 107, 132, 164, 188], "more": [0, 1, 5, 7, 11, 16, 17, 19, 28, 31, 41, 47, 57, 58, 59, 60, 67, 68, 75, 76, 77, 79, 83, 85, 87, 89, 95, 96, 98, 107, 109, 112, 119, 121, 122, 129, 135, 136, 139, 142, 143, 144, 145, 146, 151, 152, 166, 167, 168, 169, 183, 184, 187, 188, 189, 192, 193, 194, 195], "moreov": [107, 123], "most": [5, 7, 19, 32, 58, 59, 67, 68, 76, 88, 89, 95, 104, 109, 144, 152, 166, 184, 192], "mostli": [76, 166, 184], "move": [110, 164], "mp_bram": [14, 161], "msb": [0, 67, 76, 89, 104, 110], "msg": [117, 144], "msg_byte_arrai": 144, "msg_mvb": 144, "msg_port": 144, "msgd": 117, "msix": 191, "mtc": [191, 192, 198], "mtu": [48, 109, 183, 185], "mtu_check": 109, "mty": 134, "much": [20, 47, 62, 89, 119, 131, 187], "mul48": 160, "mult_region": 45, "multi": [1, 11, 17, 19, 21, 25, 44, 45, 50, 64, 76, 80, 91, 98, 99, 102, 104, 107, 112, 118, 129, 160, 187], "multi_fifo": 156, "multi_fifox": 102, "multicast": [22, 109, 183, 187], "multip": 80, "multipl": [5, 6, 9, 11, 13, 16, 17, 19, 21, 23, 28, 31, 40, 42, 44, 45, 46, 54, 58, 59, 60, 63, 67, 68, 72, 76, 83, 87, 88, 89, 98, 100, 104, 118, 119, 120, 121, 131, 144, 151, 156, 160, 161, 162, 165, 166, 174, 183, 184, 186, 187, 192, 193, 194, 195], "multiplex": [2, 17, 99, 102, 160], "multiplexor": 121, "multipli": [76, 89, 98, 120, 121, 147, 160], "multiport": [13, 161], "multir": 187, "multiv": 144, "must": [4, 5, 6, 11, 13, 14, 16, 17, 19, 23, 31, 47, 48, 49, 50, 54, 60, 64, 65, 67, 71, 74, 75, 76, 77, 80, 81, 82, 83, 84, 85, 87, 88, 89, 90, 94, 95, 96, 98, 99, 100, 101, 102, 106, 109, 110, 111, 112, 116, 118, 119, 121, 125, 131, 135, 136, 137, 138, 144, 146, 147, 148, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 180, 183, 185, 187, 188, 189, 191, 192, 196], "mux": [48, 59, 86, 102, 160, 165], "mux_a": 48, "mux_b": 48, "mux_c": 48, "mux_d": 48, "mux_dsp": 160, "mux_lat": 8, "mux_width": 99, "mvb": [0, 5, 19, 33, 35, 48, 50, 54, 59, 60, 62, 64, 69, 74, 78, 95, 100, 109, 118, 119, 132, 143, 144, 180, 183, 186, 187, 192], "mvb2mfb": 165, "mvb_agent": 144, "mvb_aggregate_last_vld": 60, "mvb_channel": 183, "mvb_channel_rout": [0, 185], "mvb_channel_router_mi": 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"n_loop_op_pro": 160, "n_one": 160, "n_to_m_handshak": 160, "nad": 147, "name": [10, 11, 17, 22, 27, 39, 45, 46, 47, 58, 59, 60, 65, 70, 71, 74, 75, 76, 87, 90, 104, 109, 110, 111, 112, 121, 122, 128, 131, 133, 135, 136, 139, 142, 143, 144, 145, 146, 147, 149, 150, 151, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 180, 183, 184, 185, 187, 189, 196], "namespac": 144, "nanosecond": [109, 120, 121, 183, 196], "natur": [3, 4, 5, 6, 7, 9, 10, 13, 14, 16, 18, 20, 33, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 59, 60, 61, 62, 63, 64, 65, 67, 68, 70, 71, 73, 74, 75, 76, 77, 78, 79, 81, 82, 83, 84, 85, 90, 91, 92, 93, 94, 96, 98, 99, 100, 101, 102, 104, 105, 106, 109, 111, 113, 116, 117, 135, 136, 149, 180, 183, 192], "nb_main": 166, "nb_preference_filt": 166, "ndk": [27, 46, 76, 135, 136, 179, 183, 186, 187, 190, 191, 192], "ndk_minim": [185, 189], "ndp": 183, "nearest": [6, 60], "neccessari": 166, "necesari": 60, "necess": 166, "necessari": [3, 59, 67, 87, 104, 109, 111, 131, 144, 152, 166, 180, 183, 184, 185, 188, 192], "need": [6, 11, 18, 19, 20, 22, 24, 25, 27, 31, 32, 38, 39, 44, 45, 50, 58, 67, 68, 76, 89, 101, 102, 110, 111, 112, 119, 129, 144, 160, 164, 166, 179, 185], "neg": [75, 107], "negat": 83, "neither": [17, 68, 87, 166], "nessesari": 11, "net": 144, "net_mod_logic_env": 144, "netcop": [0, 32, 185], "network": [0, 22, 74, 90, 109, 144, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 189, 193, 194, 195, 196], "network_mod": [179, 180], "network_ord": 74, "network_port_id": 109, "never": [17, 19, 58, 67, 87, 151], "new": [17, 21, 26, 32, 50, 52, 58, 60, 67, 80, 87, 109, 118, 119, 121, 125, 128, 131, 137, 138, 139, 142, 143, 144, 148, 150, 152, 170, 171, 172, 183, 184, 189, 193, 195, 200], "new_data": 13, "new_rx_tran": 17, "newli": [17, 18, 87, 166], "newlin": 144, "next": [11, 18, 19, 31, 49, 57, 58, 59, 60, 62, 65, 67, 75, 76, 80, 87, 89, 96, 98, 102, 104, 110, 112, 129, 135, 136, 144, 151, 166, 173, 185], "next_act": 147, "nfb": [0, 24, 25, 27, 31, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 187, 188, 189, 191, 195, 196], "nfb0": [31, 185], "nfw": 189, "nic": [187, 197], "ninit_don": 192, "no_oper": 146, "node": [185, 189], "non": [11, 17, 115, 118, 144, 166, 179, 191], "non_parametrized_class": 144, "none": [5, 18, 45, 66, 67, 79, 99, 166], "nor": [17, 68, 87, 160, 166], "normal": [14, 125, 137, 138, 187], "notat": 187, "note": [5, 11, 43, 45, 48, 49, 58, 59, 71, 76, 87, 89, 104, 128, 139, 142, 173], "notic": [58, 67, 87, 110, 184], "notifi": 109, "now": [11, 18, 30, 32, 54, 87, 89, 118, 144, 152, 179, 187], "np": 44, "np_lutram": [11, 15, 160, 161], "np_lutram_pro": [160, 161], "npp": 48, "npp_hdr_size": 48, "null": [14, 122, 126, 127, 128, 131, 139, 142, 143, 144], "nullifi": 93, "num": 144, "num_of_pkt": 75, "numa": 189, "number": [0, 3, 4, 5, 6, 9, 11, 14, 16, 17, 18, 19, 22, 24, 25, 26, 27, 28, 30, 31, 32, 33, 34, 35, 36, 37, 39, 40, 43, 44, 45, 46, 48, 49, 50, 54, 55, 59, 60, 61, 62, 63, 65, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 81, 83, 85, 87, 89, 90, 92, 94, 95, 96, 98, 99, 100, 101, 102, 104, 105, 109, 110, 111, 112, 114, 116, 117, 118, 120, 121, 125, 126, 127, 129, 131, 133, 137, 138, 144, 148, 149, 151, 152, 160, 161, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 180, 183, 184, 185, 186, 187, 189, 192, 194, 195, 196], "number_of_channel": 187, "number_of_item": [34, 35], "number_of_max_item": 34, "numer": [70, 144], "numeric_std": 144, "numericstdnowarn": 144, "o": [31, 189], "object": [125, 128, 135, 136, 137, 138, 139, 142, 143, 149, 150, 151, 166], "obligatori": [58, 180], "observ": [128, 133, 139, 141, 142, 144], "obsolet": [95, 109, 111, 156, 161], "obtain": [0, 23, 76, 112, 184, 195], "obuf_input_eq_output": 75, "obuf_meta_eq_output": 75, "occupi": [27, 89, 104], "occur": [11, 18, 19, 25, 26, 28, 30, 31, 42, 49, 58, 62, 68, 76, 96, 104, 109, 110, 118, 119, 130, 131, 144, 164, 166, 179], "occurr": [25, 87, 130], "octect": 111, "octet": [109, 111, 129], "ocurr": 151, "od": 17, "ofc": 70, "off": [60, 90, 107, 111, 122, 146, 148, 170, 171, 172, 187], "offer": 144, "offset": [19, 23, 34, 45, 48, 60, 65, 67, 71, 74, 83, 107, 109, 111, 112, 187, 195], "offset_processor": 60, "offset_width": [60, 74], "ofm": [0, 2, 27, 31, 109, 111, 112, 153, 154, 157, 158, 162, 163, 165, 184, 185, 195, 197, 198], "ofm_path": [27, 144, 166], "ofs_pmci": [0, 185], "often": [5, 6, 67, 76, 87, 104, 110, 144, 166, 184, 190], "og": 19, "ok": [65, 109], "old": [9, 60, 62, 121, 161, 164], "older": [18, 58], "omit": [12, 67], "onc": [11, 17, 18, 19, 44, 58, 59, 68, 80, 87, 130, 149, 173, 187, 193], "one": [0, 1, 3, 5, 8, 10, 11, 12, 14, 16, 17, 18, 19, 20, 21, 26, 27, 29, 31, 38, 39, 44, 45, 47, 56, 58, 59, 60, 62, 63, 64, 67, 68, 69, 70, 71, 72, 76, 80, 82, 83, 85, 87, 89, 91, 93, 94, 96, 98, 99, 101, 102, 104, 108, 109, 110, 111, 116, 118, 119, 121, 123, 124, 125, 126, 127, 128, 129, 130, 131, 133, 135, 136, 137, 138, 139, 141, 142, 143, 144, 146, 147, 150, 151, 152, 156, 160, 161, 162, 164, 165, 166, 183, 184, 186, 187, 192, 193, 194], "one_clk_writ": 14, "ones": [27, 47, 89, 98, 110, 115, 144, 151, 152, 160, 184], "onli": [0, 1, 3, 4, 5, 6, 7, 11, 14, 16, 17, 18, 19, 20, 21, 22, 25, 27, 31, 38, 48, 49, 50, 57, 58, 59, 60, 62, 65, 67, 68, 70, 71, 75, 76, 79, 80, 82, 83, 86, 87, 88, 89, 90, 93, 101, 104, 105, 106, 107, 109, 110, 111, 112, 113, 116, 117, 118, 119, 121, 124, 125, 126, 127, 130, 131, 133, 135, 136, 137, 138, 139, 141, 144, 145, 146, 147, 149, 152, 156, 159, 160, 161, 164, 166, 170, 171, 172, 173, 176, 180, 183, 184, 185, 186, 187, 188, 189, 190, 192, 200], "onto": 173, "op": [60, 101, 132], "op_": 11, "op_data_in": 11, "op_data_out": 11, "op_in_": 11, "op_in_data": 11, "op_in_meta": 11, "op_in_op": 11, "op_in_sel": 11, "op_in_src": 11, "op_item_sel": 11, "op_meta": 11, "op_oper": 11, "op_out_data": 11, "open": [23, 27, 31, 159, 167, 168, 169, 186, 189], "open_loop": 1, "oper": [0, 59, 60, 68, 89, 107, 109, 111, 118, 144, 160, 165, 166, 185, 189], "operatio": 11, "operators_pr": 11, "opposit": [83, 110], "opt": 86, "opt_mod": 90, "optic": [107, 194], "optim": [11, 59, 62, 86, 90, 156, 159, 160, 161, 164, 179, 186, 193], "option": [3, 4, 5, 12, 19, 20, 27, 31, 45, 46, 49, 58, 60, 64, 65, 71, 74, 77, 79, 82, 83, 87, 92, 101, 105, 107, 109, 111, 114, 120, 131, 135, 136, 148, 166, 171, 172, 174, 180, 185, 186], "ordder": [135, 136], "order": [5, 6, 9, 11, 17, 19, 21, 22, 23, 31, 39, 42, 45, 47, 67, 68, 71, 74, 87, 94, 96, 102, 107, 110, 117, 118, 131, 143, 144, 148, 164, 165, 166, 179, 184], "ordinari": 110, "ored": 151, "org": [13, 135, 136, 185, 189], "organ": [76, 184], "orient": [5, 128, 139, 142, 183, 191], "origin": [19, 21, 52, 55, 58, 59, 64, 68, 88, 164], "oroc": 109, "oroch": 109, "orocl": 109, "othe": 68, "other": [3, 6, 7, 9, 11, 16, 17, 18, 19, 21, 25, 31, 40, 45, 47, 49, 55, 57, 58, 59, 62, 63, 64, 66, 67, 68, 69, 71, 76, 78, 84, 87, 88, 89, 104, 107, 109, 111, 117, 118, 120, 122, 125, 128, 129, 131, 135, 136, 137, 139, 142, 143, 149, 151, 152, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 180, 184, 185, 187, 189, 192, 195], "otherwis": [4, 7, 19, 61, 67, 80, 95, 109, 111, 128, 139, 142, 143, 144, 166, 185], "our": [11, 18, 76, 87, 89, 144, 159, 186, 187, 189, 194], "out": [3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 20, 21, 24, 25, 26, 28, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 113, 114, 115, 116, 117, 120, 121, 144, 152, 164, 180, 183, 192], "out_addr": 86, "out_addr_len": 117, "out_address": 117, "out_address_typ": 117, "out_ardi": 86, "out_attribut": 117, "out_b": 86, "out_bar_apertur": 117, "out_bar_id": 117, "out_byte_cnt": 117, "out_byte_count": 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191], "package_nam": 166, "packer": 162, "packet": [0, 33, 35, 36, 37, 38, 39, 40, 44, 45, 46, 47, 48, 49, 54, 55, 56, 57, 58, 59, 60, 67, 69, 70, 71, 74, 75, 78, 108, 109, 111, 113, 125, 128, 131, 137, 138, 139, 141, 142, 144, 148, 150, 152, 159, 162, 164, 180, 186, 193, 194, 195, 196, 197], "packet_head": 131, "packet_max_s": 148, "packet_min_s": 148, "packet_plann": 164, "packet_port_env": 144, "packet_s": 131, "packet_size_max_step": 148, "packet_size_min_step": 148, "packet_size_prob": 148, "packet_splitt": 144, "packets_max_numb": 148, "packets_min_numb": 148, "packets_rev_max_numb": 148, "packets_rev_min_numb": 148, "packetsh": [39, 45], "packetsl": [39, 45], "pacsign": 177, "pactek": 108, "pad": [27, 183], "page": [47, 76, 104, 144, 155, 184], "pai": 67, "pair": [112, 166, 187], "pakcet": 19, "paket": 144, "pandoc": 31, "pane": 27, "paper": 10, "paragraph": 67, "paral": 24, "paralel": [0, 28], "parallel": [11, 17, 19, 28, 60, 88, 118, 160, 164], "param": [144, 185], "param_cfg": [128, 142, 143, 144], "paramet": [4, 14, 16, 20, 25, 31, 32, 35, 36, 38, 40, 43, 47, 58, 59, 63, 66, 67, 68, 77, 79, 81, 82, 85, 87, 90, 96, 100, 110, 111, 113, 116, 122, 123, 124, 125, 128, 131, 132, 133, 135, 136, 137, 138, 139, 142, 143, 144, 145, 146, 147, 149, 150, 152, 166, 174, 179, 180, 183, 185, 186, 187, 192, 195], "parameter": [68, 123], "parametr": [4, 186], "parametrized_class": 144, "paramt": 110, "paremet": 110, "parent": [112, 128, 131, 139, 142, 143, 144, 184, 185], "pars": [41, 144, 166, 198], "parsepcieconf": 184, "part": [11, 14, 21, 35, 39, 45, 47, 48, 49, 50, 58, 76, 78, 87, 88, 89, 109, 110, 111, 118, 119, 121, 150, 159, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 184, 186, 187, 189, 191, 192, 195], "partial": [58, 59, 68, 131], "particip": 104, "particular": [67, 112, 125, 137, 138], "partner": [159, 186, 187], "pasid": 22, "pasidvld": 22, "pasiv": 151, "pass": [17, 18, 19, 21, 59, 71, 107, 109, 118, 144, 148, 164, 166, 185, 187, 195], "passiv": [125, 135, 136, 137, 138, 144, 149], "path": [0, 21, 27, 32, 47, 64, 66, 87, 107, 119, 122, 144, 150, 164, 166, 174, 184, 188, 195], "path_to_entity_1": 184, "path_to_entity_2": 184, "pattern": [67, 129, 144, 151], "paus": [65, 71, 76, 104, 183], "pause_queu": 71, "pause_request": 65, "payload": [62, 69, 114, 116, 183, 192, 195], "pc": [109, 111, 116, 170, 171, 172, 180, 187, 191, 192, 193, 195], "pcap": 148, "pci": [22, 42, 45, 46, 87, 112, 113, 115, 185, 189, 192], "pci0": 185, "pci_ext_cap": [185, 192, 198], "pcie": [22, 27, 33, 35, 39, 40, 41, 43, 45, 76, 112, 116, 118, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 184, 185, 186, 189, 191, 193], "pcie_10b_tag_req_en": 192, "pcie_byte_count": 114, "pcie_byte_en_decod": 115, "pcie_cc_hdr_gen": 117, "pcie_cc_meta_width": [116, 192], "pcie_cc_mfb2axi": 113, "pcie_clk": 192, "pcie_con": 192, "pcie_conf": [189, 192], "pcie_cq_": 45, "pcie_cq_axi2mfb": 113, "pcie_cq_hdr_depars": 117, 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187], "pip": 178, "pip3": 174, "pipe": [44, 48, 61, 62, 69, 89, 95, 101, 116, 160, 162, 163, 164], "pipe_dsp": 160, "pipe_out": 89, "pipe_outreg": 89, "pipe_tree_add": 160, "pipe_typ": [58, 66, 86, 89], "piped_port": 61, "pipelin": [10, 17, 19, 59, 60, 66, 68, 83, 89, 107, 129, 144, 150, 164, 183], "pkg": [27, 144, 152, 184], "pkt": 35, "pkt_cnt_width": 49, "pkt_cntr_chan": 35, "pkt_cntr_disc_inc": 35, "pkt_cntr_pkt_size": 35, "pkt_cntr_sent_inc": 35, "pkt_disc_byt": 40, "pkt_disc_chan": 40, "pkt_disc_inc": 40, "pkt_discard_byt": [37, 44], "pkt_discard_chan": [37, 44], "pkt_discard_inc": [37, 44], "pkt_drop": 45, "pkt_id_width": 54, "pkt_mtu": [35, 48, 50, 54, 60, 74, 75, 131], "pkt_mtu_byt": [109, 111], "pkt_sent_byt": [37, 42, 44], "pkt_sent_chan": [37, 42, 44, 78], "pkt_sent_dst_rdi": 78, "pkt_sent_inc": [37, 42, 44], "pkt_sent_len": 78, "pkt_sent_src_rdi": 78, "pkt_size": 35, "pkt_size_max": [37, 39, 40, 42, 44, 45, 78], "place": [6, 19, 31, 68, 104, 107, 109, 110, 144, 149, 164, 184], "placehold": 184, "placement": 76, "plan": [17, 19], "plane": 48, "planned_pkt": 19, "planner": [17, 49, 75, 164], "platform": [166, 184, 185, 187, 189, 193, 194, 195], "player": 48, "player_fifo_depth": 48, "pleas": [87, 122, 124, 144, 145, 189, 195], "plot": 18, "plu": [21, 57, 163], "plug": 189, "pma": [109, 111, 132, 180, 187, 191, 195], "pma_xlaui_gti": 107, "pmci": [0, 185], "pmd": [107, 180, 185, 187, 191], "pmd0": 185, "pmd1": 185, "pmdctrl0": [0, 185], "pmdctrl1": [0, 185], "po": [60, 74], "pof": [171, 172], "point": [0, 17, 45, 60, 76, 80, 118, 150, 159, 184, 191], "pointer": [19, 34, 35, 37, 39, 41, 42, 44, 45, 46, 59, 67, 78, 144], "pointer_update_chan": 34, "pointer_update_data": 34, "pointer_update_en": 34, "pointer_width": [34, 35, 37, 39, 41, 43], "polar": [107, 180], "polynom": 130, "polynomi": 107, "pool": 150, "pop": 18, "pop_front": [144, 150], "popul": 185, "port": [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 18, 20, 22, 27, 29, 33, 34, 35, 36, 37, 38, 39, 40, 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63, 65, 68, 71, 74, 75, 77, 81, 82, 88, 90, 96, 98, 100, 109, 111, 170, 171, 172], "pp": [67, 75, 121, 196], "pps_n": 121, "pps_reg": 121, "pps_sel": 121, "pps_sel_width": 121, "pps_src": 121, "practic": [67, 76, 144, 166], "pre": [21, 23, 189], "pre_do": 144, "pre_trigg": 150, "preambl": [109, 129], "prebuilt": 27, "preced": [110, 112], "precharg": [31, 183], "precis": [24, 26, 31, 47, 65, 71, 121], "precomput": 10, "predefin": [89, 123, 125, 131, 137, 138, 166], "prefer": [67, 166], "preffer": 62, "prefix": [22, 47, 144, 148, 166], "prefixsum": 60, "prepar": [126, 127, 130, 146, 166, 183], "prepend": 60, "preprocess": 17, "prerequisit": [166, 174], "presenc": [21, 68, 104, 113, 183], "present": [11, 19, 27, 58, 64, 68, 79, 101, 105, 112, 166, 180, 183, 185], "preserv": 166, "pretti": 89, "prevent": [68, 118, 119], "previou": [11, 19, 31, 39, 45, 58, 59, 60, 68, 87, 89, 110, 118, 119, 139, 144, 147, 152, 183, 187], "previous": [19, 59, 67, 68, 87, 101, 110, 118, 119, 184], "primari": [46, 112, 151], "primarili": [90, 188], "prime": [27, 170, 171, 172, 173, 174, 177, 188, 189], "primit": [7, 156, 161], "princeton": 10, "principl": [87, 95], "print": [31, 32, 125, 131, 135, 136, 137, 138, 144, 149, 152], "prioriti": [11, 26, 184], "prioritis": 14, "privileg": 27, "pro": [170, 171, 172, 174, 177, 185, 188, 189], "probability_set": [128, 139, 142], "probabl": [26, 128, 139, 142], "probe": [31, 58, 132, 188], "probe_event_component_": 150, "probe_if": 150, "probe_inf": 150, "probe_statu": 150, "problem": [11, 68, 131, 144, 160, 179, 187], "proc": 166, "procedur": [166, 170, 171, 172, 184], "process": [0, 11, 17, 19, 21, 22, 26, 33, 41, 58, 59, 60, 67, 76, 80, 88, 104, 110, 111, 113, 116, 119, 122, 128, 131, 138, 139, 142, 143, 144, 151, 159, 164, 166, 183, 184, 191], "processing_ord": 166, "processor": 60, "prodesign": 173, "produc": [88, 131], "product": [76, 166], "profession": [159, 186], "profile_filepath": 148, "profile_gener": 148, "profile_generator_config_filepath": 148, "profile_swap": 179, "program": 166, "programm": 170, "progress": 17, "proj_onli": [166, 178], "project": [87, 166, 178, 184, 185, 189], "promiscu": 109, "prop_rdi": 144, "propabl": 38, "propag": [11, 16, 17, 18, 19, 21, 46, 60, 64, 74, 75, 80, 88, 118, 119, 166, 184], "proper": [110, 183, 187, 189], "properli": [109, 121, 144, 167, 168, 169, 185, 186], "properti": [0, 10, 83, 122, 123, 125, 134, 137, 138, 185, 190], "proport": 67, "proprietari": 149, "prot": 183, "protect": 144, "protocol": [47, 59, 82, 122, 124, 144, 145, 146, 151, 154, 187, 191, 194], "prototyp": 174, "provid": [0, 11, 12, 14, 17, 19, 25, 27, 37, 39, 44, 45, 46, 61, 67, 75, 76, 77, 82, 102, 104, 107, 113, 114, 116, 131, 144, 148, 155, 166, 183, 184, 187, 189, 191, 192, 193], "prowid": 144, "prt": 144, "pscn": 67, "pseudo": [11, 31, 160, 179], "ptc": [192, 198], "ptc_disabl": 192, "ptr": 80, "publicli": 195, "pull": [128, 141, 142, 144], "puls": [121, 135, 136, 160, 164, 196], "pulse_out": 20, "pulse_short": [20, 164], "pure": [12, 120, 131], "purpos": [19, 31, 36, 57, 59, 76, 110, 112, 113, 117, 118, 119, 122, 129, 131, 144, 150, 151, 152, 160, 166, 184, 187, 192, 195], "push_back": [131, 144, 150], "put": [11, 39, 45, 61, 72, 80, 101, 144], "py": [0, 24, 25, 27, 31, 67, 148, 174, 179, 195], "pytest": 174, "python": [0, 24, 25, 31, 32, 67, 174, 178, 179, 195], "python3": [0, 24, 25, 31, 32, 195], "p\u0159idat": 5, "qo": 183, "qsf": [179, 187], "qsfp": [107, 170, 172, 173, 174, 177, 180, 184, 185, 187, 191, 193, 194, 195], "qsfp28": [167, 168, 169, 175, 176, 194], "qsfp56": 171, "qsfp_i2c_dir": 180, "qsfp_i2c_port": 180, "qsfp_i2c_scl": 180, "qsfp_i2c_scl_i": 180, "qsfp_i2c_scl_o": 180, "qsfp_i2c_sda": 180, "qsfp_i2c_sda_i": 180, "qsfp_i2c_sda_o": 180, "qsfp_i2c_trist": 180, "qsfp_int_n": 180, "qsfp_lpmode": 180, "qsfp_modprs_n": 180, "qsfp_modsel_n": 180, "qsfp_port": 180, "qsfp_reset_n": 180, "qspf": 173, "qspi": [23, 193], "quad": 23, "quadrat": 11, "quadrupl": 183, "qualiti": 65, "quantum": 18, "quartu": [27, 120, 166, 170, 171, 172, 173, 174, 177, 185, 188, 189], "quartust": 166, "quasi": 43, "quest": [126, 127], "questa": 166, "question": 184, "queue": [6, 71, 150, 189, 194], "quick_reset_en": 11, "quicki": 139, "quickli": [128, 142, 143, 159, 193, 195], "quiet": 166, "quit": 144, "r": [0, 29, 30, 31, 32, 39, 45, 67, 107, 109, 111, 119, 172, 174, 178, 183, 189, 191, 192], "r_tile": 192, "race": 144, "rais": [68, 184], "raise_object": 144, "ram": [2, 4, 14, 16, 26, 34, 35, 37, 39, 43, 44, 46, 82, 101], "ram_typ": [4, 5, 6, 77, 79, 82, 105], "ran": 151, "rand": [31, 32, 122, 123, 133, 134, 144], "rand_gen_addr_width": 31, "rand_gen_data_width": 31, "rand_length": 131, "rand_length_rand": 131, "rand_rdi": [131, 134], "rand_rdy_rand": 131, "random": [5, 31, 45, 89, 96, 122, 125, 128, 129, 130, 132, 135, 136, 137, 138, 139, 142, 143, 144, 146, 147, 149, 151, 152, 160], "random_addr_se": 31, "random_data_se": 31, "randomiz": [125, 137, 138], "randomli": [45, 125, 128, 137, 138, 142, 143, 144, 146, 151], "rang": [18, 22, 26, 31, 32, 59, 71, 89, 104, 121, 135, 136, 147, 148, 179, 180, 183, 187, 191, 195, 196], "rate": [107, 162, 186, 188, 195], "rate_limit": 67, "rather": [87, 188], "ratio": 1, "raw": [31, 32], "rc": [117, 192], "rc_mfb_block_siz": 192, "rc_mfb_item_width": 192, "rc_mfb_region": 192, "rc_mfb_region_s": 192, "rcb": 192, "rd": [5, 6, 31, 75, 87, 146, 150], "rd_addr": [13, 14, 16, 43], "rd_aempti": [4, 77], "rd_ch": 9, "rd_chan": 43, "rd_clk": [4, 16], "rd_data": [4, 13, 14, 16, 43], "rd_data_vld": [14, 16, 43], "rd_empti": 4, "rd_en": [4, 14, 16, 43, 77, 150], "rd_latenc": [13, 17], "rd_meta_in": [14, 16], "rd_meta_out": [14, 16], "rd_pipe_en": 16, "rd_ptr": 78, "rd_rst": [4, 16], "rd_statu": 4, "rd_val": 9, "rd_vld": 9, "rdw_behav": 13, "rdy": [131, 134, 135, 136, 141, 144], "re": [59, 67, 89, 118, 187], "reach": [17, 18, 19, 40, 46, 59, 65, 67, 118, 195], "react": 31, "read": [0, 4, 5, 9, 11, 13, 14, 16, 17, 18, 19, 22, 23, 24, 25, 26, 29, 30, 31, 32, 35, 37, 39, 42, 43, 44, 45, 58, 59, 65, 67, 76, 78, 80, 82, 83, 85, 87, 88, 90, 93, 101, 102, 106, 107, 109, 110, 111, 112, 116, 117, 118, 119, 121, 122, 128, 129, 139, 142, 144, 146, 151, 152, 156, 160, 161, 180, 185, 187, 188, 189, 191, 192, 195], "read_addr": 26, "read_box": 26, "read_box_vld": 26, "read_port": [6, 13, 14, 15], "read_prior": 26, "read_req": 26, "readabl": [144, 187], "readdata": 122, "readdatavalid": [83, 122], "readi": [4, 17, 29, 31, 47, 63, 66, 76, 77, 82, 83, 87, 90, 92, 94, 95, 96, 98, 102, 104, 109, 111, 113, 116, 121, 122, 133, 134, 147, 160, 164, 183, 186, 190], "readm": [27, 174, 188, 189], "real": [110, 112, 121, 166], "reali": 151, "realist": [31, 58], "realiti": 187, "realiz": [68, 87, 89], "realli": 87, "realtime_reg": 121, "rearrang": 54, "reason": [11, 17, 18, 19, 47, 68, 109, 111, 118, 122, 144, 151], "reboot": 193, "rebuild": 166, "recalcul": [67, 93], "receiv": [0, 18, 19, 24, 29, 30, 31, 34, 39, 40, 45, 60, 70, 76, 78, 87, 90, 91, 94, 99, 101, 104, 107, 109, 110, 113, 119, 121, 124, 134, 144, 146, 156, 159, 164, 166, 180, 188, 192, 193, 195, 197], "recent": 11, "recept": [193, 196], "reciev": [11, 85, 87], "recip": 184, "recipi": 87, "reciv": 145, "recogn": 76, "recomend": [18, 166], "recommend": [3, 5, 87, 129, 144, 166, 180, 183, 184, 187, 189, 195], "reconfigur": [162, 163, 179, 197], "record": 187, "record_max_numb": 148, "record_min_numb": 148, "recording_detail": 144, "recov": 107, "recreat": 59, "recurs": 166, "recv_bts_cnt_width": [37, 44], "recv_pkt_cnt_width": [37, 44], "redefin": 144, "redirect": 71, "redistribut": 59, "reduc": [19, 25, 31, 68, 88, 184, 185], "reduct": [19, 68], "ref": [107, 146], "ref_nam": 185, "refclk_in": 107, "refclk_n": 107, "refclk_out": 107, "refclk_p": 107, "refer": [7, 10, 83, 107, 129, 144, 159, 167, 168, 169, 173, 183, 184, 185, 187, 189, 190, 194, 195], "referenc": 185, "reffer": 18, "reflect": 148, "refr_ack": 31, "refr_period": 31, "refr_period_width": 31, "refr_req": 31, "refr_req_before_test": 31, "refresh": [31, 183], "reg": [25, 58, 66, 86, 118, 185], "reg0": [19, 21], "reg4": 19, "reg_bitmap": 120, "reg_fifo": 7, "reg_out_en": 38, "regard": [17, 184], "regardless": 87, "regarr0": [0, 185], "regarr1": [0, 185], "regino": 68, "region": [33, 36, 38, 42, 43, 45, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 79, 109, 111, 113, 116, 124, 128, 139, 142, 143, 144, 145, 164, 180, 183], "region_aux_en": 73, "region_numb": 60, "region_s": [36, 48, 49, 52, 55, 56, 57, 58, 61, 63, 66, 68, 70, 72, 73, 76, 79, 128, 142, 143, 144, 145, 180], "regions_s": [128, 142, 145], "regist": [2, 3, 4, 6, 8, 10, 11, 13, 14, 16, 17, 18, 19, 21, 23, 25, 27, 29, 30, 31, 32, 37, 44, 46, 48, 49, 58, 59, 62, 67, 69, 71, 77, 85, 86, 87, 88, 89, 90, 91, 92, 94, 95, 101, 106, 107, 110, 112, 114, 118, 120, 121, 144, 156, 160, 161, 164, 180, 185, 187, 189, 191, 192, 193], "registr": 144, "regular": [59, 170, 184], "reimplement": [131, 144], "rel": [166, 185], "relat": [31, 76, 78, 144], "relax": [22, 117], "releas": [27, 118, 156, 192], "relev": [18, 184], "reli": 166, "reliabl": 107, "remad": 166, "remain": [76, 77, 81, 110, 129, 147, 156, 167, 169], "remap": 119, "rememb": [67, 88], "remot": [23, 27], "remov": [6, 9, 12, 19, 27, 48, 68, 80, 109, 160, 164, 174, 185, 187, 188], "reorder": [101, 107], "repeat": [21, 29, 45, 67, 118, 144, 151, 195], "repeater_ctrl": 180, "repetit": [128, 139, 142, 143], "replac": [5, 89, 105, 115, 186], "repli": [146, 185, 189], "replic": 14, "report": [5, 25, 45, 195], "report_gen": 31, "report_phas": 144, "repositori": [0, 2, 27, 109, 111, 148, 153, 154, 157, 158, 162, 163, 165, 166, 184, 185, 188, 197, 198], "repres": [5, 65, 67, 121, 133, 144, 179, 187], "represent": [5, 58, 185], "reprez": 131, "republ": 188, "req": [30, 144, 147, 151, 152], "reqest": 85, "requ": 87, "request": [0, 4, 6, 11, 14, 22, 23, 24, 25, 26, 29, 30, 31, 34, 35, 39, 40, 44, 45, 46, 58, 67, 71, 77, 82, 83, 85, 87, 88, 90, 102, 109, 111, 112, 113, 116, 117, 118, 119, 121, 122, 126, 127, 146, 152, 156, 164, 183, 186, 187, 189, 191, 192, 193, 195], "request_item_type_": 122, "request_typ": 122, "requier": 184, "requir": [0, 1, 5, 6, 11, 18, 29, 45, 58, 62, 67, 68, 75, 88, 89, 94, 100, 101, 109, 110, 111, 118, 119, 124, 128, 131, 139, 142, 143, 144, 145, 151, 160, 161, 166, 170, 171, 172, 174, 178, 180, 181, 184, 187, 188, 189, 192, 194, 195], "reserv": [39, 45, 49, 107, 109, 111, 112, 166, 191], "reset": [1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 14, 16, 17, 18, 20, 25, 26, 30, 31, 32, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 78, 79, 80, 82, 83, 84, 85, 86, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 114, 116, 120, 121, 128, 131, 132, 135, 136, 139, 142, 143, 146, 150, 164, 180, 183, 192, 196], "reset_": 82, "reset_ag": 151, "reset_arb": 17, "reset_eth": [180, 183], "reset_if": 144, "reset_in": 78, "reset_log": 82, "reset_m": 82, "reset_meta": 78, "reset_out": 78, "reset_sync": [128, 139, 142, 143, 151], "reset_tim": 151, "reset_tree_gen": 164, "reset_us": [180, 183], "reset_user_x2": 183, "reset_user_x3": 183, "reset_user_x4": 183, "reset_v": 11, "reset_width": [180, 183], "resiz": [31, 68, 119], "resize_buff": 109, "resize_on_tx": 111, "resolut": [43, 68, 110], "resolv": 165, "resourc": [11, 19, 25, 31, 59, 60, 62, 68, 89, 98, 100, 101, 102, 109, 156, 160, 161, 185], "resp": 183, "respect": [5, 11, 23, 41, 58, 68, 87, 89, 104, 110, 166, 184], "respond": [87, 116, 144, 146], "respones": 87, "respons": [17, 34, 83, 87, 101, 116, 118, 119, 123, 124, 132, 133, 134, 145, 146, 147, 152, 192], "rest": [31, 50, 58, 60, 166, 187], "restart": 67, "restor": 67, "restrict": [14, 17, 37, 39, 46, 52, 55, 66, 67, 76, 79, 144, 161, 166], "result": [3, 10, 11, 13, 14, 17, 18, 27, 31, 59, 67, 74, 76, 107, 118, 131, 144, 164, 174, 187], "resum": [65, 71], "ret": [144, 151], "retriev": 129, "return": [67, 71, 87, 110, 131, 144, 150, 151, 166], "rev": 112, "revers": [49, 110, 148, 160, 187], "revis": [185, 189], "rework": 74, "rfc": 109, "rhel": 189, "righ": 34, "right": [8, 23, 58, 67, 71, 76, 87, 104, 109, 110, 126, 127, 130, 135, 136, 152, 160, 179, 187], "ring": [34, 35], "rise": [1, 29, 31, 147, 150, 160], "risk": 95, "ro": [67, 112, 121], "robin": [0, 49, 90, 164], "rocki": 189, "role": 183, "roll": 144, "rom": [116, 160, 193], "root": [144, 166, 192], "rotat": [8, 17, 59], "rough": 18, "round": [0, 6, 18, 49, 60, 68, 88, 90, 164], "rout": [0, 17, 22, 59, 89, 90, 107, 192], "router": [0, 165], "row": [17, 67], "row_item": 17, "rpm": [0, 27, 189], "rq": [33, 117, 192], "rq_mfb_block_siz": 192, "rq_mfb_item_width": 192, "rq_mfb_region": 192, "rq_mfb_region_s": 192, "rr": [49, 90], "rr_arbit": 164, "rsp": 152, "rsp_item_width": 101, "rst": [7, 20, 24, 25, 26, 28, 31, 32, 33, 36, 38, 49, 59, 63, 70, 79, 110, 144], "rst_ch": 9, "rst_done": [24, 25, 26], "rst_vld": 9, "rsu": 23, "rsvd": 90, "rtl": 188, "rule": [58, 76, 90, 104, 110, 122, 124, 144, 145, 150], "run": [0, 11, 17, 18, 27, 31, 32, 40, 67, 77, 78, 81, 107, 124, 125, 128, 129, 137, 138, 139, 142, 143, 145, 146, 148, 151, 152, 166, 173, 174, 178, 180, 184, 185, 186, 192, 194, 195], "run_phas": [131, 144, 150], "run_test": 144, "rw": [39, 45, 67, 109, 111, 112, 121], "rx": [0, 22, 33, 37, 45, 46, 48, 50, 54, 58, 59, 60, 61, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 74, 75, 77, 79, 81, 88, 90, 91, 92, 95, 96, 98, 99, 101, 102, 111, 123, 124, 129, 132, 133, 134, 144, 145, 147, 166, 180, 183, 187, 188, 189, 194, 195, 197], "rx0": 94, "rx0_data": 94, "rx0_dst_rdy": 94, "rx0_fifo_en": 94, "rx0_item": 94, "rx0_item_width": 94, "rx0_mfb_data": 62, "rx0_mfb_dst_rdy": 62, "rx0_mfb_eof": 62, "rx0_mfb_eof_po": 62, "rx0_mfb_meta": 62, "rx0_mfb_sof": 62, "rx0_mfb_sof_po": 62, "rx0_mfb_src_rdy": 62, "rx0_mvb_dst_rdy": 62, "rx0_mvb_hdr": 62, "rx0_mvb_payload": 62, "rx0_mvb_src_rdy": 62, "rx0_mvb_vld": 62, "rx0_payload_en": 62, "rx0_src_rdy": 94, "rx0_vld": 94, "rx1": 94, "rx1_data": 94, "rx1_dst_rdy": 94, "rx1_item": 94, "rx1_item_width": 94, "rx1_mfb_data": 62, "rx1_mfb_dst_rdy": 62, "rx1_mfb_eof": 62, "rx1_mfb_eof_po": 62, "rx1_mfb_meta": 62, "rx1_mfb_sof": 62, "rx1_mfb_sof_po": 62, "rx1_mfb_src_rdy": 62, "rx1_mvb_dst_rdy": 62, "rx1_mvb_hdr": 62, "rx1_mvb_payload": 62, "rx1_mvb_src_rdy": 62, "rx1_mvb_vld": 62, "rx1_payload_en": 62, "rx1_src_rdy": 94, "rx1_vld": 94, "rx_addr": [85, 89], "rx_aful": [77, 81], "rx_agent": 144, "rx_ardi": [85, 89], "rx_be": 89, "rx_block_siz": [33, 38, 68, 109, 111], "rx_chan_rout": [0, 185], "rx_channel": [46, 59, 90], "rx_chsum_en": 74, "rx_clk": [75, 77, 81, 109, 111, 131, 166], "rx_clk2": 75, "rx_clk_x2": 111, "rx_compare_data": 144, "rx_compare_meta": 144, "rx_cut": 55, "rx_data": [7, 8, 47, 52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 96, 98, 99, 101, 102, 105], "rx_data_consum": 101, "rx_data_in": 61, "rx_data_out": 61, "rx_discard": [81, 92, 144], "rx_discard_": 144, "rx_dma_calypt": 39, "rx_dma_calypte_addr_manag": 34, "rx_dma_calypte_hdr_insertor": 33, "rx_dma_calypte_hdr_manag": 35, "rx_dma_calypte_input_buff": 36, "rx_dma_calypte_sw_manag": 37, "rx_dma_calypte_trans_buff": 38, "rx_dma_channel": 48, "rx_drd": [85, 89], "rx_drdy": [85, 89], "rx_drop": 56, "rx_dst_rdy": [7, 8, 47, 52, 55, 56, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 96, 98, 99, 101, 102, 105], "rx_dst_rdy_in": 61, "rx_dst_rdy_out": 61, "rx_dwr": [85, 89], "rx_env": 144, "rx_eof": [52, 55, 56, 57, 58, 66, 68, 73, 77, 79, 81, 110], "rx_eof_in": 61, "rx_eof_out": 61, "rx_eof_po": [52, 55, 56, 57, 58, 66, 68, 73, 77, 79, 81], "rx_eof_pos_in": 61, "rx_eof_pos_out": 61, "rx_eop": [47, 72], "rx_eop_po": [47, 72], "rx_gen_en": 46, "rx_hdr_addr": 78, "rx_hdr_chan": 78, "rx_hdr_dst_rdy": 78, "rx_hdr_ins_en": 48, "rx_hdr_len": 78, "rx_hdr_meta": 78, "rx_hdr_mfb_meta": 78, "rx_hdr_src_rdy": 78, "rx_hdr_vld": 78, "rx_include_crc": 111, "rx_include_ipg": 111, "rx_input": 144, "rx_input_data": 144, "rx_input_data_": 144, "rx_item": 102, "rx_item_width": [33, 38, 68, 109, 111], "rx_length": [60, 74], "rx_link_up": 180, "rx_mac_lit": [109, 166, 185, 187], "rx_mac_lite_region": 144, "rx_meta": [52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 93], "rx_meta_in": 61, "rx_meta_out": 61, "rx_metadata": 8, "rx_mfb": 144, "rx_mfb0_data": 63, "rx_mfb0_dst_rdy": 63, "rx_mfb0_eof": 63, "rx_mfb0_eof_po": 63, "rx_mfb0_meta": 63, "rx_mfb0_sof": 63, "rx_mfb0_sof_po": 63, "rx_mfb0_src_rdy": 63, "rx_mfb1_data": 63, "rx_mfb1_dst_rdy": 63, "rx_mfb1_eof": 63, "rx_mfb1_eof_po": 63, "rx_mfb1_meta": 63, "rx_mfb1_sof": 63, "rx_mfb1_sof_po": 63, "rx_mfb1_src_rdy": 63, "rx_mfb_": [110, 187], "rx_mfb_data": [33, 36, 38, 50, 54, 59, 60, 63, 64, 65, 67, 69, 70, 71, 74, 75, 109, 110, 111, 180], "rx_mfb_discard": 75, "rx_mfb_dst_rdy": [33, 36, 38, 50, 54, 59, 60, 63, 64, 65, 67, 69, 70, 71, 74, 75, 110, 111, 180], "rx_mfb_eof": [33, 36, 38, 50, 54, 59, 60, 63, 64, 65, 67, 69, 70, 71, 74, 75, 109, 110, 111, 180], "rx_mfb_eof_po": [36, 38, 50, 54, 59, 60, 63, 64, 65, 67, 69, 70, 71, 74, 75, 109, 110, 111, 180], "rx_mfb_error": 109, "rx_mfb_hdr": [180, 187], "rx_mfb_meta": [63, 64, 65, 67, 70, 71, 74, 75], "rx_mfb_queue": 71, "rx_mfb_sel": 70, "rx_mfb_sof": [33, 36, 38, 50, 54, 59, 60, 63, 64, 65, 67, 69, 70, 71, 74, 75, 109, 110, 111, 180], "rx_mfb_sof_po": [36, 50, 54, 59, 60, 63, 64, 65, 67, 69, 70, 71, 74, 75, 109, 110, 111, 180], "rx_mfb_src_rdy": [33, 36, 38, 50, 54, 59, 60, 63, 64, 65, 67, 69, 70, 71, 74, 75, 109, 110, 111, 180], "rx_mfb_t": 65, "rx_mfb_timestamp": 71, "rx_mvb": 144, "rx_mvb_channel": 59, "rx_mvb_data": [60, 64, 69, 100], "rx_mvb_discard": 54, "rx_mvb_dst_rdy": [50, 54, 59, 60, 64, 69, 100, 106], "rx_mvb_ext_en": 50, "rx_mvb_ext_onli": 50, "rx_mvb_ext_siz": 50, "rx_mvb_frame_length": 50, "rx_mvb_hdr": 69, "rx_mvb_len": 59, "rx_mvb_lut_addr": 106, "rx_mvb_meta": [69, 100], "rx_mvb_metadata": 106, "rx_mvb_mod_eof_en": 54, "rx_mvb_mod_eof_s": 54, "rx_mvb_mod_eof_typ": 54, "rx_mvb_mod_sof_en": 54, "rx_mvb_mod_sof_s": 54, "rx_mvb_mod_sof_typ": 54, "rx_mvb_payload": 69, "rx_mvb_src_rdy": [50, 54, 59, 60, 64, 69, 100, 106], "rx_mvb_switch": 69, "rx_mvb_usermeta": [50, 54], "rx_mvb_vld": [50, 54, 59, 60, 64, 69, 100, 106], "rx_mwr": 89, "rx_new_sof": 60, "rx_offset": [60, 74], "rx_old_sof": 60, "rx_op_dst_rdi": 101, "rx_op_en": 101, "rx_op_pipe_en": 101, "rx_op_respons": 101, "rx_op_src_rdi": 101, "rx_op_vld": 101, "rx_out_data": 144, "rx_out_hdr": 144, "rx_output": 144, "rx_path_40g": 107, "rx_ptr_width": 46, "rx_rd": [85, 89], "rx_region": [68, 72, 109, 111], "rx_region_s": [33, 38, 68, 109, 111], "rx_reset": [75, 77, 81, 109, 111, 131], "rx_sel": [8, 91, 98], "rx_sel_data": 99, "rx_sel_dst_rdi": [98, 99], "rx_sel_if": 98, "rx_sel_src_rdi": [98, 99], "rx_sel_vld": [98, 99], "rx_shakedown_en": 96, "rx_sof": [52, 55, 56, 57, 58, 66, 68, 73, 77, 79, 81, 110], "rx_sof_in": 61, "rx_sof_mask": 60, "rx_sof_out": 61, "rx_sof_po": [52, 55, 56, 57, 58, 66, 68, 73, 77, 79, 81, 110], "rx_sof_pos_in": 61, "rx_sof_pos_out": 61, "rx_sop": [47, 72], "rx_sop_po": [47, 72], "rx_src_rdy": [7, 8, 47, 52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 96, 98, 99, 101, 102, 105], "rx_src_rdy_in": 61, "rx_src_rdy_out": 61, "rx_statu": [77, 81], "rx_stream": [96, 98], "rx_trim_en": 52, "rx_trim_len": 52, "rx_uinstr_src_rdi": 17, "rx_valid": 93, "rx_vld": [90, 91, 92, 96, 98, 99, 101, 102, 105], "rx_word": 60, "rx_wr": [85, 89], "rxmac": [0, 185], "rxmac0": [0, 185], "rxmac1": [0, 185], "rxn": 107, "rxp": 107, "rxpolar": 107, "s10memori": [156, 161], "s_ch": 179, "s_p": 179, "safe": [6, 17, 82], "safe_read_mod": 6, "sai": [11, 17, 68, 87, 135, 136, 149, 156], "said": 89, "sake": [68, 76, 144], "same": [1, 11, 12, 13, 14, 17, 19, 21, 26, 27, 28, 30, 31, 32, 47, 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161, "sdp_memx": [160, 161], "sdp_rd_chan": 37, "sdp_rd_data": 37, "sdp_uram_xilinx": 161, "se": [31, 36], "search": [60, 107], "second": [18, 22, 35, 39, 45, 58, 59, 67, 68, 76, 87, 89, 104, 110, 120, 121, 128, 130, 131, 141, 142, 144, 147, 150, 152, 156, 174, 183, 184, 185, 187, 196], "secondari": 68, "section": [17, 23, 67, 74, 83, 104, 107, 144, 152, 183, 184, 187], "section_length": 67, "sectionlength": 67, "secur": [14, 23], "see": [0, 5, 6, 11, 16, 17, 18, 22, 23, 25, 48, 65, 67, 68, 71, 75, 77, 79, 82, 83, 89, 90, 100, 104, 107, 109, 110, 111, 113, 119, 121, 125, 137, 138, 139, 142, 143, 144, 145, 148, 152, 159, 166, 167, 168, 169, 170, 171, 172, 174, 175, 176, 183, 184, 185, 186, 187, 190, 195], "seed": [31, 45], "seem": [11, 179], "seen": [17, 25, 189], "seg": 132, "segment": [34, 109, 111, 133, 187], "sel": [8, 30, 98], "sel_shakedown_en": 98, "select": [4, 5, 10, 14, 16, 17, 25, 29, 31, 32, 35, 48, 52, 54, 59, 69, 70, 71, 74, 77, 79, 82, 90, 91, 92, 98, 99, 105, 109, 111, 113, 116, 121, 125, 137, 138, 144, 146, 156, 166, 174, 180, 183, 184, 185, 187, 189, 193, 194, 195], "selected_queu": 71, "self": [107, 174], "send": [0, 8, 11, 14, 17, 21, 23, 31, 33, 45, 46, 49, 50, 57, 59, 60, 76, 78, 80, 85, 90, 101, 104, 108, 113, 116, 119, 122, 123, 124, 126, 127, 128, 129, 130, 131, 134, 139, 141, 142, 143, 144, 145, 146, 149, 151, 152, 159, 183, 184, 191, 195], "send_empty_fram": 131, "send_fram": 131, "send_transact": 151, "sensor": 23, "sent": [19, 29, 33, 34, 37, 44, 46, 49, 57, 58, 59, 71, 72, 78, 85, 87, 89, 101, 109, 110, 111, 125, 129, 134, 137, 138, 139, 144, 146, 180, 183, 186, 187, 192], "separ": [11, 25, 31, 33, 45, 56, 59, 76, 78, 90, 104, 109, 111, 118, 119, 131, 144, 166, 187, 188, 194, 198], "seq": [32, 125, 137, 138, 144], "seq_byte_arrai": 144, "seq_cfg": [128, 139, 142, 143, 144], "seq_item_export": 144, "seq_item_port": 144, "seq_mvb": 144, "seq_rx_packet": 144, "seq_tx_rdi": 144, "seqeuenc": 151, "sequenc": [18, 23, 31, 45, 107, 124, 131, 132, 145, 146, 151, 152], "sequence_": 144, "sequence_burst_rx": 143, "sequence_byte_arrai": 144, "sequence_full_speed_rx": [128, 139, 142, 143], "sequence_item": [122, 123, 125, 128, 131, 132, 133, 134, 137, 138, 139, 142, 143, 144, 147], "sequence_item_request": 146, "sequence_item_respons": [146, 152], "sequence_lib": [125, 137, 138, 144], "sequence_lib_rx": [128, 139, 142, 143], "sequence_librari": 144, "sequence_library_rx": 134, "sequence_library_rx_fullspe": 134, "sequence_mast": 146, "sequence_master_burst": 146, "sequence_master_max": 146, "sequence_meta": 152, "sequence_mfb_data": 152, "sequence_mi": 152, "sequence_mi_sim": 152, "sequence_mvb": 144, "sequence_mvb_data": 152, "sequence_packet_const": 144, "sequence_packet_incr": 144, "sequence_packet_larg": 144, "sequence_packet_mid": 144, "sequence_packet_rand_spac": 144, "sequence_packet_smal": 144, "sequence_rand": 151, "sequence_rand_rx": 143, "sequence_rx": [123, 132, 134, 144], "sequence_rx_bas": 132, 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[4, 13, 77, 161], "shape": [67, 88], "share": [43, 47, 68, 73, 160, 166, 184], "shell": 184, "shift": [2, 5, 8, 19, 23, 52, 55, 59, 79, 80, 86, 88, 101, 105, 110, 121, 156, 160], "shift_left": 8, "shifter": [43, 59, 160], "short": [31, 110, 111], "shorten": [20, 52, 164], "shorter": 14, "shoud": 31, "should": [5, 17, 19, 20, 23, 24, 25, 26, 30, 31, 32, 35, 47, 59, 63, 67, 75, 80, 87, 89, 98, 109, 121, 131, 144, 146, 166, 173, 184, 185, 186, 187, 200], "show": [0, 11, 31, 58, 76, 87, 89, 104, 110, 122, 123, 124, 125, 128, 131, 134, 137, 138, 139, 142, 143, 144, 145, 152, 166, 174, 184, 187, 193, 195], "shown": [76, 87, 89, 104, 110, 119, 144, 179, 183, 184, 186, 187, 192], "shp_rd_chan": 37, "shp_rd_data": 37, "shreg": [58, 66, 86, 89, 144], "shrink": 75, "side": [4, 8, 21, 45, 46, 48, 58, 67, 72, 80, 82, 83, 87, 89, 107, 109, 110, 111, 119, 123, 144, 147, 187], "sideband": 113, "signal": [1, 6, 7, 8, 12, 14, 16, 17, 19, 20, 23, 25, 28, 31, 33, 35, 37, 39, 40, 41, 44, 45, 46, 49, 58, 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166, 195, 200], "simult": 31, "simultan": [0, 6, 11, 31, 54, 67, 76], "sinc": [11, 13, 17, 18, 19, 43, 68, 71, 80, 91, 118], "singl": [0, 1, 6, 8, 18, 19, 21, 40, 45, 60, 63, 67, 68, 70, 71, 76, 80, 89, 102, 104, 110, 113, 116, 135, 136, 138, 144, 161, 166, 174, 180, 183, 192], "situat": [58, 68, 76, 88, 95, 110, 118, 144, 166], "six": [76, 146], "size": [5, 7, 8, 9, 17, 18, 19, 22, 34, 35, 37, 39, 44, 45, 46, 48, 50, 54, 55, 59, 60, 61, 62, 64, 65, 66, 67, 68, 69, 71, 72, 74, 75, 78, 79, 109, 111, 112, 114, 116, 125, 128, 131, 137, 138, 139, 142, 144, 146, 148, 150, 151, 152, 164, 180, 183, 185, 192, 195], "size_max": 144, "skid": 38, "skip": [58, 166], "slack": 183, "slave": [82, 84, 87, 90, 107, 109, 111, 116, 121, 122, 144, 146, 183], "slice": [25, 29, 156, 160], "slight": [64, 110], "slightli": [11, 17, 21, 144, 190], "slot": [189, 192, 193], "slow": [67, 164], "slower": [187, 188, 189], "slowest": 151, "slr_cross": 164, "slv_array_t": [13, 14, 15, 25, 31, 54, 59, 60, 63, 69, 70, 78, 85, 89, 93, 96, 98, 106, 183, 192], "small": [19, 59, 60, 76, 110, 131, 144, 161, 164, 185], "smaller": [3, 13, 31, 40, 68, 151], "smallest": [67, 75, 76], "smarter": 121, "snippet": 184, "snoop": 117, "snyc_termin": 151, "so": [0, 6, 11, 12, 17, 19, 23, 58, 59, 60, 67, 70, 71, 76, 80, 85, 87, 88, 89, 110, 122, 144, 149, 152, 164, 166, 179, 184, 185, 187, 195], "soch": 111, "socl": 111, "sof": [41, 54, 55, 56, 57, 58, 59, 60, 63, 64, 65, 68, 70, 71, 74, 76, 78, 80, 100, 109, 110, 111, 113, 126, 127, 128, 135, 136, 142, 144, 145, 151, 170, 171, 172, 180, 183, 189], "sof_creat": 60, "sof_origin": 58, "sof_po": [33, 38, 59, 110, 145], "sof_pos_width": 76, "sof_unmask": 58, "softwar": [23, 27, 31, 39, 42, 45, 46, 67, 87, 107, 109, 111, 112, 121, 183, 185, 187, 188, 191], "sole": 110, "solut": [67, 72, 144], "solv": [11, 17, 21, 67, 95, 160], "some": [6, 10, 11, 12, 19, 20, 21, 31, 39, 44, 45, 49, 58, 67, 68, 76, 87, 89, 101, 104, 107, 109, 119, 125, 137, 138, 144, 150, 151, 160, 164, 166, 184, 187, 189, 192, 193, 195], "some_boolean": 184, "some_integ": 184, "somehow": 187, "someth": [11, 131, 148], "sometim": [18, 19, 110, 144, 166, 184, 187], "somewhat": 89, "somewher": [17, 19, 128, 139, 142], "soon": [34, 109, 111], "sooner": 166, "sop": [47, 64, 134], "sop_po": 47, "sop_pos_width": 47, "sorag": 21, "sort": 59, "sorter": 17, "sourc": [0, 17, 22, 27, 47, 49, 65, 66, 71, 75, 90, 92, 94, 96, 98, 109, 111, 113, 121, 144, 147, 159, 160, 164, 166, 183, 184, 185, 186, 187, 189, 196, 198], "sp": 179, "sp_bmem": 161, "sp_bram": 161, "sp_bram_xilinx": 161, "sp_uram_xilinx": 161, "space": [0, 3, 4, 17, 18, 19, 21, 22, 29, 30, 31, 35, 37, 39, 41, 45, 48, 49, 59, 61, 71, 80, 87, 89, 90, 109, 111, 116, 118, 119, 121, 128, 131, 139, 142, 143, 144, 149, 164, 166, 180, 183, 185, 187, 190, 192, 193, 195], "space_size_set": [128, 139, 142, 143], "spacer": 111, "span": [23, 76], "spars": 98, "special": [19, 45, 60, 164, 166, 180, 183, 187], "specif": [0, 1, 11, 20, 21, 25, 28, 31, 34, 39, 40, 44, 45, 60, 67, 71, 107, 109, 110, 112, 113, 119, 129, 148, 152, 156, 157, 158, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 185, 187, 188, 189, 190, 191, 192], "specifi": [3, 11, 18, 19, 22, 24, 26, 34, 38, 54, 55, 56, 58, 60, 74, 76, 80, 89, 104, 109, 126, 127, 131, 144, 149, 151, 166, 184, 185, 200], "speed": [45, 48, 58, 67, 71, 96, 107, 108, 109, 111, 119, 129, 144, 152, 160, 179, 180, 185, 187, 188, 189, 193, 194, 195], "spent": 6, "spike": 17, "spkt_lng": 59, "spkt_size_min": 59, "split": [0, 36, 68, 69, 70, 71, 131, 166, 183, 187], "splitter": [144, 162, 163, 187, 193], "splitter_output": [69, 70], "squar": 160, "squarer": 160, "sr": [67, 160], "sr_sync_latch": [12, 160], "src": [49, 90, 102, 144, 173, 179, 184, 191], "src_buf": [17, 164], "src_buf_col": 17, "src_buf_rd_addr": 17, "src_buf_rd_data": 17, "src_buf_row": 17, "src_channel": 90, "src_rdy": [4, 47, 76, 102, 104, 144, 145, 147, 160, 192], "ss": 27, "st": 192, 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[25, 57, 109, 111], "stat_discard": 57, "stat_pkt_lng": 35, "state": [0, 12, 31, 32, 40, 67, 71, 82, 87, 89, 116, 121, 128, 130, 139, 142, 143, 144, 149, 151, 156, 160, 183], "state_packet_data": [128, 139, 142], "state_packet_new": [128, 139, 142], "state_packet_non": [128, 139, 142], "state_packet_space_new": [128, 139, 142], "state_pakcet_spac": [128, 139, 142], "statement": 184, "static": [0, 183, 186], "statist": [0, 9, 11, 18, 24, 25, 31, 45, 46, 57, 87, 107, 109, 111, 144, 160, 164, 180], "statu": [5, 23, 25, 31, 37, 44, 48, 58, 59, 67, 79, 81, 85, 105, 107, 109, 111, 116, 117, 144, 156, 180, 181, 183, 185, 191, 192, 193], "status_data": 133, "std": [144, 152], "std_arith": 144, "std_logic": [3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 28, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 113, 114, 116, 117, 120, 121, 180, 183, 192], "std_logic_arith": 144, "std_logic_vector": [3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 28, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 113, 114, 115, 116, 117, 120, 121, 180, 183, 185, 192], "stdarithnowarn": 144, "steadi": 67, "steer": 113, "stem": 166, "step": [19, 29, 35, 47, 129, 144, 152, 166, 179, 189, 195], "stick": 144, "still": [19, 57, 104, 119, 186], "stop": [19, 35, 39, 42, 44, 45, 49, 67, 80, 110, 144, 183, 184], "stop_forc": 37, "stop_force_chan": 37, "stop_req_ack": [37, 40, 44], "stop_req_chan": [37, 40, 44], "stop_req_channel": 35, "stop_req_don": 35, "stop_req_vld": [35, 37, 40, 44], "storag": [118, 119], "store": [4, 5, 6, 10, 11, 13, 17, 18, 19, 21, 26, 34, 43, 45, 58, 59, 65, 67, 77, 80, 87, 93, 109, 111, 112, 118, 119, 126, 127, 133, 144, 150, 160, 164, 166, 185, 195], "stp": 27, "straddl": 113, "straight": [5, 67, 68, 105], "straightforward": 67, "strang": 144, "stratix": [23, 31, 109, 111, 156, 161, 164, 187, 188, 189, 190, 192], "stratix10": [3, 4, 5, 9, 14, 16, 34, 35, 37, 44, 48, 49, 50, 54, 58, 60, 65, 69, 70, 71, 74, 75, 78, 79, 89, 94, 101, 105, 109, 111, 116, 117, 166, 180, 192], "stream": [0, 17, 19, 35, 46, 48, 54, 57, 60, 62, 63, 64, 67, 71, 74, 94, 107, 109, 111, 131, 144, 162, 165, 180, 183, 186, 187, 192, 195], "stream2": 162, "stream_out_aful": 19, "stream_out_en": 19, "strech": 60, "stress": 45, "string": [3, 4, 5, 6, 9, 10, 13, 14, 15, 16, 18, 24, 28, 31, 33, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 58, 59, 60, 61, 62, 64, 65, 66, 67, 68, 69, 70, 71, 74, 75, 77, 78, 79, 81, 82, 83, 84, 86, 89, 90, 91, 93, 94, 96, 98, 99, 100, 101, 102, 105, 106, 109, 111, 113, 116, 117, 121, 128, 131, 133, 139, 142, 143, 144, 150, 166, 180, 183, 185, 192], "strobe": [39, 45, 109, 111], "strongli": [144, 166, 183, 187], "struct": 144, "structur": [144, 152, 156, 160, 161, 166, 184, 185], "stuck": [116, 144, 152, 164, 183, 187], "su": 27, "subclass": [125, 137, 138, 144], "subcompon": [48, 111, 144, 166, 184, 185, 187, 191], "subcor": 0, "subdirectori": 166, "subenviron": 144, "sublay": 187, "submit": 25, "submodul": [109, 111, 185, 198], "subnod": 185, "subpart": 27, "subprocess": 166, "subsect": [152, 187], "subsequ": 187, "subset": [17, 71], "substitut": 182, "subtract": 60, "success": [0, 31, 112, 144, 183], "successful": 38, "successfulli": [17, 109, 111, 144, 173, 189], "successor": 47, "suddenli": 67, "sudo": [27, 31, 174, 189], "suffici": [27, 76, 110], "suffix": [47, 58, 144, 166], "suggest": 184, "suit": [179, 187], "suitabl": [4, 13, 144, 156, 161], "sum": [18, 19, 25, 30, 60, 94], "sum_en": 25, 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"swrite": [131, 144], "sychron": 132, "sync_": 151, "sync_cb": 151, "sync_connect": [128, 139, 142, 143, 151], "sync_regist": 151, "sync_reset": 151, "sync_termin": 151, "synchrnou": 12, "synchron": [1, 6, 16, 24, 47, 59, 90, 91, 92, 94, 96, 98, 99, 100, 107, 109, 111, 116, 128, 139, 142, 143, 151, 160, 164, 183, 196], "synchroni": 121, "syncrhon": 151, "syntax": 185, "synth": 166, "synth_onli": 166, "synthes": 166, "synthesi": [160, 184, 189], "synthesis": 166, "synthfil": 166, "sysmon": 191, "system": [23, 40, 112, 187, 189, 196], "systemverilog": [166, 200], "sythesi": 166, "t": [11, 17, 20, 25, 31, 32, 67, 76, 87, 88, 89, 107, 109, 121, 122, 128, 131, 133, 139, 142, 143, 144, 148, 149, 166], "tabl": [31, 39, 45, 76, 89, 90, 104, 122, 123, 124, 125, 128, 134, 137, 138, 139, 142, 143, 144, 145, 152, 160, 165, 183, 184, 187], "tabul": 144, "tag": [22, 113, 117, 119, 131, 144, 166, 192, 198], "tag_8": 117, "tag_9": 117, "tak": 151, "take": [5, 17, 19, 58, 64, 67, 75, 87, 88, 89, 104, 107, 110, 119, 126, 127, 129, 130, 144, 174, 183, 184, 185, 187, 194], "taken": [0, 19, 80, 98, 110], "talk": 89, "tap": [58, 144], "targ": 166, "target": [1, 3, 5, 11, 17, 18, 19, 27, 31, 46, 50, 54, 64, 67, 68, 78, 81, 83, 84, 87, 88, 89, 111, 117, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 187, 188, 189, 192, 193], "target_default": 166, "target_func": 117, "target_myproc": 166, "target_tag": 166, "task": [29, 107, 109, 111, 125, 126, 127, 131, 137, 138, 144, 146, 149, 150, 151, 152, 187, 192], "tb": 31, "tbd": [39, 180], "tcam": [22, 180, 183, 187], "tchannel": 131, "tcl": [27, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 185, 189, 191], "tclsh": 166, "tcp": 74, "tdata": [124, 139], "tdiscard": 131, "tdut": 144, "tehn": 14, "tehr": 130, "tell": [98, 122, 144], "temp": 191, "temperatur": [23, 164], "temporari": 59, "term": [104, 185, 189, 194], "termin": [130, 149], "ternari": 161, "test": [0, 5, 31, 32, 45, 46, 58, 59, 102, 108, 113, 128, 131, 139, 142, 143, 150, 152, 154, 167, 168, 169, 180, 181, 183, 189, 190, 191], "test_mem_test": 31, "test_pci": 174, "testbench": [150, 152, 166], "tester": [154, 190], "texliv": 31, "text": [47, 144], "tfc": 111, "tfch": 111, "tfcl": 111, "th": 101, "than": [0, 1, 3, 4, 17, 25, 29, 31, 48, 54, 58, 59, 60, 67, 68, 76, 89, 101, 109, 111, 129, 144, 147, 160, 166, 184, 187, 188, 192, 193], "thank": [109, 111], "thei": [17, 19, 21, 36, 57, 58, 60, 71, 75, 76, 87, 89, 93, 94, 95, 101, 118, 128, 129, 131, 139, 142, 143, 144, 147, 160, 164, 183, 184, 185, 187, 195], "them": [0, 11, 18, 21, 25, 33, 36, 58, 59, 60, 64, 67, 68, 75, 80, 87, 89, 104, 107, 108, 110, 116, 118, 119, 126, 127, 128, 129, 138, 139, 141, 142, 143, 144, 146, 149, 152, 159, 179, 183, 184, 185, 187, 189, 190, 192], "themselv": [11, 174], "theoret": 87, "theori": 89, "ther": 130, "therefor": [18, 29, 31, 47, 52, 60, 67, 75, 76, 87, 89, 104, 121, 144, 186, 187, 194], "thesi": [1, 17, 19, 59, 119], "thi": [0, 1, 2, 3, 5, 6, 7, 10, 11, 12, 13, 14, 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122, 124, 128, 131, 135, 136, 139, 142, 143, 144, 146, 149, 150, 151, 152, 184, 187, 190], "threshh": 144, "threshl": 144, "throgh": 20, "through": [4, 18, 19, 39, 45, 58, 67, 71, 75, 76, 77, 78, 80, 85, 87, 90, 106, 109, 111, 112, 121, 122, 123, 124, 125, 133, 134, 137, 138, 143, 144, 145, 159, 164, 166, 183, 185, 186, 187, 188, 193, 195], "throughout": [183, 184, 191], "throughput": [0, 1, 17, 19, 21, 45, 46, 62, 67, 68, 75, 76, 93, 98, 119, 128, 139, 142, 143, 159, 180, 186, 187, 188, 190, 193, 195], "throught": [135, 136], "throw": [14, 16], "thrp_mea": 45, "thu": [13, 17, 18, 19, 23, 68, 76, 83, 184, 192], "ti": [109, 184], "tic": 48, "tick": [17, 24, 28, 30, 31, 67, 152], "tile": [76, 109, 111, 119, 170, 171, 172, 173, 174, 177, 180, 183, 187, 188, 192, 195], "tile_multir": 187, "till": [40, 87, 144], "time": [0, 4, 6, 11, 12, 14, 16, 18, 19, 21, 25, 26, 28, 31, 45, 58, 62, 65, 68, 71, 77, 80, 88, 90, 96, 100, 109, 110, 118, 121, 122, 131, 144, 148, 150, 151, 166, 179, 180, 184, 185, 187, 193], "time_array_add": 131, "time_reset": 65, "timeout": [17, 59, 62, 96, 131], "timeout_clk_no": 59, "timestamp": [22, 65, 109, 120, 121, 122, 153, 162, 180, 183, 187, 191], "timestamp_en": 109, "timestamp_format": 71, "timestamp_width": 71, "timestampvld": [22, 183, 187], "timestap": 183, "tkeep": 124, "tkeep_width": 124, "tlast": 124, "tlm": 144, "tlp": [22, 114], "tmeta": 131, "tmodel": 144, "tmp": [11, 25], "tmp_data": 144, "tmp_meta": 144, "to_unsign": 18, "todo": [5, 109, 144, 160, 164], "togeth": [17, 18, 21, 22, 68, 72, 80, 87, 89, 104, 112, 119, 128, 138, 141, 142, 144, 147, 151, 160, 166, 194], "too": [17, 75, 144, 184], "took": 149, "tool": [0, 25, 109, 111, 121, 144, 152, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 184, 185, 187, 188, 189, 191, 195, 196], "top": [0, 27, 46, 71, 132, 135, 136, 142, 166, 184, 185, 187, 190, 193], "top_level": [5, 144], "top_level_": 166, "top_level_archgrp": 166, "top_level_path": 166, "total": [0, 9, 11, 19, 27, 31, 37, 39, 40, 43, 44, 46, 54, 76, 90, 98, 109, 111, 192, 195], "total_error": 144, "tpacket_s": 131, "tph": 113, "tr": 144, "tr_dut": [131, 144], "tr_in_a": 131, "tr_in_b": 131, "tr_model": [131, 144], "tr_out": [131, 144], "tr_paket": 144, "tr_port": 144, "track": 17, "traffic": [18, 27, 65, 67, 125, 135, 136, 137, 138, 144, 149], "traget": [9, 37, 44], "tran": [17, 118, 164], "tranasciev": 149, "trans_a_col": 17, "trans_a_item": 17, "trans_b_col": 17, "trans_b_item": 17, "trans_comp_": 17, "trans_comp_dst_rdi": 17, "trans_comp_meta": 17, "trans_comp_src_rdi": 17, "trans_dst_rdi": 17, "trans_fifo_item": 17, "trans_fifo_s": [75, 111], "trans_len": 17, "trans_meta": 17, "trans_mtu": 17, "trans_sort": 164, "trans_src_rdi": 17, "trans_stream": 17, "trans_vld": 17, "transact": [17, 22, 29, 31, 33, 39, 41, 45, 46, 75, 76, 85, 87, 89, 91, 99, 100, 101, 102, 104, 106, 110, 111, 113, 114, 115, 117, 118, 125, 126, 127, 128, 129, 130, 131, 134, 135, 136, 137, 138, 139, 141, 142, 143, 144, 146, 149, 152, 164, 187, 191, 192, 193, 198], "transaction_count": 147, "transal": 116, "transceiv": [107, 166, 184, 185, 187], "transfer": [1, 11, 17, 45, 47, 67, 75, 76, 83, 87, 104, 106, 147, 160, 164, 183, 186, 187, 188, 189, 191, 192, 193], "transform": [47, 68, 119, 129, 192], "transit": [67, 77, 82, 110, 132], "translat": [22, 27, 166, 185, 191], "transmiss": [47, 49, 65, 76, 91, 96, 100, 104, 110, 111, 144, 193, 194, 195], "transmit": [1, 22, 45, 65, 67, 70, 71, 76, 91, 98, 99, 101, 102, 104, 107, 109, 110, 111, 129, 149, 180, 192, 193, 194, 195, 196, 197], "transmitt": [76, 104], "transport": 35, "transs": 17, "trasfer": 113, "trasform": 162, "trbuf_fifo_en": 39, "trbuf_reg_en": [39, 46], "treadi": [124, 139], "treat": 47, "treatment": 179, "tree": [27, 39, 45, 135, 136, 160, 192], "trfc": 109, "trfch": 109, "trfcl": 109, "tri": [63, 160, 166, 187], "tricki": 67, "trigger": [4, 5, 6, 20, 59, 75, 77, 79, 81, 105, 150, 166], "trim": [52, 54], "trimmer": 162, "tripl": 183, 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"twice": [58, 68, 187], "two": [4, 5, 6, 14, 17, 21, 36, 39, 45, 47, 50, 54, 55, 56, 58, 60, 62, 63, 64, 67, 68, 69, 70, 71, 72, 73, 76, 77, 80, 81, 82, 86, 87, 89, 90, 94, 96, 98, 100, 104, 109, 110, 113, 118, 121, 122, 124, 125, 128, 129, 130, 131, 133, 135, 136, 137, 138, 139, 141, 142, 143, 144, 145, 146, 149, 151, 152, 156, 161, 164, 166, 170, 179, 183, 184, 186, 187, 192], "tx": [0, 8, 22, 33, 44, 46, 48, 50, 54, 57, 58, 59, 60, 61, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 74, 75, 77, 79, 81, 88, 90, 91, 92, 94, 96, 98, 99, 101, 102, 109, 123, 124, 128, 129, 133, 134, 135, 136, 139, 142, 143, 144, 145, 147, 180, 183, 187, 189, 194, 195, 197], "tx0_mfb_data": [69, 70], "tx0_mfb_dst_rdy": [69, 70], "tx0_mfb_eof": [69, 70], "tx0_mfb_eof_po": [69, 70], "tx0_mfb_meta": 70, "tx0_mfb_sof": [69, 70], "tx0_mfb_sof_po": [69, 70], "tx0_mfb_src_rdy": [69, 70], "tx0_mvb_dst_rdy": 69, "tx0_mvb_hdr": 69, "tx0_mvb_meta": 69, "tx0_mvb_payload": 69, "tx0_mvb_src_rdy": 69, "tx0_mvb_vld": 69, "tx1_mfb_data": [69, 70], "tx1_mfb_dst_rdy": [69, 70], "tx1_mfb_eof": [69, 70], "tx1_mfb_eof_po": [69, 70], "tx1_mfb_meta": 70, "tx1_mfb_sof": [69, 70], "tx1_mfb_sof_po": [69, 70], "tx1_mfb_src_rdy": [69, 70], "tx1_mvb_dst_rdy": 69, "tx1_mvb_hdr": 69, "tx1_mvb_meta": 69, "tx1_mvb_payload": 69, "tx1_mvb_src_rdy": 69, "tx1_mvb_vld": 69, "tx_": 187, "tx_addr": [85, 89], "tx_aempti": 77, "tx_ardi": [85, 89], "tx_be": 89, "tx_block_siz": [33, 68, 109, 111], "tx_block_vld": [59, 73], "tx_channel": [46, 90], "tx_channel_b": 59, "tx_chsum_bypass": 74, "tx_clk": [75, 77, 81, 109, 111, 166], "tx_compar": 144, "tx_compare_": 144, "tx_data": [7, 8, 47, 52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 94, 96, 98, 99, 101, 102, 105], "tx_data0": 94, "tx_data1": 94, "tx_data_in": 61, "tx_data_out": 61, "tx_dma_calypt": 45, "tx_dma_chan_start_stop_ctrl": 40, "tx_dma_channel": [48, 180], "tx_dma_metadata_extractor": 41, "tx_dma_pcie_trans_buff": 43, "tx_dma_pkt_dispatch": 42, "tx_dma_sw_manag": [40, 44], "tx_drd": [85, 89], "tx_drdy": [85, 89], "tx_dst_rdy": [7, 8, 47, 52, 55, 56, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 94, 96, 98, 99, 101, 105, 110], "tx_dst_rdy_in": 61, "tx_dst_rdy_out": 61, "tx_dwr": [85, 89], "tx_enabl": 57, "tx_env": 144, "tx_env_": 144, "tx_env_bas": 144, "tx_eof": [52, 55, 56, 57, 66, 68, 73, 77, 79, 81, 110], "tx_eof_in": 61, "tx_eof_mask": 58, "tx_eof_one_hot": 59, "tx_eof_origin": 58, "tx_eof_out": 61, "tx_eof_po": [52, 55, 56, 57, 58, 66, 68, 73, 77, 79, 81, 110], "tx_eof_pos_in": 61, "tx_eof_pos_out": 61, "tx_eof_unmask": 58, "tx_eop": [47, 72], "tx_eop_po": [47, 72], "tx_gen_en": 46, "tx_input": 144, "tx_input_data": 144, "tx_input_meta": 144, "tx_item": 102, "tx_item_vld": 73, "tx_item_width": [33, 68, 94, 109, 111], "tx_length": 60, "tx_link_up": 180, "tx_mac_lit": [111, 185, 187], "tx_mask": 58, "tx_meta": [52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 93], "tx_meta_in": 61, "tx_meta_out": 61, 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111], "unabl": 83, "unalign": [23, 47, 68], "unansw": 184, "unchang": [12, 46, 67, 110, 166], "uncom": 5, "uncov": 144, "undef_behaw_when_wr_to_same_address": 14, "undefin": [6, 13, 14, 26, 28, 31, 34, 76, 87, 151, 183, 187], "under": [27, 45, 65, 67, 128, 133, 139, 142, 143, 144, 186, 188], "undergo": 110, "underli": [13, 184], "unders": 187, "underscor": 76, "understand": [67, 87], "understood": 104, "unexpect": [82, 116], "unfortun": [67, 144, 188], "unifi": 192, "uniform": [125, 137, 138, 144, 166], "uniqu": [22, 112, 118, 119, 144, 183, 185, 187], "unit": [11, 17, 18, 19, 21, 22, 48, 59, 60, 62, 67, 75, 76, 80, 83, 88, 101, 104, 109, 111, 112, 118, 119, 120, 121, 144, 153, 160, 164, 187, 191, 193, 198], "unitid": 22, "univers": [4, 5, 10, 156, 160, 161, 188], "universalclass": 10, "unix": 196, "unless": [7, 144], "unlik": 76, "unlimit": 3, "unmask": [58, 180], "unnessesari": 68, "unpack": [144, 162], "unpacking_stag": 60, "unpaus": [65, 71], "unprocess": 110, "unregist": 27, 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"value_vld_2": 25, "value_width": 25, "values_vld": 25, "varabl": 166, "vari": [11, 45, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 189, 192], "variabl": [11, 31, 124, 125, 128, 133, 137, 138, 139, 142, 143, 144, 145, 146, 147, 151, 160, 184], "variable_nam": 150, "variant": [1, 62, 109, 111, 113, 123, 153, 160, 161, 176, 185, 187, 189, 192], "variou": [46, 109, 110, 111, 112, 144, 156, 166, 184, 188], "vast": 87, "vcover": 144, "vector": [18, 44, 59, 74, 76, 84, 101, 104, 128, 132, 139, 142, 146, 147, 160, 164], "vendor": [112, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 185, 192], "ver": 144, "ver_bas": 144, "verbos": [45, 144], "veri": [7, 17, 68, 71, 87, 128, 139, 142, 143, 144, 166, 184, 190], "verif": [67, 102, 122, 130, 131, 132, 135, 136, 146, 151, 152, 166, 195], "verifi": [5, 45, 58, 62, 129, 144], "verilog": 166, "versa": [40, 109, 192], "versatil": 76, "version": [32, 59, 67, 77, 91, 111, 112, 161, 166, 170, 174, 177, 184, 185, 188, 189], "vfid": 22, "vhd": [10, 31, 144, 166, 184, 185, 191], "vhdl": [11, 112, 166, 185, 191, 192], "vhdl2008": 166, "vhdl98": 166, "vhdl_dut_u": 150, "vhdlpkgbool": 184, "vhdlpkggen": 184, "vhdlpkghexvector": 184, "vhdlpkgint": 184, "vhdlpkgstring": 184, "vhld": 144, "via": [25, 27, 29, 31, 67, 71, 76, 104, 107, 121, 148, 164, 166, 173, 180, 183, 184, 187, 191, 192, 193, 195, 198], "vice": [40, 109, 192], "view": 18, "vif": 144, "vif_nam": 144, "violat": 82, "virtex": [161, 169], "virtex7": [113, 166], "virtual": [22, 59, 76, 117, 128, 131, 139, 142, 143, 146, 150, 152, 187], "virtual_debug_en": 27, "visibl": [58, 184], "visit": [144, 184], "visual": 58, "vivado": [120, 166, 167, 168, 169, 175, 176, 188, 189], "vivado_ip_xact": 166, "vivado_set_properti": 166, "vld": [32, 95, 144, 147], "void": [128, 131, 139, 142, 143, 144, 150, 152], "voltag": [23, 164], "vsec": [112, 185, 192], "vsim": [144, 166], "vu9p": 167, "w": [0, 29, 30, 31, 32, 39, 45, 67, 109, 111, 183, 189, 191], "wa": [0, 11, 25, 31, 46, 58, 59, 67, 68, 87, 89, 101, 109, 118, 144, 151, 152, 160, 162, 165, 179, 184, 187], "wai": [0, 11, 12, 17, 18, 19, 59, 60, 64, 67, 68, 80, 88, 89, 109, 110, 118, 119, 125, 130, 135, 136, 137, 149, 152, 159, 166, 184, 185, 187], "wait": [18, 27, 29, 31, 32, 58, 63, 75, 83, 99, 101, 110, 111, 118, 119, 131, 144, 147, 150, 189], "waitrequest": [23, 83], "waitrequestallow": 83, "want": [8, 11, 18, 58, 67, 68, 87, 88, 89, 99, 109, 122, 144, 148, 152, 179, 187, 189, 195], "warn": [6, 17, 59, 68, 75, 144, 174, 180], "wast": 47, "watchdog": [131, 164], "waveform": 104, "wclk": 15, "we": [11, 15, 18, 21, 50, 67, 68, 80, 87, 88, 89, 144, 183, 185, 187, 189, 192, 194, 195], "websit": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177], "welcom": 159, "well": [7, 8, 17, 19, 42, 45, 46, 48, 57, 59, 76, 80, 87, 88, 89, 144, 166, 184, 185, 187, 190], "were": [5, 27, 45, 58, 87, 109, 111, 131, 144, 184], "what": [5, 79, 89, 101, 105, 128, 144, 152], "whatev": 67, "when": [3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 25, 26, 27, 29, 31, 33, 35, 40, 44, 47, 48, 50, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 67, 68, 71, 73, 75, 76, 78, 79, 80, 82, 83, 87, 88, 89, 91, 93, 95, 96, 98, 101, 102, 104, 105, 109, 110, 111, 112, 118, 119, 125, 126, 127, 128, 129, 130, 131, 133, 135, 136, 137, 138, 142, 144, 146, 147, 149, 150, 151, 160, 166, 179, 183, 184, 185, 187, 195], "whenev": [31, 58, 70, 144], "where": [4, 6, 8, 21, 23, 27, 45, 58, 60, 61, 67, 71, 75, 76, 80, 95, 106, 110, 111, 118, 121, 144, 146, 151, 152, 160, 166, 170, 171, 172, 183, 184, 185, 189, 190, 194, 195], "wherea": [76, 104, 144], "whether": [11, 16, 20, 60, 65, 67, 71, 76, 80, 87, 109, 111, 121, 133, 144, 146, 148, 164], "whic": 35, "which": [0, 1, 3, 7, 10, 11, 14, 17, 18, 19, 21, 27, 31, 32, 35, 36, 38, 39, 40, 42, 43, 44, 45, 47, 49, 55, 57, 58, 59, 60, 65, 67, 68, 71, 75, 76, 80, 85, 87, 89, 91, 98, 99, 101, 104, 109, 110, 111, 118, 119, 122, 124, 125, 126, 127, 128, 130, 131, 133, 135, 136, 137, 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109, 110, 144, 146, 184, 194], "wr": [5, 6, 31, 75, 80, 87, 146, 150], "wr_addr": [13, 14, 16, 78], "wr_aful": [4, 77], "wr_and_rd_en_in": 150, "wr_be": [14, 16], "wr_clk": [4, 16], "wr_data": [4, 13, 14, 16, 78], "wr_en": [4, 13, 14, 16, 78, 150], "wr_full": 4, "wr_ie": 78, "wr_rst": [4, 16], "wr_statu": 4, "wrap": [24, 25, 31, 129], "wrapper": [0, 16, 18, 27, 86, 132, 164, 186], "write": [0, 4, 5, 11, 13, 14, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 37, 39, 43, 44, 45, 49, 67, 71, 78, 82, 83, 85, 87, 90, 107, 109, 111, 112, 116, 117, 118, 119, 121, 122, 126, 127, 130, 131, 135, 136, 144, 146, 147, 149, 150, 152, 156, 160, 161, 166, 170, 171, 172, 184, 185, 188, 191, 192, 195], "write_data": 144, "write_j": 170, "write_meta": 144, "write_pof": [171, 172], "write_port": [6, 13, 14, 15], "write_reset": 144, "writedata": 122, "writeresponsevalid": 83, "written": [4, 5, 6, 16, 30, 32, 42, 43, 58, 67, 76, 78, 85, 87, 109, 144, 146, 174, 180, 200], "wrong": 144, "www": 10, "x": [10, 31, 58, 67, 70, 76, 116, 130, 131, 144, 187, 192], "x16": [46, 167, 169, 170, 171, 172, 173, 174, 175, 176, 177, 189, 192], "x8": [46, 192], "x8x8": 192, "xanosecond": 121, "xci": 166, "xcku15p": 175, "xcu200": 167, "xcu55c": 168, "xcv": 192, "xcvr": 187, "xcvu7p": 166, "xcvu9p": [169, 176], "xdc": 166, "xgmii": [109, 111], "xilinx": [4, 5, 13, 66, 79, 86, 101, 105, 107, 109, 111, 113, 119, 134, 156, 160, 161, 164, 166, 167, 168, 169, 175, 176, 184, 187, 188, 189, 190, 192], "xlgmii": [107, 109, 111], "xlgmii_clk": 107, "xlgmii_rxc": 107, "xlgmii_rxd": 107, "xlgmii_txc": 107, "xlgmii_txd": 107, "xmii": 129, "xml": 32, "xnor": 160, "xor": 160, "xor48": 160, "xp": 67, "xpm_cdc": 166, "xpm_fifo": 166, "xpm_memori": 166, "xpm_memory_sdpram": 161, "xscn": 67, "xvc_enabl": 192, "xx": 87, "xxx_root_directori": [0, 189, 191, 195], "xz": [112, 185], "yaml": 148, "ye": [146, 170, 174, 175, 176, 177, 188], "yet": [4, 83, 87, 186, 187, 195, 196], "you": [0, 6, 8, 11, 14, 17, 19, 20, 23, 24, 25, 27, 31, 67, 68, 71, 85, 87, 89, 90, 95, 109, 111, 122, 124, 128, 131, 139, 142, 143, 144, 145, 148, 151, 152, 154, 159, 160, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 183, 184, 185, 186, 187, 188, 189, 192, 195], "your": [0, 11, 24, 27, 31, 67, 71, 95, 122, 131, 152, 159, 178, 183, 184, 188, 189, 195], "your_card": 189, "your_ndk_firmwar": 189, "yourself": [11, 19], "yourselv": 89, "yum": 31, "zero": [0, 11, 14, 28, 31, 47, 49, 109, 144, 149], "zeroth": 76}, "titles": ["Minimal NDK application", "Asynchronous modules", "Basic Tools", "DSP Comparator", "ASFIFOX", "FIFOX", "FIFOX Multi", "Register FIFO", "Barrel Shifter", "Multi MEMx Counter", "H3 Class Hash", "N_LOOP_OP", "Synchronous SR latch", "Live value table memory", "Multi-port BRAM", "NP LUT RAM", "Simple dual-port BRAM", "CrossbarX", "Event Counter", "Packet Planner", "Pulse short", "Transaction Sorter", "Packages", "SDM CLIENT", "Mem logger", "Data logger", "Histogramer", "JTAG-over-protocol Client", "Latency meter", "AMM_GEN", "AMM_PROBE", "DDR4 Memory Tester", "MEM_TESTER Software", "Header Insertor", "Address Manager", "Header Manager", "Input Buffer", "Software Manager", "Transaction Buffer", "RX DMA Calypte", "Channel Start/stop control", "Metadata Extractor", "Packet Dispatcher", "Transaction buffer", "Software Manager", "TX DMA Calypte", "DMA Calypte", "FLU bus specification", "Gen Loop Switch (GLS)", "MFB Generator", "MFB FRAME EXTENDER", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "MFB FRAME TRIMMER", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "CROSSBARX STREAM2", "MFB Cutter Simple", "MFB Dropper", "MFB Enabler", "MFB Frame Masker", "Frame Packer", "Frame Unpacker", "MFB Loopback", "MFB Merger", "MFB Merger Simple", "Metadata Insertor", "Packet Delayer", "MFB PIPE", "Rate Limiter", "MFB Reconfigurator", "MFB Splitter", "MFB Splitter Simple", "Timestamp Limiter", "MFB Trasformer", "MFB Auxiliary Signals", "Checksum Calculator", "CrossbarX Stream", "MFB specification", "MFB ASFIFOX", "Crossbarx Output Buffer", "MFB FIFOX", "MFB Packet Discard ASFIFO", "MFB PD ASFIFO SIMPLE", "MI ASYNC", "MI2AVMM", "MI2AXI4", "MI indirect access", "MI Pipe", "MI bus specification", "MI Reconfigurator", "MI Splitter Plus Gen", "MVB Channel Router", "MVB DEMUX", "MVB DISCARD", "MVB Item Collision Resolver", "MVB Merge Items", "SHAKEDOWN", "MVB Merge Streams", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "MVB Merge Streams Ordered", "MVB MUX", "MVB2MFB", "MVB Operation", "MVB Shakedown", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "MVB Specification", "MVB FIFOX", "MVB Lookup Table", "40GE Ethernet PHY for Ultrascale+ FPGAs", "BUFFER", "RX MAC LITE", "MFB -> LBUS reconfigurator (TX LBUS)", "TX MAC LITE", "PCI_EXT_CAP", "PCIE CONVERSION UNITS", "PCIE Byte Count", "PCIe Byte Enable Decoder", "MTC (MI Transaction Controller)", "PCIE Header parsing/deparsing", "PTC Tag Manager", "PTC (PCIe Transaction Controller)", "TSU Format to ns Convertor", "TSU GEN", "AVMM Agent", "AVST CRDT Agent", "AXI Agent", "Byte Array agent", "Byte Array to LII convert enviroment", "Byte Array to LII convert enviroment", "Byte_array_mfb environment", "Byte array to MII transitional environment", "Byte array to pma convert enviroment", "Common package", "Components", "Intel MAC SEG", "LBUS Agent", "LII agent", "LII agent", "Logic vector agent", "Logic Vector Array agent", "logic_vector_array_axi environment", "byte array to MAC SEG", "LOGIC VECTOR ARRAY LBUS Environment", "logic_vector_array_mfb environment", "logic_vector_mvb environment", "SystemVerilog and UVM tutorial", "MFB Agent", "MI agent", "MVB agent", "FlowTest Sequence", "PMA agent", "probe agent", "RESET agent", "UVM simulation", "Controllers & TSU", "Debug Tools", "DSP components", "FIFO components", "FL Tools", "FLU Tools", "Documentation of Minimal NDK Application", "Basic logic elements", "Memory modules", "MFB Tools", "MI Tools", "Miscellaneous", "MVB Tools", "Build System", "AMD Alveo U200", "AMD Alveo U55C", "AMD VCU118@VU9P", "Bittware IA-420F", "Intel Stratix 10 DX FPGA DK", "Intel Agilex I-Series FPGA DK", "PRO DESIGN Falcon", "ReflexCES XpressSX AGI-FH400G", "Silicom fb2CGhh@KU15P", "Silicom fb4CGg3@VU9P", "Silicom N6010", "Cocotb toplevel simulation core", "F-Tile Multirate IP", "NETWORK MODULE", "BUFFER", "CRDT Agent", "The Application", "Configuration files and parameters", "Device Tree", "The DMA module", "The Network Module", "Frequently Asked Questions", "How to start", "The Memory Controller", "The MI bus interconnect", "The PCIe module", "NDK Architecture", "NDK Terminology", "NDK testing", "Time Stamp Unit", "Network Tools", "PCIe Tools", "Shift registers", "UVM Verification"], "titleterms": {"": [51, 53, 97, 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"client": [23, 27], "clock": [156, 188], "cocotb": 178, "code": [47, 144], "collis": 93, "common": [131, 144], "commun": 188, "comp": 166, "compar": [3, 131], "compon": [24, 25, 26, 28, 31, 44, 51, 53, 58, 97, 103, 119, 132, 155, 156, 166, 184, 185], "config": [133, 147], "configur": [46, 67, 76, 119, 125, 128, 137, 138, 139, 142, 143, 144, 148, 166, 180, 184, 192], "constant": 184, "constraint": 68, "contact": 184, "content": [2, 153, 154, 158, 162, 163, 165, 197, 198, 200], "control": [24, 25, 29, 30, 31, 39, 40, 45, 110, 116, 119, 153, 186, 188, 190, 192], "convers": 113, "convert": [126, 127, 130], "convertor": 120, "copi": 47, "core": [178, 179, 184, 187, 192], "core_bootstrap": 184, "core_conf": 184, "core_const": 184, "corundum": 188, "count": 114, "counter": [9, 18], "coverag": 144, "crdt": [123, 182], "creat": 144, "crossbarx": [17, 54, 75, 78], "cutter": 55, "data": [25, 68], "data_buff": 129, "ddr4": 31, "debug": [27, 154], "decod": 115, "delay": 65, "demux": 91, "depars": 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"f": 179, "falcon": 173, "fb2cghh": 175, "fb4cgg3": 176, "fdo": 144, "featur": [11, 18, 19, 24, 25, 26, 28, 31, 80, 166], "few": 87, "fh400g": 174, "fifo": [7, 131, 144, 156], "fifox": [5, 6, 79, 105], "file": [166, 184], "final": 166, "firmwar": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 185, 188, 189], "fl": 157, "flow": 11, "flowtest": 148, "flu": [47, 158], "forc": 80, "format": [120, 196], "fpga": [107, 171, 172, 185, 188, 189], "frame": [50, 52, 58, 59, 60], "frequenc": 188, "frequent": 188, "from": [183, 187], "full": 25, "function": [76, 144], "further": [184, 189], "gen": [48, 63, 69, 70, 89, 121], "gener": [17, 24, 25, 26, 28, 31, 32, 40, 41, 43, 44, 45, 47, 49, 76, 104, 105, 109, 111, 135, 136, 144, 148, 149, 183, 185], "given": 184, "gl": [48, 195], "guidelin": 47, "h3": 10, "hard": 192, "hash": 10, "have": 188, "header": [33, 35, 117], "hierarchi": 166, "high": 144, "histogram": 26, "host": 189, "how": [152, 183, 187, 189], "hw": 27, "i": [172, 184, 188], "ia": 170, "id": 112, "idl": 110, "implemen": 166, "implement": [51, 53, 97, 103, 166, 179, 188], "implementdesign": 166, "includ": 184, "incomplet": 166, "index": 76, "indirect": 85, "init": 166, "initi": 170, "inner": [128, 139, 142, 143], "input": [36, 144], "insertor": [33, 64], "instanc": [24, 25, 26, 28], "instruct": [170, 171, 172, 173], "integr": 185, "intel": [133, 171, 172], "interconnect": 191, "interfac": [6, 107, 135, 136, 144, 147, 149, 150, 183, 187, 188], "intern": [29, 31], "ip": [179, 186, 192], "ipg_gener": 129, "irrelev": 89, "iso": 188, "item": [93, 94, 122, 123, 125, 133, 134, 135, 136, 137, 138, 147, 149, 166], "jtag": 27, "jumbo": 188, "kei": [24, 25, 26, 28, 31], "kit": 188, "ku15p": 175, "lane": 194, "latch": 12, "latenc": 28, "layer": 144, "lbu": [110, 134, 141], "level": [139, 144], "librari": [134, 144], "lii": [126, 127, 135, 136], "limit": [67, 71], "list": [166, 189], "lite": [109, 111, 187], "live": 13, "load": 189, "local": [35, 39, 45, 46], "locat": 185, "logger": [24, 25], "logic": [122, 137, 138, 141, 160, 187], "logic_vector_array_axi": 139, "logic_vector_array_mfb": 142, "logic_vector_mvb": 143, "lookup": 106, "loop": 48, "loopback": 61, "low": [128, 139, 142, 143, 144], "lut": 15, "mac": [109, 111, 133, 140, 187], "machin": 110, "main": [144, 191], "make": 189, "makefil": [166, 184], "manag": [34, 35, 37, 44, 107, 118], "map": [89, 109, 111], "mask": 89, "masker": 58, "medusa": 186, "mem": 24, "mem_test": 32, "memori": [0, 13, 31, 161, 190], "memory_model": 122, "memx": 9, "merg": [94, 96, 98], "merge_n_to_m": 95, "merger": [62, 63], "meta": 152, "metadata": [41, 64], "meter": 28, "methodologi": 144, "mfb": [49, 50, 52, 55, 56, 57, 58, 61, 62, 63, 66, 68, 69, 70, 72, 73, 76, 77, 79, 80, 81, 110, 145, 152, 162], "mi": [0, 25, 29, 30, 31, 82, 85, 86, 87, 88, 89, 116, 146, 152, 163, 191], "mi2avmm": 83, "mi2axi4": 84, "mii": 129, "minim": [0, 159], "miscellan": 164, "mk": 184, "mod": 166, "model": 144, "modul": [1, 144, 161, 166, 180, 183, 184, 186, 187, 192, 195], "monitor": [125, 126, 127, 129, 130, 135, 136, 137, 138, 144, 147, 149], "more": 23, "mtc": 116, "multi": [6, 9, 14], "multir": 179, "mux": 99, "mvb": [90, 91, 92, 93, 94, 96, 98, 99, 101, 102, 104, 105, 106, 147, 152, 165], "mvb2mfb": 100, "n": 120, "n6010": 177, "n_loop_op": 11, "ndk": [0, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 188, 189, 193, 194, 195], "need": [184, 188, 189], "netfpga": 188, "network": [180, 187, 188, 197], "note": [67, 122, 144, 148, 186], "np": 15, "object": 144, "obtain": 166, "offset": 0, "ofm": 144, "one": 185, "op": 142, "open": 188, "openn": 188, "oper": [11, 67, 75, 76, 101, 104, 110], "order": 98, "osi": 188, "other": [119, 144, 166], "output": 78, "over": 27, "packag": [22, 131, 144, 184], "packer": 59, "packet": [19, 42, 65, 80, 183, 187, 188], "paramet": [76, 104, 148, 184, 189], "parametr": [144, 184], "pars": 117, "part": [27, 51, 53, 97, 103], "pass": 184, "past": 47, "pc": [107, 189], "pci_ext_cap": 112, "pcie": [46, 113, 114, 115, 117, 119, 192, 198], "pcie_cor": 192, "pcie_ctrl": 192, "pd": 81, "pdf": 31, "phase": 166, "phy": 107, "pipe": [66, 86], "pkt_end": 110, "pkt_halt": 110, "pkt_process": 110, "plan": [39, 45, 58, 108, 180, 181], "planner": 19, "platform_tag": 166, "plu": 89, "pma": [107, 130, 149], "port": [14, 16, 17, 24, 25, 26, 28, 31, 76, 89, 104, 109, 111, 135, 136, 149, 183, 194], "prepar": 189, "prioriti": 166, "pro": 173, "probe": 150, "profil": [148, 179], "program": [32, 167, 168, 169], "properti": [144, 166], "protocol": [27, 188], "ptc": [118, 119], "puls": 20, "py": 32, "pytest": [31, 32], "quartu": 184, "question": 188, "quick": [11, 178], "r": 195, "ram": 15, "random": 131, "rate": 67, "read": [6, 183], "realign": 110, "receiv": [183, 187], "reconfigur": [68, 88, 110, 187], "refer": [1, 17, 19, 23, 31, 59, 119, 156, 161], "reflexc": 174, "regist": [7, 39, 45, 109, 111, 183, 195, 199], "report": [31, 32, 144], "report_gen": 32, "repositori": 144, "request": 144, "request_item": 122, "request_subscrib": 122, "requir": 185, "reset": [11, 144, 151], "resolv": 93, "respons": [122, 144], "response_item": 122, "revis": 174, "router": 90, "run": 144, "rx": [39, 107, 109, 128, 139, 141, 142, 143], "savedesign": 166, "scenario": [76, 104, 110], "scoreboard": 144, "scratch": 195, "script": [144, 174], "sdm": 23, "seg": [133, 140], "select": [186, 192], "sequenc": [122, 123, 125, 126, 127, 128, 129, 130, 133, 134, 135, 136, 137, 138, 139, 141, 142, 143, 144, 147, 148, 149], "sequence_item": [124, 145, 146], "sequence_item_request": 122, "sequence_item_respons": 122, "sequence_rx": 129, "sequence_rx_bas": 129, "sequence_tx": 129, "sequence_tx_bas": 129, "seri": 172, "set": 89, "setupdesign": 166, "shakedown": [95, 102], "shift": [68, 199], "shifter": 8, "short": 20, "side": 68, "signal": [47, 73, 104, 196], "silicom": [175, 176, 177], "simpl": [16, 24, 25, 55, 63, 70, 81, 151], "simul": [152, 178], "singl": 156, "situat": 11, "size": 27, "sof_po": 76, "softwar": [32, 37, 44], "solut": 11, "sorter": 21, "sourc": 188, "space": [25, 27, 67, 85, 107, 112, 191], "specif": [23, 47, 58, 76, 83, 87, 104, 144, 184], "splitter": [69, 70, 89], "sr": 12, "stack": 188, "stamp": 196, "standard": 188, "start": [40, 178, 189], "state": 110, "statu": [39, 45], "stop": 40, "stratix": 171, "stream": [75, 96, 98, 194], "stream2": 54, "sub": 31, "subcompon": [35, 39, 40, 41, 43, 45, 46, 60, 105], "support": [46, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 188, 192], "sv": 129, "sv_lib": 166, "sw": [24, 25, 27, 31, 183, 187, 188], "switch": [48, 179], "sychron": 151, "synchron": [12, 144], "synth_flag": 166, "synthesi": 166, "synthesizeproject": 166, "synthetizedesign": 166, "system": [166, 184, 185], "systemverilog": 144, "tab": [39, 45, 58, 85, 89, 179, 187], "tabl": [13, 47, 106], "tag": 118, "target": 166, "tcl": [144, 166, 184], "templat": [24, 25, 26, 28], "terminologi": 194, "test": [144, 174, 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180, 181, 200], "vhdl": 184, "virtual": 144, "vivado": 184, "vld": 104, "vu9p": [169, 176], "w": 195, "warn": 148, "warp": 25, "what": [184, 188, 189], "word_realign": 110, "work": [184, 189], "wrapper": 129, "write": [6, 183], "xpresssx": 174}}) \ No newline at end of file +Search.setIndex({"alltitles": {"1. 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89, 107, 120, 121], "90": [108, 144], "91": 179, "93": [0, 31], "94": [185, 189], "95415f0": 185, "96": [0, 47, 117, 195], "96b": 121, "97": 31, "98": 87, "98xx": 87, "99": 31, "999": [121, 196], "A": [4, 5, 11, 16, 17, 18, 21, 26, 39, 40, 45, 47, 58, 65, 67, 76, 110, 118, 128, 131, 138, 139, 142, 143, 144, 146, 159, 174, 183, 184, 185, 187, 188, 191, 192, 195, 198], "AND": [34, 55, 56, 57, 73, 79, 89, 90, 102, 109, 160, 180, 183, 192], "And": [0, 33, 58, 68, 147, 184], "As": [67, 76, 87, 89, 109, 111, 129, 183, 184, 187], "At": [17, 21, 59, 60, 67, 68, 80, 87, 118, 126, 127, 144, 166], "BE": [22, 67, 87, 88, 152], "BY": 183, "Be": [27, 148], "But": [11, 19, 67, 76, 87, 146], "By": [0, 48, 67, 111, 192], "FOR": [34, 164], "For": [0, 1, 6, 7, 11, 14, 17, 18, 19, 31, 32, 41, 42, 45, 55, 57, 59, 67, 68, 76, 77, 79, 80, 87, 89, 91, 99, 107, 109, 110, 111, 112, 113, 115, 117, 118, 119, 122, 124, 126, 127, 128, 131, 139, 142, 143, 144, 145, 147, 150, 151, 152, 154, 159, 166, 167, 168, 169, 183, 184, 187, 189, 193, 194, 195], "IN": [17, 135, 136, 149], "If": [0, 4, 7, 14, 16, 18, 19, 21, 25, 31, 42, 57, 58, 63, 67, 68, 75, 77, 80, 87, 88, 89, 99, 102, 109, 111, 116, 118, 126, 127, 131, 144, 146, 147, 148, 159, 166, 179, 183, 185, 186, 187, 188, 189, 192, 195], "In": [0, 6, 7, 11, 12, 17, 23, 31, 35, 39, 45, 58, 59, 67, 68, 71, 75, 76, 83, 87, 88, 89, 90, 91, 104, 110, 111, 118, 119, 128, 129, 131, 135, 136, 139, 142, 143, 144, 147, 151, 152, 159, 166, 183, 185, 187, 190, 192, 194, 195], "It": [0, 1, 7, 18, 23, 27, 29, 37, 44, 48, 50, 54, 58, 60, 63, 65, 67, 68, 70, 77, 78, 87, 89, 90, 100, 107, 109, 112, 116, 118, 119, 120, 122, 124, 128, 129, 133, 138, 139, 142, 143, 144, 146, 152, 156, 160, 161, 164, 166, 179, 180, 183, 184, 185, 187, 191, 193], "Its": [31, 37, 59, 110, 187, 192], "NO": [146, 167, 168, 169, 171, 172, 179], "NOT": [68, 109], "No": [47, 101, 118, 128, 139, 142, 186, 188], "Not": [48, 59, 71, 76, 104, 113, 173, 188], "OF": 57, "ON": 71, "OR": [22, 89, 160, 183, 187], "ORed": 89, "Of": [60, 109, 111, 113, 183], "On": [19, 88, 104, 108, 110, 118, 119, 135, 136, 149, 170, 171, 172, 187, 189], "One": [0, 10, 29, 68, 70, 99, 101, 105, 124, 128, 141, 142, 144, 147, 160, 166], "Or": 67, "Such": [11, 21, 58, 131, 185], "That": [60, 76, 85, 87, 89, 144, 150, 187], "The": [1, 2, 3, 4, 5, 6, 8, 11, 12, 14, 16, 17, 18, 19, 21, 25, 26, 27, 29, 31, 33, 34, 35, 36, 38, 39, 40, 41, 43, 44, 45, 46, 49, 50, 52, 54, 55, 57, 58, 59, 60, 61, 65, 67, 68, 69, 71, 74, 75, 76, 77, 80, 82, 83, 85, 87, 88, 89, 90, 92, 93, 96, 99, 104, 106, 107, 109, 110, 111, 112, 113, 114, 116, 117, 118, 119, 121, 122, 123, 124, 125, 128, 129, 131, 133, 134, 137, 138, 139, 141, 142, 143, 144, 145, 146, 147, 148, 150, 152, 153, 154, 156, 159, 160, 161, 162, 164, 165, 173, 174, 179, 180, 184, 185, 188, 189, 193, 194, 195, 196, 197, 198], "Their": [104, 166], "Then": [0, 24, 29, 31, 60, 67, 71, 76, 87, 89, 119, 144, 146, 151, 184, 185, 187], "There": [4, 5, 11, 23, 25, 31, 38, 47, 59, 62, 65, 67, 71, 72, 87, 89, 92, 95, 98, 109, 110, 111, 119, 122, 126, 127, 128, 129, 130, 131, 133, 135, 136, 141, 142, 143, 144, 145, 146, 147, 149, 152, 160, 166, 179, 180, 183, 184, 185, 187, 192, 195], "These": [0, 17, 47, 48, 58, 60, 67, 68, 76, 83, 87, 89, 104, 113, 119, 122, 129, 131, 144, 166, 179, 183, 184, 186, 187, 191, 196], "To": [11, 12, 17, 18, 19, 21, 29, 31, 34, 60, 67, 68, 71, 80, 88, 89, 104, 109, 111, 118, 129, 130, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 185, 187, 189], "WITH": [55, 56, 57], "Will": 31, "With": [6, 19, 31, 58, 87, 144, 160, 185], "_conf": 184, "_const": 184, "_data": [47, 123, 144], "_det": 107, "_dst_rdy": [47, 183, 187], "_eop": 47, "_eop_po": 47, "_hdr": 123, "_help_": 179, "_meta": 144, "_n": 47, "_range_max_numb": 148, "_rx": 144, "_sop": 47, "_sop_po": 47, "_src_rdy": 47, "_tx": 144, "a0": 87, "a1": [87, 110], "a2": [87, 110], "a3": 87, "a5": 87, "ab": 13, "abcdef0123456789": 184, "abid": 110, "abil": [18, 76, 80, 107, 187], "abl": [18, 19, 23, 24, 56, 80, 87, 104, 109, 111, 118, 144, 164], "abnorm": 89, "about": [11, 17, 23, 24, 25, 35, 41, 77, 78, 79, 80, 89, 109, 113, 129, 144, 166, 183, 184, 185, 187, 189, 192], "abov": [3, 17, 47, 60, 67, 68, 76, 89, 104, 119, 121, 125, 128, 137, 138, 142, 143, 147, 166, 167, 168, 169, 184, 187, 193], "abrevi": 184, "abstract": [16, 144], "academi": 188, "acc": 44, "acceler": [155, 159, 193], "accept": [4, 17, 23, 33, 36, 40, 45, 47, 60, 76, 83, 87, 89, 102, 104, 146, 147], "access": [0, 11, 18, 23, 26, 27, 31, 37, 39, 44, 45, 46, 49, 67, 87, 88, 109, 111, 112, 121, 144, 159, 163, 164, 184, 185, 190, 191, 193], "accident": 185, "accord": [0, 4, 14, 16, 35, 40, 41, 42, 58, 59, 60, 67, 70, 71, 75, 76, 82, 83, 87, 89, 90, 104, 107, 109, 110, 111, 144, 164, 173, 180, 184, 185, 187, 192], "accordingli": [67, 89, 110, 129], "account": [19, 58, 185], "accross": [118, 119], "accumul": [18, 19, 59, 60, 65, 67, 71, 98, 129, 130], "accumult": 18, "accur": [121, 193, 196], "achiev": [3, 17, 96, 144, 184, 187], "ack": 183, "aclk": 20, "acm": 13, "across": [18, 58, 184], "act": [23, 27, 89, 146, 191], "action": [35, 68], "activ": [1, 11, 31, 44, 62, 80, 87, 95, 96, 109, 111, 119, 121, 125, 128, 129, 133, 135, 136, 137, 138, 139, 142, 143, 144, 147, 149, 150, 151, 183, 187, 192], "activity_rx": 180, "activity_tx": 180, "actual": [5, 6, 11, 17, 18, 37, 39, 44, 60, 67, 89, 109, 111, 121, 144, 146, 147, 183, 187], "actuali": 68, "acumul": [126, 127], "ad": [10, 27, 31, 46, 50, 60, 67, 109, 110, 120, 144, 159, 166, 188], "adapt": [187, 192], "adapter_error": 109, "adapter_link_up": 109, "adc": 164, "adc_sensor": 164, "add": [8, 10, 11, 21, 25, 27, 38, 47, 68, 121, 129, 144, 146, 152, 160, 174, 183, 184, 187], "add_callback": 150, "add_sequ": [128, 139, 142, 143, 144], "adder": 160, "addit": [8, 46, 47, 82, 159, 160, 161, 166, 185, 187, 192], "addition": [31, 106, 187], "additionali": 59, "addr": [31, 32, 34, 39, 42, 87, 88, 111, 144, 146, 152, 185], "addr_bas": 34, "addr_channel": 34, "addr_data_bas": 35, "addr_data_channel": 35, "addr_data_mask": 35, "addr_data_sw_point": 35, "addr_header_bas": 35, "addr_header_channel": 35, "addr_header_mask": 35, "addr_header_sw_point": 35, "addr_mask": [34, 84, 89], "addr_sw_point": 34, "addr_vld": 34, "addr_width": [34, 35, 82, 83, 84, 85, 86, 87, 89, 144, 146], "addra": 15, "addrb": 15, "address": [0, 11, 13, 14, 16, 17, 18, 19, 22, 23, 29, 30, 31, 32, 35, 37, 39, 41, 42, 43, 45, 48, 49, 61, 71, 75, 76, 80, 82, 83, 84, 87, 88, 90, 106, 109, 111, 116, 117, 121, 122, 144, 146, 148, 161, 164, 180, 183, 185, 187, 192, 195], "address_width": 122, "adher": [110, 144, 184], "adjac": 187, "adjust": [8, 58, 67, 75, 144, 184], "adn": 31, "adress": [26, 45, 83], "advanc": [89, 124, 145, 161], "advantag": [12, 17, 89, 144], "advis": 7, "aempti": [5, 6, 105], "affect": [4, 17, 37, 39, 46, 64, 65, 67, 184], "after": [3, 17, 18, 19, 23, 26, 27, 31, 32, 33, 34, 42, 44, 45, 52, 57, 58, 59, 60, 63, 67, 68, 71, 75, 83, 85, 87, 89, 93, 109, 110, 118, 130, 131, 144, 145, 150, 164, 166, 170, 171, 172, 173, 179, 185, 187, 189, 195], "after_on": 160, "afterward": 18, "aful": [5, 6, 105], "afull_offset": 81, "again": [0, 58, 63, 67, 87, 118, 183, 195], "agent": [126, 127, 128, 129, 130, 132, 133, 139, 140, 141, 142, 143, 200], "agent_rx": 144, "agent_rx_data": 123, "agent_rx_hdr": 123, "agent_tx": 144, "agent_tx_data": 123, "agent_tx_hdr": 123, "agfb014r24a2e2v": 177, "agfb014r24b2e2v": 170, "agi": [159, 179], "agi027r": [172, 180], "agib027r29a1e2vr0": [172, 174], "agib027r29a1e2vr3": 174, "agilex": [3, 4, 5, 13, 14, 16, 23, 24, 31, 34, 35, 46, 50, 52, 54, 58, 59, 60, 65, 67, 70, 71, 74, 81, 83, 84, 93, 96, 98, 100, 101, 102, 106, 109, 111, 116, 117, 156, 159, 161, 166, 187, 188, 190], "agreg": 164, "aim": 87, "algorithm": [19, 74, 75, 90, 131, 144, 164], "alhough": 110, "alias": 78, "alig": 94, "align": [19, 23, 33, 36, 38, 47, 59, 60, 68, 76, 88, 94, 100, 104, 107, 110, 117, 144, 164], "all": [0, 6, 11, 17, 18, 19, 21, 22, 25, 27, 29, 31, 32, 40, 41, 42, 43, 44, 45, 47, 48, 49, 57, 58, 60, 61, 64, 67, 68, 69, 71, 75, 76, 80, 87, 88, 89, 90, 91, 93, 98, 104, 107, 109, 111, 112, 113, 118, 119, 120, 122, 123, 125, 126, 127, 128, 129, 130, 131, 135, 136, 137, 138, 139, 142, 144, 146, 147, 149, 150, 151, 152, 159, 160, 166, 179, 180, 183, 184, 185, 187, 188, 189, 192, 194], "alloc": [183, 192], "allow": [3, 4, 6, 11, 14, 16, 17, 18, 19, 20, 21, 35, 37, 39, 42, 44, 46, 48, 49, 50, 52, 56, 58, 67, 68, 76, 77, 82, 92, 94, 104, 106, 107, 109, 110, 111, 116, 118, 129, 135, 136, 144, 154, 156, 160, 161, 174, 179, 180, 183, 184, 186, 187, 189, 191, 192, 193], "allow_single_fifo": 6, "allwai": [62, 68, 108], "almost": [5, 6, 19, 65, 71, 81, 156, 164, 195], "almost_empti": [79, 105], "almost_empty_offset": [4, 5, 6, 77, 79, 105], "almost_ful": [79, 105], "almost_full_offset": [4, 5, 6, 77, 79, 105], "alon": 11, "along": [8, 59, 60, 87, 109, 173, 187], "alow": 31, "alreadi": [19, 27, 42, 58, 110, 119, 166, 184, 185, 189], "also": [0, 3, 4, 6, 7, 8, 11, 13, 16, 19, 24, 25, 27, 31, 35, 36, 37, 47, 58, 59, 60, 67, 68, 75, 78, 82, 85, 87, 89, 104, 107, 109, 110, 118, 119, 126, 127, 128, 129, 130, 131, 139, 142, 144, 147, 148, 159, 160, 161, 166, 170, 171, 172, 176, 179, 183, 184, 185, 186, 187, 191, 192, 193, 195, 198], "altera": [4, 86, 166], "altera_syncram": 161, "altern": [27, 161], "although": [67, 76, 166, 167, 168, 169], "altogeth": [76, 187], "alu": 160, "alveo": 159, "alwai": [17, 23, 33, 36, 38, 67, 87, 88, 89, 104, 109, 110, 144, 146, 187, 188, 189, 191, 192], "am": 107, "am_in": 107, "amd": [46, 135, 136, 149, 159, 188], "american": 87, "amm": [29, 30, 31, 32, 183], "amm_addr": 31, "amm_addr_width": 31, "amm_address": 31, "amm_burst_count": 31, "amm_burst_count_width": 31, "amm_clk": 31, "amm_data_width": [29, 31], "amm_freq_khz": [24, 31, 183], "amm_gen": [31, 32], "amm_mux": 31, "amm_prob": 31, "amm_probe_en": 31, "amm_read": 31, "amm_read_data": 31, "amm_read_data_valid": 31, "amm_readi": 31, "amm_rst": 31, "amm_writ": 31, "amm_write_data": 31, "among": [183, 187, 191, 195], "amount": [6, 7, 13, 14, 19, 38, 49, 60, 63, 65, 67, 76, 91, 102, 104, 129, 130, 149, 161], "an": [0, 5, 6, 7, 11, 18, 19, 22, 26, 27, 39, 42, 45, 46, 48, 49, 50, 58, 61, 63, 67, 68, 70, 71, 76, 80, 82, 87, 89, 106, 107, 110, 112, 116, 119, 122, 129, 131, 134, 135, 136, 138, 139, 144, 146, 148, 150, 152, 154, 159, 160, 161, 164, 166, 170, 171, 172, 173, 174, 179, 183, 184, 186, 187, 190, 191, 192, 194, 195, 196], "analysi": [125, 126, 127, 130, 131, 135, 136, 137, 138, 141, 147, 149, 179], "analysis_expoert": 131, "analysis_export": [128, 131, 139, 142, 143, 144], "analysis_export_data": 144, "analysis_export_meta": 144, "analysis_export_rx": 144, "analysis_export_rx_packet": 144, "analysis_export_tx": 144, "analysis_export_tx_packet": 144, "analysis_imp": 144, "analysis_imp_dut": [131, 144], "analysis_imp_model": [131, 144], "analysis_imp_reset": 144, "analysis_imp_rx": 144, "analysis_imp_tx": 144, "analysis_port": 144, "analyz": [27, 60, 93, 109], "ancestor": 166, "anew": 93, "ani": [0, 5, 10, 11, 17, 19, 21, 25, 52, 55, 56, 57, 58, 64, 66, 67, 68, 76, 77, 79, 85, 87, 88, 89, 91, 104, 109, 128, 129, 139, 142, 143, 144, 148, 151, 166, 185, 189, 195], "anlysis_export": 144, "annot": 144, "announc": 112, "anot": 44, "anoth": [18, 19, 21, 31, 60, 68, 71, 76, 80, 87, 89, 110, 121, 131, 139, 142, 144, 152, 161, 164, 166, 184, 185, 194], "another_lib": 166, "anotherlib": 166, "answer": 87, "anyhow": 87, "anyth": [21, 65, 67, 89, 131, 179], "anywher": [67, 166], "ap": 173, "apertur": [116, 117], "api": [183, 188, 191], "app": [0, 27, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 180, 183, 185, 189, 190, 191, 195], "app_archgrp": 184, "app_clk": 183, "app_conf": [27, 189], "app_cor": [0, 185], "app_core_minimal_0": [0, 185], "app_core_minimal_1": [0, 185], "app_reset": 183, "app_root_directori": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176], "appart": [19, 68, 119], "appear": [9, 68, 76, 80, 110], "append": [129, 166], "appli": [3, 20, 35, 47, 58, 60, 61, 65, 67, 68, 104, 109, 110, 179], "applianc": 193, "applic": [27, 67, 104, 113, 166, 167, 169, 173, 185, 186, 190, 191, 193, 195, 196], "application_cor": [183, 184], "application_core_entity_onli": 184, "approach": [13, 67, 87, 144, 166], "appropri": [33, 65, 71, 75, 112, 152, 166, 183, 187, 192], "approx": [4, 77], "approxim": 174, "aproxim": 19, "ar": [0, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 16, 17, 18, 19, 21, 22, 23, 24, 26, 27, 29, 33, 34, 35, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 52, 55, 57, 58, 59, 60, 62, 63, 64, 65, 67, 68, 71, 72, 74, 75, 76, 82, 83, 85, 87, 89, 90, 93, 95, 98, 100, 101, 104, 107, 109, 110, 111, 112, 113, 115, 117, 118, 119, 121, 122, 123, 128, 129, 130, 131, 133, 135, 136, 139, 142, 143, 144, 146, 147, 148, 149, 150, 152, 153, 154, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 174, 175, 176, 177, 179, 180, 183, 184, 185, 186, 187, 190, 191, 192, 194, 195, 196, 197, 198], "arbirarili": 20, "arbitr": 164, "arbitrari": [12, 16, 17, 20, 37, 58, 63, 68, 75, 87, 104, 110, 144, 164], "arbitrarili": 87, "arch": 144, "archgrp": [166, 184], "archgrp_arr": 184, "architectur": [5, 6, 11, 14, 49, 62, 79, 101, 105, 118, 144, 156, 159, 161, 166, 180, 184, 186, 187, 189, 190, 192], "archiv": [10, 166], "ardi": [83, 87, 146], "area": [34, 46], "aren": [89, 166], "argument": [23, 31, 32, 144, 148], "arith": 144, "around": [14, 24, 59, 68, 88, 89, 118, 119], "arrai": [21, 59, 73, 118, 128, 132, 139, 142, 144, 147, 152, 160, 161, 184], "arrang": [59, 104, 121], "array_size_set": [125, 137, 138], "arria": 161, "arria10": [4, 5, 14, 16, 79, 101, 105], "arriv": [17, 21, 58, 59, 80, 109, 110, 126, 127, 164], "arrow": 67, "art": 159, "asap": 101, "asfifo": [111, 119, 156, 162], "asfifo_bram": 156, "asfifo_bram_block": 156, "asfifo_bram_datamux": 156, "asfifo_bram_releas": 156, "asfifo_bram_xilinx": 156, "asfifox": [156, 162], "asic": 144, "asid": 11, "assembl": [59, 144], "assembli": 59, "assert": [7, 12, 29, 31, 60, 70, 71, 75, 76, 83, 87, 91, 104, 107, 109, 111, 126, 127, 134, 135, 136, 144, 146, 147, 152], "assign": [17, 19, 89, 109, 118, 119, 147, 164, 179, 183, 184], "associ": [62, 69, 89, 113, 144, 184, 188, 192], "assum": [144, 192], "asx4": 191, "async": [107, 163], "async_bus_handshak": [1, 166], "async_gener": 1, "async_mask": 20, "async_open_loop": 1, "async_open_loop_smd": 1, "async_reset": [1, 164], "asynch": 48, "asynchron": [2, 4, 11, 61, 80, 82, 151, 179], "atom": [17, 109], "attach": [149, 173], "attempt": [6, 67], "attent": 67, "attribut": 68, "author": [185, 189], "auto": [5, 6, 10, 31, 79, 101, 105, 106, 118, 183], "autogener": 122, "autom": 31, "automat": [5, 6, 10, 18, 29, 58, 67, 71, 144, 156, 161, 166, 186, 190, 192], "automaticli": 78, "auxiliari": [41, 58, 59, 67, 113, 116, 159, 162, 186], "avail": [0, 4, 10, 19, 23, 25, 31, 42, 49, 58, 67, 71, 80, 90, 107, 109, 111, 118, 119, 121, 144, 166, 173, 183, 187, 189, 191, 192, 193, 195, 196], "avalon": [0, 23, 31, 83, 122, 159, 183, 187, 190, 192], "averag": [17, 19, 24, 25, 30, 45, 75], "avg": [0, 31, 75], "avmm": [83, 132, 183, 187], "avmm_address": 83, "avmm_byteen": 83, "avmm_read": 83, "avmm_readdata": 83, "avmm_readdatavalid": 83, "avmm_waitrequest": 83, "avmm_writ": 83, "avmm_writedata": 83, "avoid": [11, 19, 23, 58, 67, 71, 85, 183, 184, 187], "avst": [109, 111, 132, 187], "await": [17, 93], "awar": [67, 166], "axi": [84, 113, 117, 119, 132, 139, 159, 183, 192], "axi4": [84, 159, 190], "axi_araddr": 84, "axi_arburst": 84, "axi_arid": 84, "axi_arlen": 84, "axi_arprot": 84, "axi_arreadi": 84, "axi_ars": 84, "axi_arvalid": 84, "axi_awaddr": 84, "axi_awburst": 84, "axi_awid": 84, "axi_awlen": 84, "axi_awprot": 84, "axi_awreadi": 84, "axi_aws": 84, "axi_awvalid": 84, "axi_bid": 84, "axi_breadi": 84, "axi_bresp": 84, "axi_bvalid": 84, "axi_ccuser_width": 113, "axi_cquser_width": 113, "axi_data_width": [84, 113], "axi_if": 139, "axi_lite_interfac": 144, "axi_rdata": 84, "axi_rid": 84, "axi_rlast": 84, "axi_rreadi": 84, "axi_rresp": 84, "axi_rvalid": 84, "axi_rx_spe": 139, "axi_wdata": 84, "axi_wreadi": 84, "axi_wstrb": 84, "axi_wvalid": 84, "b": [17, 21, 31, 39, 45, 47, 60, 87, 110, 131, 144, 150, 188], "b0": [87, 144, 150, 151, 152], "b1": [144, 151, 152], "b_array_t": [25, 89], "bachelor": 1, "back": [19, 67, 71, 75, 80, 144, 147, 166, 184, 186, 187, 192, 195], "backbon": 188, "backpressur": [110, 187], "bandwidth": 47, "bar": [116, 117, 192], "bar0": [116, 185, 192], "bar0_base_addr": [116, 192], "bar1": 116, "bar1_base_addr": [116, 192], "bar2": [116, 192], "bar2_base_addr": [116, 192], "bar3": 116, "bar3_base_addr": [116, 192], "bar4": [116, 192], "bar4_base_addr": [116, 192], "bar5": 116, "bar5_base_addr": [116, 192], "bar_apertur": 117, "bar_id": 117, "bar_shift_lat": 8, "bare": 166, "barrel": [43, 59, 160], "barrel_shift": 160, "barrel_shifter_dsp": 160, "barrel_shifter_gen": [8, 110], "barrel_shifter_gen_pip": 8, "barrier": 144, "base": [0, 2, 5, 17, 25, 26, 29, 30, 31, 34, 37, 39, 45, 59, 60, 67, 69, 76, 78, 86, 88, 89, 99, 101, 107, 110, 112, 116, 117, 118, 119, 121, 122, 125, 128, 129, 137, 139, 142, 143, 144, 147, 148, 156, 160, 161, 164, 166, 184, 185, 187, 190, 192, 193], "base_address": 185, "baseh": 39, "basel": 39, "baselin": 152, "basi": 76, "basic": [25, 31, 32, 67, 71, 90, 110, 128, 135, 136, 138, 139, 141, 142, 143, 149, 159, 166, 167, 185, 187, 189, 190, 195], "bbuild": 27, "bcefst": 144, "bclk": 20, "bear": 17, "becaus": [11, 19, 20, 31, 33, 38, 58, 67, 68, 80, 87, 89, 110, 125, 137, 138, 144, 147, 166, 179, 184, 185, 187], "been": [11, 12, 17, 18, 19, 42, 55, 58, 62, 76, 104, 109, 110, 113, 118, 119, 128, 131, 139, 144, 146, 160, 166, 167, 168, 169, 185], "befor": [5, 9, 17, 18, 19, 22, 49, 58, 63, 67, 68, 71, 75, 76, 80, 85, 87, 89, 91, 101, 109, 111, 118, 119, 128, 131, 139, 142, 144, 146, 150, 166, 170, 180, 183, 184, 186, 187, 192], "before_on": 160, "begener": 49, "begin": [11, 33, 36, 38, 45, 50, 54, 59, 67, 76, 89, 110, 128, 129, 131, 142, 143, 144, 148, 150, 151, 166], "beginbursttransf": 83, "beginig": 68, "behav": [7, 12, 43, 45, 58, 128, 139, 142, 143, 144, 147, 166], "behavior": [11, 12, 44, 82, 87, 90, 110, 120, 141, 144, 147, 156, 160, 161, 164, 187], "behaviour": [13, 58, 101, 147], "behind": [60, 71, 87, 183], "beign": [131, 151], "being": [12, 27, 58, 59, 67, 68, 71, 76, 87, 88, 104, 109, 111, 128, 142, 166], "bellow": [108, 171, 172], "belong": [76, 89, 184, 187], "below": [0, 19, 22, 27, 60, 67, 71, 87, 89, 104, 113, 118, 128, 129, 131, 139, 142, 143, 144, 147, 149, 159, 166, 167, 168, 169, 174, 183, 184, 186, 187, 189, 191, 192, 195, 196], "bene\u0161": 59, "ber": 107, "ber_mon": 107, "besid": [48, 61], "best": [46, 59, 90, 166], "better": [4, 14, 16, 17, 22, 31, 64, 71, 77, 86, 87, 90, 96, 100, 110, 131, 133, 144, 166], "between": [0, 11, 17, 18, 19, 23, 24, 27, 28, 29, 31, 47, 48, 54, 59, 60, 65, 67, 68, 71, 75, 76, 77, 82, 83, 89, 96, 102, 104, 107, 118, 119, 125, 128, 129, 131, 137, 138, 139, 142, 143, 144, 146, 149, 160, 164, 166, 180, 187, 191, 193, 195], "bidirect": 144, "bifurac": 192, "bifurc": 192, "big": [98, 160], "bigger": [68, 104], "bin": [27, 89, 144], "bin2hot": 160, "binari": [18, 59, 76, 89, 160, 166, 185], "bind": [112, 132], "bip": 107, "bit": [0, 1, 3, 4, 5, 6, 7, 8, 11, 12, 14, 16, 17, 18, 20, 21, 22, 23, 25, 27, 29, 30, 31, 32, 35, 39, 45, 46, 47, 48, 49, 50, 54, 55, 59, 60, 61, 62, 63, 65, 67, 68, 69, 70, 71, 74, 75, 76, 82, 83, 84, 85, 87, 88, 90, 92, 94, 95, 96, 98, 100, 104, 107, 109, 111, 112, 113, 116, 117, 120, 121, 122, 135, 136, 144, 147, 149, 150, 151, 160, 164, 183, 187, 189, 191, 192, 195, 196], "bitrat": 107, "bitstream": [167, 168, 169, 170, 171, 172, 173, 189], "bittwar": 159, "bitwis": 160, "black": 195, "blaster": 173, "blob": [112, 185], "block": [0, 3, 8, 14, 16, 26, 27, 36, 38, 39, 43, 45, 46, 48, 49, 50, 54, 59, 61, 62, 63, 67, 68, 69, 70, 73, 74, 76, 101, 107, 109, 110, 111, 113, 116, 130, 138, 144, 147, 149, 156, 160, 183, 184, 186, 187, 192, 193], "block_aux_en": 73, "block_en": [14, 16], "block_lock": [107, 149], "block_siz": [8, 34, 36, 48, 49, 52, 55, 56, 57, 58, 61, 63, 66, 68, 70, 72, 73, 76, 79, 128, 142, 143, 144, 145, 180], "block_width": [8, 14, 16], "blok": 3, "blokov\u00fd": 5, "board": [173, 180, 183, 189, 193], "board_rev": [174, 189], "bock_width": 14, "bodfc": 109, "bodfch": 109, "bodfcl": 109, "bodi": [131, 144], "boolean": [3, 4, 5, 6, 7, 8, 10, 14, 16, 18, 24, 26, 31, 38, 39, 46, 48, 49, 57, 58, 61, 62, 63, 64, 66, 69, 71, 73, 74, 75, 77, 78, 82, 86, 89, 90, 91, 92, 94, 95, 96, 98, 101, 102, 105, 106, 109, 111, 113, 114, 116, 121, 180, 192], "boot": [71, 167, 168, 169, 174, 175, 176, 177, 185, 189, 191], "boot_en": 185, "border": 67, "bot": [68, 151], "both": [3, 4, 5, 11, 12, 17, 19, 24, 26, 43, 46, 48, 61, 67, 68, 76, 80, 82, 83, 87, 88, 89, 94, 101, 104, 107, 110, 117, 119, 120, 128, 139, 141, 142, 143, 144, 146, 147, 179, 183, 184, 187, 188], "bottleneck": 19, "bottom": [60, 174], "bound": [150, 185], "boundari": [107, 125, 137, 138], "box": [25, 26], "box_cnt": 26, "box_width": 26, "bp": 67, "brake": 180, "bram": [4, 5, 13, 26, 43, 59, 77, 79, 80, 82, 101, 105, 106, 156, 159, 161, 166, 185], "branch": 27, "brand": 58, "break": [17, 91, 102, 122, 124, 144, 145], "bridg": [23, 31], "brief": 152, "brnolog": [159, 186], "broadcast": [22, 183, 187], "brodcast": 109, "broken": [27, 116], "bs_calc": 59, "bscn": 67, "bt": 174, "bu": [0, 12, 17, 18, 23, 24, 25, 36, 37, 38, 39, 40, 43, 44, 45, 46, 54, 55, 61, 62, 66, 68, 69, 73, 76, 82, 83, 88, 89, 90, 91, 99, 100, 104, 106, 107, 109, 111, 113, 116, 117, 119, 121, 129, 132, 157, 158, 162, 163, 164, 165, 183, 185, 186, 187, 190, 192, 193, 195], "buf_a_col": 17, "buf_a_sect": 17, "buf_a_stream_row": 17, "buf_b_col": 17, "buf_b_row": 17, "buf_b_sect": 17, "buf_block": 78, "buf_byt": 78, "buf_word": 78, "buff": [29, 31, 32], "buff_rd_addr": 42, "buff_rd_chan": 42, "buff_rd_data": 42, "buff_rd_data_vld": 42, "buff_rd_en": 42, "buffer": [7, 17, 19, 29, 31, 32, 33, 34, 35, 39, 41, 42, 44, 45, 46, 54, 65, 71, 75, 80, 98, 102, 107, 109, 110, 111, 162, 164, 183, 187, 192], "buffer_ae_offset": 71, "buffer_af_offset": 71, "buffer_s": 71, "buffered_data_s": 38, "bug": [59, 144, 185], "build": [0, 27, 67, 107, 144, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 187, 193, 195], "build_phas": [128, 131, 139, 142, 143, 144, 150], "built": [27, 92, 184, 189], "buld": [167, 168, 169], "bundl": 166, "burst": [0, 29, 30, 31, 49, 83, 141, 143, 144, 146, 183], "burst_cnt": [29, 32], "burst_id": 32, "burst_siz": 49, "burst_width": 122, "burstcount": [83, 122], "bus_handshak": 166, "buse": [0, 1, 86, 104, 159, 183, 186, 187, 192], "busi": [67, 85], "buss": 47, "bypass": [14, 71, 74], "byte": [18, 19, 22, 33, 34, 35, 37, 38, 39, 40, 41, 43, 44, 45, 46, 47, 48, 49, 50, 54, 59, 60, 67, 74, 82, 83, 87, 88, 90, 109, 111, 112, 113, 116, 117, 121, 128, 132, 135, 136, 137, 138, 139, 142, 143, 146, 148, 149, 152, 161, 180, 183, 187, 192, 195, 198], "byte_aray_mfb": 144, "byte_arra_mfb": 128, "byte_arrai": [128, 129, 144, 151], "byte_array_ag": 144, "byte_array_cfg": 144, "byte_array_mfb": [125, 132, 144, 145], "byte_array_mfb_cfg": 144, "byte_array_mfb_env": 128, "byte_array_mfb_monitor": 144, "byte_array_mfb_sequ": 144, "byte_array_moinitor": 144, "byte_array_port_env": 144, "bytes_max_numb": 148, "bytes_min_numb": 148, "bytes_per_packet_max_numb": 148, "bytes_per_packet_min_numb": 148, "bytes_per_packet_rev_max_numb": 148, "bytes_per_packet_rev_min_numb": 148, "bytes_rev_max_numb": 148, "bytes_rev_min_numb": 148, "bytes_vld": [126, 127, 135, 136], "bytesh": [39, 45], "bytesl": [39, 45], "c": [10, 31, 39, 45, 87, 144], "c_char_width": 144, "c_data": 150, "c_transact": 144, "ca": 19, "cabal": 1, "cabl": [27, 167, 168, 169, 170, 171, 172, 173], "cage": 194, "calcul": [4, 19, 24, 25, 41, 45, 59, 67, 71, 75, 76, 90, 104, 109, 111, 114, 118, 131, 144, 147, 160, 162, 164, 166, 183, 195], "calibr": [31, 183], "call": [24, 71, 76, 104, 142, 143, 144, 150, 159, 166, 170, 171, 172, 183, 184, 185, 187], "callback": [132, 166], "calucul": 74, "calypt": [37, 44, 159, 186, 188, 198], "cam": [109, 161], "came": [11, 42], "can": [0, 1, 3, 4, 5, 6, 7, 8, 10, 11, 12, 14, 17, 18, 19, 20, 21, 24, 25, 26, 27, 28, 29, 31, 32, 35, 36, 40, 41, 43, 45, 46, 50, 54, 57, 58, 59, 60, 63, 65, 67, 68, 71, 74, 75, 76, 77, 80, 82, 85, 86, 87, 88, 89, 90, 91, 94, 95, 96, 98, 101, 102, 104, 106, 107, 109, 110, 111, 118, 119, 120, 122, 123, 125, 128, 129, 131, 137, 138, 139, 142, 143, 144, 146, 148, 150, 151, 152, 156, 159, 160, 164, 166, 167, 168, 169, 170, 174, 179, 183, 185, 186, 187, 189, 191, 192, 193, 194, 195, 196], "candid": [156, 161, 164], "cannot": [6, 11, 19, 58, 68, 80, 108, 111, 119, 129, 144, 146, 151, 160, 185], "capabl": [5, 27, 61, 112, 122, 174, 185, 192], "capac": [23, 98], "cappabl": 68, "capture_en": 18, "capture_fifo_item": 18, "card": [0, 22, 27, 31, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 183, 187, 190, 191, 192, 193, 195], "card_archgrp": 184, "card_conf": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176], "card_id": 192, "card_id_width": 192, "card_root_directori": 184, "care": [41, 75, 87, 110, 122, 129, 148], "careful": [124, 145], "carefulli": 102, "carri": [87, 89, 160, 183, 187], "carry_chain": 160, "case": [0, 3, 4, 6, 7, 11, 12, 19, 21, 35, 39, 45, 58, 59, 67, 68, 71, 76, 85, 87, 88, 89, 91, 93, 102, 104, 109, 110, 111, 117, 119, 129, 144, 148, 152, 166, 179, 183, 184, 185, 189, 190, 192, 195], "cass": 151, "cast": [131, 144, 150], "caus": [17, 21, 67, 68, 87, 109, 110, 111, 184], "caution": 89, "caveat": 166, "cb": 144, "cbs_simpl": 150, "cc": [113, 116, 117, 192], "cc_axi": 113, "cc_axi_data": 113, "cc_axi_keep": 113, "cc_axi_last": 113, "cc_axi_readi": 113, "cc_axi_us": 113, "cc_axi_valid": 113, "cc_mfb": 113, "cc_mfb_block_siz": 192, "cc_mfb_data": [113, 116], "cc_mfb_dst_rdy": [113, 116], "cc_mfb_eof": [113, 116], "cc_mfb_eof_po": [113, 116], "cc_mfb_item_width": 192, "cc_mfb_meta": 116, "cc_mfb_region": 192, "cc_mfb_region_s": 192, "cc_mfb_sof": [113, 116], "cc_mfb_sof_po": [113, 116], "cc_mfb_src_rdy": [113, 116], "cc_pipe": 116, "cc_user_width": 113, "cd": [0, 24, 25, 27, 31, 174], "cdc": 20, "cdgmii": [109, 111], "ce_gener": 132, "ceil": [35, 67], "cell": 185, "certain": [18, 58, 89, 164, 185], "cesnet": [0, 27, 174, 184, 185, 188], "cfc": 109, "cfch": 109, "cfcl": 109, "cfg": [125, 128, 137, 138, 139, 142, 143, 144], "cgmii": 109, "ch": 179, "ch_cnt": 90, "ch_diff": 90, "ch_max": [49, 90], "ch_min": [49, 90], "ch_next": 90, "ch_out": 90, "chain": [27, 89, 160], "chan": [0, 90], "chang": [14, 17, 18, 29, 49, 58, 64, 67, 68, 72, 87, 88, 89, 90, 109, 110, 111, 113, 116, 119, 128, 130, 131, 139, 142, 143, 144, 148, 150, 151, 152, 179, 184, 185, 188, 189], "channel": [0, 9, 22, 34, 35, 37, 39, 41, 42, 43, 44, 45, 46, 48, 49, 59, 65, 71, 76, 78, 87, 104, 129, 131, 144, 156, 160, 165, 179, 180, 183, 184, 186, 187, 189, 195], "channel_align": 132, "channel_cor": 44, "channel_id": 187, "channel_vld": 34, "channels_width": 49, "chapter": [0, 2, 109, 111, 153, 154, 157, 158, 162, 163, 165, 183, 184, 185, 186, 189, 194, 195, 197, 198], "charact": 144, "characterist": [62, 64, 68, 69], "check": [5, 10, 19, 23, 27, 45, 58, 63, 68, 85, 87, 109, 111, 118, 119, 135, 136, 144, 146, 147, 150, 164, 179, 180, 181, 184, 187], "checker": 119, "checksum": [111, 162], "checksum_calcul": 74, "child": [128, 139, 142, 143], "chip": [23, 160, 183], "choic": [5, 152, 179], "choke": 183, "choos": [3, 5, 89, 128, 130, 139, 142, 143, 184], "chosen": [5, 41, 184], "chunk": [126, 127, 130, 152], "cicl": 151, "circuit": 12, "circumst": 67, "clariti": 184, "class": [45, 117, 123, 124, 125, 128, 129, 134, 137, 138, 139, 142, 143, 144, 145, 146, 150, 151, 160], "class_typ": 131, "classic": 5, "claus": 107, "clb": [156, 161], "clear": [12, 26, 48, 76, 87, 109, 111, 152, 160], "clear_by_read": 26, "clear_by_rst": 26, "client": [153, 154, 187], "clk": [3, 5, 6, 7, 8, 9, 10, 12, 13, 14, 17, 18, 24, 25, 26, 28, 30, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 79, 83, 84, 85, 86, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 110, 114, 116, 120, 121, 131, 144, 150, 151, 166, 179], "clk2": [17, 75, 160], "clk_": 82, "clk_arb": [17, 75], "clk_en": [3, 129], "clk_eth": [180, 183], "clk_freq": 121, "clk_frequenc": 71, "clk_gen": 164, "clk_in": 78, "clk_m": 82, "clk_meta": 78, "clk_out": 78, "clk_period": [144, 152, 166], "clk_port": 166, "clk_sel": 121, "clk_sel_width": 121, "clk_src": 121, "clk_stabl": 107, "clk_user": [180, 183], "clk_user_x2": 183, "clk_user_x3": 183, "clk_user_x4": 183, "clk_x2": 54, "clock": [1, 3, 4, 5, 6, 9, 10, 12, 13, 14, 16, 17, 18, 19, 20, 25, 26, 31, 34, 37, 44, 47, 48, 50, 54, 55, 56, 57, 58, 59, 60, 61, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 82, 83, 84, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 102, 104, 106, 107, 109, 111, 116, 119, 121, 124, 129, 130, 135, 136, 144, 145, 146, 147, 149, 150, 151, 159, 161, 162, 164, 165, 166, 179, 180, 183, 187, 192, 196], "clog2": [131, 145], "clone": [27, 144], "close": [18, 185, 186, 198], "closur": 12, "cmac": [109, 111, 167, 168, 169, 175, 176, 180, 187, 188], "cmake": 27, "cmd": [85, 109, 111], "cmp": 160, "cnt": [11, 25, 30, 31, 160], "cnt_dist": 160, "cnt_max": 63, "cnt_multi_memx": [9, 160], "cnt_next": 11, "cnt_width": 9, "cnter": 25, "cnter_cnt": 25, "cnter_diff_0": 25, "cnter_diff_1": 25, "cnter_diff_2": 25, "cnter_incr_0": 25, "cnter_incr_1": 25, "cnter_incr_2": 25, "cnter_submit_0": 25, "cnter_submit_1": 25, "cnter_submit_2": 25, "cnter_width": 25, "cnters_diff": 25, "cnters_incr": 25, "cnters_submit": 25, "cntr": 49, "cntrs_width": [39, 45], "cocotb": 195, "codapa": 119, "code": [0, 1, 5, 27, 89, 131, 160, 166, 184, 200], "code_archgrp": 184, "code_coverag": 144, "colid": 17, "collect": [107, 150, 159], "collis": [11, 17, 26, 165], "color": [17, 89], "color_conf_delai": 17, "color_timeout_width": 17, "column": [17, 89], "com": [27, 87], "combin": [11, 39, 45, 59, 87, 89, 95, 111, 120, 152, 183, 184], "combinatori": 12, "combo": 189, "combo_user_const": 184, "come": [11, 17, 40, 59, 75, 76, 87, 107, 110, 135, 136, 144, 187, 192, 195], "command": [0, 23, 25, 27, 32, 85, 107, 109, 111, 144, 150, 151, 152, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 189], "comment": [144, 184, 185], "commentari": 184, "common": [3, 16, 17, 24, 25, 31, 47, 58, 62, 69, 83, 85, 86, 89, 95, 107, 123, 132, 134, 159, 166, 184, 200], "common_clock": 16, "commonli": [87, 131, 132, 133, 144, 150, 152, 166], "commun": [27, 30, 76, 104, 116, 119, 122, 123, 124, 133, 134, 135, 136, 144, 145, 146, 183, 185, 186, 190, 191, 192, 193, 198], "comp": [0, 2, 27, 31, 32, 86, 135, 136, 144, 153, 154, 157, 158, 162, 163, 165, 179, 195, 197, 198], "comp_": 166, "comp_with_data": 117, "compar": [11, 31, 44, 62, 89, 119, 125, 132, 135, 136, 137, 138, 144, 149, 160, 192], "comparer_": 144, "comparer_base_ord": 131, "comparer_base_tag": [131, 144], "comparer_base_unord": 131, "comparer_data": 144, "comparer_meta": 144, "comparer_ord": [131, 144], "comparer_tag": 131, "comparer_unord": 131, "comparesr": 144, "comparison": [3, 59, 131, 166], "compat": [11, 31, 32, 59, 66, 159, 164, 184, 185, 189], "compens": 107, "compil": [144, 166, 184, 185, 186, 192], "complet": [11, 17, 22, 32, 45, 46, 57, 67, 76, 80, 113, 116, 117, 118, 144, 159, 166, 170, 171, 172, 173, 185, 187, 189, 192], "completit": [117, 192], "complex": [11, 19, 37, 39, 46, 67, 68, 118, 122, 135, 136, 166], "compli": 17, "complic": [11, 68, 88, 146], "compon": [2, 5, 6, 7, 10, 12, 17, 18, 19, 20, 23, 27, 29, 32, 33, 34, 35, 36, 38, 40, 41, 42, 43, 45, 48, 49, 50, 52, 54, 55, 56, 57, 59, 60, 61, 63, 65, 66, 67, 68, 70, 71, 72, 74, 75, 77, 78, 79, 82, 83, 84, 85, 87, 88, 90, 91, 92, 93, 94, 95, 96, 99, 100, 101, 102, 104, 106, 107, 109, 110, 111, 113, 114, 115, 116, 117, 120, 121, 122, 125, 129, 131, 133, 135, 136, 137, 138, 144, 149, 150, 151, 152, 154, 157, 158, 159, 160, 161, 162, 163, 164, 182, 183, 187, 188, 191, 195, 196, 197, 198, 200], "compos": [76, 121, 147, 166], "comprehens": 159, "compress": [112, 185], "comput": [0, 10, 60, 119], "comun": 151, "concaten": [60, 94, 184], "concern": [68, 166, 187], "concret": 31, "concurr": 18, "condit": [67, 100, 109, 110, 144, 184, 192], "condition": 184, "conduct": [76, 104], "conector": [167, 168, 169, 170, 171, 172, 174, 175, 176, 177], "conenct": 68, "config": [49, 128, 132, 139, 142, 143, 144, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 184], "config_filepath": 148, "config_gener": 148, "config_generator_config_filepath": 148, "config_item": [122, 128, 139, 142, 143], "config_sequ": [125, 128, 137, 138, 139, 142, 143, 144], "configr": 46, "configur": [0, 1, 18, 23, 25, 27, 31, 33, 37, 39, 44, 45, 48, 49, 55, 57, 58, 59, 68, 72, 73, 87, 88, 90, 104, 106, 107, 109, 110, 111, 112, 113, 116, 121, 122, 123, 124, 126, 127, 130, 132, 135, 136, 145, 149, 151, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 183, 185, 187, 188, 189, 196], "configuret": 151, "confirm": [6, 17, 21, 35, 164], "conform": 17, "connect": [0, 4, 5, 7, 11, 12, 17, 19, 20, 27, 29, 31, 37, 39, 45, 46, 47, 48, 58, 59, 68, 71, 83, 87, 88, 89, 91, 107, 109, 111, 112, 119, 125, 126, 127, 128, 130, 131, 135, 136, 137, 138, 139, 142, 143, 144, 146, 147, 149, 150, 151, 160, 164, 167, 168, 169, 170, 171, 172, 174, 183, 185, 186, 187, 189, 192, 193, 195], "connect_phas": [128, 131, 139, 142, 143, 144], "connector": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 192, 193], "consecut": [11, 18, 67, 76, 104, 110, 125, 137, 138], "consequ": 187, "consid": [17, 19, 48, 49, 76, 89, 102, 104, 144, 184, 185, 187, 195], "consist": [18, 27, 40, 60, 67, 68, 70, 75, 80, 89, 104, 110, 118, 119, 144, 185, 186, 193], "consol": 192, "constain": 89, "constant": [20, 46, 59, 60, 67, 76, 83, 89, 104, 109, 111, 148, 160, 185, 195], "constist": [43, 45], "constr_quartu": 166, "constr_text": 166, "constr_vivado": 166, "constrain": 184, "constraint": [1, 98, 130, 144, 166, 184, 187], "construct": 152, "consum": [60, 68, 101, 102], "consume_item_width": 101, "consumpt": [7, 11, 62, 89], "contain": [0, 11, 17, 18, 19, 25, 31, 36, 39, 44, 45, 48, 49, 58, 60, 62, 68, 69, 76, 78, 80, 82, 88, 89, 91, 98, 104, 106, 109, 111, 114, 117, 119, 121, 122, 123, 124, 125, 128, 129, 131, 133, 134, 135, 136, 137, 138, 139, 141, 142, 143, 144, 146, 149, 151, 152, 156, 157, 158, 160, 162, 163, 165, 166, 174, 183, 184, 185, 186, 187, 190, 192, 193, 195, 196, 200], "containst": 145, "containt": [147, 151], "content": [26, 35, 38, 41, 59, 106, 109, 110, 111, 122, 147, 161, 185], "continu": [6, 18, 29, 45, 47, 80, 89, 110, 115, 151, 186, 195, 196], "contiuou": 115, "contol": 38, "contrast": 144, "control": [0, 6, 18, 20, 37, 44, 49, 59, 61, 67, 87, 90, 107, 109, 111, 121, 123, 124, 129, 144, 145, 149, 152, 159, 164, 180, 183, 185, 187, 189, 191, 193, 194, 195, 198], "conv_bscn2gb": 67, "conv_gbs2bscn": 67, "conv_ps2pscn": 67, "conv_pscn2p": 67, "convent": 76, "convers": [48, 67, 107, 111, 116, 121, 125, 137, 138, 198], "convert": [21, 23, 67, 83, 84, 88, 89, 100, 102, 109, 110, 111, 113, 118, 119, 120, 122, 128, 132, 133, 139, 141, 142, 143, 159, 160, 164, 170, 171, 172, 184, 187, 190, 192], "convert2block": 138, "convert2str": [125, 135, 136, 137, 138, 144, 147, 149, 152], "cooper": [144, 174], "copi": [54, 68, 125, 135, 136, 137, 138, 149, 152, 178, 189], "copr": [0, 27], "core": [0, 10, 11, 27, 39, 45, 46, 49, 107, 112, 118, 119, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 180, 183, 191, 193, 195], "core_archgrp": 184, "core_boostrap": 184, "core_func": 184, "core_root_directori": 184, "correct": [4, 5, 14, 16, 18, 35, 45, 82, 88, 109, 112, 113, 114, 116, 123, 144, 147, 150, 174, 180, 189, 192], "correctli": [58, 67, 88, 109, 129, 134, 144, 183, 185, 189], "correspond": [6, 17, 21, 27, 34, 60, 67, 71, 76, 107, 110, 118, 119, 147, 183, 184, 186, 187, 188, 194, 195], "correspons": 21, "cos521": 10, "cost": [19, 93, 98], "could": [11, 12, 17, 19, 20, 58, 59, 76, 89, 104, 144, 149, 179], "count": [0, 6, 18, 19, 24, 25, 29, 30, 31, 55, 67, 75, 91, 102, 109, 111, 160, 164, 183, 196, 198], "counter": [1, 11, 17, 25, 28, 30, 31, 35, 37, 39, 40, 42, 44, 45, 46, 49, 62, 65, 71, 96, 107, 109, 111, 152, 160, 164], "counton": 144, "coupl": [87, 180], "cours": [10, 18, 85], "cov_html": 144, "cov_packet": 144, "cover": [45, 58, 101, 180], "coverag": 5, "coverage_bas": 144, "covergroup": 144, "coverpoint": 144, "cpack": 27, "cpu": 183, "cq": [113, 116, 117, 192], "cq_axi": 113, "cq_axi_data": 113, "cq_axi_keep": 113, "cq_axi_last": 113, "cq_axi_readi": 113, "cq_axi_us": 113, "cq_axi_valid": 113, "cq_fbe": 113, "cq_lbe": 113, "cq_mfb": 113, "cq_mfb_block_siz": 192, "cq_mfb_data": [113, 116], "cq_mfb_dst_rdy": [113, 116], "cq_mfb_eof": [113, 116], "cq_mfb_eof_po": [113, 116], "cq_mfb_item_width": 192, "cq_mfb_meta": 116, "cq_mfb_region": 192, "cq_mfb_region_s": 192, "cq_mfb_sof": [113, 116], "cq_mfb_sof_po": [113, 116], "cq_mfb_src_rdy": [113, 116], "cq_pipe": 116, "cq_tph_present": 113, "cq_tph_st_tag": 113, "cq_tph_type": 113, "cq_user_width": 113, "cquser_width": 117, "cr": 107, "crash": 184, "crc": [22, 109, 111, 183, 187, 188, 195], "crc_check_en": 109, "crc_error": 109, "crc_insert_en": 111, "crc_is_receiv": 109, "crc_remove_en": 109, "crdt": 132, "creat": [17, 27, 34, 37, 48, 59, 60, 62, 68, 69, 76, 86, 104, 119, 125, 128, 129, 131, 135, 136, 137, 138, 139, 142, 143, 146, 147, 149, 150, 152, 160, 166, 173, 178, 183, 185, 187, 188, 189], "create_sequence_item": [128, 139, 142, 143, 146, 152], "creation": [104, 126, 127, 130, 139, 144], "creator": 60, "credit": [118, 123], "critic": 87, "cross": [1, 20, 29, 31, 61, 82, 144, 164], "crossbar": 17, "crossbarx": [21, 111, 162, 164], "crossbarx_stream": 75, "csr": [183, 187, 191, 193], "csv": 148, "ctl_bar_apertur": 116, "ctl_max_payload_s": 116, "ctrl": [25, 29, 30, 31, 109, 153, 164], "ctrl_reg": 121, "ctrli": 25, "ctrli_width": 25, "ctrlo": 25, "ctrlo_default": 25, "ctrlo_width": 25, "curent": 28, "current": [4, 6, 10, 14, 17, 19, 22, 27, 29, 31, 32, 33, 35, 39, 42, 45, 52, 57, 58, 59, 60, 62, 63, 65, 67, 68, 71, 76, 77, 78, 80, 83, 85, 87, 104, 109, 110, 111, 116, 118, 119, 129, 144, 146, 166, 185, 186, 187, 188, 190, 192], "current_tim": 65, "currently_stor": [4, 5, 6], "custom": [25, 146, 152, 184, 185], "customiz": 161, "cut": [55, 60, 109, 119, 126, 127, 130], "cutted_item": 55, "cutter": [41, 109, 119, 162], "cvg": 144, "cx": 75, "cx_clk_arb": 75, "cx_reset_arb": 75, "cx_use_clk2": 75, "cx_use_clk_arb": 75, "cycl": [1, 3, 5, 6, 10, 11, 13, 14, 17, 18, 19, 20, 25, 26, 30, 47, 49, 58, 59, 63, 67, 71, 76, 83, 87, 88, 90, 93, 104, 106, 110, 118, 119, 121, 124, 130, 135, 136, 144, 145, 146, 151, 156, 159, 160, 161, 162, 164, 165, 170, 171, 172], "cz": 184, "czech": 188, "d": [31, 32, 47, 87, 173, 179], "d0": [87, 152], "d1": 87, "d12": 152, "d16": 152, "d2": 87, "d3": 87, "d4": 152, "d512": 152, "d516": 152, "d8": [87, 152], "d9": 87, "damag": 45, "danger": 180, "data": [4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 19, 22, 24, 29, 30, 31, 32, 34, 35, 36, 38, 39, 42, 43, 44, 45, 46, 47, 48, 49, 52, 54, 55, 58, 59, 60, 61, 62, 63, 65, 66, 67, 70, 71, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 87, 88, 89, 90, 92, 93, 94, 95, 96, 98, 101, 102, 104, 105, 107, 109, 111, 112, 113, 116, 117, 119, 121, 122, 124, 125, 128, 129, 130, 131, 133, 134, 135, 136, 137, 138, 139, 141, 142, 143, 144, 145, 146, 147, 149, 150, 151, 152, 154, 156, 159, 160, 161, 164, 180, 183, 186, 187, 188, 189, 192, 193, 194, 195], "data_block_s": 78, "data_block_width": 78, "data_buff": 132, "data_dir": 17, "data_in": [8, 10, 12], "data_in_rdi": 10, "data_in_vld": 10, "data_item": 144, "data_item_width": 78, "data_logg": [0, 24, 25, 31], "data_logger_i": 25, "data_mux_lat": 17, "data_mux_outreg_en": 17, "data_out": [8, 10], "data_out_rdi": 10, "data_out_vld": 10, "data_pcie_hdr": 35, "data_pcie_hdr_dst_rdi": 35, "data_pcie_hdr_s": 35, "data_pcie_hdr_src_rdi": 35, "data_pointer_width": [42, 44, 45], "data_rot_lat": 17, "data_rot_outreg_en": 17, "data_vld": 149, "data_width": [4, 5, 6, 7, 10, 12, 13, 14, 15, 16, 28, 47, 82, 83, 85, 86, 87, 89, 91, 95, 99, 122, 124, 135, 136, 139, 144, 146, 149, 150, 152], "databas": [128, 133, 139, 142, 143, 144], "datapath": 195, "date": 166, "david": 59, "dba_rd_chan": 37, "dba_rd_data": 37, "dbg_gls0": [0, 185], "dbg_gls1": [0, 185], "dbg_signal_width": 40, "dd": [170, 172, 173, 174, 194], "ddr": [31, 159], "ddr4": [154, 183, 190], "ddr_logger_0": 185, "ddr_logger_1": 185, "ddr_logger_2": 185, "ddr_logger_3": 185, "ddr_tester_0": 185, "ddr_tester_1": 185, "ddr_tester_2": 185, "ddr_tester_3": 185, "deactiv": 1, "deadlock": [19, 21, 191], "deafult": 59, "deal": 60, "deassert": [7, 12, 76, 83, 87, 104, 110, 134, 152], "deb": 189, "debug": [0, 18, 19, 31, 40, 45, 46, 109, 144, 159, 164, 167, 168, 169, 173, 174, 186, 191, 192, 195], "debug_rand_addr": 31, "debugaccess": 83, "dec": [3, 111], "dec1fn": 160, "decid": [65, 80, 89, 133, 147], "declar": [47, 68, 76, 104, 166, 179, 184], "decod": [2, 41, 87, 107, 160, 198], "decreas": [68, 72, 75, 125, 137, 138], "decrement": [11, 146], "dedic": [60, 164, 166, 180, 193], "deduc": 11, "deem": 21, "deep": [4, 77, 183], "def_refr_period": 31, "default": [0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 27, 28, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 109, 111, 113, 114, 116, 117, 120, 121, 122, 128, 135, 136, 139, 142, 143, 144, 146, 148, 149, 151, 152, 160, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 180, 183, 184, 185, 186, 188, 192, 196], "default_addr_limit": 31, "default_burst_cnt": 31, "default_mod": 90, "deficit": [19, 75, 111, 164], "deficit_idle_count": 164, "defin": [5, 10, 11, 17, 18, 23, 26, 28, 37, 39, 44, 46, 47, 60, 67, 75, 79, 81, 87, 89, 98, 101, 105, 107, 111, 116, 129, 144, 146, 148, 149, 150, 152, 166, 183, 187], "definit": [11, 29, 30, 31, 109, 111, 150, 166, 183], "degrad": [107, 188], "delai": [5, 14, 17, 20, 58, 67, 87, 131, 146, 151], "delay": [71, 162], "delay_count": 20, "delet": [80, 107, 144, 146], "deliber": 184, "delimit": [40, 41, 45, 129], "demo": [180, 183], "demonst": 58, "demonstr": [11, 58, 76, 104, 159], "demultiplex": [91, 160], "demux": [160, 165], "demux_width": 91, "dens": 98, "depars": [41, 198], "depend": [11, 17, 19, 21, 27, 59, 67, 68, 79, 88, 89, 101, 104, 105, 109, 118, 119, 126, 127, 130, 135, 136, 144, 146, 149, 166, 174, 183, 187, 188, 190], "deprac": 45, "deprec": [156, 161, 183], "depreci": [30, 31, 32], "depth": [4, 5, 13, 14, 16, 27, 44, 48, 50, 59, 77, 79, 81, 94, 99, 101, 105], "deriv": [60, 68, 71, 76, 78], "descend": 184, "descrambl": [107, 130], "descrambler_gen": 107, "describ": [0, 2, 17, 47, 67, 76, 104, 107, 118, 119, 125, 128, 129, 137, 138, 139, 142, 143, 144, 147, 148, 149, 152, 153, 154, 166, 167, 168, 169, 183, 184, 185, 186, 187, 189, 191, 195, 196, 197, 198], "descript": [0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, 20, 22, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 119, 120, 121, 125, 128, 131, 132, 137, 138, 139, 142, 143, 146, 147, 152, 154, 157, 158, 162, 163, 164, 165, 174, 180, 181, 183, 185, 186, 187, 191, 192, 193, 196, 198], "descriptor": [37, 39, 46], "desctin": 17, "deseri": 107, "deserv": 166, "design": [5, 11, 12, 16, 27, 37, 41, 45, 46, 47, 76, 104, 107, 110, 119, 144, 150, 159, 164, 179, 180, 183, 185, 187, 189, 191], "desir": [18, 59, 67, 74, 85, 152, 186, 192], "deskew": 107, "desnt": 14, "despair": 67, "destin": [17, 22, 47, 49, 63, 66, 90, 92, 94, 96, 98, 109, 111, 113, 147, 160, 164, 183, 187, 195], "desynchron": 144, "detail": [0, 1, 16, 17, 19, 23, 59, 75, 104, 107, 113, 119, 135, 136, 144, 156, 159, 160, 164, 166, 174, 183, 184, 186, 187, 189], "detect": [1, 11, 17, 29, 31, 34, 67, 107, 118, 121, 156, 160, 164, 184, 195], "detector": [160, 164], "determin": [4, 5, 6, 25, 39, 43, 45, 54, 60, 62, 67, 76, 79, 87, 89, 91, 96, 105, 109, 111, 113, 122, 148, 183], "dev": [31, 171, 172, 180, 184, 185], "develop": [144, 152, 159, 162, 165, 166, 171, 172, 184, 186, 189, 193], "deviat": 45, "devic": [3, 4, 5, 6, 9, 13, 14, 15, 16, 17, 18, 23, 24, 27, 28, 31, 32, 33, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 58, 59, 60, 61, 62, 64, 65, 66, 67, 68, 69, 70, 71, 74, 75, 77, 78, 79, 81, 82, 83, 84, 86, 89, 90, 93, 94, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 111, 113, 116, 117, 121, 144, 166, 179, 180, 183, 191, 192], "devicetre": [183, 191, 192, 195], "devtre": [0, 27, 31, 166, 185, 191], "dfc": [109, 111], "dfch": [109, 111], "dfcl": [109, 111], "dfifo": 109, "dfifo_ovf": 109, "di": [5, 6, 15, 74, 131, 160], "diagnost": 187, "diagram": [0, 48, 68, 88, 110, 116, 174, 183, 184, 186, 187, 192, 193], "did": 109, "didn": 148, "differ": [3, 11, 17, 18, 21, 25, 27, 31, 43, 47, 67, 68, 75, 87, 88, 90, 93, 94, 100, 109, 110, 111, 113, 118, 119, 121, 125, 129, 131, 137, 138, 144, 146, 147, 152, 153, 159, 166, 184, 186, 187, 190, 194], "difficult": 144, "difficulti": 68, "digit": 18, "dimens": [17, 135, 136, 149], "din": 95, "din_dst_rdi": 95, "din_src_rdi": 95, "din_vld": 95, "dir": [17, 135, 136, 149], "direct": [0, 8, 17, 23, 45, 46, 47, 48, 76, 87, 88, 104, 110, 128, 139, 142, 143, 144, 147, 148, 160, 166, 191, 192, 194], "directli": [7, 14, 16, 19, 21, 24, 27, 58, 59, 67, 83, 89, 107, 121, 144, 150, 166, 184, 185, 187, 192, 195], "directori": [0, 2, 45, 121, 144, 153, 154, 157, 158, 162, 163, 165, 166, 178, 179, 184, 185, 189, 197, 198, 200], "disabl": [3, 5, 6, 14, 25, 27, 39, 45, 48, 49, 57, 61, 74, 86, 90, 95, 105, 107, 109, 111, 121, 144, 148, 150, 167, 169, 180, 189, 192, 196], "disadvantag": 144, "disc_bts_cnt_width": [37, 44], "disc_pkt_cnt_width": [37, 44], "discard": [22, 35, 39, 40, 45, 50, 54, 57, 58, 75, 81, 109, 111, 131, 144, 162, 165, 180, 183, 187, 188], "discart": [37, 44, 111], "discourag": 144, "disect": 17, "disjoint": 87, "dispatch": 45, "displai": [45, 58, 131, 174, 183, 187], "distinct": 27, "distinguish": [47, 67, 76, 166], "distmem": 13, "distr": 90, "distribut": [4, 15, 19, 87, 90, 104, 107, 125, 129, 137, 138, 151, 160, 183], "divid": [0, 31, 67, 68, 76, 87, 90, 138, 144, 150, 152, 186, 191, 192], "divis": [50, 68], "dk": [159, 180], "dl": 13, "dll": 166, "dma": [0, 33, 34, 35, 37, 38, 40, 41, 42, 43, 44, 48, 65, 71, 90, 118, 119, 159, 167, 169, 180, 184, 189, 191, 192, 193, 195, 198], "dma_bar_en": 192, "dma_bus_pack": 22, "dma_calypt": 46, "dma_cc_mfb_data": 192, "dma_cc_mfb_dst_rdi": 192, "dma_cc_mfb_eof": 192, "dma_cc_mfb_eof_po": 192, "dma_cc_mfb_meta": 192, "dma_cc_mfb_sof": 192, "dma_cc_mfb_sof_po": 192, "dma_cc_mfb_src_rdi": 192, "dma_clk": [183, 192], "dma_clk_x2": 183, "dma_cq_mfb_data": 192, "dma_cq_mfb_dst_rdi": 192, "dma_cq_mfb_eof": 192, "dma_cq_mfb_eof_po": 192, "dma_cq_mfb_meta": 192, "dma_cq_mfb_sof": 192, "dma_cq_mfb_sof_po": 192, "dma_cq_mfb_src_rdi": 192, "dma_ctrl_ndp_rx": [0, 185], "dma_ctrl_ndp_rx0": [0, 185], "dma_ctrl_ndp_rx1": [0, 185], "dma_ctrl_ndp_rx10": [0, 185], "dma_ctrl_ndp_rx11": [0, 185], "dma_ctrl_ndp_rx12": [0, 185], "dma_ctrl_ndp_rx13": [0, 185], "dma_ctrl_ndp_rx14": [0, 185], "dma_ctrl_ndp_rx15": [0, 185], "dma_ctrl_ndp_rx2": [0, 185], "dma_ctrl_ndp_rx3": [0, 185], "dma_ctrl_ndp_rx4": [0, 185], "dma_ctrl_ndp_rx5": [0, 185], "dma_ctrl_ndp_rx6": [0, 185], "dma_ctrl_ndp_rx7": [0, 185], "dma_ctrl_ndp_rx8": [0, 185], "dma_ctrl_ndp_rx9": [0, 185], "dma_ctrl_ndp_tx": [0, 185], "dma_ctrl_ndp_tx0": [0, 185], "dma_ctrl_ndp_tx1": [0, 185], "dma_ctrl_ndp_tx10": [0, 185], "dma_ctrl_ndp_tx11": [0, 185], "dma_ctrl_ndp_tx12": [0, 185], "dma_ctrl_ndp_tx13": [0, 185], "dma_ctrl_ndp_tx14": [0, 185], "dma_ctrl_ndp_tx15": [0, 185], "dma_ctrl_ndp_tx2": [0, 185], "dma_ctrl_ndp_tx3": [0, 185], "dma_ctrl_ndp_tx4": [0, 185], "dma_ctrl_ndp_tx5": [0, 185], "dma_ctrl_ndp_tx6": [0, 185], "dma_ctrl_ndp_tx7": [0, 185], "dma_ctrl_ndp_tx8": [0, 185], "dma_ctrl_ndp_tx9": [0, 185], "dma_discard": 35, "dma_downhdr_width": [62, 69, 192], "dma_endpoint": 46, "dma_ep": 192, "dma_hdr": 35, "dma_hdr_dst_rdi": 35, "dma_hdr_meta_width": 183, "dma_hdr_pointer_width": [42, 44, 45], "dma_hdr_src_rdi": 35, "dma_hdr_width": 42, "dma_mfb_region": 183, "dma_mfb_region_s": 183, "dma_modul": [0, 185], "dma_params_rx0": 185, "dma_params_tx0": 185, "dma_pcie_hdr": 35, "dma_pcie_hdr_dst_rdi": 35, "dma_pcie_hdr_s": 35, "dma_pcie_hdr_src_rdi": 35, "dma_port": 192, "dma_rc_mfb_data": 192, "dma_rc_mfb_dst_rdi": 192, "dma_rc_mfb_eof": 192, "dma_rc_mfb_eof_po": 192, "dma_rc_mfb_meta": 192, "dma_rc_mfb_sof": 192, "dma_rc_mfb_sof_po": 192, "dma_rc_mfb_src_rdi": 192, "dma_rc_mvb_data": 192, "dma_rc_mvb_dst_rdi": 192, "dma_rc_mvb_src_rdi": 192, "dma_rc_mvb_vld": 192, "dma_reset": [183, 192], "dma_reset_x2": 183, "dma_rq_mfb_data": 192, "dma_rq_mfb_dst_rdi": 192, "dma_rq_mfb_eof": 192, "dma_rq_mfb_eof_po": 192, "dma_rq_mfb_meta": 192, "dma_rq_mfb_sof": 192, "dma_rq_mfb_sof_po": 192, "dma_rq_mfb_src_rdi": 192, "dma_rq_mvb_data": 192, "dma_rq_mvb_dst_rdi": 192, "dma_rq_mvb_src_rdi": 192, "dma_rq_mvb_vld": 192, "dma_rx": 48, "dma_rx_": 183, "dma_rx_blocking_mod": 184, "dma_rx_channel": 183, "dma_rx_frame_size_max": 183, "dma_rx_mfb_data": [48, 183], "dma_rx_mfb_dst_rdi": [48, 183], "dma_rx_mfb_eof": [48, 183], "dma_rx_mfb_eof_po": [48, 183], "dma_rx_mfb_sof": [48, 183], "dma_rx_mfb_sof_po": [48, 183], "dma_rx_mfb_src_rdi": [48, 183], "dma_rx_mvb_channel": [48, 183], "dma_rx_mvb_discard": [48, 183], "dma_rx_mvb_dst_rdi": [48, 183], "dma_rx_mvb_hdr_meta": [48, 183], "dma_rx_mvb_len": [48, 183], "dma_rx_mvb_src_rdi": [48, 183], "dma_rx_mvb_vld": [48, 183], "dma_stream": 183, "dma_tx": 48, "dma_tx_": 183, "dma_tx_channel": 183, "dma_tx_frame_size_max": 183, "dma_tx_mfb_data": [48, 183], "dma_tx_mfb_dst_rdi": [48, 183], "dma_tx_mfb_eof": [48, 183], "dma_tx_mfb_eof_po": [48, 183], "dma_tx_mfb_sof": [48, 183], "dma_tx_mfb_sof_po": [48, 183], "dma_tx_mfb_src_rdi": [48, 183], "dma_tx_mvb_channel": [48, 183], "dma_tx_mvb_dst_rdi": [48, 183], "dma_tx_mvb_hdr_meta": [48, 183], "dma_tx_mvb_len": [48, 183], "dma_tx_mvb_src_rdi": [48, 183], "dma_tx_mvb_vld": [48, 183], "dma_tx_usr_choke_chan": 183, "dma_typ": [184, 186, 189], "dma_uphdr_width": [62, 69, 192], "dnf": [27, 189], "do": [5, 6, 49, 58, 67, 68, 71, 80, 89, 90, 91, 109, 113, 116, 123, 131, 144, 152, 160, 166, 179, 185, 187, 189, 195], "do_compar": [125, 135, 136, 137, 138, 147, 149], "do_copi": [125, 135, 136, 137, 138, 147, 149], "dob": 15, "doc": [22, 183, 187], "document": [0, 5, 6, 17, 27, 45, 47, 60, 76, 77, 79, 119, 128, 139, 142, 143, 144, 145, 152, 156, 160, 164, 166, 179, 184, 186, 187, 189, 195], "doe": [0, 4, 11, 21, 23, 41, 45, 47, 49, 52, 58, 60, 67, 68, 76, 83, 87, 88, 95, 102, 109, 110, 111, 116, 120, 125, 137, 138, 144, 166, 180, 183, 185, 189, 192], "doesn": [88, 89, 109, 128, 131, 133, 139, 142, 143, 144, 159, 166], "doi": 13, "domain": [1, 20, 31, 77, 82, 151, 187], "don": [11, 17, 20, 31, 87, 89, 109, 144, 148, 149], "done": [11, 17, 18, 25, 27, 31, 44, 59, 60, 67, 68, 88, 99, 109, 110, 118, 119, 131, 144, 151, 183, 184], "dont": [124, 145], "dont_car": 13, "doubl": [17, 68, 75, 109, 111, 118, 119, 156, 160, 183, 187], "doulo": 144, "dout": 95, "dout_dst_rdi": 95, "dout_src_rdi": 95, "dout_vld": 95, "down": [14, 21, 67, 88, 89, 110], "download": [27, 128, 173], "downstream": [46, 118, 119], "downto": [3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 28, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 112, 113, 114, 115, 116, 117, 120, 121, 180, 183, 192], "dp_bmem": 161, "dp_bmem_behav": 166, "dp_bmem_v7": 161, "dp_bram": [29, 161], "dp_bram_xilinx": 161, "dp_uram_xilinx": 161, "dpi": 166, "dpm": [39, 45], "dpm_rd_chan": 37, "dpm_rd_data": 37, "draft": [22, 183, 187, 191], "drc": 187, "drd": [87, 88, 146], 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"elimin": [17, 19, 119], "els": [3, 87, 89, 90, 111, 128, 131, 138, 142, 143, 144, 184], "elseif": [166, 184], "embed": [156, 161], "emif": [29, 31, 32, 183, 190], "emif_auto_precharg": [31, 183], "emif_cal_fail": [31, 183], "emif_cal_success": [31, 183], "emif_ecc_isr": 31, "emif_ecc_usr_int": 183, "emif_rst_don": [31, 183], "emif_rst_req": [31, 183], "emploi": 187, "empti": [5, 6, 19, 50, 65, 71, 76, 126, 127, 141, 151, 156, 166, 185], "emul": 102, "en": [20, 150], "ena": 134, "enabl": [0, 3, 4, 5, 6, 8, 10, 11, 14, 17, 18, 19, 20, 23, 25, 27, 31, 39, 41, 45, 46, 48, 49, 50, 52, 54, 55, 56, 58, 61, 62, 63, 64, 69, 71, 74, 75, 77, 80, 82, 83, 87, 88, 89, 90, 91, 94, 95, 96, 98, 101, 109, 111, 113, 114, 116, 117, 119, 120, 121, 129, 135, 136, 144, 146, 159, 160, 161, 162, 166, 174, 180, 183, 186, 187, 188, 192, 195, 196, 198], "enabled_chan": [37, 42, 44], "enc": 160, "encapsul": 148, "encapsulation_element_max_numb": 148, "encod": [2, 107, 130, 149, 160], "encount": 67, "end": [11, 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"epon": 107, "eq": 131, "equal": [3, 26, 31, 67, 75, 76, 87, 89, 121, 144, 166, 180, 183], "equat": 67, "eras": [26, 80], "err": [31, 134], "error": [0, 22, 31, 85, 87, 107, 108, 109, 131, 133, 141, 144, 179, 180, 183, 184, 187], "error_msg": 131, "errorcrc": [22, 183, 187], "errorfram": [22, 183, 187], "errormac": [22, 183, 187], "errormaxtu": [22, 183, 187], "errormintu": [22, 183, 187], "especi": [184, 185, 195], "essenti": [87, 144], "etc": [0, 2, 39, 45, 47, 67, 87, 102, 138, 144, 166, 184, 185, 187, 192], "eth": [0, 48, 90, 109, 111, 131, 180, 183, 185, 187, 188, 189, 195], "eth0": 185, "eth1": 185, "eth_channel": 183, "eth_core_arch": 180, "eth_hdr_pack": [22, 109, 183, 187], "eth_mac_bypass": 180, "eth_mfb_region": 183, "eth_mfb_region_s": 183, "eth_phi": [135, 136], "eth_port": 180, "eth_port_chan": 180, "eth_port_rx_mtu": 180, "eth_port_spe": 180, "eth_port_tx_mtu": 180, "eth_refclk_n": 180, "eth_refclk_p": 180, "eth_rx": 48, "eth_rx_": 183, "eth_rx_hdr_width": [109, 180, 183], "eth_rx_link_up": 183, "eth_rx_mfb_data": [48, 183], "eth_rx_mfb_dst_rdi": [48, 183], "eth_rx_mfb_eof": [48, 183], "eth_rx_mfb_eof_po": [48, 183], "eth_rx_mfb_sof": [48, 183], "eth_rx_mfb_sof_po": [48, 183], "eth_rx_mfb_src_rdi": [48, 183], "eth_rx_mvb_channel": 48, "eth_rx_mvb_data": 183, "eth_rx_mvb_discard": 48, "eth_rx_mvb_dst_rdi": [48, 183], "eth_rx_mvb_hdr_meta": 48, "eth_rx_mvb_len": 48, "eth_rx_mvb_src_rdi": [48, 183], "eth_rx_mvb_vld": [48, 183], "eth_rx_n": 180, "eth_rx_p": 180, "eth_stream": [180, 183], "eth_tx": 48, "eth_tx_hdr_width": [180, 183], "eth_tx_mfb_": 183, "eth_tx_mfb_data": [48, 183], "eth_tx_mfb_dst_rdi": [48, 183], "eth_tx_mfb_eof": [48, 183], "eth_tx_mfb_eof_po": [48, 183], "eth_tx_mfb_hdr": 183, "eth_tx_mfb_sof": [48, 183], "eth_tx_mfb_sof_po": [48, 183], "eth_tx_mfb_src_rdi": [48, 183], "eth_tx_mvb_channel": [48, 180, 183], "eth_tx_mvb_dst_rdi": 48, "eth_tx_mvb_hdr_meta": 48, "eth_tx_mvb_len": 48, "eth_tx_mvb_src_rdi": 48, "eth_tx_mvb_timestamp": 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151, 154, 159, 160, 174, 178, 183, 184, 187, 189, 192, 193, 194, 195], "example1": 5, "exce": 67, "except": [17, 41, 55, 135, 136, 166], "exception": 166, "execut": [17, 26, 27, 88, 91, 101, 166, 191, 195], "exist": [60, 102, 128, 144, 166, 174, 185, 187, 191], "exit": 31, "exp_rom_base_addr": [116, 192], "expans": [54, 116, 188], "expect": [11, 27, 58, 70, 87, 89, 144, 173, 180, 189], "experi": 189, "experiment": [49, 167, 169], "expert": [160, 161], "expir": 17, "explain": [88, 89, 144, 152, 187, 194], "explan": 166, "explicit": 166, "exponenti": 59, "export": [126, 127, 128, 130, 139, 141, 142, 143, 166], "express": [42, 45, 46, 98, 112, 113, 115, 144, 166, 192], "ext": 195, "ext_siz": 50, "extend": [54, 58, 60, 67, 75, 107, 112, 128, 131, 139, 142, 143, 144, 150, 160, 162, 185, 192], "extens": [50, 112, 146, 166, 185, 192], "extent": 185, "extern": [0, 23, 29, 31, 32, 71, 95, 107, 121, 154, 183, 188, 190, 193, 195, 196], "external_tim": 71, "external_time_src": 71, "extra": [109, 111, 144, 156, 166], "extra_librari": 166, "extra_modul": 166, "extra_vflag": 144, "extract": [46, 59, 60, 109, 119, 129], "extractor": [45, 119], "extrem": 67, "f": [31, 46, 109, 111, 172, 174, 187, 188, 195], "f0": 189, "f_extend_end_en": 75, "f_extend_end_s": 75, "f_extend_start_en": 75, "f_extend_start_s": 75, "f_gap_adjust_en": 75, "f_gap_adjust_size_avg": 75, "f_gap_adjust_size_min": 75, "f_tile": 180, "fabric": 107, "fact": [68, 126, 127, 130], "factori": 144, "fail": [31, 144, 173, 183], "failur": 31, "fake_fifo": [5, 7, 105], "fake_loopback": 61, "fake_pip": [66, 86], "fake_switch": 48, "falcon": 159, "fall": [1, 4, 77, 80, 89, 118, 119], "fall09": 10, "fals": [5, 6, 7, 8, 14, 16, 17, 18, 25, 26, 31, 39, 46, 48, 58, 61, 62, 64, 66, 71, 73, 74, 75, 78, 86, 89, 90, 91, 94, 95, 98, 101, 102, 105, 109, 111, 113, 114, 121, 166, 180, 184, 192], "famili": 166, "familiar": 185, "fancy_str": 184, "far": 61, "fashion": 17, "fast": [11, 135, 136, 160], "fast_sof": [135, 136], "faster": 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59, 60, 65, 67, 68, 71, 75, 76, 77, 87, 89, 104, 109, 110, 111, 113, 114, 115, 117, 126, 127, 128, 130, 131, 135, 136, 141, 142, 144, 146, 147, 149, 150, 152, 160, 164, 166, 173, 174, 179, 183, 184, 185, 187, 189, 192, 195, 196], "first_b": [114, 115], "first_on": [160, 164], "first_one_detector": 164, "firstib": 22, "fist": [35, 131, 151], "fit": [6, 11, 18, 19, 59], "five": [67, 76, 139, 145, 152, 179], "fix": [19, 104, 144, 146, 173, 179, 185], "fl_": 47, "fl_tool": 157, "flag": [5, 6, 22, 25, 32, 54, 55, 56, 57, 67, 73, 81, 92, 107, 108, 109, 111, 112, 113, 166, 174, 183, 187, 192, 196], "flash": [23, 170, 171, 172, 173, 191, 193], "flgb2104": [169, 176], "flip": [4, 77], "float": [109, 111, 166], "flop": [4, 77], "flow": [0, 24, 31, 64, 67, 148, 164, 167, 168, 169, 183, 187], "flowtest": 132, "flu_": 47, "flu_tool": 158, "flush": [129, 144], "flvb2104": 166, "fly": 109, "fo": 117, "focus": [46, 87], "folder": [25, 27, 31, 32, 152, 156, 161, 164, 166, 184, 189], "follow": [0, 11, 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109, 121, 146, 187, 195], "inculd": 166, "indent": 144, "independ": [0, 11, 16, 17, 19, 60, 63, 67, 90, 96, 102, 118, 119, 135, 136, 144, 156, 159, 166, 183, 184, 187, 194], "independetli": 102, "index": [6, 11, 22, 25, 29, 31, 35, 59, 87, 89, 104, 110, 112, 160, 183, 187], "indic": [4, 31, 57, 60, 67, 76, 85, 87, 89, 104, 113, 120, 144, 179, 185], "indirect": [112, 163], "indirectli": 85, "individu": [0, 1, 60, 62, 65, 71, 87, 109, 144, 166, 179, 183, 185, 186, 187, 191, 192], "ineffici": 68, "inf": [14, 60, 65], "inf_channel": 35, "inf_dst_rdi": 35, "inf_meta": 35, "inf_src_rdi": 35, "infinit": 19, "influenc": [87, 96], "info": [8, 17, 27, 78, 109, 144, 184, 187, 189], "inform": [11, 17, 23, 27, 35, 41, 44, 46, 48, 50, 54, 67, 68, 74, 77, 78, 79, 80, 83, 109, 113, 118, 119, 129, 139, 142, 143, 144, 145, 150, 152, 164, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 185, 187, 189, 192, 195, 196], "infram": [128, 133, 139, 142], "infrastructur": 47, "infrom": 11, "ingor": 102, "inherit": [129, 131, 152], "init": 123, "init_ack": 123, "init_addr_base_downto": 89, "init_addr_mask_downto": 89, "init_done_n": 192, "init_port_mapping_downto": 89, "init_sequ": [128, 139, 142, 143, 144], "init_sequence_librari": [128, 139, 142, 143, 144], "initi": [25, 37, 39, 45, 123, 144, 184, 191], "inner": [132, 144], "inout": 180, "input": [3, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 17, 19, 20, 21, 25, 26, 33, 35, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47, 48, 50, 54, 55, 56, 57, 58, 59, 61, 62, 63, 64, 65, 66, 67, 68, 72, 73, 74, 75, 78, 83, 85, 86, 89, 90, 91, 92, 94, 95, 96, 98, 99, 100, 102, 106, 108, 109, 110, 111, 115, 117, 119, 120, 121, 122, 129, 131, 150, 156, 160, 164, 166, 180, 183, 185, 186, 187], "input_1": 3, "input_2": 3, "input_data": 95, "input_data_width": 3, "input_dst_rdi": 95, "input_eq_output": 78, "input_fifo_s": 62, "input_item": 144, "input_mfb": 144, "input_mvb": 144, "input_reg": [8, 91], "input_regs_en": 3, "input_src_rdi": 95, "input_tim": 144, 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144, 147, 166, 183], "integer_vector": 180, "integr": [113, 166, 192], "intel": [4, 5, 23, 27, 31, 46, 59, 66, 79, 83, 86, 101, 105, 109, 111, 113, 116, 117, 119, 122, 123, 132, 154, 156, 159, 161, 164, 166, 170, 173, 174, 177, 179, 180, 184, 187, 188, 189, 190, 191, 192], "intel_jtag_op_control": [0, 185], "intel_jtag_op_ctrl": [0, 185], "intel_mac_seg_if": 133, "intel_sdm_control": [0, 185], "intend": [17, 107], "intensli": 58, "inter": [19, 111, 131, 144, 164], "interact": [25, 67, 87], "interconnect": [61, 183, 193], "interest": [10, 125, 137, 138], "interfac": [0, 4, 5, 9, 11, 17, 18, 19, 21, 23, 24, 25, 26, 29, 31, 33, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 54, 55, 56, 57, 58, 59, 61, 62, 63, 66, 67, 68, 69, 70, 71, 72, 73, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 95, 98, 99, 101, 102, 106, 109, 110, 111, 113, 116, 117, 118, 119, 121, 122, 123, 124, 125, 128, 129, 131, 132, 133, 134, 137, 138, 139, 141, 142, 143, 145, 146, 151, 152, 159, 164, 167, 168, 169, 180, 185, 189, 190, 192, 193, 194, 195, 198], "interface_nam": [128, 133, 139, 142, 143, 144, 147], "interfam": 131, "interleav": 89, "intern": [6, 11, 17, 19, 27, 34, 43, 44, 45, 46, 48, 59, 61, 67, 71, 76, 80, 92, 104, 110, 122, 128, 134, 139, 142, 144, 150, 183, 185, 186, 195], "interpret": [102, 166], "interrupt": [23, 31, 110, 164], "interrupt_manag": 164, "interupt": 183, "interv": [18, 67], "interval_count": 67, "interval_length": 67, "intro": 67, "introduc": [129, 144], "invalid": [6, 22, 59, 60, 67, 68, 87, 93, 104, 114, 146], "invert": [74, 107], "ip": [0, 23, 27, 29, 31, 32, 46, 107, 109, 111, 116, 118, 119, 159, 164, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 180, 184, 185, 187, 188, 189, 190, 191, 195, 198], "ipg": 111, "ipg_gener": 132, "ipg_generate_en": 111, "ipv4": [74, 148], "ipv4_min_packet_size_to_fragment_max": 148, "ipv4_min_packet_size_to_fragment_min": 148, "ipv4_prefix_max": 148, "ipv4_prefix_min": 148, "ipv6": 148, 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80, 87, 88, 89, 110, 118, 119, 122, 125, 131, 137, 138, 139, 143, 144, 147, 152, 159, 166, 179, 183, 184, 185, 187, 188, 189, 191, 192, 195], "itself": [11, 19, 46, 118, 166, 173, 185, 187], "jakub": 1, "jan": [17, 19, 119], "jenkin": 144, "jic": 170, "join": [11, 68, 144], "join_ani": 144, "json": [31, 148], "jtag": [154, 167, 168, 169, 170, 171, 172, 191], "jtag_op_cli": 27, "jtag_op_mgmt": 27, "jtagconfig": 27, "jump": 144, "just": [0, 14, 31, 58, 67, 83, 89, 123, 129, 144, 146, 147, 150, 183, 184, 187, 189], "keep": [7, 11, 12, 29, 67, 89, 190], "kei": 187, "kept": [71, 83, 118, 119], "keyword": 166, "khz": [30, 31], "kind": [109, 110], "kintex": 46, "kit": [159, 169, 171, 172, 189, 193], "know": [11, 58, 80, 144, 185], "knowledg": [160, 161], "known": 146, "komponenti": 5, "ku15p": 159, "kubalek": [17, 19, 119], "l": [0, 166], "l2": [188, 195], "lane": [59, 107, 129, 180, 192], "lane_align": 107, "lane_rx_polar": 180, "lane_tx_polar": 180, "languag": [144, 166], "lappend": [144, 166, 184], "larg": [18, 19, 27, 59, 63, 67, 110, 144, 166, 185], "large_vector": 184, "larger": [3, 6, 10, 25, 29, 31, 59, 68, 188], "largest": [40, 43, 45], "last": [6, 19, 22, 24, 30, 47, 57, 58, 60, 67, 76, 80, 85, 87, 89, 110, 113, 114, 115, 117, 118, 125, 126, 127, 129, 130, 135, 136, 137, 138, 144, 147, 149, 150, 151, 152, 156, 160, 166, 179, 184, 187], "last_b": [114, 115], "last_on": 160, "last_vld_impl": 60, "lastib": 22, "lastli": 60, "lat_mea": 45, "latch": 160, "latch_out": 12, "late": 166, "latenc": [0, 3, 6, 8, 9, 10, 11, 13, 17, 24, 30, 31, 45, 46, 58, 59, 68, 83, 87, 101, 122, 135, 136, 154, 159, 160, 161, 186, 188, 190, 192], "latency_fifo_depth": 101, "latency_fifo_en": 101, "latency_fifo_ram_typ": 101, "latency_met": [24, 28], "latency_meter_i": 28, "latency_ticks_width": 24, "latency_vld": 28, "later": [11, 18, 41, 87, 101, 124], "latex": 31, "latter": 166, "launch": [166, 184], "layer": [107, 109, 111, 119, 148, 188, 194], "layer_max_numb": 148, "layer_typ": 148, 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"librari": [25, 132, 166, 185, 188], "licens": [109, 111, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 188, 189], "life": 27, "ligc_vector_array_mfb": 137, "light": 161, "ligic": 137, "lii": 132, "like": [10, 11, 25, 49, 59, 76, 87, 89, 110, 112, 119, 123, 128, 138, 139, 142, 143, 144, 146, 152, 166, 180, 184, 187, 194, 195], "limit": [5, 7, 31, 76, 87, 90, 100, 104, 146, 162, 180, 188], "line": [5, 144, 185, 188, 189, 194], "linear": [19, 30], "link": [47, 107, 109, 111, 135, 136, 180, 183, 184, 185, 187, 189, 192, 195], "link_up": 109, "linux": [174, 188, 189], "list": [1, 27, 32, 39, 45, 59, 125, 137, 138, 144, 148, 152, 159, 179, 184, 187, 188, 192, 195], "listen": 30, "lite": [180, 197], "littl": [60, 67], "ll_transact": 144, "load": [18, 21, 27, 29, 31, 58, 67, 119, 144, 160, 166, 170, 171, 172, 173, 174, 184, 185, 193], "local": [27, 147, 183, 195], "locat": [2, 27, 39, 45, 60, 122, 144, 148, 152, 153, 154, 156, 157, 158, 161, 162, 163, 165, 166, 179, 184, 187, 197, 198], "lock": [83, 107, 130], "log": [24, 25, 33, 144], "log2": [4, 5, 8, 9, 13, 14, 15, 16, 17, 26, 28, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 81, 88, 90, 91, 98, 99, 100, 105, 106, 109, 111, 113, 116, 180, 183, 192], "logarithm": [76, 121], "logger": [31, 154], "logic": [2, 3, 6, 11, 19, 27, 29, 31, 37, 39, 42, 45, 46, 47, 61, 64, 67, 68, 75, 80, 82, 89, 92, 93, 95, 102, 107, 111, 118, 121, 123, 124, 128, 129, 131, 132, 133, 134, 135, 136, 139, 142, 144, 145, 146, 147, 150, 151, 156, 164, 180, 183, 184, 186, 192], "logic_vector": [137, 143], "logic_vector_arrai": [139, 142], "logic_vector_array_axi": [124, 132], "logic_vector_array_axi_env": 139, "logic_vector_array_mfb": [132, 138, 143], "logic_vector_array_mfb_env": 142, "logic_vector_mvb": 132, "logic_vector_mvb_env": 143, "long": [17, 20, 21, 33, 76, 80, 87, 164], "look": [11, 67, 89, 110, 121, 152, 160, 179, 187], "lookup": [152, 159, 165], "loop": [11, 67, 102, 144, 162, 174, 186, 195], "loopback": [48, 107, 159, 162, 174, 186, 187, 189, 195], "lost": 95, "lot": [18, 102, 144, 151], "low": [11, 17, 49, 67, 75, 90, 109, 111, 121, 122, 123, 124, 129, 132, 133, 134, 135, 136, 140, 145, 151, 159, 186, 188, 192], "lower": [1, 5, 6, 14, 17, 18, 21, 39, 45, 49, 55, 58, 62, 68, 75, 87, 89, 93, 100, 109, 110, 117, 120, 121, 125, 137, 138, 144, 160, 187], "lowest": [11, 23, 46, 47, 48, 49, 76, 88, 89, 104, 166, 184], "lsb": [76, 85, 95, 104, 110], "lsearch": 166, "luckili": 11, "lut": [4, 5, 13, 44, 77, 79, 82, 101, 105, 156, 161], "lut_arch": 106, "lut_depth": 106, "lut_width": 106, "lutmem": 156, "lutram": [4, 106], "lvt_mem": [13, 161], "m": [0, 6, 18, 31, 32, 95, 151, 160], "m1_": 131, "m_": 144, "m_agent": 144, "m_byte_arrai": 144, "m_byte_array_ag": 144, "m_byte_array_cfg": 144, "m_cfg": [128, 139, 142, 143], "m_compar": 144, "m_config": [128, 139, 142, 143, 144], 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119, 121, 122, 125, 137, 138, 149, 166, 184, 185, 187, 188, 192], "mainli": [19, 166, 192, 195], "maintain": [76, 104, 164], "major": [76, 87, 110, 125, 131, 137, 138, 151, 184, 188], "make": [0, 19, 25, 27, 32, 60, 67, 76, 87, 89, 107, 109, 118, 129, 144, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 184, 185, 187], "make_param": 166, "makefil": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 186, 192], "malfunct": 189, "manag": [23, 26, 33, 39, 42, 45, 119, 120, 167, 168, 169, 187, 198], "mandatori": [60, 166, 185], "mandatory_ipv4_address_rang": 148, "mandatory_ipv6_address_rang": 148, "mandatory_mac_address_rang": 148, "mani": [18, 22, 25, 79, 87, 89, 105, 119, 129, 144, 160, 184, 190], "manipul": [39, 45], "manner": 110, "manual": [27, 29, 31, 32, 67, 144, 167, 168, 169, 173, 195], "manuali": 31, "manufactur": [188, 189], "map": [0, 24, 25, 26, 28, 31, 83, 86, 87, 107, 112, 118, 119, 122, 131, 166, 183, 186, 187, 195], "mark": [6, 47, 80, 92, 95, 156, 196], "markdown": [25, 31], "marker": 107, "mash": 144, "mask": [16, 18, 22, 37, 39, 45, 58, 59, 63, 76, 80, 84, 92, 104, 109, 183, 187], "masker": 162, "masking_en": 63, "master": [44, 59, 82, 84, 87, 90, 107, 109, 111, 116, 121, 122, 144, 146, 183, 191], "master_driv": 146, "master_sequ": 146, "match": [107, 109, 144, 185], "math_pack": 144, "math_pkg": 144, "mathemat": 144, "matplotlib": 25, "matter": [11, 187], "max": [0, 5, 16, 25, 28, 30, 31, 33, 36, 38, 39, 40, 41, 42, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 90, 91, 99, 100, 106, 109, 111, 113, 116, 121, 125, 128, 137, 138, 139, 142, 143, 144, 151, 152, 180, 183, 192], "max_concurrent_ev": 18, "max_en": 25, "max_flow_inter_packet_gap": 148, "max_interval_cycl": 18, "max_paralel_ev": 28, "max_paralel_read": 24, "max_transaction_count": 147, "max_word": 60, "maxim": [25, 30, 31, 59, 109], "maximum": [3, 6, 11, 17, 18, 19, 20, 24, 25, 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"nanosecond": [109, 120, 121, 183, 196], "natur": [3, 4, 5, 6, 7, 9, 10, 13, 14, 16, 18, 20, 33, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 59, 60, 61, 62, 63, 64, 65, 67, 68, 70, 71, 73, 74, 75, 76, 77, 78, 79, 81, 82, 83, 84, 85, 90, 91, 92, 93, 94, 96, 98, 99, 100, 101, 102, 104, 105, 106, 109, 111, 113, 116, 117, 135, 136, 149, 180, 183, 192], "nb_main": 166, "nb_preference_filt": 166, "ndk": [2, 27, 46, 76, 135, 136, 159, 179, 183, 186, 187, 190, 191, 192], "ndk_minim": [185, 189], "ndp": 183, "nearest": [6, 60], "neccessari": 166, "necesari": 60, "necess": 166, "necessari": [3, 59, 67, 87, 104, 109, 111, 131, 144, 152, 166, 180, 183, 184, 185, 188, 192], "need": [6, 11, 18, 19, 20, 22, 24, 25, 27, 31, 32, 38, 39, 44, 45, 50, 58, 67, 68, 76, 89, 101, 102, 110, 111, 112, 119, 129, 144, 160, 164, 166, 179, 185], "neg": [75, 107], "negat": 83, "neither": [17, 68, 87, 166], "nessesari": 11, "net": 144, "net_mod_logic_env": 144, "netcop": [0, 32, 185], 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187, 189, 192, 194, 195, 196], "number_of_channel": 187, "number_of_item": [34, 35], "number_of_max_item": 34, "numer": [70, 144], "numeric_std": 144, "numericstdnowarn": 144, "o": [31, 189], "object": [125, 128, 135, 136, 137, 138, 139, 142, 143, 149, 150, 151, 166], "obligatori": [58, 180], "observ": [128, 133, 139, 141, 142, 144], "obsolet": [95, 109, 111, 156, 161], "obtain": [0, 23, 76, 112, 159, 184, 195], "obuf_input_eq_output": 75, "obuf_meta_eq_output": 75, "occupi": [27, 89, 104], "occur": [11, 18, 19, 25, 26, 28, 30, 31, 42, 49, 58, 62, 68, 76, 96, 104, 109, 110, 118, 119, 130, 131, 144, 164, 166, 179], "occurr": [25, 87, 130], "octect": 111, "octet": [109, 111, 129], "ocurr": 151, "od": 17, "ofc": 70, "off": [60, 90, 107, 111, 122, 146, 148, 170, 171, 172, 187], "offer": 144, "offici": 159, "offset": [19, 23, 34, 45, 48, 60, 65, 67, 71, 74, 83, 107, 109, 111, 112, 187, 195], "offset_processor": 60, "offset_width": [60, 74], "ofm": [0, 27, 31, 109, 111, 112, 153, 154, 157, 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101, 105, 107, 109, 111, 114, 120, 131, 135, 136, 148, 166, 171, 172, 174, 180, 185, 186], "ordder": [135, 136], "order": [5, 6, 9, 11, 17, 19, 21, 22, 23, 31, 39, 42, 45, 47, 67, 68, 71, 74, 87, 94, 96, 102, 107, 110, 117, 118, 131, 143, 144, 148, 164, 165, 166, 179, 184], "ordinari": 110, "ored": 151, "org": [13, 135, 136, 185, 189], "organ": [76, 184], "orient": [5, 128, 139, 142, 183, 191], "origin": [19, 21, 52, 55, 58, 59, 64, 68, 88, 164], "oroc": 109, "oroch": 109, "orocl": 109, "othe": 68, "other": [3, 6, 7, 9, 11, 16, 17, 18, 19, 21, 25, 31, 40, 45, 47, 49, 55, 57, 58, 59, 62, 63, 64, 66, 67, 68, 69, 71, 76, 78, 84, 87, 88, 89, 104, 107, 109, 111, 117, 118, 120, 122, 125, 128, 129, 131, 135, 136, 137, 139, 142, 143, 149, 151, 152, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 180, 184, 185, 187, 189, 192, 195], "otherwis": [4, 7, 19, 61, 67, 80, 95, 109, 111, 128, 139, 142, 143, 144, 159, 166, 185], "our": [11, 18, 76, 87, 89, 144, 159, 186, 187, 189, 194], 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109, 118, 119, 180], "overlap": [17, 31], "overrid": [17, 75, 148, 166], "overridden": 147, "overriden": 166, "overview": [0, 155, 184], "overwrit": [11, 60, 67, 87, 148], "overwritten": [75, 80, 148, 166, 184], "own": [17, 19, 39, 44, 45, 48, 59, 60, 71, 88, 95, 110, 118, 119, 125, 126, 127, 131, 135, 136, 137, 138, 144, 149, 159, 183, 184, 187, 188, 192, 195], "p": [31, 32, 67, 76, 119, 170, 171, 172, 177, 180, 192, 195], "p1": 47, "p2": 47, "p2mp": 107, "p_sequenc": 144, "p_tile": 192, "pack": 144, "packag": [0, 24, 25, 27, 31, 107, 109, 112, 122, 123, 124, 125, 128, 132, 134, 137, 138, 139, 141, 142, 145, 146, 151, 159, 166, 174, 178, 183, 185, 187, 189, 191], "package_nam": 166, "packer": 162, "packet": [0, 33, 35, 36, 37, 38, 39, 40, 44, 45, 46, 47, 48, 49, 54, 55, 56, 57, 58, 59, 60, 67, 69, 70, 71, 74, 75, 78, 108, 109, 111, 113, 125, 128, 131, 137, 138, 139, 141, 142, 144, 148, 150, 152, 159, 162, 164, 180, 186, 193, 194, 195, 196, 197], "packet_head": 131, "packet_max_s": 148, "packet_min_s": 148, "packet_plann": 164, "packet_port_env": 144, "packet_s": 131, "packet_size_max_step": 148, "packet_size_min_step": 148, "packet_size_prob": 148, "packet_splitt": 144, "packets_max_numb": 148, "packets_min_numb": 148, "packets_rev_max_numb": 148, "packets_rev_min_numb": 148, "packetsh": [39, 45], "packetsl": [39, 45], "pacsign": 177, "pactek": 108, "pad": [27, 183], "page": [47, 76, 104, 144, 155, 184], "pai": 67, "pair": [112, 166, 187], "pakcet": 19, "paket": 144, "pandoc": 31, "pane": 27, "paper": 10, "paragraph": 67, "paral": 24, "paralel": [0, 28], "parallel": [11, 17, 19, 28, 60, 88, 118, 160, 164], "param": [144, 185], "param_cfg": [128, 142, 143, 144], "paramet": [4, 14, 16, 20, 25, 31, 32, 35, 36, 38, 40, 43, 47, 58, 59, 63, 66, 67, 68, 77, 79, 81, 82, 85, 87, 90, 96, 100, 110, 111, 113, 116, 122, 123, 124, 125, 128, 131, 132, 133, 135, 136, 137, 138, 139, 142, 143, 144, 145, 146, 147, 149, 150, 152, 166, 174, 179, 180, 183, 185, 186, 187, 192, 195], "parameter": [68, 123], "parametr": [4, 186], "parametrized_class": 144, "paramt": 110, "paremet": 110, "parent": [112, 128, 131, 139, 142, 143, 144, 184, 185], "pars": [41, 144, 166, 198], "parsepcieconf": 184, "part": [11, 14, 21, 35, 39, 45, 47, 48, 49, 50, 58, 76, 78, 87, 88, 89, 109, 110, 111, 118, 119, 121, 150, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 184, 186, 187, 189, 191, 192, 195], "partial": [58, 59, 68, 131], "particip": 104, "particular": [67, 112, 125, 137, 138], "partner": [159, 186, 187], "pasid": 22, "pasidvld": 22, "pasiv": 151, "pass": [17, 18, 19, 21, 59, 71, 107, 109, 118, 144, 148, 164, 166, 185, 187, 195], "passiv": [125, 135, 136, 137, 138, 144, 149], "path": [0, 21, 27, 32, 47, 64, 66, 87, 107, 119, 122, 144, 150, 164, 166, 174, 184, 188, 195], "path_to_entity_1": 184, "path_to_entity_2": 184, "pattern": [67, 129, 144, 151], "paus": [65, 71, 76, 104, 183], "pause_queu": 71, "pause_request": 65, "payload": [62, 69, 114, 116, 183, 192, 195], "pc": [109, 111, 116, 170, 171, 172, 180, 187, 191, 192, 193, 195], "pcap": 148, "pci": [22, 42, 45, 46, 87, 112, 113, 115, 185, 189, 192], "pci0": 185, "pci_ext_cap": [185, 192, 198], "pcie": [22, 27, 33, 35, 39, 40, 41, 43, 45, 76, 112, 116, 118, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 184, 185, 186, 189, 191, 193], "pcie_10b_tag_req_en": 192, "pcie_byte_count": 114, "pcie_byte_en_decod": 115, "pcie_cc_hdr_gen": 117, "pcie_cc_meta_width": [116, 192], "pcie_cc_mfb2axi": 113, "pcie_clk": 192, "pcie_con": 192, "pcie_conf": [189, 192], "pcie_cq_": 45, "pcie_cq_axi2mfb": 113, "pcie_cq_hdr_depars": 117, "pcie_cq_meta_width": [41, 45, 46, 116, 192], "pcie_cq_mfb_block_s": [45, 46], "pcie_cq_mfb_data": [45, 46], "pcie_cq_mfb_dst_rdi": [45, 46], "pcie_cq_mfb_eof": [45, 46], "pcie_cq_mfb_eof_po": [45, 46], "pcie_cq_mfb_item_width": [45, 46], "pcie_cq_mfb_meta": [45, 46], "pcie_cq_mfb_region": [45, 46], "pcie_cq_mfb_region_s": [45, 46], "pcie_cq_mfb_sof": [45, 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196], "perceiv": 67, "percentag": [130, 139, 142], "percentig": 128, "perform": [0, 6, 11, 17, 19, 23, 25, 31, 68, 72, 104, 107, 109, 110, 111, 112, 121, 144, 160, 164, 166, 195], "perhap": 89, "period": [20, 31, 45, 58, 63, 71, 75, 107, 160, 164, 166, 183], "peripher": 23, "perman": [183, 187], "permiss": [39, 45], "permit": 113, "permut": 6, "pg213": 113, "ph": 113, "phandl": 185, "phase": [67, 128, 131, 139, 142, 143, 144, 150], "phase_sav": 166, "phoni": 166, "phy": [183, 187, 197], "phy_40g": 107, "physic": [107, 149, 186, 187, 194], "pick": [125, 137, 138], "pictur": [67, 87, 104, 110, 144, 187], "piec": 144, "pin": [107, 187], "pip": 178, "pip3": 174, "pipe": [44, 48, 61, 62, 69, 89, 95, 101, 116, 160, 162, 163, 164], "pipe_dsp": 160, "pipe_out": 89, "pipe_outreg": 89, "pipe_tree_add": 160, "pipe_typ": [58, 66, 86, 89], "piped_port": 61, "pipelin": [10, 17, 19, 59, 60, 66, 68, 83, 89, 107, 129, 144, 150, 164, 183], "pkg": [27, 144, 152, 184], "pkt": 35, "pkt_cnt_width": 49, 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"pma_xlaui_gti": 107, "pmci": [0, 185], "pmd": [107, 180, 185, 187, 191], "pmd0": 185, "pmd1": 185, "pmdctrl0": [0, 185], "pmdctrl1": [0, 185], "po": [60, 74], "pof": [171, 172], "point": [0, 17, 45, 60, 76, 80, 118, 150, 159, 184, 191], "pointer": [19, 34, 35, 37, 39, 41, 42, 44, 45, 46, 59, 67, 78, 144], "pointer_update_chan": 34, "pointer_update_data": 34, "pointer_update_en": 34, "pointer_width": [34, 35, 37, 39, 41, 43], "polar": [107, 180], "polynom": 130, "polynomi": 107, "pool": 150, "pop": 18, "pop_front": [144, 150], "popul": 185, "popular": 159, "port": [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 18, 20, 22, 27, 29, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 110, 113, 114, 115, 116, 117, 119, 120, 121, 125, 126, 127, 130, 131, 132, 137, 138, 144, 146, 147, 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189], "probability_set": [128, 139, 142], "probabl": [26, 128, 139, 142], "probe": [31, 58, 132, 188], "probe_event_component_": 150, "probe_if": 150, "probe_inf": 150, "probe_statu": 150, "problem": [11, 68, 131, 144, 160, 179, 187], "proc": 166, "procedur": [166, 170, 171, 172, 184], "process": [0, 11, 17, 19, 21, 22, 26, 33, 41, 58, 59, 60, 67, 76, 80, 88, 104, 110, 111, 113, 116, 119, 122, 128, 131, 138, 139, 142, 143, 144, 151, 159, 164, 166, 183, 184, 191], "processing_ord": 166, "processor": 60, "prodesign": 173, "produc": [88, 131], "product": [76, 166], "profession": [159, 186], "profile_filepath": 148, "profile_gener": 148, "profile_generator_config_filepath": 148, "profile_swap": 179, "program": 166, "programm": 170, "progress": 17, "proj_onli": [166, 178], "project": [87, 166, 178, 184, 185, 189], "promiscu": 109, "prop_rdi": 144, "propabl": 38, "propag": [11, 16, 17, 18, 19, 21, 46, 60, 64, 74, 75, 80, 88, 118, 119, 166, 184], "proper": [110, 183, 187, 189], "properli": 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"python": [0, 24, 25, 31, 32, 67, 174, 178, 179, 195], "python3": [0, 24, 25, 31, 32, 195], "p\u0159idat": 5, "qo": 183, "qsf": [179, 187], "qsfp": [107, 170, 172, 173, 174, 177, 180, 184, 185, 187, 191, 193, 194, 195], "qsfp28": [167, 168, 169, 175, 176, 194], "qsfp56": 171, "qsfp_i2c_dir": 180, "qsfp_i2c_port": 180, "qsfp_i2c_scl": 180, "qsfp_i2c_scl_i": 180, "qsfp_i2c_scl_o": 180, "qsfp_i2c_sda": 180, "qsfp_i2c_sda_i": 180, "qsfp_i2c_sda_o": 180, "qsfp_i2c_trist": 180, "qsfp_int_n": 180, "qsfp_lpmode": 180, "qsfp_modprs_n": 180, "qsfp_modsel_n": 180, "qsfp_port": 180, "qsfp_reset_n": 180, "qspf": 173, "qspi": [23, 193], "quad": 23, "quadrat": 11, "quadrupl": 183, "qualiti": 65, "quantum": 18, "quartu": [27, 120, 166, 170, 171, 172, 173, 174, 177, 185, 188, 189], "quartust": 166, "quasi": 43, "quest": [126, 127], "questa": 166, "question": 184, "queue": [6, 71, 150, 189, 194], "quick_reset_en": 11, "quicki": 139, "quickli": [128, 142, 143, 193, 195], "quiet": 166, "quit": 144, "r": [0, 29, 30, 31, 32, 39, 45, 67, 107, 109, 111, 119, 172, 174, 178, 183, 189, 191, 192], "r_tile": 192, "race": 144, "rais": [68, 184], "raise_object": 144, "ram": [2, 4, 14, 16, 26, 34, 35, 37, 39, 43, 44, 46, 82, 101], "ram_typ": [4, 5, 6, 77, 79, 82, 105], "ran": 151, "rand": [31, 32, 122, 123, 133, 134, 144], "rand_gen_addr_width": 31, "rand_gen_data_width": 31, "rand_length": 131, "rand_length_rand": 131, "rand_rdi": [131, 134], "rand_rdy_rand": 131, "random": [5, 31, 45, 89, 96, 122, 125, 128, 129, 130, 132, 135, 136, 137, 138, 139, 142, 143, 144, 146, 147, 149, 151, 152, 160], "random_addr_se": 31, "random_data_se": 31, "randomiz": [125, 137, 138], "randomli": [45, 125, 128, 137, 138, 142, 143, 144, 146, 151], "rang": [18, 22, 26, 31, 32, 59, 71, 89, 104, 121, 135, 136, 147, 148, 159, 179, 180, 183, 187, 191, 195, 196], "rapid": 159, "rate": [107, 159, 162, 186, 188, 195], "rate_limit": 67, "rather": [87, 188], "ratio": 1, "raw": [31, 32], "rc": [117, 192], "rc_mfb_block_siz": 192, "rc_mfb_item_width": 192, "rc_mfb_region": 192, "rc_mfb_region_s": 192, "rcb": 192, "rd": [5, 6, 31, 75, 87, 146, 150], "rd_addr": [13, 14, 16, 43], "rd_aempti": [4, 77], "rd_ch": 9, "rd_chan": 43, "rd_clk": [4, 16], "rd_data": [4, 13, 14, 16, 43], "rd_data_vld": [14, 16, 43], "rd_empti": 4, "rd_en": [4, 14, 16, 43, 77, 150], "rd_latenc": [13, 17], "rd_meta_in": [14, 16], "rd_meta_out": [14, 16], "rd_pipe_en": 16, "rd_ptr": 78, "rd_rst": [4, 16], "rd_statu": 4, "rd_val": 9, "rd_vld": 9, "rdw_behav": 13, "rdy": [131, 134, 135, 136, 141, 144], "re": [59, 67, 89, 118, 187], "reach": [17, 18, 19, 40, 46, 59, 65, 67, 118, 195], "react": 31, "read": [0, 4, 5, 9, 11, 13, 14, 16, 17, 18, 19, 22, 23, 24, 25, 26, 29, 30, 31, 32, 35, 37, 39, 42, 43, 44, 45, 58, 59, 65, 67, 76, 78, 80, 82, 83, 85, 87, 88, 90, 93, 101, 102, 106, 107, 109, 110, 111, 112, 116, 117, 118, 119, 121, 122, 128, 129, 139, 142, 144, 146, 151, 152, 156, 160, 161, 180, 185, 187, 188, 189, 191, 192, 195], "read_addr": 26, "read_box": 26, "read_box_vld": 26, "read_port": [6, 13, 14, 15], "read_prior": 26, "read_req": 26, "readabl": [144, 187], "readdata": 122, "readdatavalid": [83, 122], "readi": [4, 17, 29, 31, 47, 63, 66, 76, 77, 82, 83, 87, 90, 92, 94, 95, 96, 98, 102, 104, 109, 111, 113, 116, 121, 122, 133, 134, 147, 160, 164, 183, 186, 190], "readm": [27, 174, 188, 189], "real": [110, 112, 121, 166], "reali": 151, "realist": [31, 58], "realiti": 187, "realiz": [68, 87, 89], "realli": 87, "realtime_reg": 121, "rearrang": 54, "reason": [11, 17, 18, 19, 47, 68, 109, 111, 118, 122, 144, 151], "reboot": 193, "rebuild": 166, "recalcul": [67, 93], "receiv": [0, 18, 19, 24, 29, 30, 31, 34, 39, 40, 45, 60, 70, 76, 78, 87, 90, 91, 94, 99, 101, 104, 107, 109, 110, 113, 119, 121, 124, 134, 144, 146, 156, 159, 164, 166, 180, 188, 192, 193, 195, 197], "recent": 11, "recept": [193, 196], "reciev": [11, 85, 87], "recip": 184, "recipi": 87, "reciv": 145, "recogn": 76, "recomend": [18, 166], "recommend": [3, 5, 87, 129, 144, 166, 180, 183, 184, 187, 189, 195], "reconfigur": [162, 163, 179, 197], "record": 187, "record_max_numb": 148, "record_min_numb": 148, "recording_detail": 144, "recov": 107, "recreat": 59, "recurs": 166, "recv_bts_cnt_width": [37, 44], "recv_pkt_cnt_width": [37, 44], "redefin": 144, "redirect": 71, "redistribut": 59, "reduc": [19, 25, 31, 68, 88, 184, 185], "reduct": [19, 68], "ref": [107, 146], "ref_nam": 185, "refclk_in": 107, "refclk_n": 107, "refclk_out": 107, "refclk_p": 107, "refer": [7, 10, 83, 107, 129, 144, 167, 168, 169, 173, 183, 184, 185, 187, 189, 190, 194, 195], "referenc": 185, "reffer": 18, "reflect": 148, "reflexc": 159, "refr_ack": 31, "refr_period": 31, "refr_period_width": 31, "refr_req": 31, "refr_req_before_test": 31, "refresh": [31, 183], "reg": [25, 58, 66, 86, 118, 185], "reg0": [19, 21], "reg4": 19, "reg_bitmap": 120, "reg_fifo": 7, "reg_out_en": 38, "regard": [17, 184], "regardless": 87, "regarr0": [0, 185], "regarr1": [0, 185], "regino": 68, "region": [33, 36, 38, 42, 43, 45, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 79, 109, 111, 113, 116, 124, 128, 139, 142, 143, 144, 145, 164, 180, 183], "region_aux_en": 73, "region_numb": 60, "region_s": [36, 48, 49, 52, 55, 56, 57, 58, 61, 63, 66, 68, 70, 72, 73, 76, 79, 128, 142, 143, 144, 145, 180], "regions_s": [128, 142, 145], "regist": [3, 4, 6, 8, 10, 11, 13, 14, 16, 17, 18, 19, 21, 23, 25, 27, 29, 30, 31, 32, 37, 44, 46, 48, 49, 58, 59, 62, 67, 69, 71, 77, 85, 86, 87, 88, 89, 90, 91, 92, 94, 95, 101, 106, 107, 110, 112, 114, 118, 120, 121, 144, 156, 160, 161, 164, 180, 185, 187, 189, 191, 192, 193], "registr": 144, "regular": [59, 170, 184], "reimplement": [131, 144], "rel": [166, 185], "relat": [31, 76, 78, 144], "relax": [22, 117], "releas": [27, 118, 156, 159, 192], "relev": [18, 184], "reli": 166, "reliabl": 107, "remad": 166, "remain": [76, 77, 81, 110, 129, 147, 156, 167, 169], "remap": 119, "rememb": [67, 88], "remot": [23, 27], "remov": [6, 9, 12, 19, 27, 48, 68, 80, 109, 156, 160, 161, 164, 174, 185, 187, 188], "reorder": [101, 107], "repeat": [21, 29, 45, 67, 118, 144, 151, 195], "repeater_ctrl": 180, "repetit": [128, 139, 142, 143], "replac": [5, 89, 105, 115, 159, 186], "repli": [146, 185, 189], "replic": 14, "report": [5, 25, 45, 195], "report_gen": 31, "report_phas": 144, "repositori": [0, 2, 27, 109, 111, 148, 153, 154, 157, 158, 162, 163, 165, 166, 184, 185, 188, 197, 198], "repres": [5, 65, 67, 121, 133, 144, 179, 187], "represent": [5, 58, 185], "reprez": 131, "republ": 188, "req": [30, 144, 147, 151, 152], "reqest": 85, "requ": 87, "request": [0, 4, 6, 11, 14, 22, 23, 24, 25, 26, 29, 30, 31, 34, 35, 39, 40, 44, 45, 46, 58, 67, 71, 77, 82, 83, 85, 87, 88, 90, 102, 109, 111, 112, 113, 116, 117, 118, 119, 121, 122, 126, 127, 146, 152, 156, 164, 183, 186, 187, 189, 191, 192, 193, 195], "request_item_type_": 122, "request_typ": 122, "requier": 184, "requir": [0, 1, 5, 6, 11, 18, 29, 45, 58, 62, 67, 68, 75, 88, 89, 94, 100, 101, 109, 110, 111, 118, 119, 124, 128, 131, 139, 142, 143, 144, 145, 151, 160, 161, 166, 170, 171, 172, 174, 178, 180, 181, 184, 187, 188, 189, 192, 194, 195], "reserv": [39, 45, 49, 107, 109, 111, 112, 166, 191], "reset": [1, 3, 4, 5, 6, 8, 9, 10, 12, 13, 14, 16, 17, 18, 20, 25, 26, 30, 31, 32, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 78, 79, 80, 82, 83, 84, 85, 86, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 114, 116, 120, 121, 128, 131, 132, 135, 136, 139, 142, 143, 146, 150, 164, 180, 183, 192, 196], "reset_": 82, "reset_ag": 151, "reset_arb": 17, "reset_eth": [180, 183], "reset_if": 144, "reset_in": 78, "reset_log": 82, "reset_m": 82, "reset_meta": 78, "reset_out": 78, "reset_sync": [128, 139, 142, 143, 151], "reset_tim": 151, "reset_tree_gen": 164, "reset_us": [180, 183], "reset_user_x2": 183, "reset_user_x3": 183, "reset_user_x4": 183, "reset_v": 11, "reset_width": [180, 183], "resiz": [31, 68, 119], "resize_buff": 109, "resize_on_tx": 111, "resolut": [43, 68, 110], "resolv": 165, "resourc": [11, 19, 25, 31, 59, 60, 62, 68, 89, 98, 100, 101, 102, 109, 156, 160, 161, 185], "resp": 183, "respect": [5, 11, 23, 41, 58, 68, 87, 89, 104, 110, 159, 166, 184], "respond": [87, 116, 144, 146], "respones": 87, "respons": [17, 34, 83, 87, 101, 116, 118, 119, 123, 124, 132, 133, 134, 145, 146, 147, 152, 192], "rest": [31, 50, 58, 60, 166, 187], "restart": 67, "restor": 67, "restrict": [14, 17, 37, 39, 46, 52, 55, 66, 67, 76, 79, 144, 166], "result": [3, 10, 11, 13, 14, 17, 18, 27, 31, 59, 67, 74, 76, 107, 118, 131, 144, 164, 174, 187], "resum": [65, 71], "ret": [144, 151], "retriev": 129, "return": [67, 71, 87, 110, 131, 144, 150, 151, 166], "rev": 112, "revers": [49, 110, 148, 160, 187], "revis": [185, 189], "rework": 74, "rfc": 109, "rhel": 189, "righ": 34, "right": [8, 23, 58, 67, 71, 76, 87, 104, 109, 110, 126, 127, 130, 135, 136, 152, 160, 179, 187], "ring": [34, 35], "rise": [1, 29, 31, 147, 150, 160], "risk": 95, "ro": [67, 112, 121], "robin": [0, 49, 90, 164], "rocki": 189, "role": 183, "roll": 144, "rom": [116, 160, 193], "root": [144, 166, 192], "rotat": [8, 17, 59], "rough": 18, "round": [0, 6, 18, 49, 60, 68, 88, 90, 164], "rout": [0, 17, 22, 59, 89, 90, 107, 192], "router": [0, 165], "row": [17, 67], "row_item": 17, "rpm": [0, 27, 189], "rq": [33, 117, 192], "rq_mfb_block_siz": 192, "rq_mfb_item_width": 192, "rq_mfb_region": 192, "rq_mfb_region_s": 192, "rr": [49, 90], "rr_arbit": 164, "rsp": 152, "rsp_item_width": 101, "rst": [7, 20, 24, 25, 26, 28, 31, 32, 33, 36, 38, 49, 59, 63, 70, 79, 110, 144], "rst_ch": 9, "rst_done": [24, 25, 26], "rst_vld": 9, "rsu": 23, "rsvd": 90, "rtl": 188, "rule": [58, 76, 90, 104, 110, 122, 124, 144, 145, 150], "run": [0, 11, 17, 18, 27, 31, 32, 40, 67, 77, 78, 81, 107, 124, 125, 128, 129, 137, 138, 139, 142, 143, 145, 146, 148, 151, 152, 166, 173, 174, 178, 180, 184, 185, 186, 192, 194, 195], "run_phas": [131, 144, 150], "run_test": 144, "rw": [39, 45, 67, 109, 111, 112, 121], "rx": [0, 22, 33, 37, 45, 46, 48, 50, 54, 58, 59, 60, 61, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 74, 75, 77, 79, 81, 88, 90, 91, 92, 95, 96, 98, 99, 101, 102, 111, 123, 124, 129, 132, 133, 134, 144, 145, 147, 159, 166, 180, 183, 187, 188, 189, 194, 195, 197], "rx0": 94, "rx0_data": 94, "rx0_dst_rdy": 94, "rx0_fifo_en": 94, "rx0_item": 94, "rx0_item_width": 94, "rx0_mfb_data": 62, "rx0_mfb_dst_rdy": 62, "rx0_mfb_eof": 62, "rx0_mfb_eof_po": 62, "rx0_mfb_meta": 62, "rx0_mfb_sof": 62, "rx0_mfb_sof_po": 62, "rx0_mfb_src_rdy": 62, "rx0_mvb_dst_rdy": 62, "rx0_mvb_hdr": 62, "rx0_mvb_payload": 62, "rx0_mvb_src_rdy": 62, "rx0_mvb_vld": 62, "rx0_payload_en": 62, "rx0_src_rdy": 94, "rx0_vld": 94, "rx1": 94, "rx1_data": 94, "rx1_dst_rdy": 94, "rx1_item": 94, "rx1_item_width": 94, "rx1_mfb_data": 62, "rx1_mfb_dst_rdy": 62, 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124, 144, 147, 150], "sand": 147, "save": [19, 25, 29, 32, 100, 101, 135, 136, 144, 147, 160], "sc": [144, 185, 189], "sc_output_": 144, "scalabl": [17, 159, 193], "scale": [31, 102], "scan": 27, "scenario": [131, 144], "schemat": [171, 172], "scheme": [39, 45, 46, 166], "scienc": 188, "scope": [22, 166], "scoped_to_ref": 166, "scoreboard": [5, 131], "scoreboard_channel_head": 131, "scrambl": [107, 130, 149], "scrambler": [107, 130], "scrambler_gen": 107, "script": [24, 27, 31, 32, 67, 166, 170, 171, 172, 173, 179, 184, 185, 189, 195], "sdc": 179, "sdm": [153, 191], "sdp": [39, 45, 46], "sdp_bmem": 161, "sdp_bmem_v7": 161, "sdp_bram": [16, 161], "sdp_bram_b": 16, "sdp_bram_behav": 161, "sdp_bram_xilinx": 161, "sdp_memx": [160, 161], "sdp_rd_chan": 37, "sdp_rd_data": 37, "sdp_uram_xilinx": 161, "se": [31, 36], "search": [60, 107], "second": [18, 22, 35, 39, 45, 58, 59, 67, 68, 76, 87, 89, 104, 110, 120, 121, 128, 130, 131, 141, 142, 144, 147, 150, 152, 156, 159, 174, 183, 184, 185, 187, 196], "secondari": 68, "section": [17, 23, 67, 74, 83, 104, 107, 144, 152, 183, 184, 187], "section_length": 67, "sectionlength": 67, "secur": [14, 23], "see": [0, 5, 6, 11, 16, 17, 18, 22, 23, 25, 48, 65, 67, 68, 71, 75, 77, 79, 82, 83, 89, 90, 100, 104, 107, 109, 110, 111, 113, 119, 121, 125, 137, 138, 139, 142, 143, 144, 145, 148, 152, 159, 166, 167, 168, 169, 170, 171, 172, 174, 175, 176, 183, 184, 185, 186, 187, 190, 195], "seed": [31, 45], "seem": [11, 179], "seen": [17, 25, 189], "seg": 132, "segment": [34, 109, 111, 133, 187], "sel": [8, 30, 98], "sel_shakedown_en": 98, "select": [4, 5, 10, 14, 16, 17, 25, 29, 31, 32, 35, 48, 52, 54, 59, 69, 70, 71, 74, 77, 79, 82, 90, 91, 92, 98, 99, 105, 109, 111, 113, 116, 121, 125, 137, 138, 144, 146, 156, 166, 174, 180, 183, 184, 185, 187, 189, 193, 194, 195], "selected_queu": 71, "self": [107, 174], "send": [0, 8, 11, 14, 17, 21, 23, 31, 33, 45, 46, 49, 50, 57, 59, 60, 76, 78, 80, 85, 90, 101, 104, 108, 113, 116, 119, 122, 123, 124, 126, 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179, 183, 187, 188], "signaltap": 27, "signifi": [44, 76, 104], "signific": [67, 89], "significantli": [1, 29, 166], "silicom": 159, "sim": 166, "sim_flag": 144, "sim_lib": 166, "sim_modul": 166, "similar": [43, 87, 107, 110, 152, 156, 184], "similarli": [45, 166, 195], "simluat": 152, "simpl": [0, 6, 11, 39, 41, 43, 45, 46, 61, 62, 65, 67, 68, 76, 87, 89, 90, 102, 104, 106, 116, 124, 125, 131, 132, 137, 138, 144, 145, 147, 160, 162, 164, 166, 184, 187, 188, 190, 195], "simple_simpl": 144, "simpler": [1, 11, 161], "simplest": 110, "simpli": [12, 71, 144, 159, 166, 195], "simplic": [76, 110, 144], "simplifi": [58, 59, 67, 76, 104, 107, 110, 125, 128, 137, 138, 139, 142, 143, 144, 159, 174, 192, 193], "simul": [19, 31, 47, 67, 75, 139, 144, 147, 151, 164, 166, 195, 200], "simult": 31, "simultan": [0, 6, 11, 31, 54, 67, 76], "sinc": [11, 13, 17, 18, 19, 43, 68, 71, 80, 91, 118, 156, 161], "singl": [0, 1, 6, 8, 18, 19, 21, 40, 45, 60, 63, 67, 68, 70, 71, 76, 80, 89, 102, 104, 110, 113, 116, 135, 136, 138, 144, 159, 161, 166, 174, 180, 183, 192], "situat": [58, 68, 76, 88, 95, 110, 118, 144, 166], "six": [76, 146], "size": [5, 7, 8, 9, 17, 18, 19, 22, 34, 35, 37, 39, 44, 45, 46, 48, 50, 54, 55, 59, 60, 61, 62, 64, 65, 66, 67, 68, 69, 71, 72, 74, 75, 78, 79, 109, 111, 112, 114, 116, 125, 128, 131, 137, 138, 139, 142, 144, 146, 148, 150, 151, 152, 164, 180, 183, 185, 192, 195], "size_max": 144, "skid": 38, "skip": [58, 166], "slack": 183, "slave": [82, 84, 87, 90, 107, 109, 111, 116, 121, 122, 144, 146, 183], "slice": [25, 29, 156, 160], "slight": [64, 110], "slightli": [11, 17, 21, 144, 190], "slot": [189, 192, 193], "slow": [67, 164], "slower": [187, 188, 189], "slowest": 151, "slr_cross": 164, "slv_array_t": [13, 14, 15, 25, 31, 54, 59, 60, 63, 69, 70, 78, 85, 89, 93, 96, 98, 106, 183, 192], "small": [19, 59, 60, 76, 110, 131, 144, 161, 164, 185], "smaller": [3, 13, 31, 40, 68, 151], "smallest": [67, 75, 76], "smarter": 121, "snippet": 184, "snoop": 117, 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189, 190, 191, 192], "specifi": [3, 11, 18, 19, 22, 24, 26, 34, 38, 54, 55, 56, 58, 60, 74, 76, 80, 89, 104, 109, 126, 127, 131, 144, 149, 151, 166, 184, 185, 200], "speed": [45, 48, 58, 67, 71, 96, 107, 108, 109, 111, 119, 129, 144, 152, 159, 160, 179, 180, 185, 187, 188, 189, 193, 194, 195], "spent": 6, "spike": 17, "spkt_lng": 59, "spkt_size_min": 59, "split": [0, 36, 68, 69, 70, 71, 131, 166, 183, 187], "splitter": [144, 162, 163, 187, 193], "splitter_output": [69, 70], "squar": 160, "squarer": 160, "sr": [67, 160], "sr_sync_latch": [12, 160], "src": [49, 90, 102, 144, 173, 179, 184, 191], "src_buf": [17, 164], "src_buf_col": 17, "src_buf_rd_addr": 17, "src_buf_rd_data": 17, "src_buf_row": 17, "src_channel": 90, "src_rdy": [4, 47, 76, 102, 104, 144, 145, 147, 160, 192], "ss": 27, "st": 192, "st_sp_dbg_chan": [40, 45, 46], "st_sp_dbg_meta": [40, 45, 46], "st_sp_dbg_signal_w": [45, 46], "stabl": 107, "stage": [7, 10, 19, 59, 60, 70, 80, 86, 166, 184], "stai": [25, 49, 58, 63, 76, 80, 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7, 8, 9, 10, 12, 13, 14, 15, 16, 18, 20, 24, 25, 26, 28, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 84, 85, 86, 87, 89, 90, 91, 92, 93, 94, 95, 96, 98, 99, 100, 101, 102, 105, 106, 107, 109, 110, 111, 113, 114, 115, 116, 117, 120, 121, 180, 183, 185, 192], "stdarithnowarn": 144, "steadi": 67, "steer": 113, "stem": 166, "step": [19, 29, 35, 47, 129, 144, 152, 166, 179, 189, 195], "stick": 144, "still": [19, 57, 104, 119, 159, 186], "stop": [19, 35, 39, 42, 44, 45, 49, 67, 80, 110, 144, 183, 184], "stop_forc": 37, "stop_force_chan": 37, "stop_req_ack": [37, 40, 44], "stop_req_chan": [37, 40, 44], "stop_req_channel": 35, "stop_req_don": 35, "stop_req_vld": [35, 37, 40, 44], "storag": [118, 119], "store": [4, 5, 6, 10, 11, 13, 17, 18, 19, 21, 26, 34, 43, 45, 58, 59, 65, 67, 77, 80, 87, 93, 109, 111, 112, 118, 119, 126, 127, 133, 144, 150, 160, 164, 166, 185, 195], "stp": 27, "straddl": 113, "straight": [5, 67, 68, 105], "straightforward": 67, "strang": 144, "stratix": [23, 31, 109, 111, 156, 159, 161, 164, 187, 188, 189, 190, 192], "stratix10": [3, 4, 5, 9, 14, 16, 34, 35, 37, 44, 48, 49, 50, 54, 58, 60, 65, 69, 70, 71, 74, 75, 78, 79, 89, 94, 101, 105, 109, 111, 116, 117, 166, 180, 192], "stream": [0, 17, 19, 35, 46, 48, 54, 57, 60, 62, 63, 64, 67, 71, 74, 94, 107, 109, 111, 131, 144, 159, 162, 165, 180, 183, 186, 187, 192, 195], "stream2": 162, "stream_out_aful": 19, "stream_out_en": 19, "strech": 60, "stress": 45, "string": [3, 4, 5, 6, 9, 10, 13, 14, 15, 16, 18, 24, 28, 31, 33, 34, 35, 37, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 58, 59, 60, 61, 62, 64, 65, 66, 67, 68, 69, 70, 71, 74, 75, 77, 78, 79, 81, 82, 83, 84, 86, 89, 90, 91, 93, 94, 96, 98, 99, 100, 101, 102, 105, 106, 109, 111, 113, 116, 117, 121, 128, 131, 133, 139, 142, 143, 144, 150, 166, 180, 183, 185, 192], "strobe": [39, 45, 109, 111], "strongli": [144, 166, 183, 187], "struct": 144, "structur": [144, 152, 156, 160, 161, 166, 184, 185], "stuck": [116, 144, 152, 164, 183, 187], "su": 27, "subclass": [125, 137, 138, 144], "subcompon": [48, 111, 144, 166, 184, 185, 187, 191], "subcor": 0, "subdirectori": 166, "subenviron": 144, "sublay": 187, "submit": 25, "submodul": [109, 111, 185, 198], "subnod": 185, "subpart": 27, "subprocess": 166, "subsect": [152, 187], "subsequ": 187, "subset": [17, 71, 159], "substitut": 182, "subtract": 60, "success": [0, 31, 112, 144, 183], "successful": 38, "successfulli": [17, 109, 111, 144, 173, 189], "successor": 47, "suddenli": 67, "sudo": [27, 31, 174, 189], "suffici": [27, 76, 110], "suffix": [47, 58, 144, 166], "suggest": 184, "suit": [179, 187], "suitabl": [4, 13, 144, 156, 161], "sum": [18, 19, 25, 30, 60, 94], "sum_en": 25, "sum_extra_width": 25, "sum_on": 160, "sumbit": 25, "summar": 59, "super": [59, 128, 131, 139, 142, 143, 144, 150, 164], "superpacket": 60, "suppli": 166, "support": [4, 6, 10, 11, 13, 14, 16, 22, 23, 27, 32, 35, 42, 47, 48, 49, 54, 65, 67, 68, 71, 76, 83, 88, 90, 109, 110, 111, 113, 117, 119, 121, 156, 161, 162, 165, 166, 180, 184, 186, 187, 189, 190, 193, 194, 195], "supported_platform_tag": 166, "supported_tag": 166, "suppos": 62, "suppress": 144, "sure": [27, 67, 87, 129], "surpass": 67, "surpris": 87, "surround": 144, "sv": [32, 132, 144, 152], "sw": [0, 18, 32, 34, 37, 39, 44, 46, 67, 106, 109, 111, 179, 185, 195], "sw_addr": 106, "sw_addr_width": [37, 39], "sw_be": 106, "sw_din": 106, "sw_dout": 106, "sw_dout_vld": 106, "sw_read": 106, "sw_rst": 25, "sw_slice": 106, "sw_timeout_w": 96, "sw_timeout_width": 62, "sw_width": 106, "sw_write": 106, "swap": [74, 179], "switch": [17, 19, 27, 62, 63, 67, 69, 96, 109, 122, 144, 148, 162, 174, 186, 189, 195], "switchabl": 174, "swrite": [131, 144], "sychron": 132, "sync_": 151, "sync_cb": 151, "sync_connect": [128, 139, 142, 143, 151], "sync_regist": 151, "sync_reset": 151, "sync_termin": 151, "synchrnou": 12, "synchron": [1, 6, 16, 24, 47, 59, 90, 91, 92, 94, 96, 98, 99, 100, 107, 109, 111, 116, 128, 139, 142, 143, 151, 160, 164, 183, 196], "synchroni": 121, "syncrhon": 151, "syntax": 185, "synth": 166, "synth_onli": 166, "synthes": 166, "synthesi": [160, 184, 189], "synthesis": 166, "synthfil": 166, "sysmon": 191, "system": [23, 40, 112, 187, 189, 196], "systemverilog": [166, 200], "sythesi": 166, "t": [11, 17, 20, 25, 31, 32, 67, 76, 87, 88, 89, 107, 109, 121, 122, 128, 131, 133, 139, 142, 143, 144, 148, 149, 159, 166], "tabl": [31, 39, 45, 76, 89, 90, 104, 122, 123, 124, 125, 128, 134, 137, 138, 139, 142, 143, 144, 145, 152, 159, 160, 165, 183, 184, 187], "tabul": 144, "tag": [22, 113, 117, 119, 131, 144, 166, 192, 198], "tag_8": 117, "tag_9": 117, "tak": 151, "take": [5, 17, 19, 58, 64, 67, 75, 87, 88, 89, 104, 107, 110, 119, 126, 127, 129, 130, 144, 174, 183, 184, 185, 187, 194], "taken": [0, 19, 80, 98, 110], "talk": 89, "tap": [58, 144], "targ": 166, "target": [1, 3, 5, 11, 17, 18, 19, 27, 31, 46, 50, 54, 64, 67, 68, 78, 81, 83, 84, 87, 88, 89, 111, 117, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 187, 188, 189, 192, 193], "target_default": 166, "target_func": 117, "target_myproc": 166, "target_tag": 166, "task": [29, 107, 109, 111, 125, 126, 127, 131, 137, 138, 144, 146, 149, 150, 151, 152, 187, 192], "tb": 31, "tbd": [39, 180], "tcam": [22, 180, 183, 187], "tchannel": 131, "tcl": [27, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 185, 189, 191], "tclsh": 166, "tcp": 74, "tdata": [124, 139], "tdiscard": 131, "tdut": 144, "tehn": 14, "tehr": 130, "tell": [98, 122, 144], "temp": 191, "temperatur": [23, 164], "temporari": 59, "ten": 159, "term": [104, 185, 189, 194], "termin": [130, 149], "ternari": 161, "test": [0, 5, 31, 32, 45, 46, 58, 59, 102, 108, 113, 128, 131, 139, 142, 143, 150, 152, 154, 167, 168, 169, 180, 181, 183, 189, 190, 191], "test_mem_test": 31, "test_pci": 174, "testbench": [150, 152, 166], "tester": [154, 190], "texliv": 31, "text": [47, 144], "tfc": 111, "tfch": 111, "tfcl": 111, "th": 101, "than": [0, 1, 3, 4, 17, 25, 29, 31, 48, 54, 58, 59, 60, 67, 68, 76, 89, 101, 109, 111, 129, 144, 147, 160, 166, 184, 187, 188, 192, 193], "thank": [109, 111], "thei": [17, 19, 21, 36, 57, 58, 60, 71, 75, 76, 87, 89, 93, 94, 95, 101, 118, 128, 129, 131, 139, 142, 143, 144, 147, 160, 164, 183, 184, 185, 187, 195], "them": [0, 11, 18, 21, 25, 33, 36, 58, 59, 60, 64, 67, 68, 75, 80, 87, 89, 104, 107, 108, 110, 116, 118, 119, 126, 127, 128, 129, 138, 139, 141, 142, 143, 144, 146, 149, 152, 159, 179, 183, 184, 185, 187, 189, 190, 192], "themselv": [11, 174], "theoret": 87, "theori": 89, "ther": 130, "therefor": [18, 29, 31, 47, 52, 60, 67, 75, 76, 87, 89, 104, 121, 144, 186, 187, 194], "thesi": [1, 17, 19, 59, 119], "thi": [0, 1, 2, 3, 5, 6, 7, 10, 11, 12, 13, 14, 17, 18, 19, 20, 21, 23, 25, 27, 29, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 67, 68, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, 83, 84, 85, 87, 88, 89, 90, 91, 93, 94, 95, 98, 101, 102, 104, 106, 109, 110, 111, 113, 114, 115, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 180, 182, 183, 184, 185, 186, 187, 188, 189, 191, 192, 194, 195, 196, 197, 198, 200], "thing": [58, 60, 71, 76, 80, 144, 151, 184, 195], "think": 20, "third": [22, 35, 39, 45, 76, 87, 89, 144, 152, 183, 184, 187], "this_item": 144, "this_typ": 144, "those": [10, 11, 76, 87, 109, 110, 111, 125, 126, 127, 137, 144, 147, 166, 184], "though": [21, 76, 89, 183, 187], "three": [27, 62, 67, 76, 78, 87, 90, 104, 122, 124, 128, 131, 135, 136, 139, 142, 143, 144, 146, 149, 150, 151, 152, 184, 187, 190], "threshh": 144, "threshl": 144, "throgh": 20, "through": [4, 18, 19, 39, 45, 58, 67, 71, 75, 76, 77, 78, 80, 85, 87, 90, 106, 109, 111, 112, 121, 122, 123, 124, 125, 133, 134, 137, 138, 143, 144, 145, 164, 166, 183, 185, 186, 187, 188, 193, 195], "throughout": [183, 184, 191], "throughput": [0, 1, 17, 19, 21, 45, 46, 62, 67, 68, 75, 76, 93, 98, 119, 128, 139, 142, 143, 159, 180, 186, 187, 188, 190, 193, 195], "throught": [135, 136], "throw": [14, 16], "thrp_mea": 45, "thu": [13, 17, 18, 19, 23, 68, 76, 83, 184, 192], "ti": [109, 184], "tic": 48, "tick": [17, 24, 28, 30, 31, 67, 152], "tile": [76, 109, 111, 119, 170, 171, 172, 173, 174, 177, 180, 183, 187, 188, 192, 195], "tile_multir": 187, "till": [40, 87, 144], "time": [0, 4, 6, 11, 12, 14, 16, 18, 19, 21, 25, 26, 28, 31, 45, 58, 62, 65, 68, 71, 77, 80, 88, 90, 96, 100, 109, 110, 118, 121, 122, 131, 144, 148, 150, 151, 166, 179, 180, 184, 185, 187, 193], "time_array_add": 131, "time_reset": 65, "timeout": [17, 59, 62, 96, 131], "timeout_clk_no": 59, "timestamp": [22, 65, 109, 120, 121, 122, 153, 162, 180, 183, 187, 191], "timestamp_en": 109, "timestamp_format": 71, "timestamp_width": 71, "timestampvld": [22, 183, 187], "timestap": 183, "tkeep": 124, "tkeep_width": 124, "tlast": 124, "tlm": 144, "tlp": [22, 114], "tmeta": 131, "tmodel": 144, "tmp": [11, 25], "tmp_data": 144, "tmp_meta": 144, "to_unsign": 18, "todo": [5, 109, 144, 160, 164], "togeth": [17, 18, 21, 22, 68, 72, 80, 87, 89, 104, 112, 119, 128, 138, 141, 142, 144, 147, 151, 160, 166, 194], "too": [17, 75, 144, 184], "took": 149, "tool": [0, 25, 109, 111, 121, 144, 152, 159, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 183, 184, 185, 187, 188, 189, 191, 195, 196], "top": [0, 27, 46, 71, 132, 135, 136, 142, 166, 184, 185, 187, 190, 193], "top_level": [5, 144], "top_level_": 166, "top_level_archgrp": 166, "top_level_path": 166, "total": [0, 9, 11, 19, 27, 31, 37, 39, 40, 43, 44, 46, 54, 76, 90, 98, 109, 111, 192, 195], "total_error": 144, "tpacket_s": 131, "tph": 113, "tr": 144, "tr_dut": [131, 144], "tr_in_a": 131, "tr_in_b": 131, "tr_model": [131, 144], "tr_out": [131, 144], "tr_paket": 144, "tr_port": 144, "track": 17, "traffic": [18, 27, 65, 67, 125, 135, 136, 137, 138, 144, 149], "traget": [9, 37, 44], "tran": [17, 118, 164], "tranasciev": 149, "trans_a_col": 17, "trans_a_item": 17, "trans_b_col": 17, "trans_b_item": 17, "trans_comp_": 17, "trans_comp_dst_rdi": 17, "trans_comp_meta": 17, "trans_comp_src_rdi": 17, "trans_dst_rdi": 17, "trans_fifo_item": 17, "trans_fifo_s": [75, 111], "trans_len": 17, "trans_meta": 17, "trans_mtu": 17, "trans_sort": 164, "trans_src_rdi": 17, "trans_stream": 17, "trans_vld": 17, "transact": [17, 22, 29, 31, 33, 39, 41, 45, 46, 75, 76, 85, 87, 89, 91, 99, 100, 101, 102, 104, 106, 110, 111, 113, 114, 115, 117, 118, 125, 126, 127, 128, 129, 130, 131, 134, 135, 136, 137, 138, 139, 141, 142, 143, 144, 146, 149, 152, 164, 187, 191, 192, 193, 198], "transaction_count": 147, "transal": 116, "transceiv": [107, 166, 184, 185, 187], "transfer": [1, 11, 17, 45, 47, 67, 75, 76, 83, 87, 104, 106, 147, 159, 160, 164, 183, 186, 187, 188, 189, 191, 192, 193], "transform": [47, 68, 119, 129, 192], "transit": [67, 77, 82, 110, 132], "translat": [22, 27, 166, 185, 191], "transmiss": [47, 49, 65, 76, 91, 96, 100, 104, 110, 111, 144, 193, 194, 195], "transmit": [1, 22, 45, 65, 67, 70, 71, 76, 91, 98, 99, 101, 102, 104, 107, 109, 110, 111, 129, 149, 180, 192, 193, 194, 195, 196, 197], "transmitt": [76, 104], "transport": 35, "transs": 17, "trasfer": 113, "trasform": 162, "trbuf_fifo_en": 39, "trbuf_reg_en": [39, 46], "treadi": [124, 139], "treat": 47, "treatment": 179, "tree": [27, 39, 45, 135, 136, 160, 192], "trfc": 109, "trfch": 109, "trfcl": 109, "tri": [63, 160, 166, 187], "tricki": 67, "trigger": [4, 5, 6, 20, 59, 75, 77, 79, 81, 105, 150, 166], "trim": [52, 54], "trimmer": 162, "tripl": 183, "true": [3, 4, 6, 7, 8, 10, 13, 14, 16, 17, 24, 25, 26, 27, 38, 46, 48, 49, 57, 58, 61, 62, 63, 66, 69, 71, 73, 75, 77, 78, 82, 89, 90, 92, 95, 96, 98, 101, 102, 106, 109, 111, 116, 121, 144, 166, 180, 184], "truli": 133, "truncat": 54, "trx": 144, "try": [11, 31, 59, 89, 187, 188], "try_get": [128, 139, 142, 144], "try_next_item": 144, "ts_demo_en": 180, "ts_dv": 121, "ts_format": 65, "ts_mult_smart_dsp": 121, "ts_mult_use_dsp": 121, "ts_n": [120, 121], "ts_tsu": 120, "ts_width": 65, "tsel": 14, "tsu": [0, 22, 65, 71, 109, 159, 180, 183, 184, 185, 187, 193, 196], "tsu_clk": [180, 183, 196], "tsu_format_to_n": [120, 121], "tsu_gen": [121, 196], "tsu_reset": [183, 196], "tsu_rst": 180, "tsu_ts_dv": [109, 180], "tsu_ts_n": [109, 180, 183, 196], "tsu_ts_vld": [183, 196], "ttarget": 166, "ttarget_": 166, "ttarget_myproc": 166, "ttext": 144, "ttx": 144, "tune": [159, 166], "tunnig": 166, "turn": [5, 68, 107, 111, 187], "tuser": [117, 124, 139], "tuser_width": [124, 139], "tutori": 200, "tvalid": 124, "twice": [58, 68, 187], "two": [4, 5, 6, 14, 17, 21, 36, 39, 45, 47, 50, 54, 55, 56, 58, 60, 62, 63, 64, 67, 68, 69, 70, 71, 72, 73, 76, 77, 80, 81, 82, 86, 87, 89, 90, 94, 96, 98, 100, 104, 109, 110, 113, 118, 121, 122, 124, 125, 128, 129, 130, 131, 133, 135, 136, 137, 138, 139, 141, 142, 143, 144, 145, 146, 149, 151, 152, 156, 159, 161, 164, 166, 170, 179, 183, 184, 186, 187, 192], "tx": [0, 8, 22, 33, 44, 46, 48, 50, 54, 57, 58, 59, 60, 61, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 74, 75, 77, 79, 81, 88, 90, 91, 92, 94, 96, 98, 99, 101, 102, 109, 123, 124, 128, 129, 133, 134, 135, 136, 139, 142, 143, 144, 145, 147, 159, 180, 183, 187, 189, 194, 195, 197], "tx0_mfb_data": [69, 70], "tx0_mfb_dst_rdy": [69, 70], "tx0_mfb_eof": [69, 70], "tx0_mfb_eof_po": [69, 70], "tx0_mfb_meta": 70, "tx0_mfb_sof": [69, 70], "tx0_mfb_sof_po": [69, 70], "tx0_mfb_src_rdy": [69, 70], "tx0_mvb_dst_rdy": 69, "tx0_mvb_hdr": 69, "tx0_mvb_meta": 69, "tx0_mvb_payload": 69, "tx0_mvb_src_rdy": 69, "tx0_mvb_vld": 69, "tx1_mfb_data": [69, 70], "tx1_mfb_dst_rdy": [69, 70], "tx1_mfb_eof": [69, 70], "tx1_mfb_eof_po": [69, 70], "tx1_mfb_meta": 70, "tx1_mfb_sof": [69, 70], "tx1_mfb_sof_po": [69, 70], "tx1_mfb_src_rdy": [69, 70], "tx1_mvb_dst_rdy": 69, "tx1_mvb_hdr": 69, "tx1_mvb_meta": 69, "tx1_mvb_payload": 69, "tx1_mvb_src_rdy": 69, "tx1_mvb_vld": 69, "tx_": 187, "tx_addr": [85, 89], "tx_aempti": 77, "tx_ardi": [85, 89], "tx_be": 89, "tx_block_siz": [33, 68, 109, 111], "tx_block_vld": [59, 73], "tx_channel": [46, 90], "tx_channel_b": 59, "tx_chsum_bypass": 74, "tx_clk": [75, 77, 81, 109, 111, 166], "tx_compar": 144, "tx_compare_": 144, "tx_data": [7, 8, 47, 52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 94, 96, 98, 99, 101, 102, 105], "tx_data0": 94, "tx_data1": 94, "tx_data_in": 61, "tx_data_out": 61, "tx_dma_calypt": 45, "tx_dma_chan_start_stop_ctrl": 40, "tx_dma_channel": [48, 180], "tx_dma_metadata_extractor": 41, "tx_dma_pcie_trans_buff": 43, "tx_dma_pkt_dispatch": 42, "tx_dma_sw_manag": [40, 44], "tx_drd": [85, 89], "tx_drdy": [85, 89], "tx_dst_rdy": [7, 8, 47, 52, 55, 56, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 94, 96, 98, 99, 101, 105, 110], "tx_dst_rdy_in": 61, "tx_dst_rdy_out": 61, "tx_dwr": [85, 89], "tx_enabl": 57, "tx_env": 144, "tx_env_": 144, "tx_env_bas": 144, "tx_eof": [52, 55, 56, 57, 66, 68, 73, 77, 79, 81, 110], "tx_eof_in": 61, "tx_eof_mask": 58, "tx_eof_one_hot": 59, "tx_eof_origin": 58, "tx_eof_out": 61, "tx_eof_po": [52, 55, 56, 57, 58, 66, 68, 73, 77, 79, 81, 110], "tx_eof_pos_in": 61, "tx_eof_pos_out": 61, "tx_eof_unmask": 58, "tx_eop": [47, 72], "tx_eop_po": [47, 72], "tx_gen_en": 46, "tx_input": 144, "tx_input_data": 144, "tx_input_meta": 144, "tx_item": 102, "tx_item_vld": 73, "tx_item_width": [33, 68, 94, 109, 111], "tx_length": 60, "tx_link_up": 180, "tx_mac_lit": [111, 185, 187], "tx_mask": 58, "tx_meta": [52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 93], "tx_meta_in": 61, "tx_meta_out": 61, "tx_metadata": 8, "tx_mfb": 144, "tx_mfb_": 187, "tx_mfb_data": [33, 36, 38, 49, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 70, 71, 75, 78, 100, 109, 110, 111, 180], "tx_mfb_dst_rdy": [33, 36, 38, 49, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 70, 71, 75, 78, 100, 109, 110, 111, 180], "tx_mfb_eof": [33, 36, 38, 49, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 70, 71, 75, 78, 100, 109, 110, 111, 180], "tx_mfb_eof_po": [33, 36, 38, 49, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 70, 71, 75, 78, 100, 109, 110, 111, 180], "tx_mfb_meta": [33, 49, 60, 62, 63, 64, 65, 67, 70, 71, 75, 78, 100], "tx_mfb_meta_new": 64, "tx_mfb_sof": [33, 36, 38, 49, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 70, 71, 75, 78, 100, 109, 110, 111, 180], "tx_mfb_sof_po": [33, 36, 38, 49, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 70, 71, 75, 78, 100, 109, 110, 111, 180], "tx_mfb_src_rdy": [33, 36, 38, 49, 50, 54, 59, 60, 62, 63, 64, 65, 67, 69, 70, 71, 75, 78, 100, 109, 110, 111, 180], "tx_mfb_usermeta": 50, "tx_mvb_": 187, "tx_mvb_channel": [59, 78], "tx_mvb_data": [60, 69, 74, 109, 180], "tx_mvb_discard": 59, "tx_mvb_dst_rdy": [50, 54, 59, 60, 62, 69, 74, 78, 106, 109, 180], "tx_mvb_hdr": 62, "tx_mvb_hdr_meta": [59, 78], "tx_mvb_len": [59, 78], "tx_mvb_lut_addr": 106, "tx_mvb_lut_data": 106, "tx_mvb_meta": 74, "tx_mvb_metadata": 106, "tx_mvb_payload": [62, 69], "tx_mvb_src_rdy": [50, 54, 59, 60, 62, 69, 74, 78, 106, 109, 180], "tx_mvb_usermeta": [50, 54], "tx_mvb_vld": [50, 54, 59, 60, 62, 69, 74, 78, 106, 109, 180], "tx_mwr": 89, "tx_new_sof": 60, "tx_next": 102, "tx_offset": 60, "tx_old_sof": 60, "tx_op": 101, "tx_op_data": 101, "tx_op_data_consum": 101, "tx_op_dst_rdi": 101, "tx_op_src_rdi": 101, "tx_op_vld": 101, "tx_out": 144, "tx_out_": 144, "tx_output": 144, "tx_path_40g": 107, "tx_pkt_lng": 59, "tx_ptr_width": 46, "tx_rd": [85, 89], "tx_region": [33, 68, 72, 109, 111], "tx_region_s": [33, 68, 109, 111], "tx_region_shar": 73, "tx_region_vld": 73, "tx_reset": [75, 77, 81, 109, 111], "tx_respons": 101, "tx_response_vld": 101, "tx_sel_channel": 46, "tx_sof": [52, 55, 56, 57, 66, 68, 73, 77, 79, 81, 110], "tx_sof_in": 61, "tx_sof_mask": [58, 60], "tx_sof_one_hot": 59, "tx_sof_origin": 58, "tx_sof_out": 61, "tx_sof_po": [52, 55, 56, 57, 58, 66, 68, 73, 77, 79, 81], "tx_sof_pos_b": 59, "tx_sof_pos_in": 61, "tx_sof_pos_out": 61, "tx_sof_unmask": 58, "tx_sop": [47, 72], "tx_sop_po": [47, 72], "tx_src_rdy": [7, 8, 47, 52, 55, 56, 57, 58, 60, 66, 68, 72, 73, 77, 79, 81, 90, 91, 92, 93, 94, 96, 98, 99, 101, 105, 110], "tx_src_rdy_in": 61, "tx_src_rdy_origin": 58, "tx_src_rdy_out": 61, "tx_src_rdy_unmask": 58, "tx_statu": 77, "tx_valid": 93, "tx_vld": [90, 91, 92, 94, 96, 98, 99, 101, 102, 105], "tx_word": 60, "tx_wr": [85, 89], "txmac": [0, 185], "txmac0": [0, 185], "txmac1": [0, 185], "txn": 107, "txp": 107, "txpolar": 107, "txt": 178, "type": [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24, 25, 26, 28, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 81, 82, 83, 84, 85, 86, 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189, 192], "variabl": [11, 31, 124, 125, 128, 133, 137, 138, 139, 142, 143, 144, 145, 146, 147, 151, 160, 184], "variable_nam": 150, "variant": [1, 62, 109, 111, 113, 123, 153, 160, 161, 176, 185, 187, 189, 192], "variou": [46, 109, 110, 111, 112, 144, 156, 166, 184, 188], "vast": 87, "vcover": 144, "vcu118": 159, "vector": [18, 44, 59, 74, 76, 84, 101, 104, 128, 132, 139, 142, 146, 147, 160, 164], "vendor": [112, 159, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 184, 185, 192], "ver": 144, "ver_bas": 144, "verbos": [45, 144], "veri": [7, 17, 68, 71, 87, 128, 139, 142, 143, 144, 166, 184, 190], "verif": [67, 102, 122, 130, 131, 132, 135, 136, 146, 151, 152, 159, 166, 195], "verifi": [5, 45, 58, 62, 129, 144], "verilog": 166, "versa": [40, 109, 192], "versatil": 76, "version": [32, 59, 67, 77, 91, 111, 112, 156, 159, 161, 166, 170, 174, 177, 184, 185, 188, 189], "vfid": 22, "vhd": [10, 31, 144, 166, 184, 185, 191], "vhdl": [11, 112, 166, 185, 191, 192], "vhdl2008": 166, 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171, 172, 173, 174, 175, 176, 177, 189, 192], "x8": [46, 192], "x8x8": 192, "xanosecond": 121, "xci": 166, "xcku15p": 175, "xcu200": 167, "xcu55c": 168, "xcv": 192, "xcvr": 187, "xcvu7p": 166, "xcvu9p": [169, 176], "xdc": 166, "xgmii": [109, 111], "xilinx": [4, 5, 13, 66, 79, 86, 101, 105, 107, 109, 111, 113, 119, 134, 156, 160, 161, 164, 166, 167, 168, 169, 175, 176, 184, 187, 188, 189, 190, 192], "xlgmii": [107, 109, 111], "xlgmii_clk": 107, "xlgmii_rxc": 107, "xlgmii_rxd": 107, "xlgmii_txc": 107, "xlgmii_txd": 107, "xmii": 129, "xml": 32, "xnor": 160, "xor": 160, "xor48": 160, "xp": 67, "xpm_cdc": 166, "xpm_fifo": 166, "xpm_memori": 166, "xpm_memory_sdpram": 161, "xpresssx": 159, "xscn": 67, "xvc_enabl": 192, "xx": 87, "xxx_root_directori": [0, 189, 191, 195], "xz": [112, 185], "yaml": 148, "ye": [146, 170, 174, 175, 176, 177, 188], "yet": [4, 83, 87, 159, 186, 187, 195, 196], "you": [0, 6, 8, 11, 14, 17, 19, 20, 23, 24, 25, 27, 31, 67, 68, 71, 85, 87, 89, 90, 95, 109, 111, 122, 124, 128, 131, 139, 142, 143, 144, 145, 148, 151, 152, 154, 159, 160, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 179, 183, 184, 185, 186, 187, 188, 189, 192, 195], "your": [0, 11, 24, 27, 31, 67, 71, 95, 122, 131, 152, 159, 178, 183, 184, 188, 189, 195], "your_card": 189, "your_ndk_firmwar": 189, "yourself": [11, 19], "yourselv": 89, "yum": 31, "zero": [0, 11, 14, 28, 31, 47, 49, 109, 144, 149], "zeroth": 76}, "titles": ["Minimal NDK application", "Asynchronous modules", "Basic Tools", "DSP Comparator", "ASFIFOX", "FIFOX", "FIFOX Multi", "Register FIFO", "Barrel Shifter", "Multi MEMx Counter", "H3 Class Hash", "N_LOOP_OP", "Synchronous SR latch", "Live value table memory", "Multi-port BRAM", "NP LUT RAM", "Simple dual-port BRAM", "CrossbarX", "Event Counter", "Packet Planner", "Pulse short", "Transaction Sorter", "Packages", "SDM CLIENT", "Mem logger", "Data logger", "Histogramer", "JTAG-over-protocol Client", "Latency meter", "AMM_GEN", "AMM_PROBE", "DDR4 Memory Tester", "MEM_TESTER Software", "Header Insertor", "Address Manager", "Header Manager", "Input Buffer", "Software Manager", "Transaction Buffer", "RX DMA Calypte", "Channel Start/stop control", "Metadata Extractor", "Packet Dispatcher", "Transaction buffer", "Software Manager", "TX DMA Calypte", "DMA Calypte", "FLU bus specification", "Gen Loop Switch (GLS)", "MFB Generator", "MFB FRAME EXTENDER", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "MFB FRAME TRIMMER", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "CROSSBARX STREAM2", "MFB Cutter Simple", "MFB Dropper", "MFB Enabler", "MFB Frame Masker", "Frame Packer", "Frame Unpacker", "MFB Loopback", "MFB Merger", "MFB Merger Simple", "Metadata Insertor", "Packet Delayer", "MFB PIPE", "Rate Limiter", "MFB Reconfigurator", "MFB Splitter", "MFB Splitter Simple", "Timestamp Limiter", "MFB Trasformer", "MFB Auxiliary Signals", "Checksum Calculator", "CrossbarX Stream", "MFB specification", "MFB ASFIFOX", "Crossbarx Output Buffer", "MFB FIFOX", "MFB Packet Discard ASFIFO", "MFB PD ASFIFO SIMPLE", "MI ASYNC", "MI2AVMM", "MI2AXI4", "MI indirect access", "MI Pipe", "MI bus specification", "MI Reconfigurator", "MI Splitter Plus Gen", "MVB Channel Router", "MVB DEMUX", "MVB DISCARD", "MVB Item Collision Resolver", "MVB Merge Items", "SHAKEDOWN", "MVB Merge Streams", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "MVB Merge Streams Ordered", "MVB MUX", "MVB2MFB", "MVB Operation", "MVB Shakedown", "The verification of this component will be designed and implemented as part of the bachelor\u2019s thesis.", "MVB Specification", "MVB FIFOX", "MVB Lookup Table", "40GE Ethernet PHY for Ultrascale+ FPGAs", "BUFFER", "RX MAC LITE", "MFB -> LBUS reconfigurator (TX LBUS)", "TX MAC LITE", "PCI_EXT_CAP", "PCIE CONVERSION UNITS", "PCIE Byte Count", "PCIe Byte Enable Decoder", "MTC (MI Transaction Controller)", "PCIE Header parsing/deparsing", "PTC Tag Manager", "PTC (PCIe Transaction Controller)", "TSU Format to ns Convertor", "TSU GEN", "AVMM Agent", "AVST CRDT Agent", "AXI Agent", "Byte Array agent", "Byte Array to LII convert enviroment", "Byte Array to LII convert enviroment", "Byte_array_mfb environment", "Byte array to MII transitional environment", "Byte array to pma convert enviroment", "Common package", "Components", "Intel MAC SEG", "LBUS Agent", "LII agent", "LII agent", "Logic vector agent", "Logic Vector Array agent", "logic_vector_array_axi environment", "byte array to MAC SEG", "LOGIC VECTOR ARRAY LBUS Environment", "logic_vector_array_mfb environment", "logic_vector_mvb environment", "SystemVerilog and UVM tutorial", "MFB Agent", "MI agent", "MVB agent", "FlowTest Sequence", "PMA agent", "probe agent", "RESET agent", "UVM simulation", "Controllers & TSU", "Debug Tools", "DSP components", "FIFO components", "FL Tools", "FLU Tools", "Overview", "Basic logic elements", "Memory modules", "MFB Tools", "MI Tools", "Miscellaneous", "MVB Components", "Build System", "AMD Alveo U200", "AMD Alveo U55C", "AMD VCU118@VU9P", "Bittware IA-420F", "Intel Stratix 10 DX FPGA DK", "Intel Agilex I-Series FPGA DK", "PRO DESIGN Falcon", "ReflexCES XpressSX AGI-FH400G", "Silicom fb2CGhh@KU15P", "Silicom fb4CGg3@VU9P", "Silicom N6010", "Cocotb toplevel simulation core", "F-Tile Multirate IP", "NETWORK MODULE", "BUFFER", "CRDT Agent", "The Application", "Configuration files and parameters", "Device Tree", "The DMA module", "The Network Module", "Frequently Asked Questions", "How to start", "The Memory Controller", "The MI bus interconnect", "The PCIe module", "NDK Architecture", "NDK Terminology", "NDK testing", "Time Stamp Unit", "Network Tools", "PCIe Tools", "Shift registers", "UVM Verification"], "titleterms": {"": [51, 53, 97, 103], "1": [39, 45, 58, 76, 85, 89, 104, 110, 166, 179, 187], "10": 171, "2": [45, 76, 89, 104, 110, 166, 187], "3": [89, 110, 166, 187], "4": [110, 166, 187], "40ge": 107, "420f": 170, "5": 110, "6": 110, "A": 87, "The": [0, 51, 53, 97, 103, 166, 183, 186, 187, 190, 191, 192], "ab": 89, "access": [85, 183, 187, 195], "ad": 184, "adapt": [109, 111], "add": 166, "addinputfil": 166, "addit": [11, 19, 80], "addr_bas": 89, "address": [25, 27, 34, 67, 85, 89, 107, 112, 191], "advanc": 166, "agent": [122, 123, 124, 125, 134, 135, 136, 137, 138, 144, 145, 146, 147, 149, 150, 151, 182], "agi": 174, "agilex": 172, "alloc": 191, "also": 188, "alveo": [167, 168], "amd": [167, 168, 169], "amm_gen": 29, "amm_prob": 30, "an": [188, 189], "app_conf": 184, "applic": [0, 159, 183, 184, 187, 188, 189], "ar": [188, 189], "architectur": [17, 18, 19, 21, 29, 31, 59, 68, 80, 88, 89, 107, 109, 111, 119, 193], "arcitectur": 60, "arrai": [125, 126, 127, 129, 130, 137, 138, 140, 141, 166], "asfifo": [80, 81], "asfifox": [4, 77], "ask": 188, "async": 82, "asynchron": [1, 156], "author": 184, "auxiliari": 73, "avail": 188, "avmm": 122, "avst": 123, "axi": 124, "bachelor": [51, 53, 97, 103], "barrel": 8, "base": 189, "basic": [2, 144, 160], "batch": 166, "behavior": 6, "between": 188, "bind": 150, "bit": 89, "bittwar": 170, "block": [4, 5, 6, 11, 17, 23, 47, 60, 65, 71, 75, 118, 119], "board": 174, "boot": [170, 171, 172, 173], "bram": [14, 16], "bu": [29, 30, 31, 47, 87, 135, 136, 149, 159, 191], "buffer": [36, 38, 43, 78, 108, 181], "build": [166, 179, 184, 185, 188, 189], "byte": [16, 114, 115, 125, 126, 127, 129, 130, 140], "byte_array_mfb": 128, "byte_array_port": 144, "c": 32, "calcul": 74, "callback": 150, "calypt": [39, 45, 46], "can": [184, 188], "captur": 18, "card": [112, 159, 184, 185, 188, 189], "card_conf": 184, "card_const": 184, "card_nam": 184, "ce_gener": 129, "channel": [40, 90, 194], "channel_align": 129, "check": 189, "checksum": 74, "chip": [166, 188], "class": [10, 122, 131], "client": [23, 27], "clock": [156, 188], "cocotb": 178, "code": [47, 144], "collis": 93, "common": [131, 144], "commun": 188, "comp": 166, "compar": [3, 131], "compon": [24, 25, 26, 28, 31, 44, 51, 53, 58, 97, 103, 119, 132, 155, 156, 165, 166, 184, 185], "config": [133, 147], "configur": [46, 67, 76, 119, 125, 128, 137, 138, 139, 142, 143, 144, 148, 166, 180, 184, 192], "constant": 184, "constraint": 68, "contact": 184, "content": [2, 153, 154, 158, 162, 163, 165, 197, 198, 200], "control": [24, 25, 29, 30, 31, 39, 40, 45, 110, 116, 119, 153, 186, 188, 190, 192], "convers": 113, "convert": [126, 127, 130], "convertor": 120, "copi": 47, "core": [178, 179, 184, 187, 192], "core_bootstrap": 184, "core_conf": 184, "core_const": 184, "corundum": 188, "count": 114, "counter": [9, 18], "coverag": 144, "crdt": [123, 182], "creat": 144, "crossbarx": [17, 54, 75, 78], "cutter": 55, "data": [25, 68], "data_buff": 129, "ddr4": 31, "debug": [27, 154], "decod": 115, "delay": 65, "demux": 91, "depars": 117, "depend": [184, 189], "descript": [24, 25, 26, 28, 31, 76, 87, 104, 135, 136, 149, 166, 184], "design": [51, 53, 97, 103, 166, 173, 184], "develop": [185, 188], "devic": [112, 167, 168, 169, 185], "diagram": [4, 5, 6, 11, 17, 23, 47, 60, 65, 71, 75, 76, 87, 104, 118, 119], "differ": 188, "differnt": 89, "direct": 141, "discard": [80, 92], "dispatch": 42, "distribut": 49, "dk": [171, 172], "dma": [39, 45, 46, 183, 186, 188, 194], "do": [184, 188], "doc": 180, "doe": 188, "dr": 184, "driver": [135, 136, 144, 147, 149], "dropper": 56, "dsp": [3, 155], "dt": 185, "dtb": 185, "dual": [16, 156], "dx": 171, "effect": 68, "element": 160, "enabl": [16, 57, 115], "endpoint": 112, "entiti": [180, 192], "env": 129, "enviro": [126, 127, 130], "environ": [128, 129, 139, 141, 142, 143, 144], "eof_po": 76, "ethernet": [107, 183, 188, 194], "evalfil": 166, "event": 18, "exampl": [47, 49, 58, 76, 89, 104, 110, 144, 148, 152, 166, 185], "extend": 50, "extra": 112, "extractor": 41, "f": 179, "falcon": 173, "fb2cghh": 175, "fb4cgg3": 176, "fdo": 144, "featur": [11, 18, 19, 24, 25, 26, 28, 31, 80, 166], "few": 87, "fh400g": 174, "fifo": [7, 131, 144, 156], "fifox": [5, 6, 79, 105], "file": [166, 184], "final": 166, "firmwar": [167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 185, 188, 189], "fl": 157, "flow": 11, "flowtest": 148, "flu": [47, 158], "forc": 80, "format": [120, 196], "fpga": [107, 171, 172, 185, 188, 189], "frame": [50, 52, 58, 59, 60], "frequenc": 188, "frequent": 188, "from": [183, 187], "full": 25, "function": [76, 144], "further": [184, 189], "gen": [48, 63, 69, 70, 89, 121], "gener": [17, 24, 25, 26, 28, 31, 32, 40, 41, 43, 44, 45, 47, 49, 76, 104, 105, 109, 111, 135, 136, 144, 148, 149, 183, 185], "given": 184, "gl": [48, 195], "guidelin": 47, "h3": 10, "hard": 192, "hash": 10, "have": 188, "header": [33, 35, 117], "hierarchi": 166, "high": 144, "histogram": 26, "host": 189, "how": [152, 183, 187, 189], "hw": 27, "i": [172, 184, 188], "ia": 170, "id": 112, "idl": 110, "implemen": 166, "implement": [51, 53, 97, 103, 166, 179, 188], "implementdesign": 166, "includ": 184, "incomplet": 166, "index": 76, "indirect": 85, "init": 166, "initi": 170, "inner": [128, 139, 142, 143], "input": [36, 144], "insertor": [33, 64], "instanc": [24, 25, 26, 28], "instruct": [170, 171, 172, 173], "integr": 185, "intel": [133, 171, 172], "interconnect": 191, "interfac": [6, 107, 135, 136, 144, 147, 149, 150, 183, 187, 188], "intern": [29, 31], "ip": [179, 186, 192], "ipg_gener": 129, "irrelev": 89, "iso": 188, "item": [93, 94, 122, 123, 125, 133, 134, 135, 136, 137, 138, 147, 149, 166], "jtag": 27, "jumbo": 188, "kei": [24, 25, 26, 28, 31], "kit": 188, "ku15p": 175, "lane": 194, "latch": 12, "latenc": 28, "layer": 144, "lbu": [110, 134, 141], "level": [139, 144], "librari": [134, 144, 159], "lii": [126, 127, 135, 136], "limit": [67, 71], "list": [166, 189], "lite": [109, 111, 187], "live": 13, "load": 189, "local": [35, 39, 45, 46], "locat": 185, "logger": [24, 25], "logic": [122, 137, 138, 141, 160, 187], "logic_vector_array_axi": 139, "logic_vector_array_mfb": 142, "logic_vector_mvb": 143, "lookup": 106, "loop": 48, "loopback": 61, "low": [128, 139, 142, 143, 144], "lut": 15, "mac": [109, 111, 133, 140, 187], "machin": 110, "main": [144, 191], "make": 189, "makefil": [166, 184], "manag": [34, 35, 37, 44, 107, 118], "map": [89, 109, 111], "mask": 89, "masker": 58, "medusa": 186, "mem": 24, "mem_test": 32, "memori": [0, 13, 31, 161, 190], "memory_model": 122, "memx": 9, "merg": [94, 96, 98], "merge_n_to_m": 95, "merger": [62, 63], "meta": 152, "metadata": [41, 64], "meter": 28, "methodologi": 144, "mfb": [49, 50, 52, 55, 56, 57, 58, 61, 62, 63, 66, 68, 69, 70, 72, 73, 76, 77, 79, 80, 81, 110, 145, 152, 162], "mi": [0, 25, 29, 30, 31, 82, 85, 86, 87, 88, 89, 116, 146, 152, 163, 191], "mi2avmm": 83, "mi2axi4": 84, "mii": 129, "minim": 0, "miscellan": 164, "mk": 184, "mod": 166, "model": 144, "modul": [1, 144, 159, 161, 166, 180, 183, 184, 186, 187, 192, 195], "monitor": [125, 126, 127, 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144, "vivado": 184, "vld": 104, "vu9p": [169, 176], "w": 195, "warn": 148, "warp": 25, "what": [184, 188, 189], "word_realign": 110, "work": [184, 189], "wrapper": 129, "write": [6, 183], "xpresssx": 174}}) \ No newline at end of file diff --git a/devel/shift.html b/devel/shift.html index 8d6e64f4b..a80f1c2e3 100644 --- a/devel/shift.html +++ b/devel/shift.html @@ -1,52 +1,134 @@ - - - - - - - - Shift registers — NDK-FPGA Docs documentation - - - - - - - - - + + + + + + + Shift registers — NDK-FPGA documentation + + + + + + - - - - - - -
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    UVM Verification

    New verifications should be written in UVM methodology. This directory contains common agents and environments. Only the highly specified code such as model should be in directory with component.

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