diff --git a/.editorconfig b/.editorconfig index a2594f358..128377312 100644 --- a/.editorconfig +++ b/.editorconfig @@ -10,7 +10,7 @@ charset = utf-8 indent_style = tab # Ignore section -[*.{pcap,ip}] +[*.{pcap,ip,qsys}] end_of_line = unset insert_final_newline = unset trim_trailing_whitespace = unset diff --git a/VERSION b/VERSION index bcaffe19b..faef31a43 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -0.7.0 \ No newline at end of file +0.7.0 diff --git a/apps/minimal/build/dk-dev-1sdx-p/app_conf.tcl b/apps/minimal/build/dk-dev-1sdx-p/app_conf.tcl index 8cff3e639..143767eab 100644 --- a/apps/minimal/build/dk-dev-1sdx-p/app_conf.tcl +++ b/apps/minimal/build/dk-dev-1sdx-p/app_conf.tcl @@ -19,7 +19,7 @@ set DMA_TX_CHANNELS 16 # In blocking mode, packets are dropped only when the RX DMA channel is off. # In non-blocking mode, packets are dropped whenever they cannot be sent. set DMA_RX_BLOCKING_MODE true -# Special example of 400G DMA, Ethernet is not connected to DMA and must be set +# Special example of 400G DMA, Ethernet is not connected to DMA and must be set # special PCIe config.: 2x PCIe Gen4 x8x8, requires PCIe expansion connector. set DMA_400G_DEMO false diff --git a/apps/minimal/build/pd-falcon/Makefile b/apps/minimal/build/pd-falcon/Makefile index f93a65a96..f4fee5490 100644 --- a/apps/minimal/build/pd-falcon/Makefile +++ b/apps/minimal/build/pd-falcon/Makefile @@ -22,4 +22,4 @@ all: 100g2 100g2: OUTPUT_NAME:=$(OUTPUT_NAME)-100g2 100g2: build -include $(CARD_BASE)/src/card.mk \ No newline at end of file +include $(CARD_BASE)/src/card.mk diff --git a/apps/minimal/tests/cocotb/cocotb_test.py b/apps/minimal/tests/cocotb/cocotb_test.py index 909d73fbc..3ed169518 100644 --- a/apps/minimal/tests/cocotb/cocotb_test.py +++ b/apps/minimal/tests/cocotb/cocotb_test.py @@ -1,13 +1,16 @@ import sys import cocotb -import logging -from cocotb.triggers import Timer, RisingEdge, Combine, Join, First, with_timeout +#import logging +from cocotb.triggers import Timer from ndk_core import NFBDevice import cocotbext.ofm.utils.sim.modelsim as ms import cocotb.utils +from cocotbext.ofm.utils.sim.bus import MfbBus, MiBus, DmaUpMvbBus, DmaDownMvbBus + + e = cocotb.external st = cocotb.utils.get_sim_time @@ -30,7 +33,7 @@ async def test_mi_access_unaligned(dut): #for i in range(46, 64): # FIXME: Test fails (for US+) for i in range(24, 42): for x in range(0, 5): - data = bytes([(j%256) for j in range(i)]) + data = bytes([(j % 256) for j in range(i)]) await e(c.write)(x, data) rdata = await e(c.read)(x, len(data)) assert data == rdata, f"{list(data)}, {list(rdata)}" @@ -85,6 +88,7 @@ async def _test_ndp_sendmsg(dut, dev=None, nfb=None): await e(eth.txmac.enable)() pkt = bytes([i for i in range(72)]) + def eth_tx_monitor_cb(p): print(len(p), bytes(p).hex()) #assert bytes(p) == pkt @@ -93,7 +97,7 @@ def eth_tx_monitor_cb(p): count = 1 for i in range(count): - pkt = bytes([(i%256) for i in range(72 + i)]) + pkt = bytes([(i % 256) for i in range(72 + i)]) await e(nfb.ndp.tx[0].sendmsg)([(pkt, bytes(), 0)]) await Timer(20, units='us') @@ -117,7 +121,7 @@ def eth_tx_monitor_cb(p): pkts = range(20, 28) for i in pkts: - pkt = bytes([(i%256) for i in range(72 + i)]) + pkt = bytes([(i % 256) for i in range(72 + i)]) await e(nfb.ndp.tx[0].sendmsg)([(pkt, bytes(), 0)]) await Timer(15, units='us') @@ -134,8 +138,6 @@ async def test_ndp_send_msgs(dut): await _test_ndp_sendmsg_burst(dut, dev, nfb) -from cocotbext.ofm.utils.sim.bus import * - core = NFBDevice.core_instance_from_top(cocotb.top) pcic = core.pcie_i.pcie_core_i diff --git a/apps/minimal/tests/cocotb/issues/issue1.py b/apps/minimal/tests/cocotb/issues/issue1.py index f1d549f8c..de61ee2a8 100644 --- a/apps/minimal/tests/cocotb/issues/issue1.py +++ b/apps/minimal/tests/cocotb/issues/issue1.py @@ -1,14 +1,10 @@ -import sys -import logging - import cocotb import cocotb.utils -from cocotb.triggers import Timer, RisingEdge, Combine, Join, First, with_timeout +from cocotb.triggers import Timer, RisingEdge, First -import cocotbext.ofm.utils.sim.modelsim as ms import cocotbext.ofm.utils.sim.modelsim as ms -from cocotbext.ofm.utils.sim.bus import * +from cocotbext.ofm.utils.sim.bus import MfbBus, DmaDownMvbBus from cocotbext.ofm.utils.scapy import simple_tcp_bytes from ndk_core import NFBDevice diff --git a/apps/minimal/tests/cocotb/issues/issue2.py b/apps/minimal/tests/cocotb/issues/issue2.py index 6a845f5a9..d85b60caf 100644 --- a/apps/minimal/tests/cocotb/issues/issue2.py +++ b/apps/minimal/tests/cocotb/issues/issue2.py @@ -1,14 +1,9 @@ -import sys -import logging - import cocotb import cocotb.utils -from cocotb.triggers import Timer, RisingEdge, Combine, Join, First, with_timeout import cocotbext.ofm.utils.sim.modelsim as ms -from cocotbext.ofm.utils.sim.bus import * -from cocotbext.ofm.utils.scapy import simple_tcp_bytes +from cocotbext.ofm.utils.sim.bus import MiBus from ndk_core import NFBDevice @@ -17,13 +12,15 @@ e = cocotb.external st = cocotb.utils.get_sim_time + def ms_add_cursor(name, time=None): if time is None: time = st() - ms.cmd(f"wave cursor add") + ms.cmd("wave cursor add") ms.cmd(f'wave cursor configure -name {{{name}}} -time {{{time}}} -lock 1') + async def get_dev_init(dut): dev = NFBDevice(dut) await dev.init() @@ -31,7 +28,7 @@ async def get_dev_init(dut): async def wr_rd(c, length, offset=0): - data = bytes([(j%256) for j in range(length)]) + data = bytes([(j % 256) for j in range(length)]) await e(c.write)(offset, data) rdata = await e(c.read)(offset, length) assert rdata == data, f'writen: {list(data)}, readen: {list(rdata)}' @@ -45,10 +42,6 @@ async def mtc_big_write_tr(dut): await wr_rd(c, 126, 3) - - - - core = NFBDevice.core_instance_from_top(cocotb.top) core_path = ms.cocotb2path(core) diff --git a/apps/minimal/top/app_subcore.vhd b/apps/minimal/top/app_subcore.vhd index 11cdbab3e..3447d4948 100644 --- a/apps/minimal/top/app_subcore.vhd +++ b/apps/minimal/top/app_subcore.vhd @@ -42,11 +42,11 @@ port ( -- ========================================================================= CLK : in std_logic; RESET : in std_logic; - + -- ========================================================================= -- DMA INTERFACES -- ========================================================================= - + -- MFB+MVB interface to DMA module (to software) -- ------------------------------------------------------------------------- DMA_RX_MVB_LEN : out std_logic_vector(MFB_REGIONS*log2(USR_PKT_SIZE_MAX+1)-1 downto 0); @@ -65,7 +65,7 @@ port ( DMA_RX_MFB_EOF_POS : out std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0); DMA_RX_MFB_SRC_RDY : out std_logic; DMA_RX_MFB_DST_RDY : in std_logic; - + -- MFB+MVB interface from DMA module (from software) -- ------------------------------------------------------------------------- -- MVB interface (aligned to SOF) @@ -89,7 +89,7 @@ port ( -- ========================================================================= -- ETH INTERFACES -- ========================================================================= - + -- MFB+MVB interface with incoming network packets -- ------------------------------------------------------------------------- -- MVB interface with packet headers (aligned to EOF) @@ -117,7 +117,7 @@ port ( ETH_TX_MFB_EOF_POS : out std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0); ETH_TX_MFB_SRC_RDY : out std_logic; ETH_TX_MFB_DST_RDY : in std_logic; - + -- ========================================================================= -- MI INTERFACE -- ========================================================================= @@ -222,7 +222,7 @@ begin RX_MVB_VLD => DMA_TX_MVB_VLD, RX_MVB_SRC_RDY => DMA_TX_MVB_SRC_RDY, RX_MVB_DST_RDY => DMA_TX_MVB_DST_RDY, - + RX_MFB_DATA => DMA_TX_MFB_DATA, RX_MFB_SOF => DMA_TX_MFB_SOF, RX_MFB_EOF => DMA_TX_MFB_EOF, @@ -230,7 +230,7 @@ begin RX_MFB_EOF_POS => DMA_TX_MFB_EOF_POS, RX_MFB_SRC_RDY => DMA_TX_MFB_SRC_RDY, RX_MFB_DST_RDY => DMA_TX_MFB_DST_RDY, - + TX_MFB_DATA => ethi_tx_mfb_data, TX_MFB_META_NEW => ethi_tx_mfb_hdr, TX_MFB_SOF => ethi_tx_mfb_sof, diff --git a/apps/minimal/top/application_core.vhd b/apps/minimal/top/application_core.vhd index d470f88ae..17c0821bc 100644 --- a/apps/minimal/top/application_core.vhd +++ b/apps/minimal/top/application_core.vhd @@ -135,7 +135,7 @@ architecture FULL of APPLICATION_CORE is signal split_mi_wr : std_logic_vector(MI_PORTS-1 downto 0); signal split_mi_ardy : std_logic_vector(MI_PORTS-1 downto 0) := (others => '0'); signal split_mi_drd : slv_array_t (MI_PORTS-1 downto 0)(MI_DATA_WIDTH-1 downto 0); - signal split_mi_drdy : std_logic_vector(MI_PORTS-1 downto 0) := (others => '0'); + signal split_mi_drdy : std_logic_vector(MI_PORTS-1 downto 0) := (others => '0'); begin @@ -210,7 +210,7 @@ begin port map( CLK => APP_CLK, RESET => APP_RESET(0), - + RX_DWR => sync_mi_dwr, RX_ADDR => sync_mi_addr, RX_BE => sync_mi_be, @@ -301,7 +301,7 @@ begin DMA_TX_MFB_EOF_POS => app_dma_tx_mfb_eof_pos_deser(i), DMA_TX_MFB_SRC_RDY => app_dma_tx_mfb_src_rdy_deser(i), DMA_TX_MFB_DST_RDY => app_dma_tx_mfb_dst_rdy_deser(i), - + ETH_RX_MVB_DATA => eth_rx_mvb_data_deser(i), ETH_RX_MVB_VLD => eth_rx_mvb_vld_deser(i), ETH_RX_MVB_SRC_RDY => ETH_RX_MVB_SRC_RDY(i), @@ -314,7 +314,7 @@ begin ETH_RX_MFB_EOF_POS => eth_rx_mfb_eof_pos_deser(i), ETH_RX_MFB_SRC_RDY => ETH_RX_MFB_SRC_RDY(i), ETH_RX_MFB_DST_RDY => ETH_RX_MFB_DST_RDY(i), - + ETH_TX_MFB_DATA => eth_tx_mfb_data_deser(i), ETH_TX_MFB_HDR => eth_tx_mfb_hdr_deser(i), ETH_TX_MFB_SOF => eth_tx_mfb_sof_deser(i), @@ -323,7 +323,7 @@ begin ETH_TX_MFB_EOF_POS => eth_tx_mfb_eof_pos_deser(i), ETH_TX_MFB_SRC_RDY => ETH_TX_MFB_SRC_RDY(i), ETH_TX_MFB_DST_RDY => ETH_TX_MFB_DST_RDY(i), - + MI_DWR => split_mi_dwr(i), MI_ADDR => split_mi_addr(i), MI_BE => split_mi_be(i), @@ -538,7 +538,7 @@ begin HBM_AXI_BRESP => HBM_AXI_BRESP, HBM_AXI_BVALID => HBM_AXI_BVALID, HBM_AXI_BREADY => HBM_AXI_BREADY, - + DDR_CLK => MEM_CLK, DDR_RESET => MEM_RST, DDR_AVMM_READY => MEM_AVMM_READY, @@ -558,7 +558,7 @@ begin EMIF_CAL_SUCCESS => EMIF_CAL_SUCCESS, EMIF_CAL_FAIL => EMIF_CAL_FAIL, EMIF_AUTO_PRECHARGE => EMIF_AUTO_PRECHARGE, - + MI_DWR => split_mi_dwr(ETH_STREAMS), MI_ADDR => split_mi_addr(ETH_STREAMS), MI_BE => split_mi_be(ETH_STREAMS), diff --git a/apps/minimal/top/mem_tester_wrap.vhd b/apps/minimal/top/mem_tester_wrap.vhd index a518a950f..0e51dae17 100644 --- a/apps/minimal/top/mem_tester_wrap.vhd +++ b/apps/minimal/top/mem_tester_wrap.vhd @@ -60,7 +60,7 @@ port ( -- ========================================================================= CLK : in std_logic; RESET : in std_logic; - + -- ========================================================================= -- HBM AXI INTERFACES (clocked at HBM_CLK) -- ========================================================================= @@ -217,7 +217,7 @@ begin port map( CLK => CLK, RESET => RESET, - + RX_DWR => MI_DWR, RX_ADDR => MI_ADDR, RX_BE => MI_BE, @@ -251,7 +251,7 @@ begin MI_DATA_WIDTH => MI_DATA_WIDTH, MI_ADDR_WIDTH => MI_ADDR_WIDTH, - + RAND_GEN_DATA_WIDTH => MT_RND_GEN_DATA_WIDTH, RAND_GEN_ADDR_WIDTH => MT_RND_GEN_ADDR_WIDTH, RANDOM_DATA_SEED => ddr_random_data_seed_f, @@ -267,7 +267,7 @@ begin port map( AMM_CLK => DDR_CLK (i), AMM_RST => DDR_RESET (i), - + AMM_READY => DDR_AVMM_READY (i), AMM_READ => DDR_AVMM_READ (i), AMM_WRITE => DDR_AVMM_WRITE (i), @@ -287,8 +287,8 @@ begin EMIF_CAL_SUCCESS => EMIF_CAL_SUCCESS (i), EMIF_CAL_FAIL => EMIF_CAL_FAIL (i), EMIF_AUTO_PRECHARGE => EMIF_AUTO_PRECHARGE (i), - - MI_CLK => CLK, + + MI_CLK => CLK, MI_RST => RESET, MI_DWR => split_mi_dwr (i), MI_ADDR => split_mi_addr (i), @@ -331,7 +331,7 @@ begin ); ddr_logger_i : entity work.MEM_LOGGER - generic map ( + generic map ( MEM_DATA_WIDTH => DDR_DATA_WIDTH , MEM_ADDR_WIDTH => DDR_ADDR_WIDTH , MEM_BURST_COUNT_WIDTH => DDR_BURST_WIDTH , @@ -339,10 +339,10 @@ begin MI_DATA_WIDTH => MI_DATA_WIDTH , MI_ADDR_WIDTH => MI_ADDR_WIDTH ) - port map ( + port map ( CLK => DDR_CLK (i), RST => DDR_RESET (i), - + MEM_READY => DDR_AVMM_READY (i), MEM_READ => DDR_AVMM_READ (i), MEM_WRITE => DDR_AVMM_WRITE (i), @@ -351,7 +351,7 @@ begin MEM_WRITE_DATA => DDR_AVMM_WRITEDATA (i), MEM_BURST_COUNT => DDR_AVMM_BURSTCOUNT (i), MEM_READ_DATA_VALID => DDR_AVMM_READDATAVALID (i), - + MI_DWR => ddr_log_mi_dwr (i), MI_ADDR => ddr_log_mi_addr (i), MI_BE => ddr_log_mi_be (i), diff --git a/apps/minimal/uvm/env/model.sv b/apps/minimal/uvm/env/model.sv index 14f017892..217ecb501 100644 --- a/apps/minimal/uvm/env/model.sv +++ b/apps/minimal/uvm/env/model.sv @@ -1,7 +1,7 @@ /* * file : model_minimal.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: Model create expectated output from input. + * description: Model create expectated output from input. * date : 2021 * author : Radek Iša * @@ -65,7 +65,7 @@ class model #(ETH_STREAMS, ETH_CHANNELS, ETH_RX_HDR_WIDTH, DMA_STREAMS, DMA_RX_C packet = uvm_app_core::packet #(DMA_HDR_META_WIDTH, DMA_RX_CHANNELS, DMA_PKT_MTU, ITEM_WIDTH)::type_id::create("packet", this); packet.start = item.start; - packet.data = item.data; + packet.data = item.data; packet.meta = '0; if (DMA_STREAMS != ETH_STREAMS) begin packet.channel = (index*APP_RX_CHANNELS) + eth_to_dma[index].port_get(item.channel%ETH_CHANNELS); @@ -98,7 +98,7 @@ class model #(ETH_STREAMS, ETH_CHANNELS, ETH_RX_HDR_WIDTH, DMA_STREAMS, DMA_RX_C packet = uvm_app_core::packet #(0, 2**ETH_TX_CHANNEL_WIDTH, 2**ETH_TX_LENGTH_WIDTH-1, ITEM_WIDTH)::type_id::create("packet", this); packet.start = item.start; eth_channel = ((index * DMA_TX_CHANNELS) + item.channel)/((DMA_STREAMS*DMA_TX_CHANNELS)/(ETH_STREAMS*ETH_CHANNELS)); - packet.channel = eth_channel; + packet.channel = eth_channel; packet.discard = 1'b0; packet.data = item.data; diff --git a/apps/minimal/uvm/test_pkg.sv b/apps/minimal/uvm/test_pkg.sv index 3462b7a91..9b9c5f1d0 100644 --- a/apps/minimal/uvm/test_pkg.sv +++ b/apps/minimal/uvm/test_pkg.sv @@ -1,7 +1,7 @@ /* * file : test_pkg.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: DUT configuration file. This file contains top level generic paramet + * description: DUT configuration file. This file contains top level generic paramet * date : 2021 * author : Radek Iša * diff --git a/apps/minimal/uvm/testbench.sv b/apps/minimal/uvm/testbench.sv index cdbe0f190..908587aaa 100644 --- a/apps/minimal/uvm/testbench.sv +++ b/apps/minimal/uvm/testbench.sv @@ -15,7 +15,7 @@ import uvm_pkg::*; module testbench; ///////////////////////// - // PARAMETRIZE TESTS + // PARAMETRIZE TESTS typedef test::base#(test_pkg::ETH_STREAMS, test_pkg::ETH_CHANNELS, test_pkg::ETH_PKT_MTU, test_pkg::ETH_RX_HDR_WIDTH, test_pkg::ETH_TX_HDR_WIDTH, test_pkg::DMA_STREAMS, test_pkg::DMA_RX_CHANNELS, test_pkg::DMA_TX_CHANNELS, test_pkg::DMA_HDR_META_WIDTH, test_pkg::DMA_PKT_MTU, test_pkg::REGIONS, test_pkg::MFB_REG_SIZE, test_pkg::MFB_BLOCK_SIZE, test_pkg::MFB_ITEM_WIDTH, test_pkg::MEM_PORTS, test_pkg::MEM_ADDR_WIDTH, test_pkg::MEM_BURST_WIDTH, test_pkg::MEM_DATA_WIDTH, test_pkg::MI_DATA_WIDTH, test_pkg::MI_ADDR_WIDTH) test_base; diff --git a/apps/minimal/uvm/tests/base.sv b/apps/minimal/uvm/tests/base.sv index 249bf8e8e..324f5e664 100644 --- a/apps/minimal/uvm/tests/base.sv +++ b/apps/minimal/uvm/tests/base.sv @@ -1,7 +1,7 @@ /* * file : test.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: base test + * description: base test * date : 2021 * author : Radek Iša * diff --git a/apps/minimal/uvm/tests/fifo.sv b/apps/minimal/uvm/tests/fifo.sv index c8f1ffad0..c6e665033 100644 --- a/apps/minimal/uvm/tests/fifo.sv +++ b/apps/minimal/uvm/tests/fifo.sv @@ -1,7 +1,7 @@ /* * file : test.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: base test + * description: base test * date : 2021 * author : Radek Iša * diff --git a/apps/minimal/uvm/tests/full_speed.sv b/apps/minimal/uvm/tests/full_speed.sv index 5af982921..d2038e29d 100644 --- a/apps/minimal/uvm/tests/full_speed.sv +++ b/apps/minimal/uvm/tests/full_speed.sv @@ -1,7 +1,7 @@ /* * file : test.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: base test + * description: base test * date : 2021 * author : Radek Iša * diff --git a/cards/README.md b/cards/README.md index 6e7329f78..967c62f2d 100644 --- a/cards/README.md +++ b/cards/README.md @@ -15,4 +15,4 @@ Unless otherwise noted, the content of this repository is available under the BS ## Repository Maintainer -- Jakub Cabal, cabal@cesnet.cz \ No newline at end of file +- Jakub Cabal, cabal@cesnet.cz diff --git a/cards/amd/alveo-u200/constr/pcie_half.xdc b/cards/amd/alveo-u200/constr/pcie_half.xdc index 2638767e6..d9b2b3f30 100644 --- a/cards/amd/alveo-u200/constr/pcie_half.xdc +++ b/cards/amd/alveo-u200/constr/pcie_half.xdc @@ -44,8 +44,8 @@ set_property PACKAGE_PIN BD21 [get_ports {PCIE_SYSRST_N}] set_property IOSTANDARD LVCMOS12 [get_ports {PCIE_SYSRST_N}] set_property PULLUP true [get_ports {PCIE_SYSRST_N}] -set_property PACKAGE_PIN AM11 [get_ports {PCIE_SYSCLK_P}] -set_property PACKAGE_PIN AM10 [get_ports {PCIE_SYSCLK_N}] +set_property PACKAGE_PIN AM11 [get_ports {PCIE_SYSCLK_P}] +set_property PACKAGE_PIN AM10 [get_ports {PCIE_SYSCLK_N}] create_clock -period 10.000 -name pcie_clk_p -waveform {0.000 5.000} [get_ports {PCIE_SYSCLK_P}] diff --git a/cards/amd/alveo-u200/constr/qsfp.xdc b/cards/amd/alveo-u200/constr/qsfp.xdc index 7c7d6dfe1..8a037cf26 100644 --- a/cards/amd/alveo-u200/constr/qsfp.xdc +++ b/cards/amd/alveo-u200/constr/qsfp.xdc @@ -12,18 +12,18 @@ set_property PACKAGE_PIN BE21 [get_ports {QSFP0_INT_N}] set_property PACKAGE_PIN AV21 [get_ports {QSFP1_INT_N}] set_property IOSTANDARD LVCMOS12 [get_ports {QSFP?_INT_N}] set_property PULLUP true [get_ports {QSFP?_INT_N}] - + set_property PACKAGE_PIN BD18 [get_ports {QSFP0_LPMODE}] set_property PACKAGE_PIN AV22 [get_ports {QSFP1_LPMODE}] set_property IOSTANDARD LVCMOS12 [get_ports {QSFP?_LPMODE}] set_property SLEW SLOW [get_ports {QSFP?_LPMODE}] set_property DRIVE 8 [get_ports {QSFP?_LPMODE}] - + set_property PACKAGE_PIN BE20 [get_ports {QSFP0_MODPRS_N}] set_property PACKAGE_PIN BC19 [get_ports {QSFP1_MODPRS_N}] set_property IOSTANDARD LVCMOS12 [get_ports {QSFP?_MODPRS_N}] set_property PULLUP true [get_ports {QSFP?_MODPRS_N}] - + set_property PACKAGE_PIN BE17 [get_ports {QSFP0_RESET_N}] set_property PACKAGE_PIN BC18 [get_ports {QSFP1_RESET_N}] set_property IOSTANDARD LVCMOS12 [get_ports {QSFP?_RESET_N}] @@ -44,13 +44,13 @@ set_property SLEW SLOW [get_ports {QSFP?_RESET_N}] #set_property SLEW SLOW [get_ports {QSFP?_FREQ_SEL[*]}] #set_property DRIVE 8 [get_ports {QSFP?_FREQ_SEL[*]}] -#TODO I2C +#TODO I2C #set_property PACKAGE_PIN B8 [get_ports {QSFP0_SCL}] #set_property PACKAGE_PIN C9 [get_ports {QSFP1_SCL}] #set_property IOSTANDARD LVCMOS12 [get_ports {QSFP?_SCL}] #set_property DRIVE 4 [get_ports {QSFP?_SCL}] #set_property SLEW SLOW [get_ports {QSFP?_SCL}] -# +# #set_property PACKAGE_PIN B7 [get_ports {QSFP0_SDA}] #set_property PACKAGE_PIN D8 [get_ports {QSFP1_SDA}] #set_property IOSTANDARD LVCMOS12 [get_ports {QSFP?_SDA}] diff --git a/cards/amd/alveo-u200/src/fpga.vhd b/cards/amd/alveo-u200/src/fpga.vhd index 3af53b762..e29ddab44 100644 --- a/cards/amd/alveo-u200/src/fpga.vhd +++ b/cards/amd/alveo-u200/src/fpga.vhd @@ -32,7 +32,7 @@ port ( PCIE_TX_P : out std_logic_vector(PCIE_LANES -1 downto 0); PCIE_TX_N : out std_logic_vector(PCIE_LANES -1 downto 0); - -- 156.250 MHz external clock + -- 156.250 MHz external clock SYSCLK_P : in std_logic; SYSCLK_N : in std_logic; @@ -83,12 +83,12 @@ architecture FULL of FPGA is constant ETH_LANE_RXPOLARITY : std_logic_vector(2*ETH_LANES-1 downto 0) := "00000000"; constant ETH_LANE_TXPOLARITY : std_logic_vector(2*ETH_LANES-1 downto 0) := "00000000"; constant DEVICE : string := "ULTRASCALE"; - + signal sysclk_ibuf : std_logic; signal sysclk_bufg : std_logic; signal sysrst_cnt : unsigned(4 downto 0) := (others => '0'); signal sysrst : std_logic := '1'; - + signal eth_refclk_p : std_logic_vector(2-1 downto 0); signal eth_refclk_n : std_logic_vector(2-1 downto 0); signal eth_rx_p : std_logic_vector(2*ETH_LANES-1 downto 0); @@ -142,7 +142,7 @@ begin end process; -- QSFP MAPPING ------------------------------------------------------------ - eth_refclk_p <= QSFP1_REFCLK_P & QSFP0_REFCLK_P; + eth_refclk_p <= QSFP1_REFCLK_P & QSFP0_REFCLK_P; eth_refclk_n <= QSFP1_REFCLK_N & QSFP0_REFCLK_N; eth_rx_p <= QSFP1_RX_P & QSFP0_RX_P; @@ -187,7 +187,7 @@ begin PLL_OUT3_DIV => 12, USE_PCIE_CLK => false, - + PCIE_LANES => PCIE_LANES, PCIE_CLKS => PCIE_CLKS, PCIE_CONS => PCIE_CONS, diff --git a/cards/amd/alveo-u200/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci b/cards/amd/alveo-u200/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci index 762ba2cd0..44f0a1781 100644 --- a/cards/amd/alveo-u200/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci +++ b/cards/amd/alveo-u200/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci @@ -1248,4 +1248,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci b/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci index 839d28f6b..2c272f72e 100644 --- a/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci +++ b/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci @@ -1721,4 +1721,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci b/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci index ccfca29bb..08782b8df 100644 --- a/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci +++ b/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci @@ -1721,4 +1721,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u200/src/ip/xvc_vsec/xvc_vsec.xci b/cards/amd/alveo-u200/src/ip/xvc_vsec/xvc_vsec.xci index 975f804ab..ecafec99e 100644 --- a/cards/amd/alveo-u200/src/ip/xvc_vsec/xvc_vsec.xci +++ b/cards/amd/alveo-u200/src/ip/xvc_vsec/xvc_vsec.xci @@ -137,4 +137,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/fpga.vhd b/cards/amd/alveo-u55c/src/fpga.vhd index f2054b584..ec20dbf76 100644 --- a/cards/amd/alveo-u55c/src/fpga.vhd +++ b/cards/amd/alveo-u55c/src/fpga.vhd @@ -24,7 +24,7 @@ use unisim.vcomponents.all; entity FPGA is port ( - -- 100 MHz external clocks + -- 100 MHz external clocks SYSCLK2_P : in std_logic; SYSCLK2_N : in std_logic; SYSCLK3_P : in std_logic; @@ -68,7 +68,7 @@ port ( QSFP_STA_LED_G : out std_logic_vector(1 downto 0); QSFP_STA_LED_Y : out std_logic_vector(1 downto 0); - -- HBM CATTRIP + -- HBM CATTRIP HBM_CATTRIP : out std_logic ); end entity; @@ -94,7 +94,7 @@ architecture FULL of FPGA is constant HBM_LEN_WIDTH : natural := 4; constant HBM_SIZE_WIDTH : natural := 3; constant HBM_RESP_WIDTH : natural := 2; - + signal sysclk_ibuf : std_logic; signal sysclk_bufg : std_logic; signal sysrst_cnt : unsigned(4 downto 0) := (others => '0'); @@ -102,7 +102,7 @@ architecture FULL of FPGA is signal pcie_ref_clk_p : std_logic_vector(PCIE_CLKS-1 downto 0); signal pcie_ref_clk_n : std_logic_vector(PCIE_CLKS-1 downto 0); - + signal eth_refclk_p : std_logic_vector(2-1 downto 0); signal eth_refclk_n : std_logic_vector(2-1 downto 0); signal eth_rx_p : std_logic_vector(2*ETH_LANES-1 downto 0); @@ -1272,7 +1272,7 @@ architecture FULL of FPGA is DRAM_0_STAT_CATTRIP : OUT STD_LOGIC; DRAM_0_STAT_TEMP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); DRAM_1_STAT_CATTRIP : OUT STD_LOGIC; - DRAM_1_STAT_TEMP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + DRAM_1_STAT_TEMP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); end component; @@ -1303,7 +1303,7 @@ begin end process; -- QSFP MAPPING ------------------------------------------------------------ - eth_refclk_p <= QSFP1_REFCLK_P & QSFP0_REFCLK_P; + eth_refclk_p <= QSFP1_REFCLK_P & QSFP0_REFCLK_P; eth_refclk_n <= QSFP1_REFCLK_N & QSFP0_REFCLK_N; eth_rx_p <= QSFP1_RX_P & QSFP0_RX_P; @@ -1433,7 +1433,7 @@ begin PLL_OUT3_DIV => 12, USE_PCIE_CLK => False, - + PCIE_LANES => PCIE_LANES, PCIE_CLKS => PCIE_CLKS, PCIE_CONS => PCIE_CONS, diff --git a/cards/amd/alveo-u55c/src/ip/axi_quad_spi/axi_quad_spi_0.xci b/cards/amd/alveo-u55c/src/ip/axi_quad_spi/axi_quad_spi_0.xci index 4be952d6f..4fff89566 100644 --- a/cards/amd/alveo-u55c/src/ip/axi_quad_spi/axi_quad_spi_0.xci +++ b/cards/amd/alveo-u55c/src/ip/axi_quad_spi/axi_quad_spi_0.xci @@ -864,4 +864,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci b/cards/amd/alveo-u55c/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci index 4d61d4af8..1da2e2adc 100644 --- a/cards/amd/alveo-u55c/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci +++ b/cards/amd/alveo-u55c/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci @@ -1248,4 +1248,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/ip/hbm/hbm_ip.xci b/cards/amd/alveo-u55c/src/ip/hbm/hbm_ip.xci index ac8f76a60..dd69dc249 100644 --- a/cards/amd/alveo-u55c/src/ip/hbm/hbm_ip.xci +++ b/cards/amd/alveo-u55c/src/ip/hbm/hbm_ip.xci @@ -6725,4 +6725,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/ip/pcie_gen3_x16/pcie4_uscale_plus.xci b/cards/amd/alveo-u55c/src/ip/pcie_gen3_x16/pcie4_uscale_plus.xci index 20b751e64..440963f64 100644 --- a/cards/amd/alveo-u55c/src/ip/pcie_gen3_x16/pcie4_uscale_plus.xci +++ b/cards/amd/alveo-u55c/src/ip/pcie_gen3_x16/pcie4_uscale_plus.xci @@ -1801,4 +1801,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/ip/pcie_gen3_x8ll/pcie4_uscale_plus.xci b/cards/amd/alveo-u55c/src/ip/pcie_gen3_x8ll/pcie4_uscale_plus.xci index e30a2e65d..5466f8e36 100644 --- a/cards/amd/alveo-u55c/src/ip/pcie_gen3_x8ll/pcie4_uscale_plus.xci +++ b/cards/amd/alveo-u55c/src/ip/pcie_gen3_x8ll/pcie4_uscale_plus.xci @@ -1801,4 +1801,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus/pcie4_uscale_plus.xci b/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus/pcie4_uscale_plus.xci index 01ca4d290..03b6b1313 100644 --- a/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus/pcie4_uscale_plus.xci +++ b/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus/pcie4_uscale_plus.xci @@ -1801,4 +1801,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus_1/pcie4_uscale_plus_1.xci b/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus_1/pcie4_uscale_plus_1.xci index 58a9bf3f8..0f6694d92 100644 --- a/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus_1/pcie4_uscale_plus_1.xci +++ b/cards/amd/alveo-u55c/src/ip/pcie_gen4_x8/pcie4_uscale_plus_1/pcie4_uscale_plus_1.xci @@ -1801,4 +1801,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/alveo-u55c/src/ip/xvc_vsec/xvc_vsec.xci b/cards/amd/alveo-u55c/src/ip/xvc_vsec/xvc_vsec.xci index 0fe3838ab..ab307d940 100644 --- a/cards/amd/alveo-u55c/src/ip/xvc_vsec/xvc_vsec.xci +++ b/cards/amd/alveo-u55c/src/ip/xvc_vsec/xvc_vsec.xci @@ -137,4 +137,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/vcu118/constr/ddr4.xdc b/cards/amd/vcu118/constr/ddr4.xdc index 8990969bc..d34ad061e 100644 --- a/cards/amd/vcu118/constr/ddr4.xdc +++ b/cards/amd/vcu118/constr/ddr4.xdc @@ -165,7 +165,7 @@ set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4A_CK_P[*]] set_property PACKAGE_PIN BD36 [get_ports DDR4A_TEN] set_property IOSTANDARD LVCMOS12 [get_ports DDR4A_TEN] - + #DDR4B interface # Internal Clocks set_property PACKAGE_PIN C36 [get_ports DDR4B_REFCLK_P] diff --git a/cards/amd/vcu118/src/fpga.vhd b/cards/amd/vcu118/src/fpga.vhd index 4088e8594..32508a962 100644 --- a/cards/amd/vcu118/src/fpga.vhd +++ b/cards/amd/vcu118/src/fpga.vhd @@ -120,7 +120,7 @@ architecture FULL of FPGA is signal boot_mi_drd : std_logic_vector(31 downto 0); signal boot_mi_ardy : std_logic; signal boot_mi_drdy : std_logic; - + signal misc_in : std_logic_vector(MISC_IN_WIDTH-1 downto 0) := (others => '0'); signal misc_out : std_logic_vector(MISC_OUT_WIDTH-1 downto 0); diff --git a/cards/amd/vcu118/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci b/cards/amd/vcu118/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci index 87fa3317d..1143f05bb 100644 --- a/cards/amd/vcu118/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci +++ b/cards/amd/vcu118/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.xci @@ -1248,4 +1248,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci b/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci index 64447685e..b581c3a9d 100644 --- a/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci +++ b/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x16/pcie4_uscale_plus.xci @@ -1721,4 +1721,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci b/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci index 346ff5b88..13a7304f9 100644 --- a/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci +++ b/cards/amd/vcu118/src/ip/pcie4_uscale_plus/x8_low_latency/pcie4_uscale_plus.xci @@ -1721,4 +1721,4 @@ } } } -} \ No newline at end of file +} diff --git a/cards/bittware/ia-420f/constr/pcie.qsf b/cards/bittware/ia-420f/constr/pcie.qsf index 1f91f0a56..9c594f3ff 100644 --- a/cards/bittware/ia-420f/constr/pcie.qsf +++ b/cards/bittware/ia-420f/constr/pcie.qsf @@ -82,7 +82,7 @@ set_location_assignment PIN_BR56 -to PCIE_TX_N[0] set_location_assignment PIN_BP55 -to PCIE_TX_P[0] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK0 diff --git a/cards/bittware/ia-420f/constr/qsfp.qsf b/cards/bittware/ia-420f/constr/qsfp.qsf index 104b4a3e7..3a976a72f 100644 --- a/cards/bittware/ia-420f/constr/qsfp.qsf +++ b/cards/bittware/ia-420f/constr/qsfp.qsf @@ -46,7 +46,7 @@ set_location_assignment PIN_AU2 -to QSFP_TX_N[0] set_location_assignment PIN_AV1 -to QSFP_TX_P[0] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to QSFP_REFCLK_156M @@ -61,4 +61,4 @@ set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_bti_clock=true" -to QSFP_REFCLK_156M set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P diff --git a/cards/bittware/ia-420f/src/fpga.vhd b/cards/bittware/ia-420f/src/fpga.vhd index 0351d4a25..e9148e5df 100644 --- a/cards/bittware/ia-420f/src/fpga.vhd +++ b/cards/bittware/ia-420f/src/fpga.vhd @@ -85,8 +85,8 @@ port ( P1_DDR4_DQS_P : inout std_logic_vector(8 downto 0); P1_DDR4_DQS_N : inout std_logic_vector(8 downto 0); P1_DDR4_DQ : inout std_logic_vector(71 downto 0); - P1_RZQ : in std_logic; - + P1_RZQ : in std_logic; + -- ========================================================================= -- I2C -- ========================================================================= @@ -244,7 +244,7 @@ architecture FULL of FPGA is constant AMM_FREQ_KHZ : natural := 333333; signal status_led_g : std_logic_vector(STATUS_LEDS-1 downto 0); - signal status_led_r : std_logic_vector(STATUS_LEDS-1 downto 0); + signal status_led_r : std_logic_vector(STATUS_LEDS-1 downto 0); -- IO Expander signal io_reset : std_logic; signal io_reset_sync : std_logic; @@ -283,7 +283,7 @@ architecture FULL of FPGA is signal mem_rst_n : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_pll_locked : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_pll_locked_sync : std_logic_vector(MEM_PORTS-1 downto 0); - + signal mem_avmm_ready : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_read : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_write : std_logic_vector(MEM_PORTS-1 downto 0); @@ -293,7 +293,7 @@ architecture FULL of FPGA is signal mem_avmm_readdata : slv_array_t(MEM_PORTS-1 downto 0)(MEM_DATA_WIDTH-1 downto 0); signal mem_avmm_readdata_full : slv_array_t(MEM_PORTS-1 downto 0)(576-1 downto 0); signal mem_avmm_readdatavalid : std_logic_vector(MEM_PORTS-1 downto 0); - + signal emif_rst_req : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_rst_done : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_ecc_usr_int : std_logic_vector(MEM_PORTS-1 downto 0); @@ -418,7 +418,7 @@ begin ETH_PORT_CHAN => ETH_PORT_CHAN, ETH_PORT_LEDS => 1, -- fake, this board has no ETH LEDs ETH_LANES => ETH_LANES, - + QSFP_PORTS => 1, QSFP_I2C_PORTS => 1, QSFP_I2C_TRISTATE => false, @@ -426,17 +426,17 @@ begin STATUS_LEDS => STATUS_LEDS, MISC_IN_WIDTH => MISC_IN_WIDTH, MISC_OUT_WIDTH => MISC_OUT_WIDTH, - + PCIE_ENDPOINTS => PCIE_ENDPOINTS, PCIE_ENDPOINT_TYPE => PCIE_MOD_ARCH, PCIE_ENDPOINT_MODE => PCIE_ENDPOINT_MODE, - + DMA_ENDPOINTS => DMA_ENDPOINTS, DMA_MODULES => DMA_MODULES, - + DMA_RX_CHANNELS => DMA_RX_CHANNELS/DMA_MODULES, DMA_TX_CHANNELS => DMA_TX_CHANNELS/DMA_MODULES, - + MEM_PORTS => MEM_PORTS, MEM_ADDR_WIDTH => MEM_ADDR_WIDTH, MEM_DATA_WIDTH => MEM_DATA_WIDTH, @@ -458,10 +458,10 @@ begin PCIE_RX_N => PCIE_RX_N, PCIE_TX_P => PCIE_TX_P, PCIE_TX_N => PCIE_TX_N, - + ETH_REFCLK_P => QSFP_REFCLK_156M & QSFP_REFCLK_156M, ETH_REFCLK_N => (others => '0'), - + ETH_RX_P => QSFP_RX_P, ETH_RX_N => QSFP_RX_N, ETH_TX_P => QSFP_TX_P, @@ -469,7 +469,7 @@ begin ETH_LED_R => open, ETH_LED_G => open, - + QSFP_I2C_SCL_I(0) => qsfp_scl, QSFP_I2C_SDA_I(0) => qsfp_sda, QSFP_I2C_SCL_O(0) => qsfp_scl_o, @@ -563,11 +563,11 @@ begin ddr4_cal_p0_i : component ddr4_calibration port map ( - calbus_read_0 => calbus_read(0), - calbus_write_0 => calbus_write(0), - calbus_address_0 => calbus_address(0), - calbus_wdata_0 => calbus_wdata(0), - calbus_rdata_0 => calbus_rdata(0), + calbus_read_0 => calbus_read(0), + calbus_write_0 => calbus_write(0), + calbus_address_0 => calbus_address(0), + calbus_wdata_0 => calbus_wdata(0), + calbus_rdata_0 => calbus_rdata(0), calbus_seq_param_tbl_0 => calbus_seq_param_tbl(0), calbus_clk => calbus_clk(0) ); @@ -617,14 +617,14 @@ begin calbus_seq_param_tbl => calbus_seq_param_tbl(1), calbus_clk => calbus_clk(1) ); - + ddr4_cal_p1_i : component ddr4_calibration port map ( - calbus_read_0 => calbus_read(1), - calbus_write_0 => calbus_write(1), - calbus_address_0 => calbus_address(1), - calbus_wdata_0 => calbus_wdata(1), - calbus_rdata_0 => calbus_rdata(1), + calbus_read_0 => calbus_read(1), + calbus_write_0 => calbus_write(1), + calbus_address_0 => calbus_address(1), + calbus_wdata_0 => calbus_wdata(1), + calbus_rdata_0 => calbus_rdata(1), calbus_seq_param_tbl_0 => calbus_seq_param_tbl(1), calbus_clk => calbus_clk(1) ); diff --git a/cards/intel/dk-dev-1sdx-p/constr/ddr4_sodimm.qsf b/cards/intel/dk-dev-1sdx-p/constr/ddr4_sodimm.qsf index 201890cfa..92fc97f49 100644 --- a/cards/intel/dk-dev-1sdx-p/constr/ddr4_sodimm.qsf +++ b/cards/intel/dk-dev-1sdx-p/constr/ddr4_sodimm.qsf @@ -319,10 +319,10 @@ set_location_assignment PIN_BE31 -to DDR4_DIMM_CH1_DQ[65] set_location_assignment PIN_BF31 -to DDR4_DIMM_CH1_DQ[67] set_location_assignment PIN_BF32 -to DDR4_DIMM_CH1_DQS_N[8] set_location_assignment PIN_BG32 -to DDR4_DIMM_CH1_DQS_P[8] -set_location_assignment PIN_BA30 -to DDR4_DIMM_CH1_DQ[68] +set_location_assignment PIN_BA30 -to DDR4_DIMM_CH1_DQ[68] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== #### TODO added to solve fiting issues @@ -367,7 +367,7 @@ set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4_DIMM_CH0_CK_P[1] set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4_DIMM_CH0_CK_N[1] set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4_DIMM_CH0_CKE[1] set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4_DIMM_CH0_ODT[1] - + set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4_DIMM_CH1_DQS_N[9] set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4_DIMM_CH1_DQS_N[10] set_instance_assignment -name IO_STANDARD "1.2 V" -to DDR4_DIMM_CH1_DQS_N[11] diff --git a/cards/intel/dk-dev-1sdx-p/constr/general.qsf b/cards/intel/dk-dev-1sdx-p/constr/general.qsf index 312a973d7..a9ad03ba0 100644 --- a/cards/intel/dk-dev-1sdx-p/constr/general.qsf +++ b/cards/intel/dk-dev-1sdx-p/constr/general.qsf @@ -28,10 +28,10 @@ set_location_assignment PIN_G33 -to I2C3_1V8_SCL set_location_assignment PIN_C33 -to I2C3_1V8_SDA # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== -set_instance_assignment -name IO_STANDARD LVDS -to FPGA_SYSCLK0_100M_P +set_instance_assignment -name IO_STANDARD LVDS -to FPGA_SYSCLK0_100M_P set_instance_assignment -name IO_STANDARD "1.8 V" -to USER_LED_G set_instance_assignment -name IO_STANDARD "1.8 V" -to I2C1_1V8_SCL diff --git a/cards/intel/dk-dev-1sdx-p/constr/pcie.qsf b/cards/intel/dk-dev-1sdx-p/constr/pcie.qsf index 28b5550bd..278299caf 100644 --- a/cards/intel/dk-dev-1sdx-p/constr/pcie.qsf +++ b/cards/intel/dk-dev-1sdx-p/constr/pcie.qsf @@ -160,7 +160,7 @@ set_location_assignment PIN_AN47 -to PCIE1_TX_N[0] set_location_assignment PIN_AN48 -to PCIE1_TX_P[0] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD HCSL -to PCIE0_SYSCLK1_P diff --git a/cards/intel/dk-dev-1sdx-p/constr/qsfp.qsf b/cards/intel/dk-dev-1sdx-p/constr/qsfp.qsf index b4ce3700a..fc06c87c3 100644 --- a/cards/intel/dk-dev-1sdx-p/constr/qsfp.qsf +++ b/cards/intel/dk-dev-1sdx-p/constr/qsfp.qsf @@ -59,7 +59,7 @@ set_location_assignment PIN_BJ1 -to QSFP2_TX_P[0] set_location_assignment PIN_BJ2 -to QSFP2_TX_N[0] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD "1.8 V" -to ZQSFP_1V8_PORT_EN @@ -79,6 +79,6 @@ set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_bti_clock=TR set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=156250000" -to CLK_156P25M_QSFP1_P set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP1_TX_P -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP1_RX_P +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP1_RX_P set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP2_TX_P set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP2_RX_P diff --git a/cards/intel/dk-dev-1sdx-p/src/fpga.vhd b/cards/intel/dk-dev-1sdx-p/src/fpga.vhd index e591ce6ce..eb41e2fdf 100644 --- a/cards/intel/dk-dev-1sdx-p/src/fpga.vhd +++ b/cards/intel/dk-dev-1sdx-p/src/fpga.vhd @@ -47,13 +47,13 @@ port ( -- ========================================================================= ZQSFP_1V8_PORT_EN : out std_logic; ZQSFP_1V8_PORT_INT_N : in std_logic; - + CLK_312P5M_QSFP0_P : in std_logic; CLK_156P25M_QSFP0_P : in std_logic; CLK_312P5M_QSFP1_P : in std_logic; CLK_156P25M_QSFP1_P : in std_logic; CLK_312P5M_QSFP2_P : in std_logic; - + QSFP1_RX_P : in std_logic_vector(4-1 downto 0); QSFP1_RX_N : in std_logic_vector(4-1 downto 0); QSFP1_TX_P : out std_logic_vector(4-1 downto 0); @@ -68,7 +68,7 @@ port ( -- ========================================================================= -- I2C interface with temperature sensor --I2C_DDR4_DIMM_SDA : inout std_logic; - --I2C_DDR4_DIMM_SCL : inout std_logic; + --I2C_DDR4_DIMM_SCL : inout std_logic; -- EMIF DIMM0 interface CLK_133M_DIMM_1_P : in std_logic; -- DIMM1 CLK = CH0 CLK @@ -90,10 +90,10 @@ port ( DDR4_DIMM_CH0_DQ : inout std_logic_vector(72-1 downto 0); --DDR4_DIMM_CH0_RZQ : inout std_logic; DDR4_DIMM_CH0_RZQ : in std_logic; - + --DDR4_DIMM_CH0_C2 : out std_logic; --Module rank address (select of the whole memory?) --DDR4_DIMM_CH0_EVENT_N : in std_logic; --Asserted on critical temperature - --DDR4_DIMM_CH0_SAVE_N : in std_logic; + --DDR4_DIMM_CH0_SAVE_N : in std_logic; -- EMIF DIMM1 interface CLK_133M_DIMM_0_P : in std_logic; @@ -107,9 +107,9 @@ port ( DDR4_DIMM_CH1_CKE : out std_logic_vector(2-1 downto 0); DDR4_DIMM_CH1_CS_N : out std_logic_vector(4-1 downto 0); DDR4_DIMM_CH1_ODT : out std_logic_vector(2-1 downto 0); - DDR4_DIMM_CH1_RESET_N : out std_logic_vector(0 downto 0); - DDR4_DIMM_CH1_PAR : out std_logic_vector(0 downto 0); - DDR4_DIMM_CH1_ALERT_N : in std_logic_vector(0 downto 0); + DDR4_DIMM_CH1_RESET_N : out std_logic_vector(0 downto 0); + DDR4_DIMM_CH1_PAR : out std_logic_vector(0 downto 0); + DDR4_DIMM_CH1_ALERT_N : in std_logic_vector(0 downto 0); DDR4_DIMM_CH1_DQS_P : inout std_logic_vector(18-1 downto 0); DDR4_DIMM_CH1_DQS_N : inout std_logic_vector(18-1 downto 0); DDR4_DIMM_CH1_DQ : inout std_logic_vector(72-1 downto 0); @@ -117,9 +117,9 @@ port ( DDR4_DIMM_CH1_RZQ : in std_logic; -- --DDR4_DIMM_CH1_C2 : out std_logic; - --DDR4_DIMM_CH1_EVENT_N : in std_logic; - --DDR4_DIMM_CH1_SAVE_N : in std_logic; - + --DDR4_DIMM_CH1_EVENT_N : in std_logic; + --DDR4_DIMM_CH1_SAVE_N : in std_logic; + -- I2C -- ========================================================================= I2C1_1V8_SCL : inout std_logic; @@ -139,45 +139,45 @@ architecture FULL of FPGA is component emif_s10dx is port ( - local_reset_req : in std_logic := 'X'; - local_reset_done : out std_logic; - pll_ref_clk : in std_logic := 'X'; - pll_ref_clk_out : out std_logic; - pll_locked : out std_logic; - oct_rzqin : in std_logic := 'X'; - mem_ck : out std_logic_vector(0 downto 0); - mem_ck_n : out std_logic_vector(0 downto 0); - mem_a : out std_logic_vector(16 downto 0); - mem_act_n : out std_logic_vector(0 downto 0); - mem_ba : out std_logic_vector(1 downto 0); - mem_bg : out std_logic_vector(1 downto 0); - mem_cke : out std_logic_vector(0 downto 0); - mem_cs_n : out std_logic_vector(0 downto 0); - mem_odt : out std_logic_vector(0 downto 0); - mem_reset_n : out std_logic_vector(0 downto 0); - mem_par : out std_logic_vector(0 downto 0); - mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); - mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); - mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); - mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); - mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); - local_cal_success : out std_logic; - local_cal_fail : out std_logic; - emif_usr_reset_n : out std_logic; - emif_usr_clk : out std_logic; - ctrl_ecc_user_interrupt_0 : out std_logic; - amm_ready_0 : out std_logic; - amm_read_0 : in std_logic := 'X'; - amm_write_0 : in std_logic := 'X'; - amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); - amm_readdata_0 : out std_logic_vector(511 downto 0); - amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); - amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); - amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => 'X'); - amm_readdatavalid_0 : out std_logic + local_reset_req : in std_logic := 'X'; + local_reset_done : out std_logic; + pll_ref_clk : in std_logic := 'X'; + pll_ref_clk_out : out std_logic; + pll_locked : out std_logic; + oct_rzqin : in std_logic := 'X'; + mem_ck : out std_logic_vector(0 downto 0); + mem_ck_n : out std_logic_vector(0 downto 0); + mem_a : out std_logic_vector(16 downto 0); + mem_act_n : out std_logic_vector(0 downto 0); + mem_ba : out std_logic_vector(1 downto 0); + mem_bg : out std_logic_vector(1 downto 0); + mem_cke : out std_logic_vector(0 downto 0); + mem_cs_n : out std_logic_vector(0 downto 0); + mem_odt : out std_logic_vector(0 downto 0); + mem_reset_n : out std_logic_vector(0 downto 0); + mem_par : out std_logic_vector(0 downto 0); + mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); + mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); + mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); + mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); + mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); + local_cal_success : out std_logic; + local_cal_fail : out std_logic; + emif_usr_reset_n : out std_logic; + emif_usr_clk : out std_logic; + ctrl_ecc_user_interrupt_0 : out std_logic; + amm_ready_0 : out std_logic; + amm_read_0 : in std_logic := 'X'; + amm_write_0 : in std_logic := 'X'; + amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); + amm_readdata_0 : out std_logic_vector(511 downto 0); + amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); + amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); + amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => 'X'); + amm_readdatavalid_0 : out std_logic ); end component; - + constant PCIE_LANES : integer := 16; constant PCIE_CLKS : integer := 2; constant PCIE_CONS : integer := 2; @@ -205,7 +205,7 @@ architecture FULL of FPGA is constant MEM_ADDR_WIDTH : integer := 27; constant MEM_DATA_WIDTH : integer := 512; constant MEM_BURST_WIDTH : integer := 7; - + signal ddr4_reset_n : std_logic_vector(1 downto 0); signal ddr4_act_n : std_logic_vector(1 downto 0); signal ddr4_par : std_logic_vector(1 downto 0); @@ -214,7 +214,7 @@ architecture FULL of FPGA is -- External memory interfaces (clocked at MEM_CLK) signal mem_clk : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_rst_n : std_logic_vector(MEM_PORTS-1 downto 0); - + signal mem_avmm_ready : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_read : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_write : std_logic_vector(MEM_PORTS-1 downto 0); @@ -223,7 +223,7 @@ architecture FULL of FPGA is signal mem_avmm_writedata : slv_array_t(MEM_PORTS-1 downto 0)(MEM_DATA_WIDTH-1 downto 0); signal mem_avmm_readdata : slv_array_t(MEM_PORTS-1 downto 0)(MEM_DATA_WIDTH-1 downto 0); signal mem_avmm_readdatavalid : std_logic_vector(MEM_PORTS-1 downto 0); - + signal emif_rst_req : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_rst_done : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_ecc_usr_int : std_logic_vector(MEM_PORTS-1 downto 0); diff --git a/cards/intel/dk-dev-agi027res/config/card_const.tcl b/cards/intel/dk-dev-agi027res/config/card_const.tcl index 2499719bd..653b57176 100755 --- a/cards/intel/dk-dev-agi027res/config/card_const.tcl +++ b/cards/intel/dk-dev-agi027res/config/card_const.tcl @@ -45,4 +45,4 @@ Allowed PCIe configurations: # Current setup is same for all IP cores, due to use of one pll with frequency (830,156Mhz), for all IP's: # This setup value is defined as half of pll frequency -set TSU_FREQUENCY 415039062 \ No newline at end of file +set TSU_FREQUENCY 415039062 diff --git a/cards/intel/dk-dev-agi027res/constr/cxl.qsf b/cards/intel/dk-dev-agi027res/constr/cxl.qsf index b29632979..0dfac2092 100644 --- a/cards/intel/dk-dev-agi027res/constr/cxl.qsf +++ b/cards/intel/dk-dev-agi027res/constr/cxl.qsf @@ -85,7 +85,7 @@ set_location_assignment PIN_ER22 -to cxl_tx_n[14] set_location_assignment PIN_FD16 -to cxl_tx_n[15] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD "1.0 V" -to fpga_cxl_perstn diff --git a/cards/intel/dk-dev-agi027res/constr/ddr4_sodimm.qsf b/cards/intel/dk-dev-agi027res/constr/ddr4_sodimm.qsf index c0683e2d8..0e4694fc4 100644 --- a/cards/intel/dk-dev-agi027res/constr/ddr4_sodimm.qsf +++ b/cards/intel/dk-dev-agi027res/constr/ddr4_sodimm.qsf @@ -156,7 +156,7 @@ set_location_assignment PIN_L32 -to DDR4_DDIMM_DQS_N[2] set_location_assignment PIN_AD30 -to DDR4_DDIMM_DQS_N[0] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD "1.2 V" -to FPGA_DIMM_SCL diff --git a/cards/intel/dk-dev-agi027res/constr/general.qsf b/cards/intel/dk-dev-agi027res/constr/general.qsf index b0c9558ee..e4ee28c42 100644 --- a/cards/intel/dk-dev-agi027res/constr/general.qsf +++ b/cards/intel/dk-dev-agi027res/constr/general.qsf @@ -37,7 +37,7 @@ set_location_assignment PIN_KU60 -to qsfpdd_1v2_port_en set_location_assignment PIN_KJ59 -to qsfpdd_1v2_port_int_n # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to clk_sys_100m_p @@ -65,7 +65,7 @@ set_instance_assignment -name IO_STANDARD "1.2 V" -to qsfpdd_1v2_port_int_n set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name DEVICE AGIB027R29A1E2VR0 +set_global_assignment -name DEVICE AGIB027R29A1E2VR0 set_global_assignment -name FAMILY Agilex set_global_assignment -name USE_CONF_DONE SDM_IO16 diff --git a/cards/intel/dk-dev-agi027res/constr/pcie.qsf b/cards/intel/dk-dev-agi027res/constr/pcie.qsf index bccafea47..7cfc0c8a4 100644 --- a/cards/intel/dk-dev-agi027res/constr/pcie.qsf +++ b/cards/intel/dk-dev-agi027res/constr/pcie.qsf @@ -84,7 +84,7 @@ set_location_assignment PIN_E69 -to pcie_ep_tx_n[14] set_location_assignment PIN_P69 -to pcie_ep_tx_n[15] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD "1.0 V" -to fpga_pcie_perstn diff --git a/cards/intel/dk-dev-agi027res/constr/qsfp.qsf b/cards/intel/dk-dev-agi027res/constr/qsfp.qsf index a441dc9ac..ced98ce45 100644 --- a/cards/intel/dk-dev-agi027res/constr/qsfp.qsf +++ b/cards/intel/dk-dev-agi027res/constr/qsfp.qsf @@ -86,7 +86,7 @@ set_location_assignment PIN_GW80 -to qsfpdd1_tx_p[1] set_location_assignment PIN_GG78 -to qsfpdd1_tx_p[0] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== # Quartus sets automatically diff --git a/cards/intel/dk-dev-agi027res/constr/timing.sdc b/cards/intel/dk-dev-agi027res/constr/timing.sdc index e5678e9c6..6e99c0cbe 100644 --- a/cards/intel/dk-dev-agi027res/constr/timing.sdc +++ b/cards/intel/dk-dev-agi027res/constr/timing.sdc @@ -43,7 +43,7 @@ set FHIP_10G8_CLK_CH21 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_ set FHIP_10G8_CLK_CH20 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x10g1_g.eth_ip_g[3].FTILE_8x10g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch20] set FHIP_10G8_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x10g1_g.eth_ip_g[0].FTILE_8x10g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 10G8 design +# Fix hold timing issues for 10G8 design set_clock_groups -asynchronous -group $FHIP_10G8_CLK_CH23 -group $FHIP_10G8_CLK_CH16 set_clock_groups -asynchronous -group $FHIP_10G8_CLK_CH23 -group $FHIP_10G8_CLK_CH17 set_clock_groups -asynchronous -group $FHIP_10G8_CLK_CH23 -group $FHIP_10G8_CLK_CH21 @@ -65,7 +65,7 @@ set FHIP_25G8_CLK_CH20 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_ set FHIP_25G8_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x25g1_g.eth_ip_g[4].FTILE_8x25g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch19] set FHIP_25G8_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x25g1_g.eth_ip_g[0].FTILE_8x25g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 40G2 design +# Fix hold timing issues for 40G2 design set_clock_groups -asynchronous -group $FHIP_25G8_CLK_CH23 -group $FHIP_25G8_CLK_CH16 set_clock_groups -asynchronous -group $FHIP_25G8_CLK_CH23 -group $FHIP_25G8_CLK_CH17 set_clock_groups -asynchronous -group $FHIP_25G8_CLK_CH23 -group $FHIP_25G8_CLK_CH21 @@ -81,7 +81,7 @@ set_clock_groups -asynchronous -group $FHIP_25G8_CLK_CH23 -group $FHIP_25G8_CLK_ set FHIP_40G2_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x40g4_g.eth_ip_g[1].FTILE_2x40g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch19] set FHIP_40G2_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x40g4_g.eth_ip_g[0].FTILE_2x40g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 40G2 design +# Fix hold timing issues for 40G2 design set_clock_groups -asynchronous -group $FHIP_40G2_CLK_CH23 -group $FHIP_40G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_40G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_40G2_CLK_CH23 @@ -99,7 +99,7 @@ set FHIP_50G8_CLK_CH15 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_ set FHIP_50G8_CLK_CH21 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x50g1_g.eth_ip_g[1].FTILE_8x50g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch21] set FHIP_50G8_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x50g1_g.eth_ip_g[0].FTILE_8x50g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 50G8 design +# Fix hold timing issues for 50G8 design set_clock_groups -asynchronous -group $$FHIP_50G8_CLK_CH23 -group $FHIP_50G8_CLK_CH9 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_50G8_CLK_CH9 set_clock_groups -asynchronous -group $$FHIP_50G8_CLK_CH23 -group $FHIP_50G8_CLK_CH11 @@ -123,7 +123,7 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_50G8_CLK set FHIP_100G2_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x100g4_g.eth_ip_g[1].FTILE_2x100g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch19] set FHIP_100G2_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x100g4_g.eth_ip_g[0].FTILE_2x100g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 100G2 design +# Fix hold timing issues for 100G2 design set_clock_groups -asynchronous -group $FHIP_100G2_CLK_CH23 -group $FHIP_100G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G2_CLK_CH23 @@ -137,7 +137,7 @@ set FHIP_100G4_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod set FHIP_100G4_CLK_CH15 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_4x100g2_g.eth_ip_g[2].FTILE_4x100g2_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch15] set FHIP_100G4_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_4x100g2_g.eth_ip_g[0].FTILE_4x100g2_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 100G4 design +# Fix hold timing issues for 100G4 design set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G4_CLK_CH11 set_clock_groups -asynchronous -group $FHIP_100G4_CLK_CH23 -group $FHIP_100G4_CLK_CH11 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G4_CLK_CH19 @@ -154,7 +154,7 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G4_CL set FHIP_200G2_CLK_CH15 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x200g4_g.eth_ip_g[1].ftile_2x200g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch15] set FHIP_200G2_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x200g4_g.eth_ip_g[0].ftile_2x200g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 200G2 design +# Fix hold timing issues for 200G2 design set_clock_groups -asynchronous -group $FHIP_200G2_CLK_CH23 -group $FHIP_200G2_CLK_CH15 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_200G2_CLK_CH15 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_200G2_CLK_CH23 @@ -165,5 +165,5 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_200G2_CL # ============ set FHIP_400G1_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|eth_port_mode_sel_g.ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 400G1 design -set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_400G1_CLK_CH23 \ No newline at end of file +# Fix hold timing issues for 400G1 design +set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_400G1_CLK_CH23 diff --git a/cards/intel/dk-dev-agi027res/src/fpga.vhd b/cards/intel/dk-dev-agi027res/src/fpga.vhd index 7c6af3422..fceff3db6 100644 --- a/cards/intel/dk-dev-agi027res/src/fpga.vhd +++ b/cards/intel/dk-dev-agi027res/src/fpga.vhd @@ -29,7 +29,7 @@ port ( fpga_i2c2_en : out std_logic; fpga_i2c2_scl : inout std_logic; fpga_i2c2_sda : inout std_logic; - + -- User LEDs fpga_led : out std_logic_vector(3 downto 0); @@ -63,10 +63,10 @@ port ( -- ========================================================================= qsfpdd1_fpga_led : out std_logic_vector(3-1 downto 0); qsfpdd0_fpga_led : out std_logic_vector(3-1 downto 0); - + qsfpdd_1v2_port_en : out std_logic; qsfpdd_1v2_port_int_n : in std_logic; - + -- QSFPDD reference clock 100MHz from U22 --refclk_fgt12ach0_p : in std_logic; -- QSFPDD reference clock 153.6MHz from U22 @@ -77,7 +77,7 @@ port ( --refclk_fgt12ach5_p : in std_logic; -- QSFPDD reference clock 184.32MHz from U22 --refclk_fgt12ach6_p : in std_logic; - + --qsfpdd0_rx_p : in std_logic_vector(8-1 downto 0); --qsfpdd0_rx_n : in std_logic_vector(8-1 downto 0); --qsfpdd0_tx_p : out std_logic_vector(8-1 downto 0); @@ -129,45 +129,45 @@ architecture FULL of FPGA is component emif_agi027 is port ( - local_reset_req : in std_logic := 'X'; - local_reset_done : out std_logic; - pll_ref_clk : in std_logic := 'X'; - pll_locked : out std_logic; - oct_rzqin : in std_logic := 'X'; - mem_ck : out std_logic_vector(0 downto 0); - mem_ck_n : out std_logic_vector(0 downto 0); - mem_a : out std_logic_vector(16 downto 0); - mem_act_n : out std_logic_vector(0 downto 0); - mem_ba : out std_logic_vector(1 downto 0); - mem_bg : out std_logic_vector(1 downto 0); - mem_cke : out std_logic_vector(0 downto 0); - mem_cs_n : out std_logic_vector(0 downto 0); - mem_odt : out std_logic_vector(0 downto 0); - mem_reset_n : out std_logic_vector(0 downto 0); - mem_par : out std_logic_vector(0 downto 0); - mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); - mem_dqs : inout std_logic_vector(17 downto 0) := (others => 'X'); - mem_dqs_n : inout std_logic_vector(17 downto 0) := (others => 'X'); - mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); - local_cal_success : out std_logic; - local_cal_fail : out std_logic; - calbus_read : in std_logic := 'X'; - calbus_write : in std_logic := 'X'; - calbus_address : in std_logic_vector(19 downto 0) := (others => 'X'); - calbus_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); - calbus_rdata : out std_logic_vector(31 downto 0); - calbus_seq_param_tbl : out std_logic_vector(4095 downto 0); - calbus_clk : in std_logic := 'X'; - emif_usr_reset_n : out std_logic; - emif_usr_clk : out std_logic; - ctrl_ecc_user_interrupt_0 : out std_logic; - amm_ready_0 : out std_logic; - amm_read_0 : in std_logic := 'X'; - amm_write_0 : in std_logic := 'X'; - amm_address_0 : in std_logic_vector(27 downto 0) := (others => 'X'); - amm_readdata_0 : out std_logic_vector(511 downto 0); - amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); - amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); + local_reset_req : in std_logic := 'X'; + local_reset_done : out std_logic; + pll_ref_clk : in std_logic := 'X'; + pll_locked : out std_logic; + oct_rzqin : in std_logic := 'X'; + mem_ck : out std_logic_vector(0 downto 0); + mem_ck_n : out std_logic_vector(0 downto 0); + mem_a : out std_logic_vector(16 downto 0); + mem_act_n : out std_logic_vector(0 downto 0); + mem_ba : out std_logic_vector(1 downto 0); + mem_bg : out std_logic_vector(1 downto 0); + mem_cke : out std_logic_vector(0 downto 0); + mem_cs_n : out std_logic_vector(0 downto 0); + mem_odt : out std_logic_vector(0 downto 0); + mem_reset_n : out std_logic_vector(0 downto 0); + mem_par : out std_logic_vector(0 downto 0); + mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); + mem_dqs : inout std_logic_vector(17 downto 0) := (others => 'X'); + mem_dqs_n : inout std_logic_vector(17 downto 0) := (others => 'X'); + mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); + local_cal_success : out std_logic; + local_cal_fail : out std_logic; + calbus_read : in std_logic := 'X'; + calbus_write : in std_logic := 'X'; + calbus_address : in std_logic_vector(19 downto 0) := (others => 'X'); + calbus_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); + calbus_rdata : out std_logic_vector(31 downto 0); + calbus_seq_param_tbl : out std_logic_vector(4095 downto 0); + calbus_clk : in std_logic := 'X'; + emif_usr_reset_n : out std_logic; + emif_usr_clk : out std_logic; + ctrl_ecc_user_interrupt_0 : out std_logic; + amm_ready_0 : out std_logic; + amm_read_0 : in std_logic := 'X'; + amm_write_0 : in std_logic := 'X'; + amm_address_0 : in std_logic_vector(27 downto 0) := (others => 'X'); + amm_readdata_0 : out std_logic_vector(511 downto 0); + amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); + amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); amm_readdatavalid_0 : out std_logic; mmr_slave_waitrequest_0 : out std_logic; -- waitrequest mmr_slave_read_0 : in std_logic := 'X'; -- read @@ -231,13 +231,13 @@ architecture FULL of FPGA is constant MEM_MMR_ADDR_WIDTH : integer := 10; constant MEM_MMR_DATA_WIDTH : integer := 32; constant MEM_MMR_BURST_WIDTH : integer := 2; - - signal calbus_read : std_logic; - signal calbus_write : std_logic; - signal calbus_address : std_logic_vector(19 downto 0); - signal calbus_wdata : std_logic_vector(31 downto 0); - signal calbus_rdata : std_logic_vector(31 downto 0) := (others => 'X'); - signal calbus_seq_param_tbl : std_logic_vector(4095 downto 0) := (others => 'X'); + + signal calbus_read : std_logic; + signal calbus_write : std_logic; + signal calbus_address : std_logic_vector(19 downto 0); + signal calbus_wdata : std_logic_vector(31 downto 0); + signal calbus_rdata : std_logic_vector(31 downto 0) := (others => 'X'); + signal calbus_seq_param_tbl : std_logic_vector(4095 downto 0) := (others => 'X'); signal calbus_clk : std_logic; -- External memory interfaces (clocked at MEM_CLK) @@ -246,7 +246,7 @@ architecture FULL of FPGA is signal mem_rst_n : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_pll_locked : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_pll_locked_sync : std_logic_vector(MEM_PORTS-1 downto 0); - + signal mem_avmm_ready : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_read : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_write : std_logic_vector(MEM_PORTS-1 downto 0); @@ -260,16 +260,16 @@ architecture FULL of FPGA is signal mem_mmr_read_data : slv_array_t(MEM_PORTS - 1 downto 0)(MEM_MMR_DATA_WIDTH-1 downto 0); signal mem_mmr_write_data : slv_array_t(MEM_PORTS - 1 downto 0)(MEM_MMR_DATA_WIDTH-1 downto 0); signal mem_mmr_burst_count : slv_array_t(MEM_PORTS - 1 downto 0)(MEM_MMR_BURST_WIDTH-1 downto 0); - signal mem_mmr_waitrequest : std_logic_vector(MEM_PORTS - 1 downto 0); + signal mem_mmr_waitrequest : std_logic_vector(MEM_PORTS - 1 downto 0); signal mem_mmr_read : std_logic_vector(MEM_PORTS - 1 downto 0); signal mem_mmr_write : std_logic_vector(MEM_PORTS - 1 downto 0); signal mem_mmr_begin_burst_transfer : std_logic_vector(MEM_PORTS - 1 downto 0); - signal mem_mmr_read_data_valid : std_logic_vector(MEM_PORTS - 1 downto 0); + signal mem_mmr_read_data_valid : std_logic_vector(MEM_PORTS - 1 downto 0); signal mem_refr_req : std_logic_vector(MEM_PORTS - 1 downto 0); signal mem_refr_ack : std_logic_vector(MEM_PORTS - 1 downto 0); signal mem_refr_period : slv_array_t(MEM_PORTS - 1 downto 0)(MEM_REFR_PERIOD_WIDTH - 1 downto 0); - + signal emif_rst_req : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_rst_done : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_ecc_usr_int : std_logic_vector(MEM_PORTS-1 downto 0); @@ -467,16 +467,16 @@ begin mem_dq => DDR4_DDIMM_DQ, local_cal_success => emif_cal_success(0), local_cal_fail => emif_cal_fail(0), - calbus_read => calbus_read, - calbus_write => calbus_write, + calbus_read => calbus_read, + calbus_write => calbus_write, calbus_address => calbus_address, - calbus_wdata => calbus_wdata, - calbus_rdata => calbus_rdata, - calbus_seq_param_tbl => calbus_seq_param_tbl, - calbus_clk => calbus_clk, - emif_usr_reset_n => mem_rst_n(0), - emif_usr_clk => mem_clk(0), - ctrl_ecc_user_interrupt_0 => emif_ecc_usr_int(0), + calbus_wdata => calbus_wdata, + calbus_rdata => calbus_rdata, + calbus_seq_param_tbl => calbus_seq_param_tbl, + calbus_clk => calbus_clk, + emif_usr_reset_n => mem_rst_n(0), + emif_usr_clk => mem_clk(0), + ctrl_ecc_user_interrupt_0 => emif_ecc_usr_int(0), amm_ready_0 => mem_avmm_ready(0), amm_read_0 => mem_avmm_read(0), amm_write_0 => mem_avmm_write(0), @@ -486,29 +486,29 @@ begin amm_burstcount_0 => mem_avmm_burstcount(0), amm_readdatavalid_0 => mem_avmm_readdatavalid(0), mmr_slave_waitrequest_0 => mem_mmr_waitrequest(0), - mmr_slave_read_0 => mem_mmr_read(0), - mmr_slave_write_0 => mem_mmr_write(0), - mmr_slave_address_0 => mem_mmr_address(0), - mmr_slave_readdata_0 => mem_mmr_read_data(0), - mmr_slave_writedata_0 => mem_mmr_write_data(0), - mmr_slave_burstcount_0 => mem_mmr_burst_count(0), + mmr_slave_read_0 => mem_mmr_read(0), + mmr_slave_write_0 => mem_mmr_write(0), + mmr_slave_address_0 => mem_mmr_address(0), + mmr_slave_readdata_0 => mem_mmr_read_data(0), + mmr_slave_writedata_0 => mem_mmr_write_data(0), + mmr_slave_burstcount_0 => mem_mmr_burst_count(0), mmr_slave_beginbursttransfer_0 => mem_mmr_begin_burst_transfer(0), - mmr_slave_readdatavalid_0 => mem_mmr_read_data_valid(0), + mmr_slave_readdatavalid_0 => mem_mmr_read_data_valid(0), ctrl_auto_precharge_req_0 => emif_auto_precharge(0) ); - + -- Each EMIF instance must be connected to the I/O SSM. -- Only one calibration IP is allowed for each I/O row. All the EMIFs in the same I/O row -- must be connected to the same calibration I/P. You can specify the number of EMIF - -- interfaces to be connected to the calibration IP when parameterizing the IP. - + -- interfaces to be connected to the calibration IP when parameterizing the IP. + emif_cal_0 : component emif_agi027_cal port map ( - calbus_read_0 => calbus_read, - calbus_write_0 => calbus_write, - calbus_address_0 => calbus_address, - calbus_wdata_0 => calbus_wdata, - calbus_rdata_0 => calbus_rdata, + calbus_read_0 => calbus_read, + calbus_write_0 => calbus_write, + calbus_address_0 => calbus_address, + calbus_wdata_0 => calbus_wdata, + calbus_rdata_0 => calbus_rdata, calbus_seq_param_tbl_0 => calbus_seq_param_tbl, calbus_clk => calbus_clk, cal_debug_clk_clk => mem_clk(0), @@ -535,13 +535,13 @@ begin REFRESH_PERIOD_TICKS => mem_refr_period (0), REFRESH_DONE_ANY => mem_refr_ack (0), - AMM_READY => not mem_mmr_waitrequest (0), - AMM_READ => mem_mmr_read (0), - AMM_WRITE => mem_mmr_write (0), - AMM_ADDRESS => mem_mmr_address (0), - AMM_READ_DATA => mem_mmr_read_data (0), - AMM_WRITE_DATA => mem_mmr_write_data (0), - AMM_BURST_COUNT => mem_mmr_burst_count (0), + AMM_READY => not mem_mmr_waitrequest (0), + AMM_READ => mem_mmr_read (0), + AMM_WRITE => mem_mmr_write (0), + AMM_ADDRESS => mem_mmr_address (0), + AMM_READ_DATA => mem_mmr_read_data (0), + AMM_WRITE_DATA => mem_mmr_write_data (0), + AMM_BURST_COUNT => mem_mmr_burst_count (0), AMM_READ_DATA_VALID => mem_mmr_read_data_valid (0) ); diff --git a/cards/prodesign/pd-falcon/constr/general.qsf b/cards/prodesign/pd-falcon/constr/general.qsf index 0e518bc6f..9a71a316b 100644 --- a/cards/prodesign/pd-falcon/constr/general.qsf +++ b/cards/prodesign/pd-falcon/constr/general.qsf @@ -18,17 +18,17 @@ set_location_assignment PIN_BK21 -to LED_USR_Y_RGY2 set_location_assignment PIN_BL21 -to LED_USR_G_RGY2 # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== -set_instance_assignment -name IO_STANDARD LVDS -to UFPGA_CLK100 +set_instance_assignment -name IO_STANDARD LVDS -to UFPGA_CLK100 -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_R_RGY1 -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_Y_RGY1 -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_G_RGY1 -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_R_RGY2 -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_Y_RGY2 -set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_G_RGY2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_R_RGY1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_Y_RGY1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_G_RGY1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_R_RGY2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_Y_RGY2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to LED_USR_G_RGY2 # ============================================================================== # Others assignments diff --git a/cards/prodesign/pd-falcon/readme.rst b/cards/prodesign/pd-falcon/readme.rst index fa833dc4e..ae073296d 100644 --- a/cards/prodesign/pd-falcon/readme.rst +++ b/cards/prodesign/pd-falcon/readme.rst @@ -3,7 +3,7 @@ PRO DESIGN Falcon --------------------------- - Card Information: - - Vendor: PRO DESIGN + - Vendor: PRO DESIGN - Name: PRO DESIGN Falcon (PD-FALCON-1SM21BEU2F55E2VG-DS-AP-PCIE-150) - Ethernet Ports: 4x QSFP-DD - PCIe Connectors: 1x diff --git a/cards/prodesign/pd-falcon/src/fpga.vhd b/cards/prodesign/pd-falcon/src/fpga.vhd index c0f3f30fe..a4c4ee04e 100644 --- a/cards/prodesign/pd-falcon/src/fpga.vhd +++ b/cards/prodesign/pd-falcon/src/fpga.vhd @@ -33,22 +33,22 @@ port ( REFCLK_R9A2 : in std_logic; -- 156.25 MHZ REFCLK_R9C2 : in std_logic; -- 156.25 MHZ - QSFP1_RX_P : in std_logic_vector(4-1 downto 0); + QSFP1_RX_P : in std_logic_vector(4-1 downto 0); QSFP1_RX_N : in std_logic_vector(4-1 downto 0); QSFP1_TX_P : out std_logic_vector(4-1 downto 0); QSFP1_TX_N : out std_logic_vector(4-1 downto 0); - QSFP2_RX_P : in std_logic_vector(4-1 downto 0); + QSFP2_RX_P : in std_logic_vector(4-1 downto 0); QSFP2_RX_N : in std_logic_vector(4-1 downto 0); QSFP2_TX_P : out std_logic_vector(4-1 downto 0); QSFP2_TX_N : out std_logic_vector(4-1 downto 0); - QSFP3_RX_P : in std_logic_vector(4-1 downto 0); + QSFP3_RX_P : in std_logic_vector(4-1 downto 0); QSFP3_RX_N : in std_logic_vector(4-1 downto 0); QSFP3_TX_P : out std_logic_vector(4-1 downto 0); QSFP3_TX_N : out std_logic_vector(4-1 downto 0); - QSFP4_RX_P : in std_logic_vector(4-1 downto 0); + QSFP4_RX_P : in std_logic_vector(4-1 downto 0); QSFP4_RX_N : in std_logic_vector(4-1 downto 0); QSFP4_TX_P : out std_logic_vector(4-1 downto 0); QSFP4_TX_N : out std_logic_vector(4-1 downto 0); diff --git a/cards/reflexces/agi-fh400g/bts/test_eth.py b/cards/reflexces/agi-fh400g/bts/test_eth.py index 53b6822f8..0cc88d32b 100644 --- a/cards/reflexces/agi-fh400g/bts/test_eth.py +++ b/cards/reflexces/agi-fh400g/bts/test_eth.py @@ -5,9 +5,7 @@ # SPDX-License-Identifier: BSD-3-Clause import time -import random import re -import signal import os import subprocess # pytest, pytest-depends, pytest-html @@ -16,23 +14,25 @@ # AUXILIARY FUNCTIONS # ============================================================================== -def nfb_bus(addr,pcie_index=0,value=None): - if (value==None): # read - return int("0x"+subprocess.Popen("nfb-bus -i%d %s" % (pcie_index,hex(addr)),shell=True,stdout=subprocess.PIPE).stdout.read().strip().decode("utf-8"),16) + +def nfb_bus(addr, pcie_index=0, value=None): + if value is None: # read + return int("0x"+subprocess.Popen("nfb-bus -i%d %s" % (pcie_index, hex(addr)), shell=True, stdout=subprocess.PIPE).stdout.read().strip().decode("utf-8"), 16) else: # write - return subprocess.call("nfb-bus -i%d %s %s" % (pcie_index,hex(addr),hex(value)),shell=True) + return subprocess.call("nfb-bus -i%d %s %s" % (pcie_index, hex(addr), hex(value)), shell=True) + -def nfb_eth_results(channel,rx=True): - if rx==True: - proc = subprocess.run("nfb-eth -i%d -r" % (channel),shell=True,check=True,stdout=subprocess.PIPE) +def nfb_eth_results(channel, rx=True): + if rx is True: + proc = subprocess.run("nfb-eth -i%d -r" % (channel), shell=True, check=True, stdout=subprocess.PIPE) else: - proc = subprocess.run("nfb-eth -i%d -t" % (channel),shell=True,check=True,stdout=subprocess.PIPE) + proc = subprocess.run("nfb-eth -i%d -t" % (channel), shell=True, check=True, stdout=subprocess.PIPE) result = [] stdout = proc.stdout.decode("utf-8") result_lines = stdout.split('\n') for line in result_lines: print(line) - if rx==True: + if rx is True: match = re.match(r"^.*(Processed|Received|Erroneous).*:\s*([0-9]+)", line) else: match = re.match(r"^.*(Processed|Transmitted|Erroneous).*:\s*([0-9]+)", line) @@ -41,14 +41,17 @@ def nfb_eth_results(channel,rx=True): result.append(int(match.group(2))) return result + def nfb_eth_enable(): os.system("nfb-eth -e1") return + def nfb_eth_reset(): os.system("nfb-eth -R") return + def nfb_eth_set_mac_filter(gen_offset): # Enable MAC filter on RX os.system("nfb-eth -rM normal") @@ -57,69 +60,76 @@ def nfb_eth_set_mac_filter(gen_offset): # Set allowed Destination MAC os.system("nfb-eth -rM add 11:22:33:44:55:66") # Set Destination MAC to FPGA generator - nfb_bus(gen_offset+0x10,0,0x44332211) - nfb_bus(gen_offset+0x14,0,0x6655) + nfb_bus(gen_offset+0x10, 0, 0x44332211) + nfb_bus(gen_offset+0x14, 0, 0x6655) return + def generator_stop(gen_offset): # generator - stop - nfb_bus(gen_offset,0,0) + nfb_bus(gen_offset, 0, 0) return -def generator_run(gen_offset,frame_size): + +def generator_run(gen_offset, frame_size): # generator - set size - nfb_bus(gen_offset+0x4,0,frame_size) + nfb_bus(gen_offset+0x4, 0, frame_size) # generator - start - nfb_bus(gen_offset,0,1) + nfb_bus(gen_offset, 0, 1) return -def gls_setup(gls_offset,rx_loop,tx_loop,rx_gen,tx_gen): - nfb_bus(gls_offset,0,rx_loop) - nfb_bus(gls_offset+0x4,0,tx_loop) - nfb_bus(gls_offset+0x8,0,rx_gen) - nfb_bus(gls_offset+0xC,0,tx_gen) + +def gls_setup(gls_offset, rx_loop, tx_loop, rx_gen, tx_gen): + nfb_bus(gls_offset, 0, rx_loop) + nfb_bus(gls_offset+0x4, 0, tx_loop) + nfb_bus(gls_offset+0x8, 0, rx_gen) + nfb_bus(gls_offset+0xC, 0, tx_gen) return # TEST FUNCTIONS # ============================================================================== + gls_offset = 0x5000 tx_gen_offset = 0x50C0 + def check_ndk_sw(): print("Info: Check NDK software tools:") - rt=subprocess.call(['which', 'nfb-info']) + rt = subprocess.call(['which', 'nfb-info']) if rt > 0: print("Error: NDK software is not installed.") return rt print("Info: Check NDK driver debug mode:") - rt=subprocess.call("nfb-bus 0x0",shell=True) + rt = subprocess.call("nfb-bus 0x0", shell=True) if rt > 0: print("Error: NDK driver is not debug mode.") return rt + def test_check_ndk_sw(): assert check_ndk_sw() == 0 + @pytest.mark.depends(on=['test_check_ndk_sw']) -@pytest.mark.parametrize("frame_size", range(64, 1518, 32)) +@pytest.mark.parametrize("frame_size", range(64, 1518, 32)) def test_eth_loopback_mac_filter(frame_size): error = 0 generator_stop(tx_gen_offset) - gls_setup(gls_offset,0x0,0x0,0x1,0x1) + gls_setup(gls_offset, 0x0, 0x0, 0x1, 0x1) nfb_eth_enable() nfb_eth_set_mac_filter(tx_gen_offset) nfb_eth_reset() - generator_run(tx_gen_offset,frame_size-4) + generator_run(tx_gen_offset, frame_size-4) time.sleep(2) generator_stop(tx_gen_offset) time.sleep(0.5) - rx_abts, rx_ppts, rx_apts, rx_errs = nfb_eth_results(0,True) - tx_abts, tx_ppts, tx_apts, tx_errs = nfb_eth_results(0,False) - print("Info: Processed Packet counters: TX = %d, RX %d." %(tx_ppts, rx_ppts)) - print("Info: Accepted Packet counters: TX = %d, RX %d." %(tx_apts, rx_apts)) - print("Info: Error Packet counters: TX = %d, RX %d." %(tx_errs, rx_errs)) - print("Info: Accepted Bytes counters: TX = %d, RX %d." %(tx_abts, rx_abts)) + rx_abts, rx_ppts, rx_apts, rx_errs = nfb_eth_results(0, True) + tx_abts, tx_ppts, tx_apts, tx_errs = nfb_eth_results(0, False) + print("Info: Processed Packet counters: TX = %d, RX %d." % (tx_ppts, rx_ppts)) + print("Info: Accepted Packet counters: TX = %d, RX %d." % (tx_apts, rx_apts)) + print("Info: Error Packet counters: TX = %d, RX %d." % (tx_errs, rx_errs)) + print("Info: Accepted Bytes counters: TX = %d, RX %d." % (tx_abts, rx_abts)) if rx_ppts != rx_ppts: print("Error: Processed Packet counters do not match.") error = 1 diff --git a/cards/reflexces/agi-fh400g/bts/test_pcie.py b/cards/reflexces/agi-fh400g/bts/test_pcie.py index 7bfcbcc11..5ad66cb01 100644 --- a/cards/reflexces/agi-fh400g/bts/test_pcie.py +++ b/cards/reflexces/agi-fh400g/bts/test_pcie.py @@ -15,23 +15,25 @@ # AUXILIARY FUNCTIONS # ============================================================================== -def nfb_bus(addr,pcie_index=0,value=None): - if (value==None): # read - return int("0x"+subprocess.Popen("nfb-bus -i%d %s" % (pcie_index,hex(addr)),shell=True,stdout=subprocess.PIPE).stdout.read().strip().decode("utf-8"),16) + +def nfb_bus(addr, pcie_index=0, value=None): + if value is None: # read + return int("0x"+subprocess.Popen("nfb-bus -i%d %s" % (pcie_index, hex(addr)), shell=True, stdout=subprocess.PIPE).stdout.read().strip().decode("utf-8"), 16) else: # write - return subprocess.call("nfb-bus -i%d %s %s" % (pcie_index,hex(addr),hex(value)),shell=True) + return subprocess.call("nfb-bus -i%d %s %s" % (pcie_index, hex(addr), hex(value)), shell=True) + -def nfb_dma_results(channel,rx=True): - if rx==True: - proc = subprocess.run("nfb-dma -i%d -r" % (channel),shell=True,check=True,stdout=subprocess.PIPE) +def nfb_dma_results(channel, rx=True): + if rx is True: + proc = subprocess.run("nfb-dma -i%d -r" % (channel), shell=True, check=True, stdout=subprocess.PIPE) else: - proc = subprocess.run("nfb-dma -i%d -t" % (channel),shell=True,check=True,stdout=subprocess.PIPE) + proc = subprocess.run("nfb-dma -i%d -t" % (channel), shell=True, check=True, stdout=subprocess.PIPE) result = [] stdout = proc.stdout.decode("utf-8") result_lines = stdout.split('\n') for line in result_lines: print(line) - if rx==True: + if rx is True: match = re.match(r"^.*(Received|Discarded).*:\s*([0-9]+)", line) else: match = re.match(r"^.*(Sent).*:\s*([0-9]+)", line) @@ -39,12 +41,14 @@ def nfb_dma_results(channel,rx=True): result.append(int(match.group(2))) return result + def nfb_dma_reset(): - proc = subprocess.run("nfb-dma -R",shell=True,check=True,timeout=10) + proc = subprocess.run("nfb-dma -R", shell=True, check=True, timeout=10) if proc.returncode > 0: print("Error: Unexpected error in nfb-dma.") return proc.returncode + def ndp_stop(proc): error = 0 packet_count = 0 @@ -73,45 +77,46 @@ def ndp_stop(proc): match = re.match(r"^(Bytes).*:\s*([0-9]+)", line) if match: bytes_count = int(match.group(2)) - return (packet_count,bytes_count,error) + return (packet_count, bytes_count, error) + -def dma_channel_check(channel,frame_size,rx): +def dma_channel_check(channel, frame_size, rx): error = nfb_dma_reset() if error > 0: return error if rx: hw_cnt_offset = 0 dir_s = "RX" - ndp = subprocess.Popen("ndp-read -i%d" % (channel),shell=True,stdout=subprocess.PIPE,stderr=subprocess.PIPE) + ndp = subprocess.Popen("ndp-read -i%d" % (channel), shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) # RX generator - stop - nfb_bus(0x5080,0,0) + nfb_bus(0x5080, 0, 0) # RX set loopback mux - nfb_bus(0x5000,0,0) + nfb_bus(0x5000, 0, 0) # RX set generator mux - nfb_bus(0x5008,0,1) + nfb_bus(0x5008, 0, 1) # RX generator - set size - nfb_bus(0x5084,0,frame_size) + nfb_bus(0x5084, 0, frame_size) # RX generator - start - nfb_bus(0x5080,0,1) + nfb_bus(0x5080, 0, 1) time.sleep(4) # RX generator - stop - nfb_bus(0x5080,0,0) + nfb_bus(0x5080, 0, 0) time.sleep(0.2) else: hw_cnt_offset = 2 dir_s = "TX" # RX set loopback mux - nfb_bus(0x5000,0,1) + nfb_bus(0x5000, 0, 1) # TX set generator mux - nfb_bus(0x500C,0,1) + nfb_bus(0x500C, 0, 1) # start ndp-generate - ndp = subprocess.Popen("ndp-generate -i%d -s%d" % (channel,frame_size),shell=True,stdout=subprocess.PIPE,stderr=subprocess.PIPE) + ndp = subprocess.Popen("ndp-generate -i%d -s%d" % (channel, frame_size), shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) time.sleep(4) packet_count, bytes_count, ndp_error = ndp_stop(ndp) hw_cnt = nfb_dma_results(channel) - print("Info: Packet counters: SW = %d, HW %d." %(packet_count, hw_cnt[0])) - print("Info: Bytes counters: Sw = %d, HW %d." %(bytes_count, hw_cnt[1])) + print("Info: Packet counters: SW = %d, HW %d." % (packet_count, hw_cnt[0])) + print("Info: Bytes counters: Sw = %d, HW %d." % (bytes_count, hw_cnt[1])) if hw_cnt[hw_cnt_offset] != packet_count: print("Error: Packet counters do not match.") error = 1 @@ -119,12 +124,13 @@ def dma_channel_check(channel,frame_size,rx): print("Error: Bytes counters do not match.") error = 1 if error == 0: - print("Info: The %s DMA test (channel: %d, frame size: %d) has PASSed." %(dir_s,channel,frame_size)) + print("Info: The %s DMA test (channel: %d, frame size: %d) has PASSed." % (dir_s, channel, frame_size)) if ndp_error > 0: print("Error: Unexpected error in NDK tools.") error = 1 return error + def dma_loopback_basic(channels=32): print("Info: Starting DMA loopback test...") print("Info: all channels, random frame size in range 64 to 2048 bytes") @@ -134,11 +140,11 @@ def dma_loopback_basic(channels=32): if error > 0: return error # RX set loopback mux - nfb_bus(0x5000,0,1) + nfb_bus(0x5000, 0, 1) # TX set generator mux - nfb_bus(0x500C,0,1) - ndp_rd = subprocess.Popen("ndp-read",shell=True,stdout=subprocess.PIPE,stderr=subprocess.PIPE) - ndp_gn = subprocess.Popen("ndp-generate -s64-2048",shell=True,stdout=subprocess.PIPE,stderr=subprocess.PIPE) + nfb_bus(0x500C, 0, 1) + ndp_rd = subprocess.Popen("ndp-read", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + ndp_gn = subprocess.Popen("ndp-generate -s64-2048", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) time.sleep(4) gen_pkt, gen_bts, ndp_gn_error = ndp_stop(ndp_gn) rd_pkt, rd_bts, ndp_rd_error = ndp_stop(ndp_rd) @@ -146,8 +152,8 @@ def dma_loopback_basic(channels=32): hw_cnt = nfb_dma_results(i) dis_pkt = dis_pkt + hw_cnt[2] dis_bts = dis_bts + hw_cnt[3] - print("Info: Packet counters: generator = %d, reader %d, discard %d." %(gen_pkt, rd_pkt, dis_pkt)) - print("Info: Bytes counters: generator = %d, reader %d, discard %d." %(gen_bts, rd_bts, dis_bts)) + print("Info: Packet counters: generator = %d, reader %d, discard %d." % (gen_pkt, rd_pkt, dis_pkt)) + print("Info: Bytes counters: generator = %d, reader %d, discard %d." % (gen_bts, rd_bts, dis_bts)) if rd_pkt != (gen_pkt-dis_pkt): print("Error: Packet counters do not match.") error = 1 @@ -159,6 +165,7 @@ def dma_loopback_basic(channels=32): error = 1 return error + def dma_loopback(channels=32): print("Info: Starting DMA loopback data integrity test...") print("Info: all channels, random frame size in range 64 to 2048 bytes") @@ -166,20 +173,20 @@ def dma_loopback(channels=32): if error > 0: return error # RX set loopback mux - nfb_bus(0x5000,0,1) + nfb_bus(0x5000, 0, 1) # TX set generator mux - nfb_bus(0x500C,0,1) - ndp = subprocess.Popen("ndp-loopback-hw -s64-2048",shell=True,stdout=subprocess.PIPE,stderr=subprocess.PIPE) + nfb_bus(0x500C, 0, 1) + ndp = subprocess.Popen("ndp-loopback-hw -s64-2048", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) time.sleep(5) gen_pkt, gen_bts, ndp_error = ndp_stop(ndp) hw_pkt = 0 hw_bts = 0 for i in range(channels): - hw_cnt = nfb_dma_results(i,False) + hw_cnt = nfb_dma_results(i, False) hw_pkt = hw_pkt + hw_cnt[0] hw_bts = hw_bts + hw_cnt[1] - print("Info: Packet counters: generator = %d, discard %d." %(gen_pkt, hw_pkt)) - print("Info: Bytes counters: generator = %d, discard %d." %(gen_bts, hw_bts)) + print("Info: Packet counters: generator = %d, discard %d." % (gen_pkt, hw_pkt)) + print("Info: Bytes counters: generator = %d, discard %d." % (gen_bts, hw_bts)) if hw_pkt != gen_pkt: print("Error: Packet counters do not match.") error = 1 @@ -194,70 +201,80 @@ def dma_loopback(channels=32): # TEST FUNCTIONS # ============================================================================== + def check_ndk_sw(): print("Info: Check NDK software tools:") - rt=subprocess.call(['which', 'nfb-info']) + rt = subprocess.call(['which', 'nfb-info']) if rt > 0: print("Error: NDK software is not installed.") return rt print("Info: Check NDK driver debug mode:") - rt=subprocess.call("nfb-bus 0x0",shell=True) + rt = subprocess.call("nfb-bus 0x0", shell=True) if rt > 0: print("Error: NDK driver is not debug mode.") return rt + def test_check_ndk_sw(): assert check_ndk_sw() == 0 + def check_pcie_device_in_lspci(): print("Info: Print all devices in lspci:") - subprocess.call("lspci",shell=True) + subprocess.call("lspci", shell=True) print("Info: Try find our device in lspci...:") - rt=subprocess.call("lspci | grep 'Ethernet controller: Cesnet, z.s.p.o.'",shell=True) + rt = subprocess.call("lspci | grep 'Ethernet controller: Cesnet, z.s.p.o.'", shell=True) if rt > 0: print("Error: The card is not visible in the PCI device list.") return rt + def test_check_pcie_device_in_lspci(): assert check_pcie_device_in_lspci() == 0 + def mi_bus_random_rw_access(): error_cnt = 0 dwr_list = [] print("Info: Starting MI bus test...") for i in range(64): - dwr_list.append(random.randint(0,(2**32-1))) - nfb_bus((i*4),0,dwr_list[i]) - print("Info: MI write %d to %d" %(dwr_list[i],i*4)) + dwr_list.append(random.randint(0, (2**32-1))) + nfb_bus((i*4), 0, dwr_list[i]) + print("Info: MI write %d to %d" % (dwr_list[i], i*4)) for i in range(64): drd = nfb_bus(i*4) - print("Info: MI read %s from %s" %(hex(drd),hex(i*4))) + print("Info: MI read %s from %s" % (hex(drd), hex(i*4))) if drd != (dwr_list[i]): error_cnt = error_cnt + 1 if error_cnt > 0: - print("Error: Some MI requests failed. Read error counts: %d" %(error_cnt)) + print("Error: Some MI requests failed. Read error counts: %d" % (error_cnt)) return error_cnt -@pytest.mark.depends(on=['test_check_pcie_device_in_lspci','test_check_ndk_sw']) + +@pytest.mark.depends(on=['test_check_pcie_device_in_lspci', 'test_check_ndk_sw']) def test_mi_bus_random_rw_access(): assert mi_bus_random_rw_access() == 0 -@pytest.mark.depends(on=['test_check_pcie_device_in_lspci','test_check_ndk_sw']) + +@pytest.mark.depends(on=['test_check_pcie_device_in_lspci', 'test_check_ndk_sw']) @pytest.mark.parametrize("channels", range(32)) -@pytest.mark.parametrize("frame_size", [64,256,1024]) -def test_dma_rx_channels(channels,frame_size): - assert dma_channel_check(channels,frame_size,True) == 0 - -@pytest.mark.depends(on=['test_check_pcie_device_in_lspci','test_check_ndk_sw']) +@pytest.mark.parametrize("frame_size", [64, 256, 1024]) +def test_dma_rx_channels(channels, frame_size): + assert dma_channel_check(channels, frame_size, True) == 0 + + +@pytest.mark.depends(on=['test_check_pcie_device_in_lspci', 'test_check_ndk_sw']) @pytest.mark.parametrize("channels", range(32)) -@pytest.mark.parametrize("frame_size", [64,256,1024]) -def test_dma_tx_channels(channels,frame_size): - assert dma_channel_check(channels,frame_size,False) == 0 +@pytest.mark.parametrize("frame_size", [64, 256, 1024]) +def test_dma_tx_channels(channels, frame_size): + assert dma_channel_check(channels, frame_size, False) == 0 -@pytest.mark.depends(on=['test_check_pcie_device_in_lspci','test_check_ndk_sw']) + +@pytest.mark.depends(on=['test_check_pcie_device_in_lspci', 'test_check_ndk_sw']) def test_dma_loopback_basic(): assert dma_loopback_basic() == 0 -@pytest.mark.depends(on=['test_check_pcie_device_in_lspci','test_check_ndk_sw']) + +@pytest.mark.depends(on=['test_check_pcie_device_in_lspci', 'test_check_ndk_sw']) def test_dma_loopback_data_integrity(): assert dma_loopback() == 0 diff --git a/cards/reflexces/agi-fh400g/constr/general.qsf b/cards/reflexces/agi-fh400g/constr/general.qsf index 25c50dbef..77dde6c87 100644 --- a/cards/reflexces/agi-fh400g/constr/general.qsf +++ b/cards/reflexces/agi-fh400g/constr/general.qsf @@ -135,52 +135,52 @@ set_location_assignment PIN_BM64 -to FLASH_BYTE_N set_location_assignment PIN_BC65 -to FLASH_WP_N set_location_assignment PIN_AY66 -to FLASH_RST_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[2] set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[3] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SCLK -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SCLK +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SDA -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK0_P -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK1_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK0_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK1_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK0_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK1_P -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_EXT_SYNC_1HZ +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_EXT_SYNC_1HZ -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_INT_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_GEN_LOL_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_INT_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_GEN_LOL_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_DEV_POR_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_RST_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_SOFT_RST -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_RST_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_DEV_POR_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_RST_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_SOFT_RST +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_RST_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_IMG_SEL_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_REBOOT_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_DONE -set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_STATUS_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_IMG_SEL_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_REBOOT_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_DONE +set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_STATUS_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_REQ_CONF_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CFG_IMG_SEL +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_REQ_CONF_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CFG_IMG_SEL -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_A[*] -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_D[*] -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE0_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE1_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_OE_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WE_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RY_BY_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_BYTE_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WP_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RST_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_A[*] +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_D[*] +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE0_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE1_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_OE_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WE_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RY_BY_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_BYTE_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WP_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RST_N set_global_assignment -name OCP_HW_EVAL DISABLE -# this parameter was set as disable beacouse it makes problem with build for ftile IP cores \ No newline at end of file +# this parameter was set as disable beacouse it makes problem with build for ftile IP cores diff --git a/cards/reflexces/agi-fh400g/constr/hps.qsf b/cards/reflexces/agi-fh400g/constr/hps.qsf index 10ec18af5..c1588b651 100644 --- a/cards/reflexces/agi-fh400g/constr/hps.qsf +++ b/cards/reflexces/agi-fh400g/constr/hps.qsf @@ -67,7 +67,7 @@ set_location_assignment PIN_BF34 -to HPS_DDR4_PAR set_location_assignment PIN_AA31 -to HPS_DDR4_REFCLK_P set_location_assignment PIN_AD32 -to HPS_DDR4_REFCLK_N -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to HPS_DDR4_REFCLK_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to HPS_DDR4_REFCLK_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to HPS_DDR4_REFCLK_P set_location_assignment PIN_N33 -to HPS_DDR4_ADDR[0] @@ -179,15 +179,15 @@ set_location_assignment PIN_W4 -to HPS_DDR4_DQ[3] set_location_assignment PIN_AN31 -to HPS_DDR4_OCT_RZQ -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_CLK_100MHZ +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_CLK_100MHZ set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_LED_R set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_LED_G -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_CLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_STP -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_STP +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_NXT set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[0] set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[1] set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[2] @@ -220,4 +220,4 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_M10_SPI_SCK set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_M10_RST_N set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_M10_INT_N -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_M10_ACK \ No newline at end of file +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_M10_ACK diff --git a/cards/reflexces/agi-fh400g/constr/multirate.qsf b/cards/reflexces/agi-fh400g/constr/multirate.qsf index c54110cfe..f932f2561 100644 --- a/cards/reflexces/agi-fh400g/constr/multirate.qsf +++ b/cards/reflexces/agi-fh400g/constr/multirate.qsf @@ -38,4 +38,4 @@ set_instance_assignment -name IP_COLOCATE F_TILE -from ag_i|network_mod_i|eth_co set_instance_assignment -name IP_RECONFIG_ID 25 -to ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|FTILE_MULTIRATE_ETH_8x25G1_8x10G1_g.eth_ip_g[6].FTILE_MULTIRATE_ETH_8x25G1_8x10G1_i|ftile_eth_ip_i|eth_f_dr_0 -entity FPGA set_instance_assignment -name IP_COLOCATE F_TILE -from ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|FTILE_MULTIRATE_ETH_8x25G1_8x10G1_g.eth_ip_g[0].FTILE_MULTIRATE_ETH_8x25G1_8x10G1_i|dr_ctrl_g.dr_ctrl_i|dr_f_0 -to ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|FTILE_MULTIRATE_ETH_8x25G1_8x10G1_g.eth_ip_g[7].FTILE_MULTIRATE_ETH_8x25G1_8x10G1_i|ftile_eth_ip_i|eth_f_dr_0 -entity FPGA -set_instance_assignment -name IP_RECONFIG_ID 29 -to ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|FTILE_MULTIRATE_ETH_8x25G1_8x10G1_g.eth_ip_g[7].FTILE_MULTIRATE_ETH_8x25G1_8x10G1_i|ftile_eth_ip_i|eth_f_dr_0 -entity FPGA \ No newline at end of file +set_instance_assignment -name IP_RECONFIG_ID 29 -to ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|FTILE_MULTIRATE_ETH_8x25G1_8x10G1_g.eth_ip_g[7].FTILE_MULTIRATE_ETH_8x25G1_8x10G1_i|ftile_eth_ip_i|eth_f_dr_0 -entity FPGA diff --git a/cards/reflexces/agi-fh400g/constr/qsfp_misc.qsf b/cards/reflexces/agi-fh400g/constr/qsfp_misc.qsf index 1a346a2c6..5b5a5cf37 100644 --- a/cards/reflexces/agi-fh400g/constr/qsfp_misc.qsf +++ b/cards/reflexces/agi-fh400g/constr/qsfp_misc.qsf @@ -58,4 +58,4 @@ set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_LED_G[3] set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_LED_G[4] set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_LED_G[5] set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_LED_G[6] -set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_LED_G[7] \ No newline at end of file +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_LED_G[7] diff --git a/cards/reflexces/agi-fh400g/constr/sodimm.qsf b/cards/reflexces/agi-fh400g/constr/sodimm.qsf index a2c57ee34..1b43f23f6 100644 --- a/cards/reflexces/agi-fh400g/constr/sodimm.qsf +++ b/cards/reflexces/agi-fh400g/constr/sodimm.qsf @@ -109,7 +109,7 @@ set_location_assignment PIN_LR25 -to SODIMM0_DQ[26] set_location_assignment PIN_LN26 -to SODIMM0_DQ[30] set_location_assignment PIN_KU36 -to SODIMM0_REFCLK_P -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM0_REFCLK_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM0_REFCLK_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM0_REFCLK_P #set_location_assignment PIN_KR37 -to SODIMM0_REFCLK_N set_location_assignment PIN_KJ37 -to SODIMM0_OCT_RZQ @@ -256,7 +256,7 @@ set_location_assignment PIN_KR53 -to SODIMM1_NDQS[4] set_location_assignment PIN_KF52 -to SODIMM1_DM_DBI[4] set_location_assignment PIN_MA56 -to SODIMM1_REFCLK_P -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM1_REFCLK_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM1_REFCLK_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM1_REFCLK_P #set_location_assignment PIN_LW55 -to SODIMM1_REFCLK_N set_location_assignment PIN_LN56 -to SODIMM1_OCT_RZQ diff --git a/cards/reflexces/agi-fh400g/constr/timing.sdc b/cards/reflexces/agi-fh400g/constr/timing.sdc index a0ab4db8f..8a4cd707c 100644 --- a/cards/reflexces/agi-fh400g/constr/timing.sdc +++ b/cards/reflexces/agi-fh400g/constr/timing.sdc @@ -41,7 +41,7 @@ set FHIP_10G8_CLK_CH21 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_ set FHIP_10G8_CLK_CH20 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x10g1_g.eth_ip_g[3].FTILE_8x10g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch20] set FHIP_10G8_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x10g1_g.eth_ip_g[0].FTILE_8x10g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 10G8 design +# Fix hold timing issues for 10G8 design set_clock_groups -asynchronous -group $FHIP_10G8_CLK_CH23 -group $FHIP_10G8_CLK_CH16 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_10G8_CLK_CH16 set_clock_groups -asynchronous -group $FHIP_10G8_CLK_CH23 -group $FHIP_10G8_CLK_CH17 @@ -95,7 +95,7 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_25G8_CLK_ set FHIP_40G2_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x40g4_g.eth_ip_g[1].FTILE_2x40g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch19] set FHIP_40G2_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x40g4_g.eth_ip_g[0].FTILE_2x40g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 40G2 design +# Fix hold timing issues for 40G2 design set_clock_groups -asynchronous -group $FHIP_40G2_CLK_CH23 -group $FHIP_40G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_40G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_40G2_CLK_CH23 @@ -113,7 +113,7 @@ set FHIP_50G8_CLK_CH15 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_ set FHIP_50G8_CLK_CH21 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x50g1_g.eth_ip_g[1].FTILE_8x50g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch21] set FHIP_50G8_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_8x50g1_g.eth_ip_g[0].FTILE_8x50g1_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 50G8 design +# Fix hold timing issues for 50G8 design set_clock_groups -asynchronous -group $FHIP_50G8_CLK_CH23 -group $FHIP_50G8_CLK_CH9 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_50G8_CLK_CH9 set_clock_groups -asynchronous -group $FHIP_50G8_CLK_CH23 -group $FHIP_50G8_CLK_CH11 @@ -137,7 +137,7 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_50G8_CLK_ set FHIP_100G2_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x100g4_g.eth_ip_g[1].FTILE_2x100g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch19] set FHIP_100G2_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x100g4_g.eth_ip_g[0].FTILE_2x100g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 100G2 design +# Fix hold timing issues for 100G2 design set_clock_groups -asynchronous -group $FHIP_100G2_CLK_CH23 -group $FHIP_100G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G2_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G2_CLK_CH23 @@ -151,7 +151,7 @@ set FHIP_100G4_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod set FHIP_100G4_CLK_CH15 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_4x100g2_g.eth_ip_g[2].FTILE_4x100g2_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch15] set FHIP_100G4_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_4x100g2_g.eth_ip_g[0].FTILE_4x100g2_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 100G4 design +# Fix hold timing issues for 100G4 design set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G4_CLK_CH11 set_clock_groups -asynchronous -group $FHIP_100G4_CLK_CH23 -group $FHIP_100G4_CLK_CH11 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G4_CLK_CH19 @@ -168,7 +168,7 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G4_CL set FHIP_200G2_CLK_CH15 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x200g4_g.eth_ip_g[1].ftile_2x200g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch15] set FHIP_200G2_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_2x200g4_g.eth_ip_g[0].ftile_2x200g4_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 200G2 design +# Fix hold timing issues for 200G2 design set_clock_groups -asynchronous -group $FHIP_200G2_CLK_CH23 -group $FHIP_200G2_CLK_CH15 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_200G2_CLK_CH15 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_200G2_CLK_CH23 @@ -179,7 +179,7 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_200G2_CL # ============ set FHIP_400G1_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_1x400g8_g.eth_ip_g[0].FTILE_1x400g8_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] -# Fix hold timing issues for 400G1 design +# Fix hold timing issues for 400G1 design set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_400G1_CLK_CH23 @@ -218,7 +218,7 @@ set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_25G8 set FHIP_100G2MR_CLK_CH19 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|FTILE_MULTIRATE_ETH_2x100G4_g.eth_ip_g[1].FTILE_MULTIRATE_ETH_2x100G4_i|ftile_eth_ip_i|eth_f_dr_0|tx_clkout|ch19] set FHIP_100G2MR_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|FTILE_MULTIRATE_ETH_2x100G4_g.eth_ip_g[0].FTILE_MULTIRATE_ETH_2x100G4_i|ftile_eth_ip_i|eth_f_dr_0|tx_clkout|ch23] -# Fix hold timing issues for 100G2 Multirate design +# Fix hold timing issues for 100G2 Multirate design set_clock_groups -asynchronous -group $FHIP_100G2MR_CLK_CH23 -group $FHIP_100G2MR_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G2MR_CLK_CH19 set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_100G2MR_CLK_CH23 diff --git a/cards/reflexces/agi-fh400g/src/fpga.vhd b/cards/reflexces/agi-fh400g/src/fpga.vhd index 0004430fb..ed47a7375 100644 --- a/cards/reflexces/agi-fh400g/src/fpga.vhd +++ b/cards/reflexces/agi-fh400g/src/fpga.vhd @@ -57,7 +57,7 @@ port ( AG_M10_REBOOT_N : out std_logic; -- MAX10 reboot request M10_AG_STATUS_N : in std_logic; -- MAX10 status M10_AG_DONE : in std_logic; -- MAX10 configuration done - + -- ========================================================================= -- AGILEX CONFIGURATION REUEST INTERFACE -- ========================================================================= @@ -77,7 +77,7 @@ port ( --FLASH_RY_BY_N : in std_logic; -- Memory Ready/busy signal (both) --FLASH_BYTE_N : out std_logic; -- Memory data bus width (8bits for both, active is LOW) --FLASH_WP_N : out std_logic; -- Memory data Write protect signal (for both, active is LOW) - --FLASH_RST_N : out std_logic; -- Memory reset signal (for both, active is LOW) + --FLASH_RST_N : out std_logic; -- Memory reset signal (for both, active is LOW) -- ========================================================================= -- PCIE INTERFACES @@ -347,7 +347,7 @@ architecture FULL of FPGA is cal_debug_reset_n_reset : in std_logic := 'X' -- reset ); end component sodimm_cal; - + component emif_agi027_cal is port ( calbus_read_0 : out std_logic; -- calbus_read @@ -397,7 +397,7 @@ architecture FULL of FPGA is signal pcie_ext_rx_n : std_logic_vector(15 downto 0); signal pcie_ext_tx_p : std_logic_vector(15 downto 0); signal pcie_ext_tx_n : std_logic_vector(15 downto 0); - + signal calbus_read : std_logic_vector(MEM_PORTS-1 downto 0); signal calbus_write : std_logic_vector(MEM_PORTS-1 downto 0); signal calbus_address : slv_array_t(MEM_PORTS-1 downto 0)(19 downto 0); @@ -411,7 +411,7 @@ architecture FULL of FPGA is signal mem_rst_n : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_pll_locked : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_pll_locked_sync : std_logic_vector(MEM_PORTS-1 downto 0); - + signal mem_avmm_ready : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_read : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_write : std_logic_vector(MEM_PORTS-1 downto 0); @@ -422,7 +422,7 @@ architecture FULL of FPGA is signal mem_avmm_writedata_f : slv_array_t(MEM_PORTS-1 downto 0)(576-1 downto 0) := (others => (others => '0')); signal mem_avmm_readdata_f : slv_array_t(MEM_PORTS-1 downto 0)(576-1 downto 0) := (others => (others => '0')); signal mem_avmm_readdatavalid : std_logic_vector(MEM_PORTS-1 downto 0); - + signal emif_rst_req : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_rst_done : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_ecc_usr_int : std_logic_vector(MEM_PORTS-1 downto 0); @@ -462,7 +462,7 @@ begin AG_I2C_SCLK <= 'Z'; AG_I2C_SDA <= 'Z'; - + AG_SOFT_RST <= '0'; AG_M10_RST_N <= '1'; @@ -512,7 +512,7 @@ begin PCI_DEVICE_ID => X"C400", PCI_SUBVENDOR_ID => X"0000", PCI_SUBDEVICE_ID => X"0000", - + ETH_CORE_ARCH => NET_MOD_ARCH, ETH_PORTS => ETH_PORTS, ETH_PORT_SPEED => ETH_PORT_SPEED, @@ -606,7 +606,7 @@ begin PCIE_CLK => pcie_clk, PCIE_RESET => pcie_reset, - + BOOT_MI_CLK => boot_mi_clk, BOOT_MI_RESET => boot_mi_reset, BOOT_MI_DWR => boot_mi_dwr, @@ -650,7 +650,7 @@ begin FLASH_WR_DATA => flash_wr_data, FLASH_WR_EN => flash_wr_en, FLASH_RD_DATA => flash_rd_data - ); + ); FLASHCTRL_I: entity work.flashctrl generic map ( @@ -725,8 +725,8 @@ begin mem_dq(71 downto 64) => SODIMM0_CHKB, mem_dbi_n => SODIMM0_DM_DBI, local_cal_success => emif_cal_success(0), - local_cal_fail => emif_cal_fail(0), - emif_usr_reset_n => mem_rst_n(0), + local_cal_fail => emif_cal_fail(0), + emif_usr_reset_n => mem_rst_n(0), emif_usr_clk => mem_clk(0), amm_ready_0 => mem_avmm_ready(0), amm_read_0 => mem_avmm_read(0), @@ -737,12 +737,12 @@ begin amm_burstcount_0 => mem_avmm_burstcount(0), amm_readdatavalid_0 => mem_avmm_readdatavalid(0), amm_byteenable_0 => (others => '1'), - calbus_read => calbus_read(0), - calbus_write => calbus_write(0), + calbus_read => calbus_read(0), + calbus_write => calbus_write(0), calbus_address => calbus_address(0), - calbus_wdata => calbus_wdata(0), - calbus_rdata => calbus_rdata(0), - calbus_seq_param_tbl => calbus_seq_param_tbl(0), + calbus_wdata => calbus_wdata(0), + calbus_rdata => calbus_rdata(0), + calbus_seq_param_tbl => calbus_seq_param_tbl(0), calbus_clk => calbus_clk(0) ); @@ -771,8 +771,8 @@ begin mem_dq(71 downto 64) => SODIMM1_CHKB, mem_dbi_n => SODIMM1_DM_DBI, local_cal_success => emif_cal_success(1), - local_cal_fail => emif_cal_fail(1), - emif_usr_reset_n => mem_rst_n(1), + local_cal_fail => emif_cal_fail(1), + emif_usr_reset_n => mem_rst_n(1), emif_usr_clk => mem_clk(1), amm_ready_0 => mem_avmm_ready(1), amm_read_0 => mem_avmm_read(1), @@ -783,12 +783,12 @@ begin amm_burstcount_0 => mem_avmm_burstcount(1), amm_readdatavalid_0 => mem_avmm_readdatavalid(1), amm_byteenable_0 => (others => '1'), - calbus_read => calbus_read(1), - calbus_write => calbus_write(1), + calbus_read => calbus_read(1), + calbus_write => calbus_write(1), calbus_address => calbus_address(1), - calbus_wdata => calbus_wdata(1), - calbus_rdata => calbus_rdata(1), - calbus_seq_param_tbl => calbus_seq_param_tbl(1), + calbus_wdata => calbus_wdata(1), + calbus_rdata => calbus_rdata(1), + calbus_seq_param_tbl => calbus_seq_param_tbl(1), calbus_clk => calbus_clk(1) ); @@ -881,11 +881,11 @@ begin emif_cal_i : component emif_agi027_cal port map ( - calbus_read_0 => calbus_read(0), - calbus_write_0 => calbus_write(0), - calbus_address_0 => calbus_address(0), - calbus_wdata_0 => calbus_wdata(0), - calbus_rdata_0 => calbus_rdata(0), + calbus_read_0 => calbus_read(0), + calbus_write_0 => calbus_write(0), + calbus_address_0 => calbus_address(0), + calbus_wdata_0 => calbus_wdata(0), + calbus_rdata_0 => calbus_rdata(0), calbus_seq_param_tbl_0 => calbus_seq_param_tbl(0), calbus_clk => calbus_clk(0), cal_debug_clk_clk => mem_clk(0), diff --git a/cards/reflexces/agi-fh400g/src/ip/ftile_mr_eth.ip.tcl b/cards/reflexces/agi-fh400g/src/ip/ftile_mr_eth.ip.tcl index ed9564253..d41615346 100644 --- a/cards/reflexces/agi-fh400g/src/ip/ftile_mr_eth.ip.tcl +++ b/cards/reflexces/agi-fh400g/src/ip/ftile_mr_eth.ip.tcl @@ -39,7 +39,7 @@ proc do_adjust_ftile_mr_eth_ip_1x100g {} { set_instance_parameter_value eth_f_dr_0 {RCFG_GRP_GUI} {100G-4} set_instance_parameter_value eth_f_dr_0 {RSFEC_TYPE_P0_GUI} {2} set_instance_parameter_value eth_f_dr_0 {START_PROF_GUI} {1x100GE-4} - + set_interface_property o_p1_clk_tx_div EXPORT_OF eth_f_dr_0.o_p1_clk_tx_div set_interface_property o_p1_clk_rec_div64 EXPORT_OF eth_f_dr_0.o_p1_clk_rec_div64 set_interface_property o_p1_clk_rec_div EXPORT_OF eth_f_dr_0.o_p1_clk_rec_div diff --git a/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.qsf b/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.qsf index 7711c6bec..c876b7dcc 100644 --- a/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.qsf +++ b/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.qsf @@ -145,52 +145,52 @@ set_location_assignment PIN_BM64 -to FLASH_BYTE_N set_location_assignment PIN_BC65 -to FLASH_WP_N set_location_assignment PIN_AY66 -to FLASH_RST_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[2] set_instance_assignment -name IO_STANDARD "1.2 V" -to HW_ID[3] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_G[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_LED_R[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SCLK -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SCLK +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_I2C_SDA -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK0_P -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK1_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK0_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK1_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK0_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK1_P -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_EXT_SYNC_1HZ +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_EXT_SYNC_1HZ -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_INT_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_GEN_LOL_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_INT_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CLK_GEN_LOL_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_DEV_POR_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_RST_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_SOFT_RST -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_RST_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_DEV_POR_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_RST_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_SOFT_RST +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_RST_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_IMG_SEL_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_REBOOT_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_DONE -set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_STATUS_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_IMG_SEL_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_M10_REBOOT_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_DONE +set_instance_assignment -name IO_STANDARD "1.2 V" -to M10_AG_STATUS_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_REQ_CONF_N -set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CFG_IMG_SEL +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_REQ_CONF_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to AG_CFG_IMG_SEL -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_A[*] -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_D[*] -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE0_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE1_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_OE_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WE_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RY_BY_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_BYTE_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WP_N -#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RST_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_A[*] +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_D[*] +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE0_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_CE1_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_OE_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WE_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RY_BY_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_BYTE_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_WP_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to FLASH_RST_N set_location_assignment PIN_U17 -to HPS_CLK_100MHZ @@ -251,7 +251,7 @@ set_location_assignment PIN_BF34 -to HPS_DDR4_PAR set_location_assignment PIN_AA31 -to HPS_DDR4_REFCLK_P set_location_assignment PIN_AD32 -to HPS_DDR4_REFCLK_N -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to HPS_DDR4_REFCLK_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to HPS_DDR4_REFCLK_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to HPS_DDR4_REFCLK_P set_location_assignment PIN_N33 -to HPS_DDR4_ADDR[0] @@ -363,15 +363,15 @@ set_location_assignment PIN_W4 -to HPS_DDR4_DQ[3] set_location_assignment PIN_AN31 -to HPS_DDR4_OCT_RZQ -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_CLK_100MHZ +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_CLK_100MHZ set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_LED_R set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_LED_G -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_CLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_STP -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DIR -set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_NXT +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_CLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_STP +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DIR +set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_NXT set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[0] set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[1] set_instance_assignment -name IO_STANDARD "1.8 V" -to HPS_USB_DATA[2] @@ -1022,7 +1022,7 @@ set_location_assignment PIN_LR25 -to SODIMM0_DQ[26] set_location_assignment PIN_LN26 -to SODIMM0_DQ[30] set_location_assignment PIN_KU36 -to SODIMM0_REFCLK_P -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM0_REFCLK_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM0_REFCLK_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM0_REFCLK_P #set_location_assignment PIN_KR37 -to SODIMM0_REFCLK_N set_location_assignment PIN_KJ37 -to SODIMM0_OCT_RZQ @@ -1169,7 +1169,7 @@ set_location_assignment PIN_KR53 -to SODIMM1_NDQS[4] set_location_assignment PIN_KF52 -to SODIMM1_DM_DBI[4] set_location_assignment PIN_MA56 -to SODIMM1_REFCLK_P -set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM1_REFCLK_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SODIMM1_REFCLK_P set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM1_REFCLK_P #set_location_assignment PIN_LW55 -to SODIMM1_REFCLK_N set_location_assignment PIN_LN56 -to SODIMM1_OCT_RZQ diff --git a/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.vhd b/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.vhd index 7d3ec5b9c..eecfdee9a 100644 --- a/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.vhd +++ b/cards/reflexces/agi-fh400g/tutorials/leds_example/fpga.vhd @@ -50,7 +50,7 @@ port ( AG_M10_REBOOT_N : out std_logic; -- MAX10 reboot request M10_AG_STATUS_N : in std_logic; -- MAX10 status M10_AG_DONE : in std_logic; -- MAX10 configuration done - + -- ========================================================================= -- AGILEX CONFIGURATION REUEST INTERFACE -- ========================================================================= @@ -70,7 +70,7 @@ port ( --FLASH_RY_BY_N : in std_logic; -- Memory Ready/busy signal (both) --FLASH_BYTE_N : out std_logic; -- Memory data bus width (8bits for both, active is LOW) --FLASH_WP_N : out std_logic; -- Memory data Write protect signal (for both, active is LOW) - --FLASH_RST_N : out std_logic; -- Memory reset signal (for both, active is LOW) + --FLASH_RST_N : out std_logic; -- Memory reset signal (for both, active is LOW) -- ========================================================================= -- PCIE INTERFACES @@ -273,7 +273,7 @@ begin AG_I2C_SCLK <= 'Z'; AG_I2C_SDA <= 'Z'; - + AG_SOFT_RST <= '0'; AG_M10_RST_N <= '1'; diff --git a/cards/reflexces/agi-fh400g/tutorials/leds_example/math_pack.vhd b/cards/reflexces/agi-fh400g/tutorials/leds_example/math_pack.vhd index 8890446d4..b2a1a062a 100644 --- a/cards/reflexces/agi-fh400g/tutorials/leds_example/math_pack.vhd +++ b/cards/reflexces/agi-fh400g/tutorials/leds_example/math_pack.vhd @@ -19,7 +19,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ---! \brief Package with basic math functions +--! \brief Package with basic math functions --! \details This package contains math functions: log2, max, min and div_roundup. package math_pack is @@ -71,7 +71,7 @@ package math_pack is function tsel(cond : boolean; true_val: std_logic_vector; false_val: std_logic_vector) return std_logic_vector; function tsel(cond : boolean; true_val: string; false_val: string) return string; - --!\brief returns smalest value witch is diveded by base and is not smallest that x + --!\brief returns smalest value witch is diveded by base and is not smallest that x function ceil(x,base : integer) return integer; -- Round the given 'value' up, so that the lower 'rounding_width' bits are zero @@ -107,10 +107,10 @@ package math_pack is function enlarge_left(vector : signed; width_addition : integer) return signed; function enlarge_right(vector : unsigned; width_addition : integer) return unsigned; function enlarge_right(vector : signed; width_addition : integer) return signed; - + end math_pack; ---! \brief Body of package with basic math functions +--! \brief Body of package with basic math functions package body math_pack is --! \brief Logarithm with base 2. @@ -157,7 +157,7 @@ package body math_pack is return R; end if; end; - + --! \brief Selects lower number from two given. function min(L, R: integer) return integer is begin @@ -167,7 +167,7 @@ package body math_pack is return R; end if; end; - + --! \brief Selects lower number from two given. function minimum(L, R: integer) return integer is begin diff --git a/cards/reflexces/agi-fh400g/tutorials/leds_example/reset.vhd b/cards/reflexces/agi-fh400g/tutorials/leds_example/reset.vhd index 3126922fd..2d7da93b6 100644 --- a/cards/reflexces/agi-fh400g/tutorials/leds_example/reset.vhd +++ b/cards/reflexces/agi-fh400g/tutorials/leds_example/reset.vhd @@ -17,9 +17,9 @@ entity ASYNC_RESET is TWO_REG : BOOLEAN := false; --! For two reg = true, for three reg = false OUT_REG : BOOLEAN := false; --! Registering of output reset by single normal register in destination clock domain. REPLICAS : INTEGER := 1 --! Number of output register replicas (registers actually replicated only when OUT_REG is true). - ); + ); Port ( - --! A clock domain + --! A clock domain CLK : in STD_LOGIC; --! Clock ASYNC_RST : in STD_LOGIC; --! Asynchronous reset OUT_RST : out STD_LOGIC_VECTOR(max(REPLICAS,1)-1 downto 0) --! Output reset @@ -35,7 +35,7 @@ architecture FULL of ASYNC_RESET is --! ------------------------------------------------------------------------- --! Signals --! ------------------------------------------------------------------------- - + signal rff1 : std_logic := '1'; signal rff2 : std_logic := '1'; signal rff_out : std_logic := '1'; @@ -44,7 +44,7 @@ architecture FULL of ASYNC_RESET is attribute dont_touch : string; attribute shreg_extract : string; attribute async_reg : string; - + --! Xilinx attributes for rff1_reg and rff2_reg -- attribute dont_touch of rff1 : signal is "true"; attribute shreg_extract of rff1 : signal is "no"; @@ -60,7 +60,7 @@ architecture FULL of ASYNC_RESET is attribute ALTERA_ATTRIBUTE of rff2 : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; --! ------------------------------------------------------------------------- - + begin --! ------------------------------------------------------------------------- @@ -85,40 +85,40 @@ begin end process; --! ------------------------------------------------------------------------- - + --! Generics two synchronization registers two_reg_sync : if TWO_REG generate rff_out <= rff2; - - end generate; - + + end generate; + --! ------------------------------------------------------------------------- - + --! Generics three synchronization registers three_reg_sync : if NOT TWO_REG generate - + --! Signals signal rff3 : std_logic := '1'; - + --! Attributes for rff3_reg attribute shreg_extract of rff3 : signal is "no"; attribute async_reg of rff3 : signal is "true"; attribute ALTERA_ATTRIBUTE of rff3 : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; - + begin - + rff3_reg : process(CLK, ASYNC_RST) begin if (ASYNC_RST = '1') then rff3 <= '1'; elsif (rising_edge(CLK)) then - rff3 <= rff2; + rff3 <= rff2; end if; end process; - + rff_out <= rff3; - + end generate; --! ------------------------------------------------------------------------- @@ -138,7 +138,7 @@ begin replicas_gen : for i in 0 to REPLICAS-1 generate signal rff_reg_out : std_logic := '1'; - + attribute dont_touch of rff_reg_out : signal is "true"; attribute maxfan of rff_reg_out : signal is 64; attribute ALTERA_ATTRIBUTE of rff_reg_out : signal is "-name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; diff --git a/cards/silicom/fb2cghh/constr/ddr4.xdc b/cards/silicom/fb2cghh/constr/ddr4.xdc index 29bd029f1..306144dd6 100644 --- a/cards/silicom/fb2cghh/constr/ddr4.xdc +++ b/cards/silicom/fb2cghh/constr/ddr4.xdc @@ -6,39 +6,39 @@ # DDR4A interface # Internal Clocks -set_property PACKAGE_PIN AU32 [get_ports {REFCLKA_DDR4_N}] -set_property PACKAGE_PIN AT32 [get_ports {REFCLKA_DDR4_P}] +set_property PACKAGE_PIN AU32 [get_ports {REFCLKA_DDR4_N}] +set_property PACKAGE_PIN AT32 [get_ports {REFCLKA_DDR4_P}] set_property IOSTANDARD DIFF_SSTL12 [get_ports [list REFCLKA_DDR4_*]] create_clock -period 3.750 [get_ports REFCLKA_DDR4_P] #General Pins -set_property PACKAGE_PIN AR21 [get_ports {DDR4A_A[0]}] -set_property PACKAGE_PIN AV22 [get_ports {DDR4A_A[1]}] -set_property PACKAGE_PIN AP23 [get_ports {DDR4A_A[2]}] -set_property PACKAGE_PIN AK23 [get_ports {DDR4A_A[3]}] -set_property PACKAGE_PIN AT21 [get_ports {DDR4A_A[4]}] -set_property PACKAGE_PIN AV23 [get_ports {DDR4A_A[5]}] -set_property PACKAGE_PIN BB23 [get_ports {DDR4A_A[6]}] -set_property PACKAGE_PIN AT24 [get_ports {DDR4A_A[7]}] -set_property PACKAGE_PIN AW24 [get_ports {DDR4A_A[8]}] -set_property PACKAGE_PIN AU24 [get_ports {DDR4A_A[9]}] -set_property PACKAGE_PIN AV21 [get_ports {DDR4A_A[10]}] -set_property PACKAGE_PIN AY24 [get_ports {DDR4A_A[11]}] -set_property PACKAGE_PIN AL22 [get_ports {DDR4A_A[12]}] -set_property PACKAGE_PIN AT22 [get_ports {DDR4A_A[13]}] -set_property PACKAGE_PIN AY21 [get_ports {DDR4A_A[14]}] -set_property PACKAGE_PIN BA22 [get_ports {DDR4A_A[15]}] -set_property PACKAGE_PIN BB25 [get_ports {DDR4A_A[16]}] +set_property PACKAGE_PIN AR21 [get_ports {DDR4A_A[0]}] +set_property PACKAGE_PIN AV22 [get_ports {DDR4A_A[1]}] +set_property PACKAGE_PIN AP23 [get_ports {DDR4A_A[2]}] +set_property PACKAGE_PIN AK23 [get_ports {DDR4A_A[3]}] +set_property PACKAGE_PIN AT21 [get_ports {DDR4A_A[4]}] +set_property PACKAGE_PIN AV23 [get_ports {DDR4A_A[5]}] +set_property PACKAGE_PIN BB23 [get_ports {DDR4A_A[6]}] +set_property PACKAGE_PIN AT24 [get_ports {DDR4A_A[7]}] +set_property PACKAGE_PIN AW24 [get_ports {DDR4A_A[8]}] +set_property PACKAGE_PIN AU24 [get_ports {DDR4A_A[9]}] +set_property PACKAGE_PIN AV21 [get_ports {DDR4A_A[10]}] +set_property PACKAGE_PIN AY24 [get_ports {DDR4A_A[11]}] +set_property PACKAGE_PIN AL22 [get_ports {DDR4A_A[12]}] +set_property PACKAGE_PIN AT22 [get_ports {DDR4A_A[13]}] +set_property PACKAGE_PIN AY21 [get_ports {DDR4A_A[14]}] +set_property PACKAGE_PIN BA22 [get_ports {DDR4A_A[15]}] +set_property PACKAGE_PIN BB25 [get_ports {DDR4A_A[16]}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4A_A[*]] -set_property PACKAGE_PIN BB22 [get_ports {DDR4A_BA[0]}] -set_property PACKAGE_PIN AW23 [get_ports {DDR4A_BA[1]}] +set_property PACKAGE_PIN BB22 [get_ports {DDR4A_BA[0]}] +set_property PACKAGE_PIN AW23 [get_ports {DDR4A_BA[1]}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4A_BA[*]] set_property PACKAGE_PIN AY22 [get_ports {DDR4A_CKE}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4A_CKE[*]] -set_property PACKAGE_PIN ba25 [get_ports {DDR4A_CS_N}] +set_property PACKAGE_PIN ba25 [get_ports {DDR4A_CS_N}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4A_CS_N] set_property PACKAGE_PIN AR14 [get_ports {DDR4A_LDM[0]}] @@ -54,16 +54,16 @@ set_property PACKAGE_PIN AP19 [get_ports {DDR4A_UDM[2]}] set_property PACKAGE_PIN AT20 [get_ports {DDR4A_UDM[3]}] set_property IOSTANDARD POD12_DCI [get_ports DDR4A_UDM[*]] -set_property PACKAGE_PIN AR12 [get_ports {DDR4A_DQ[0]}] -set_property PACKAGE_PIN AP15 [get_ports {DDR4A_DQ[1]}] -set_property PACKAGE_PIN AP13 [get_ports {DDR4A_DQ[2]}] -set_property PACKAGE_PIN AM14 [get_ports {DDR4A_DQ[3]}] -set_property PACKAGE_PIN AT12 [get_ports {DDR4A_DQ[4]}] -set_property PACKAGE_PIN AM15 [get_ports {DDR4A_DQ[5]}] -set_property PACKAGE_PIN AR13 [get_ports {DDR4A_DQ[6]}] -set_property PACKAGE_PIN AP14 [get_ports {DDR4A_DQ[7]}] -set_property PACKAGE_PIN AK19 [get_ports {DDR4A_DQ[8]}] -set_property PACKAGE_PIN AH17 [get_ports {DDR4A_DQ[9]}] +set_property PACKAGE_PIN AR12 [get_ports {DDR4A_DQ[0]}] +set_property PACKAGE_PIN AP15 [get_ports {DDR4A_DQ[1]}] +set_property PACKAGE_PIN AP13 [get_ports {DDR4A_DQ[2]}] +set_property PACKAGE_PIN AM14 [get_ports {DDR4A_DQ[3]}] +set_property PACKAGE_PIN AT12 [get_ports {DDR4A_DQ[4]}] +set_property PACKAGE_PIN AM15 [get_ports {DDR4A_DQ[5]}] +set_property PACKAGE_PIN AR13 [get_ports {DDR4A_DQ[6]}] +set_property PACKAGE_PIN AP14 [get_ports {DDR4A_DQ[7]}] +set_property PACKAGE_PIN AK19 [get_ports {DDR4A_DQ[8]}] +set_property PACKAGE_PIN AH17 [get_ports {DDR4A_DQ[9]}] set_property PACKAGE_PIN AM17 [get_ports {DDR4A_DQ[10]}] set_property PACKAGE_PIN AJ16 [get_ports {DDR4A_DQ[11]}] set_property PACKAGE_PIN AL19 [get_ports {DDR4A_DQ[12]}] @@ -154,148 +154,148 @@ set_property PACKAGE_PIN AM19 [get_ports {DDR4A_UDQS_P[2]}] set_property PACKAGE_PIN AR17 [get_ports {DDR4A_UDQS_P[3]}] set_property IOSTANDARD DIFF_POD12_DCI [get_ports DDR4A_UDQS_P[*]] -set_property PACKAGE_PIN AY23 [get_ports {DDR4A_ODT}] +set_property PACKAGE_PIN AY23 [get_ports {DDR4A_ODT}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4A_ODT*] -set_property PACKAGE_PIN BA21 [get_ports {DDR4A_BG[0]}] -set_property PACKAGE_PIN AL21 [get_ports {DDR4A_BG[1]}] +set_property PACKAGE_PIN BA21 [get_ports {DDR4A_BG[0]}] +set_property PACKAGE_PIN AL21 [get_ports {DDR4A_BG[1]}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4A_BG[*]] set_property PACKAGE_PIN AV20 [get_ports {DDR4A_RESET_N}] set_property IOSTANDARD LVCMOS12 [get_ports DDR4A_RESET_N] set_property DRIVE 8 [get_ports DDR4A_RESET_N] -set_property PACKAGE_PIN AW21 [get_ports {DDR4A_ACT_N}] +set_property PACKAGE_PIN AW21 [get_ports {DDR4A_ACT_N}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4A_ACT_N] -set_property PACKAGE_PIN BB24 [get_ports {DDR4A_CK_N}] +set_property PACKAGE_PIN BB24 [get_ports {DDR4A_CK_N}] set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4A_CK_N[*]] -set_property PACKAGE_PIN BA24 [get_ports {DDR4A_CK_P}] +set_property PACKAGE_PIN BA24 [get_ports {DDR4A_CK_P}] set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4A_CK_P[*]] # DDR4B interface # Internal Clocks -set_property PACKAGE_PIN G29 [get_ports {REFCLKB_DDR4_N}] -set_property PACKAGE_PIN G28 [get_ports {REFCLKB_DDR4_P}] +set_property PACKAGE_PIN G29 [get_ports {REFCLKB_DDR4_N}] +set_property PACKAGE_PIN G28 [get_ports {REFCLKB_DDR4_P}] set_property IOSTANDARD DIFF_SSTL12 [get_ports [list REFCLKB_DDR4_*]] create_clock -period 3.750 [get_ports REFCLKB_DDR4_P] #General Pins -set_property PACKAGE_PIN J24 [get_ports {DDR4B_A[0]}] -set_property PACKAGE_PIN G24 [get_ports {DDR4B_A[1]}] -set_property PACKAGE_PIN K26 [get_ports {DDR4B_A[2]}] -set_property PACKAGE_PIN E25 [get_ports {DDR4B_A[3]}] -set_property PACKAGE_PIN G23 [get_ports {DDR4B_A[4]}] -set_property PACKAGE_PIN G26 [get_ports {DDR4B_A[5]}] -set_property PACKAGE_PIN J25 [get_ports {DDR4B_A[6]}] -set_property PACKAGE_PIN H25 [get_ports {DDR4B_A[7]}] -set_property PACKAGE_PIN K25 [get_ports {DDR4B_A[8]}] -set_property PACKAGE_PIN H24 [get_ports {DDR4B_A[9]}] -set_property PACKAGE_PIN F23 [get_ports {DDR4B_A[10]}] -set_property PACKAGE_PIN J27 [get_ports {DDR4B_A[11]}] -set_property PACKAGE_PIN F26 [get_ports {DDR4B_A[12]}] -set_property PACKAGE_PIN H27 [get_ports {DDR4B_A[13]}] -set_property PACKAGE_PIN F25 [get_ports {DDR4B_A[14]}] -set_property PACKAGE_PIN B22 [get_ports {DDR4B_A[15]}] -set_property PACKAGE_PIN G27 [get_ports {DDR4B_A[16]}] +set_property PACKAGE_PIN J24 [get_ports {DDR4B_A[0]}] +set_property PACKAGE_PIN G24 [get_ports {DDR4B_A[1]}] +set_property PACKAGE_PIN K26 [get_ports {DDR4B_A[2]}] +set_property PACKAGE_PIN E25 [get_ports {DDR4B_A[3]}] +set_property PACKAGE_PIN G23 [get_ports {DDR4B_A[4]}] +set_property PACKAGE_PIN G26 [get_ports {DDR4B_A[5]}] +set_property PACKAGE_PIN J25 [get_ports {DDR4B_A[6]}] +set_property PACKAGE_PIN H25 [get_ports {DDR4B_A[7]}] +set_property PACKAGE_PIN K25 [get_ports {DDR4B_A[8]}] +set_property PACKAGE_PIN H24 [get_ports {DDR4B_A[9]}] +set_property PACKAGE_PIN F23 [get_ports {DDR4B_A[10]}] +set_property PACKAGE_PIN J27 [get_ports {DDR4B_A[11]}] +set_property PACKAGE_PIN F26 [get_ports {DDR4B_A[12]}] +set_property PACKAGE_PIN H27 [get_ports {DDR4B_A[13]}] +set_property PACKAGE_PIN F25 [get_ports {DDR4B_A[14]}] +set_property PACKAGE_PIN B22 [get_ports {DDR4B_A[15]}] +set_property PACKAGE_PIN G27 [get_ports {DDR4B_A[16]}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4B_A[*]] -set_property PACKAGE_PIN J23 [get_ports {DDR4B_BA[0]}] -set_property PACKAGE_PIN D25 [get_ports {DDR4B_BA[1]}] +set_property PACKAGE_PIN J23 [get_ports {DDR4B_BA[0]}] +set_property PACKAGE_PIN D25 [get_ports {DDR4B_BA[1]}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4B_BA[*]] -set_property PACKAGE_PIN D23 [get_ports {DDR4B_CKE}] +set_property PACKAGE_PIN D23 [get_ports {DDR4B_CKE}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4B_CKE[*]] -set_property PACKAGE_PIN B27 [get_ports {DDR4B_CS_N}] +set_property PACKAGE_PIN B27 [get_ports {DDR4B_CS_N}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4B_CS_N] -set_property PACKAGE_PIN N16 [get_ports {DDR4B_LDM[0]}] -set_property PACKAGE_PIN K17 [get_ports {DDR4B_LDM[1]}] -set_property PACKAGE_PIN B18 [get_ports {DDR4B_LDM[2]}] -set_property PACKAGE_PIN C27 [get_ports {DDR4B_LDM[3]}] -set_property PACKAGE_PIN F21 [get_ports {DDR4B_LDM[4]}] +set_property PACKAGE_PIN N16 [get_ports {DDR4B_LDM[0]}] +set_property PACKAGE_PIN K17 [get_ports {DDR4B_LDM[1]}] +set_property PACKAGE_PIN B18 [get_ports {DDR4B_LDM[2]}] +set_property PACKAGE_PIN C27 [get_ports {DDR4B_LDM[3]}] +set_property PACKAGE_PIN F21 [get_ports {DDR4B_LDM[4]}] set_property IOSTANDARD POD12_DCI [get_ports DDR4B_LDM[*]] -set_property PACKAGE_PIN F15 [get_ports {DDR4B_UDM[0]}] -set_property PACKAGE_PIN B14 [get_ports {DDR4B_UDM[1]}] -set_property PACKAGE_PIN L20 [get_ports {DDR4B_UDM[2]}] -set_property PACKAGE_PIN M19 [get_ports {DDR4B_UDM[3]}] +set_property PACKAGE_PIN F15 [get_ports {DDR4B_UDM[0]}] +set_property PACKAGE_PIN B14 [get_ports {DDR4B_UDM[1]}] +set_property PACKAGE_PIN L20 [get_ports {DDR4B_UDM[2]}] +set_property PACKAGE_PIN M19 [get_ports {DDR4B_UDM[3]}] set_property IOSTANDARD POD12_DCI [get_ports DDR4B_UDM[*]] -set_property PACKAGE_PIN P12 [get_ports {DDR4B_DQ[0]}] -set_property PACKAGE_PIN M14 [get_ports {DDR4B_DQ[1]}] -set_property PACKAGE_PIN P13 [get_ports {DDR4B_DQ[2]}] -set_property PACKAGE_PIN N12 [get_ports {DDR4B_DQ[3]}] -set_property PACKAGE_PIN N15 [get_ports {DDR4B_DQ[4]}] -set_property PACKAGE_PIN M12 [get_ports {DDR4B_DQ[5]}] -set_property PACKAGE_PIN P15 [get_ports {DDR4B_DQ[6]}] -set_property PACKAGE_PIN M13 [get_ports {DDR4B_DQ[7]}] -set_property PACKAGE_PIN G17 [get_ports {DDR4B_DQ[8]}] -set_property PACKAGE_PIN E16 [get_ports {DDR4B_DQ[9]}] -set_property PACKAGE_PIN G16 [get_ports {DDR4B_DQ[10]}] -set_property PACKAGE_PIN F18 [get_ports {DDR4B_DQ[11]}] -set_property PACKAGE_PIN H17 [get_ports {DDR4B_DQ[12]}] -set_property PACKAGE_PIN E17 [get_ports {DDR4B_DQ[13]}] -set_property PACKAGE_PIN F16 [get_ports {DDR4B_DQ[14]}] -set_property PACKAGE_PIN E18 [get_ports {DDR4B_DQ[15]}] -set_property PACKAGE_PIN K16 [get_ports {DDR4B_DQ[16]}] -set_property PACKAGE_PIN H14 [get_ports {DDR4B_DQ[17]}] -set_property PACKAGE_PIN K15 [get_ports {DDR4B_DQ[18]}] -set_property PACKAGE_PIN J14 [get_ports {DDR4B_DQ[19]}] -set_property PACKAGE_PIN L16 [get_ports {DDR4B_DQ[20]}] -set_property PACKAGE_PIN H15 [get_ports {DDR4B_DQ[21]}] -set_property PACKAGE_PIN J15 [get_ports {DDR4B_DQ[22]}] -set_property PACKAGE_PIN H16 [get_ports {DDR4B_DQ[23]}] -set_property PACKAGE_PIN D17 [get_ports {DDR4B_DQ[24]}] -set_property PACKAGE_PIN A16 [get_ports {DDR4B_DQ[25]}] -set_property PACKAGE_PIN D18 [get_ports {DDR4B_DQ[26]}] -set_property PACKAGE_PIN A15 [get_ports {DDR4B_DQ[27]}] -set_property PACKAGE_PIN D15 [get_ports {DDR4B_DQ[28]}] -set_property PACKAGE_PIN C17 [get_ports {DDR4B_DQ[29]}] -set_property PACKAGE_PIN C15 [get_ports {DDR4B_DQ[30]}] -set_property PACKAGE_PIN B17 [get_ports {DDR4B_DQ[31]}] -set_property PACKAGE_PIN B19 [get_ports {DDR4B_DQ[32]}] -set_property PACKAGE_PIN C21 [get_ports {DDR4B_DQ[33]}] -set_property PACKAGE_PIN A19 [get_ports {DDR4B_DQ[34]}] -set_property PACKAGE_PIN A21 [get_ports {DDR4B_DQ[35]}] -set_property PACKAGE_PIN D19 [get_ports {DDR4B_DQ[36]}] -set_property PACKAGE_PIN B21 [get_ports {DDR4B_DQ[37]}] -set_property PACKAGE_PIN A20 [get_ports {DDR4B_DQ[38]}] -set_property PACKAGE_PIN D20 [get_ports {DDR4B_DQ[39]}] -set_property PACKAGE_PIN H19 [get_ports {DDR4B_DQ[40]}] -set_property PACKAGE_PIN K21 [get_ports {DDR4B_DQ[41]}] -set_property PACKAGE_PIN J19 [get_ports {DDR4B_DQ[42]}] -set_property PACKAGE_PIN K20 [get_ports {DDR4B_DQ[43]}] -set_property PACKAGE_PIN K18 [get_ports {DDR4B_DQ[44]}] -set_property PACKAGE_PIN H20 [get_ports {DDR4B_DQ[45]}] -set_property PACKAGE_PIN L18 [get_ports {DDR4B_DQ[46]}] -set_property PACKAGE_PIN J20 [get_ports {DDR4B_DQ[47]}] -set_property PACKAGE_PIN A23 [get_ports {DDR4B_DQ[48]}] -set_property PACKAGE_PIN C26 [get_ports {DDR4B_DQ[49]}] -set_property PACKAGE_PIN C24 [get_ports {DDR4B_DQ[50]}] -set_property PACKAGE_PIN A26 [get_ports {DDR4B_DQ[51]}] -set_property PACKAGE_PIN A24 [get_ports {DDR4B_DQ[52]}] -set_property PACKAGE_PIN B26 [get_ports {DDR4B_DQ[53]}] -set_property PACKAGE_PIN A25 [get_ports {DDR4B_DQ[54]}] -set_property PACKAGE_PIN C25 [get_ports {DDR4B_DQ[55]}] -set_property PACKAGE_PIN N19 [get_ports {DDR4B_DQ[56]}] -set_property PACKAGE_PIN N20 [get_ports {DDR4B_DQ[57]}] -set_property PACKAGE_PIN P22 [get_ports {DDR4B_DQ[58]}] -set_property PACKAGE_PIN N21 [get_ports {DDR4B_DQ[59]}] -set_property PACKAGE_PIN P19 [get_ports {DDR4B_DQ[60]}] -set_property PACKAGE_PIN N22 [get_ports {DDR4B_DQ[61]}] -set_property PACKAGE_PIN P18 [get_ports {DDR4B_DQ[62]}] -set_property PACKAGE_PIN P20 [get_ports {DDR4B_DQ[63]}] -set_property PACKAGE_PIN E21 [get_ports {DDR4B_DQ[64]}] -set_property PACKAGE_PIN G22 [get_ports {DDR4B_DQ[65]}] -set_property PACKAGE_PIN E22 [get_ports {DDR4B_DQ[66]}] -set_property PACKAGE_PIN G21 [get_ports {DDR4B_DQ[67]}] -set_property PACKAGE_PIN D22 [get_ports {DDR4B_DQ[68]}] -set_property PACKAGE_PIN H21 [get_ports {DDR4B_DQ[69]}] -set_property PACKAGE_PIN E20 [get_ports {DDR4B_DQ[70]}] -set_property PACKAGE_PIN H22 [get_ports {DDR4B_DQ[71]}] +set_property PACKAGE_PIN P12 [get_ports {DDR4B_DQ[0]}] +set_property PACKAGE_PIN M14 [get_ports {DDR4B_DQ[1]}] +set_property PACKAGE_PIN P13 [get_ports {DDR4B_DQ[2]}] +set_property PACKAGE_PIN N12 [get_ports {DDR4B_DQ[3]}] +set_property PACKAGE_PIN N15 [get_ports {DDR4B_DQ[4]}] +set_property PACKAGE_PIN M12 [get_ports {DDR4B_DQ[5]}] +set_property PACKAGE_PIN P15 [get_ports {DDR4B_DQ[6]}] +set_property PACKAGE_PIN M13 [get_ports {DDR4B_DQ[7]}] +set_property PACKAGE_PIN G17 [get_ports {DDR4B_DQ[8]}] +set_property PACKAGE_PIN E16 [get_ports {DDR4B_DQ[9]}] +set_property PACKAGE_PIN G16 [get_ports {DDR4B_DQ[10]}] +set_property PACKAGE_PIN F18 [get_ports {DDR4B_DQ[11]}] +set_property PACKAGE_PIN H17 [get_ports {DDR4B_DQ[12]}] +set_property PACKAGE_PIN E17 [get_ports {DDR4B_DQ[13]}] +set_property PACKAGE_PIN F16 [get_ports {DDR4B_DQ[14]}] +set_property PACKAGE_PIN E18 [get_ports {DDR4B_DQ[15]}] +set_property PACKAGE_PIN K16 [get_ports {DDR4B_DQ[16]}] +set_property PACKAGE_PIN H14 [get_ports {DDR4B_DQ[17]}] +set_property PACKAGE_PIN K15 [get_ports {DDR4B_DQ[18]}] +set_property PACKAGE_PIN J14 [get_ports {DDR4B_DQ[19]}] +set_property PACKAGE_PIN L16 [get_ports {DDR4B_DQ[20]}] +set_property PACKAGE_PIN H15 [get_ports {DDR4B_DQ[21]}] +set_property PACKAGE_PIN J15 [get_ports {DDR4B_DQ[22]}] +set_property PACKAGE_PIN H16 [get_ports {DDR4B_DQ[23]}] +set_property PACKAGE_PIN D17 [get_ports {DDR4B_DQ[24]}] +set_property PACKAGE_PIN A16 [get_ports {DDR4B_DQ[25]}] +set_property PACKAGE_PIN D18 [get_ports {DDR4B_DQ[26]}] +set_property PACKAGE_PIN A15 [get_ports {DDR4B_DQ[27]}] +set_property PACKAGE_PIN D15 [get_ports {DDR4B_DQ[28]}] +set_property PACKAGE_PIN C17 [get_ports {DDR4B_DQ[29]}] +set_property PACKAGE_PIN C15 [get_ports {DDR4B_DQ[30]}] +set_property PACKAGE_PIN B17 [get_ports {DDR4B_DQ[31]}] +set_property PACKAGE_PIN B19 [get_ports {DDR4B_DQ[32]}] +set_property PACKAGE_PIN C21 [get_ports {DDR4B_DQ[33]}] +set_property PACKAGE_PIN A19 [get_ports {DDR4B_DQ[34]}] +set_property PACKAGE_PIN A21 [get_ports {DDR4B_DQ[35]}] +set_property PACKAGE_PIN D19 [get_ports {DDR4B_DQ[36]}] +set_property PACKAGE_PIN B21 [get_ports {DDR4B_DQ[37]}] +set_property PACKAGE_PIN A20 [get_ports {DDR4B_DQ[38]}] +set_property PACKAGE_PIN D20 [get_ports {DDR4B_DQ[39]}] +set_property PACKAGE_PIN H19 [get_ports {DDR4B_DQ[40]}] +set_property PACKAGE_PIN K21 [get_ports {DDR4B_DQ[41]}] +set_property PACKAGE_PIN J19 [get_ports {DDR4B_DQ[42]}] +set_property PACKAGE_PIN K20 [get_ports {DDR4B_DQ[43]}] +set_property PACKAGE_PIN K18 [get_ports {DDR4B_DQ[44]}] +set_property PACKAGE_PIN H20 [get_ports {DDR4B_DQ[45]}] +set_property PACKAGE_PIN L18 [get_ports {DDR4B_DQ[46]}] +set_property PACKAGE_PIN J20 [get_ports {DDR4B_DQ[47]}] +set_property PACKAGE_PIN A23 [get_ports {DDR4B_DQ[48]}] +set_property PACKAGE_PIN C26 [get_ports {DDR4B_DQ[49]}] +set_property PACKAGE_PIN C24 [get_ports {DDR4B_DQ[50]}] +set_property PACKAGE_PIN A26 [get_ports {DDR4B_DQ[51]}] +set_property PACKAGE_PIN A24 [get_ports {DDR4B_DQ[52]}] +set_property PACKAGE_PIN B26 [get_ports {DDR4B_DQ[53]}] +set_property PACKAGE_PIN A25 [get_ports {DDR4B_DQ[54]}] +set_property PACKAGE_PIN C25 [get_ports {DDR4B_DQ[55]}] +set_property PACKAGE_PIN N19 [get_ports {DDR4B_DQ[56]}] +set_property PACKAGE_PIN N20 [get_ports {DDR4B_DQ[57]}] +set_property PACKAGE_PIN P22 [get_ports {DDR4B_DQ[58]}] +set_property PACKAGE_PIN N21 [get_ports {DDR4B_DQ[59]}] +set_property PACKAGE_PIN P19 [get_ports {DDR4B_DQ[60]}] +set_property PACKAGE_PIN N22 [get_ports {DDR4B_DQ[61]}] +set_property PACKAGE_PIN P18 [get_ports {DDR4B_DQ[62]}] +set_property PACKAGE_PIN P20 [get_ports {DDR4B_DQ[63]}] +set_property PACKAGE_PIN E21 [get_ports {DDR4B_DQ[64]}] +set_property PACKAGE_PIN G22 [get_ports {DDR4B_DQ[65]}] +set_property PACKAGE_PIN E22 [get_ports {DDR4B_DQ[66]}] +set_property PACKAGE_PIN G21 [get_ports {DDR4B_DQ[67]}] +set_property PACKAGE_PIN D22 [get_ports {DDR4B_DQ[68]}] +set_property PACKAGE_PIN H21 [get_ports {DDR4B_DQ[69]}] +set_property PACKAGE_PIN E20 [get_ports {DDR4B_DQ[70]}] +set_property PACKAGE_PIN H22 [get_ports {DDR4B_DQ[71]}] set_property IOSTANDARD POD12_DCI [get_ports DDR4B_DQ[*]] set_property PACKAGE_PIN N14 [get_ports {DDR4B_LDQS_N[0]}] @@ -324,23 +324,23 @@ set_property PACKAGE_PIN K22 [get_ports {DDR4B_UDQS_P[2]}] set_property PACKAGE_PIN M21 [get_ports {DDR4B_UDQS_P[3]}] set_property IOSTANDARD DIFF_POD12_DCI [get_ports DDR4B_UDQS_P[*]] -set_property PACKAGE_PIN D24 [get_ports {DDR4B_ODT}] +set_property PACKAGE_PIN D24 [get_ports {DDR4B_ODT}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4B_ODT*] -set_property PACKAGE_PIN F24 [get_ports {DDR4B_BG[0]}] -set_property PACKAGE_PIN E26 [get_ports {DDR4B_BG[1]}] +set_property PACKAGE_PIN F24 [get_ports {DDR4B_BG[0]}] +set_property PACKAGE_PIN E26 [get_ports {DDR4B_BG[1]}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4B_BG[*]] -set_property IOSTANDARD LVCMOS12 [get_ports DDR4B_BG[1]] +set_property IOSTANDARD LVCMOS12 [get_ports DDR4B_BG[1]] -set_property PACKAGE_PIN D14 [get_ports {DDR4B_RESET_N}] +set_property PACKAGE_PIN D14 [get_ports {DDR4B_RESET_N}] set_property IOSTANDARD LVCMOS12 [get_ports DDR4B_RESET_N] set_property DRIVE 8 [get_ports DDR4B_RESET_N] set_property PACKAGE_PIN E23 [get_ports {DDR4B_ACT_N}] set_property IOSTANDARD SSTL12_DCI [get_ports DDR4B_ACT_N] -set_property PACKAGE_PIN D27 [get_ports {DDR4B_CK_N}] +set_property PACKAGE_PIN D27 [get_ports {DDR4B_CK_N}] set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4B_CK_N[*]] -set_property PACKAGE_PIN E27 [get_ports {DDR4B_CK_P}] -set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4B_CK_P[*]] \ No newline at end of file +set_property PACKAGE_PIN E27 [get_ports {DDR4B_CK_P}] +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4B_CK_P[*]] diff --git a/cards/silicom/fb2cghh/constr/pcie.xdc b/cards/silicom/fb2cghh/constr/pcie.xdc index cac1c4060..79337f63b 100644 --- a/cards/silicom/fb2cghh/constr/pcie.xdc +++ b/cards/silicom/fb2cghh/constr/pcie.xdc @@ -10,7 +10,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {PCIE_SYSRST_N}] set_property PACKAGE_PIN AL16 [get_ports {PCIE_RST1V2_N}] set_property IOSTANDARD LVCMOS12 [get_ports {PCIE_RST1V2_N}] -set_property PACKAGE_PIN AN10 [get_ports {PCIE_SYSCLK_P}] -set_property PACKAGE_PIN AN9 [get_ports {PCIE_SYSCLK_N}] +set_property PACKAGE_PIN AN10 [get_ports {PCIE_SYSCLK_P}] +set_property PACKAGE_PIN AN9 [get_ports {PCIE_SYSCLK_N}] create_clock -period 10.000 -name pcie_clk_p -waveform {0.000 5.000} [get_ports PCIE_SYSCLK_P] diff --git a/cards/silicom/fb2cghh/constr/qsfp.xdc b/cards/silicom/fb2cghh/constr/qsfp.xdc index b37e12a8f..e1acdf81a 100644 --- a/cards/silicom/fb2cghh/constr/qsfp.xdc +++ b/cards/silicom/fb2cghh/constr/qsfp.xdc @@ -11,29 +11,29 @@ set_property PACKAGE_PIN A10 [get_ports {QSFP0_INT_N}] set_property PACKAGE_PIN D10 [get_ports {QSFP1_INT_N}] set_property IOSTANDARD LVCMOS33 [get_ports {QSFP?_INT_N}] - + set_property PACKAGE_PIN A9 [get_ports {QSFP0_LPMODE}] set_property PACKAGE_PIN D9 [get_ports {QSFP1_LPMODE}] set_property IOSTANDARD LVCMOS33 [get_ports {QSFP?_LPMODE}] set_property SLEW SLOW [get_ports {QSFP?_LPMODE}] set_property DRIVE 4 [get_ports {QSFP?_LPMODE}] - + set_property PACKAGE_PIN B9 [get_ports {QSFP0_MODPRS_N}] set_property PACKAGE_PIN E10 [get_ports {QSFP1_MODPRS_N}] set_property IOSTANDARD LVCMOS33 [get_ports {QSFP?_MODPRS_N}] - + set_property PACKAGE_PIN A8 [get_ports {QSFP0_RESET_N}] set_property PACKAGE_PIN C10 [get_ports {QSFP1_RESET_N}] set_property IOSTANDARD LVCMOS33 [get_ports {QSFP?_RESET_N}] set_property DRIVE 4 [get_ports {QSFP?_RESET_N}] set_property SLEW SLOW [get_ports {QSFP?_RESET_N}] - + set_property PACKAGE_PIN B8 [get_ports {QSFP0_SCL}] set_property PACKAGE_PIN C9 [get_ports {QSFP1_SCL}] set_property IOSTANDARD LVCMOS33 [get_ports {QSFP?_SCL}] set_property DRIVE 4 [get_ports {QSFP?_SCL}] set_property SLEW SLOW [get_ports {QSFP?_SCL}] - + set_property PACKAGE_PIN B7 [get_ports {QSFP0_SDA}] set_property PACKAGE_PIN D8 [get_ports {QSFP1_SDA}] set_property IOSTANDARD LVCMOS33 [get_ports {QSFP?_SDA}] @@ -48,10 +48,10 @@ set_property package_pin W33 [get_ports {QSFP0_REFCLK_N}] set_property package_pin W32 [get_ports {QSFP0_REFCLK_P}] set_property package_pin P31 [get_ports {QSFP1_REFCLK_N}] set_property package_pin P30 [get_ports {QSFP1_REFCLK_P}] - + create_clock -period 6.206 [get_ports QSFP0_REFCLK_P] create_clock -period 6.206 [get_ports QSFP1_REFCLK_P] - + set_property PACKAGE_PIN Y40 [get_ports {QSFP0_RX_N[0]}] set_property PACKAGE_PIN Y39 [get_ports {QSFP0_RX_P[0]}] set_property PACKAGE_PIN Y35 [get_ports {QSFP0_TX_N[0]}] @@ -71,7 +71,7 @@ set_property PACKAGE_PIN U42 [get_ports {QSFP0_RX_N[3]}] set_property PACKAGE_PIN U41 [get_ports {QSFP0_RX_P[3]}] set_property PACKAGE_PIN U37 [get_ports {QSFP0_TX_N[3]}] set_property PACKAGE_PIN U36 [get_ports {QSFP0_TX_P[3]}] - + set_property PACKAGE_PIN M40 [get_ports {QSFP1_RX_N[0]}] set_property PACKAGE_PIN M39 [get_ports {QSFP1_RX_P[0]}] set_property PACKAGE_PIN M35 [get_ports {QSFP1_TX_N[0]}] diff --git a/cards/silicom/fb2cghh/src/Modules.tcl b/cards/silicom/fb2cghh/src/Modules.tcl index 61bbcb4f1..0458d7d2a 100644 --- a/cards/silicom/fb2cghh/src/Modules.tcl +++ b/cards/silicom/fb2cghh/src/Modules.tcl @@ -13,7 +13,7 @@ set LED_SERIAL_CTRL_BASE "$ENTITY_BASE/comp/led_ctrl" set BMC_BASE "$ENTITY_BASE/comp/bmc_driver" set AXI_QUAD_FLASH_CONTROLLER_BASE "$ENTITY_BASE/comp/axi_quad_flash_controller" set BOOT_CTRL_BASE "$OFM_PATH/core/comp/misc/boot_ctrl" -set AXI2AVMM_BRIDGE_BASE "$OFM_PATH/comp/mem_tools/convertors/axi2avmm_ddr_bridge" +set AXI2AVMM_BRIDGE_BASE "$OFM_PATH/comp/mem_tools/convertors/axi2avmm_ddr_bridge" set FPGA_COMMON_BASE "$ARCHGRP_ARR(CORE_BASE)/top" # Components diff --git a/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/Modules.tcl b/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/Modules.tcl index 5de48d847..fc79b759c 100644 --- a/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/Modules.tcl +++ b/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/Modules.tcl @@ -11,4 +11,4 @@ set AXI4_LITE_MI_BRIDGE_BASE "$ENTITY_BASE/comp/axi4_lite_mi_bridge/" lappend COMPONENTS [list "AXI4_LITE_MI_BRIDGE" $AXI4_LITE_MI_BRIDGE_BASE "FULL"] # Files -lappend MOD "$ENTITY_BASE/axi_quad_flash_controller.vhd" \ No newline at end of file +lappend MOD "$ENTITY_BASE/axi_quad_flash_controller.vhd" diff --git a/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/axi_quad_flash_controller.vhd b/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/axi_quad_flash_controller.vhd index d373e44a6..aeda1f9e9 100644 --- a/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/axi_quad_flash_controller.vhd +++ b/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/axi_quad_flash_controller.vhd @@ -18,7 +18,7 @@ entity AXI_QUAD_FLASH_CONTROLLER is G_AXI_ADDR_WIDTH : integer := 7; G_MI_ADDR_WIDTH : integer := 8; G_AXI_DATA_WIDTH : integer := 32 - + ); port ( @@ -27,7 +27,7 @@ entity AXI_QUAD_FLASH_CONTROLLER is SPI_CLK : in std_logic; RST : in std_logic; - -- MI32 protocol + -- MI32 protocol AXI_MI_ADDR : in std_logic_vector(G_MI_ADDR_WIDTH - 1 downto 0); AXI_MI_DWR : in std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0); AXI_MI_WR : in std_logic; @@ -62,9 +62,9 @@ architecture FULL of AXI_QUAD_FLASH_CONTROLLER is ext_spi_clk : in std_logic; -- AXI clock is expected to be faster than ext_spi_clk. s_axi_aclk : in std_logic; - -- Negative reset + -- Negative reset s_axi_aresetn : in std_logic; - -- AXI_LITE interface + -- AXI_LITE interface s_axi_awaddr : in std_logic_vector(6 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; @@ -82,7 +82,7 @@ architecture FULL of AXI_QUAD_FLASH_CONTROLLER is s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; - + -- STARTUP_IO_S cfgclk : out std_logic; cfgmclk : out std_logic; @@ -97,8 +97,8 @@ architecture FULL of AXI_QUAD_FLASH_CONTROLLER is ); end component; - -- Signals - -- Write Address Channel + -- Signals + -- Write Address Channel signal awaddr_s : std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0); signal awvalid_s : std_logic; signal awready_s : std_logic; @@ -107,7 +107,7 @@ architecture FULL of AXI_QUAD_FLASH_CONTROLLER is signal wdata_s : std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0); signal wstrb_s : std_logic_vector((G_AXI_DATA_WIDTH/8)-1 downto 0); signal wvalid_s : std_logic; - signal wready_s : std_logic; + signal wready_s : std_logic; --Write Response Channel signal bresp_s : std_logic_vector(1 downto 0); @@ -115,9 +115,9 @@ architecture FULL of AXI_QUAD_FLASH_CONTROLLER is signal bready_s : std_logic; -- Read Address Channel - signal araddr_s : std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0); - signal arvalid_s : std_logic; - signal arready_s : std_logic; + signal araddr_s : std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0); + signal arvalid_s : std_logic; + signal arready_s : std_logic; --Read Data Channel signal rdata_s : std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0); @@ -130,7 +130,7 @@ begin axi_bridge_i : entity work.AXI4_LITE_MI_BRIDGE generic map( G_AXI_ADDR_WIDTH => G_AXI_ADDR_WIDTH, - G_MI_ADDR_WIDTH => G_MI_ADDR_WIDTH, + G_MI_ADDR_WIDTH => G_MI_ADDR_WIDTH, G_AXI_DATA_WIDTH => G_AXI_DATA_WIDTH ) port map ( diff --git a/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/comp/axi4_lite_mi_bridge/axi4_lite_mi_bridge.vhd b/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/comp/axi4_lite_mi_bridge/axi4_lite_mi_bridge.vhd index a17c9452f..4e9cd9292 100644 --- a/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/comp/axi4_lite_mi_bridge/axi4_lite_mi_bridge.vhd +++ b/cards/silicom/fb2cghh/src/comp/axi_quad_flash_controller/comp/axi4_lite_mi_bridge/axi4_lite_mi_bridge.vhd @@ -21,7 +21,7 @@ entity AXI4_LITE_MI_BRIDGE is G_MI_ADDR_WIDTH : integer := 8; -- Data width of AXI G_AXI_DATA_WIDTH : integer := 32 - + ); port( CLK : in std_logic; @@ -29,10 +29,10 @@ entity AXI4_LITE_MI_BRIDGE is -- Write Address Channel ports AWADDR : out std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0); - AWVALID : out std_logic; + AWVALID : out std_logic; AWREADY : in std_logic; - -- Write Data Channel ports + -- Write Data Channel ports WDATA : out std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0); WSTRB : out std_logic_vector((G_AXI_DATA_WIDTH/8)-1 downto 0); WVALID : out std_logic; @@ -44,17 +44,17 @@ entity AXI4_LITE_MI_BRIDGE is BREADY : out std_logic; -- Read Address Channel ports - ARADDR : out std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0); - ARVALID : out std_logic; - ARREADY : in std_logic; + ARADDR : out std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0); + ARVALID : out std_logic; + ARREADY : in std_logic; - -- Read Data Channel ports + -- Read Data Channel ports RDATA : in std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0); RRESP : in std_logic_vector(1 downto 0); RVALID : in std_logic; RREADY : out std_logic; - -- MI32 protocol signals + -- MI32 protocol signals AXI_MI_ADDR : in std_logic_vector(G_MI_ADDR_WIDTH - 1 downto 0); AXI_MI_DWR : in std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0); AXI_MI_WR : in std_logic; @@ -69,10 +69,10 @@ end entity; architecture FULL of AXI4_LITE_MI_BRIDGE is type t_fsm_axi_bridge is ( - st_idle, -- waiting for MI request + st_idle, -- waiting for MI request st_wr_response, -- response to WR flag st_rd_response -- response to RD flag - ); + ); -- Control logic (FSM) signal state, next_state: t_fsm_axi_bridge := st_idle; @@ -95,13 +95,13 @@ begin AWADDR <= AXI_MI_ADDR(6 downto 0); ARADDR <= AXI_MI_ADDR(6 downto 0); - + AWVALID <= AXI_MI_WR when awvalid_reg_q = '1' else '0'; WVALID <= AXI_MI_WR when wvalid_reg_q = '1' else '0'; ARVALID <= AXI_MI_RD when arvalid_reg_q = '1' else '0'; process (clk) - begin + begin if rising_edge(clk) then if RST = '1' then state <= st_idle; @@ -117,8 +117,8 @@ begin bvalid_reg_q <= bvalid_reg_d; end if; end if; - end process; - + end process; + --delay register bvalid_reg_d <= BVALID; @@ -133,14 +133,14 @@ begin AXI_MI_ARDY <= '0'; AXI_MI_DRDY <= '0'; RREADY <= '0'; - + case (state) is when st_idle => awvalid_reg_d <= '0'; wvalid_reg_d <= '0'; - + --Request for write - if AXI_MI_WR = '1' then + if AXI_MI_WR = '1' then next_state <= st_wr_response; awvalid_reg_d <= '1'; wvalid_reg_d <= '1'; @@ -153,7 +153,7 @@ begin end if; when st_wr_response => - -- AXI protocol + -- AXI protocol BREADY <= '1'; if AWREADY = '1' then awvalid_reg_d <= '0'; @@ -163,30 +163,30 @@ begin wvalid_reg_d <= '0'; end if; - -- Write process is done, ready for new data + -- Write process is done, ready for new data if BVALID = '1' and BRESP /= "11" then next_state <= st_idle; AXI_MI_ARDY <= '1'; end if; - + when st_rd_response => -- AXI protocol RREADY <= '1'; - if ARREADY = '1' then + if ARREADY = '1' then arvalid_reg_d <= '0'; end if; - + -- Read process is done, back to st_idle if RVALID = '1' and RRESP /= "11" then next_state <= st_idle; AXI_MI_DRDY <= '1'; AXI_MI_ARDY <= '1'; end if; - + when others => next_state <= st_idle; end case; end process; - -end architecture; \ No newline at end of file + +end architecture; diff --git a/cards/silicom/fb2cghh/src/comp/bmc_driver/bmc_driver.vhd b/cards/silicom/fb2cghh/src/comp/bmc_driver/bmc_driver.vhd index 5399f32e5..ee81b7908 100644 --- a/cards/silicom/fb2cghh/src/comp/bmc_driver/bmc_driver.vhd +++ b/cards/silicom/fb2cghh/src/comp/bmc_driver/bmc_driver.vhd @@ -1,4 +1,4 @@ --- bmc_driver.vhd: Board Management Controller driver +-- bmc_driver.vhd: Board Management Controller driver -- Copyright (C) 2022 CESNET z. s. p. o. -- Author(s): David Beneš -- @@ -14,7 +14,7 @@ use work.type_pack.all; -- This component is bridge unit between MI32 protocol and SPI protocol -- for communication with BMC device. -- BMC device is capable of rebooting FPGA and changing boot flash. --- This component supports 200 MHz clock. Default SPI frequency is +-- This component supports 200 MHz clock. Default SPI frequency is -- 806 kHz and can be changed by divide ratio. SPI_CLK = (CLK/(4*spi_freq_div)) entity BMC_DRIVER is generic( @@ -27,14 +27,14 @@ entity BMC_DRIVER is CLK : in std_logic; RST : in std_logic; - -- SPI interface for communication with BMC device + -- SPI interface for communication with BMC device SPI_CLK : out std_logic; SPI_NSS : out std_logic; SPI_MOSI : out std_logic; SPI_MISO : in std_logic; SPI_INT : in std_logic; - -- MI32 protocol signals + -- MI32 protocol signals BMC_MI_ADDR : in std_logic_vector(G_MI_ADDR_WIDTH - 1 downto 0); BMC_MI_DWR : in std_logic_vector(G_MI_DATA_WIDTH - 1 downto 0); BMC_MI_WR : in std_logic; @@ -48,7 +48,7 @@ end BMC_DRIVER; architecture FULL of BMC_DRIVER is type t_fsm_led_ctrl is ( - st_idle, -- waiting for commands + st_idle, -- waiting for commands st_boot_request, -- reboot st_write, -- writing 1 byte to SPI slave device st_write_delay, -- delay between bytes @@ -56,7 +56,7 @@ architecture FULL of BMC_DRIVER is st_read, -- reading 1 byte data from SPI st_read_delay, -- delay between bytes st_eos -- end of sequence - ); + ); -- Control logic (FSM) signal state, next_state: t_fsm_led_ctrl := st_idle; @@ -83,7 +83,7 @@ architecture FULL of BMC_DRIVER is signal miso_word_cnt_d : unsigned(2 downto 0) :=(others => '0'); signal miso_word_cnt_q : unsigned(2 downto 0) :=(others => '0'); - -- Pulse generator + -- Pulse generator signal pulse_cnt : unsigned(17 downto 0):=(others => '0'); signal pulse_event : std_logic; signal pulse_gen_en : std_logic; @@ -94,7 +94,7 @@ architecture FULL of BMC_DRIVER is signal delay_cnt_d : unsigned(7 downto 0); signal delay_cnt_q : unsigned(7 downto 0); - -- Delay between write and read in ms + -- Delay between write and read in ms signal wait_duration_d : std_logic_vector(15 downto 0):= (others => '0'); signal wait_duration_q : std_logic_vector(15 downto 0):= (others => '0'); signal wait_cnt_d : unsigned(15 downto 0):= (others => '0'); @@ -102,7 +102,7 @@ architecture FULL of BMC_DRIVER is signal timeout_event_d : std_logic; signal timeout_event_q : std_logic; - -- Interrupt + -- Interrupt signal interrupt_event : std_logic; signal interrupt_re0 : std_logic; signal interrupt_re1 : std_logic; @@ -114,7 +114,7 @@ architecture FULL of BMC_DRIVER is signal status_ready_d : std_logic; signal status_ready_q : std_logic; - -- SPI buffer + -- SPI buffer signal spi_clk_s : std_logic:= '0'; signal spi_clk_d : std_logic:= '0'; signal spi_clk_q : std_logic:= '0'; @@ -144,24 +144,24 @@ architecture FULL of BMC_DRIVER is begin ----------------------------------------------------------------------------- -- INTERRUPT DETECTION - ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- int_p: process(CLK) begin - if rising_edge(CLK) then + if rising_edge(CLK) then -- Detection of interrupt rising_edge(re) interrupt_re0 <= SPI_INT; interrupt_re1 <= interrupt_re0; interrupt_event <= interrupt_re0 and (not interrupt_re1); - -- Saving 're' information - if interrupt_event = '1' then + -- Saving 're' information + if interrupt_event = '1' then interrupt_detected <= '1'; end if; - if RST = '1' then + if RST = '1' then interrupt_detected <= '0'; interrupt_event <= '0'; - elsif state = st_idle then + elsif state = st_idle then interrupt_detected <= '0'; end if; end if; @@ -172,7 +172,7 @@ begin ----------------------------------------------------------------------------- mem_p: process (CLK) - begin + begin if rising_edge(CLK) then if RST = '1' then state <= st_idle; @@ -241,13 +241,13 @@ begin bmc_mi_drd_d(16) <= status_done_q; -- Status done, occurs when the transaction is done or clock is set up bmc_mi_drd_d(17) <= '0'; bmc_mi_drd_d(18) <= timeout_event_q; -- Timeout indication due to missing interrupt from BMC device (device is not ready to transmit data) - bmc_mi_drd_d(19) <= status_ready_q; -- Ready for another transaction (st_idle) + bmc_mi_drd_d(19) <= status_ready_q; -- Ready for another transaction (st_idle) bmc_mi_drd_d(23 downto 20) <= (others => '0'); bmc_mi_drd_d(31 downto 24) <= x"02"; -- Controller version when others => bmc_mi_drd_d <= (others => '0'); end case; - bmc_mi_drdy_d <= bmc_mi_rd_s; + bmc_mi_drdy_d <= bmc_mi_rd_s; end process; fsm_p: process(all) @@ -273,13 +273,13 @@ begin spi_clk_d <= spi_clk_s; spi_freq_div_d <= spi_freq_div_q; boot_cmd_d <= boot_cmd_q; - + case(state) is when st_idle => spi_nss_d <= '1'; spi_mosi_d <= '1'; status_ready_d <= '1'; - status_done_d <= '0'; + status_done_d <= '0'; mosi_data_cnt_d <= (others => '0'); mosi_word_cnt_d <= (others => '0'); @@ -293,7 +293,7 @@ begin mosi_data_d(31 downto 0) <= BMC_MI_DWR; when "01" => -- 31 downto 28: CMD configuration - -- 27 downto 16: SUB_CMD configuration + -- 27 downto 16: SUB_CMD configuration mosi_data_d(47 downto 32) <= BMC_MI_DWR(31 downto 16); -- Reboot @@ -328,15 +328,15 @@ begin end if; when others => null; - end case; + end case; end if; - if boot_cmd_q = '1' then + if boot_cmd_q = '1' then next_state <= st_boot_request; end if; when st_boot_request => - if boot_timeout(25) = '1' then + if boot_timeout(25) = '1' then status_done_d <= '0'; timeout_event_d <= '0'; next_state <= st_write; @@ -346,10 +346,10 @@ begin spi_clk_en <= '1'; delay_cnt_d <= (others => '0'); - if spi_clk_event = '1' then + if spi_clk_event = '1' then spi_nss_d <= '0'; - if spi_clk_s = '0' then + if spi_clk_s = '0' then mosi_data_d <= mosi_data_q(mosi_data_q'high - 1 downto 0) & '0'; spi_mosi_d <= mosi_data_q(mosi_data_q'high); mosi_data_cnt_d <= mosi_data_cnt_q + 1; @@ -364,7 +364,7 @@ begin when st_write_delay => spi_clk_en <= '1'; mosi_data_cnt_d <= (others => '0'); - + if spi_clk_event = '1' then spi_nss_d <= '1'; delay_cnt_d <= delay_cnt_q + 1; @@ -373,7 +373,7 @@ begin next_state <= st_write; mosi_word_cnt_d <= mosi_word_cnt_q + 1; - if mosi_word_cnt_q = 6 - 1 then + if mosi_word_cnt_q = 6 - 1 then next_state <= st_wait; end if; end if; @@ -382,17 +382,17 @@ begin when st_wait => pulse_gen_en <= '1'; - if pulse_event = '1' then + if pulse_event = '1' then wait_cnt_d <= wait_cnt_q + 1; end if; - if interrupt_detected = '1' then + if interrupt_detected = '1' then next_state <= st_read; elsif wait_cnt_q = to_integer(unsigned(wait_duration_q)) then next_state <= st_read; timeout_event_d <= '1'; - end if; - + end if; + when st_read => spi_clk_en <= '1'; delay_cnt_d <= (others => '0'); @@ -400,7 +400,7 @@ begin if spi_clk_event = '1' then spi_nss_d <= '0'; - if spi_clk_s = '1' then + if spi_clk_s = '1' then miso_data_d <= miso_data_q(miso_data_q'high - 1 downto 0) & spi_miso_s; miso_data_cnt_d <= miso_data_cnt_q + 1; end if; @@ -417,30 +417,30 @@ begin when st_read_delay => spi_clk_en <= '1'; miso_data_cnt_d <= (others => '0'); - + if spi_clk_event = '1' then spi_nss_d <= '1'; delay_cnt_d <= delay_cnt_q + 1; - + if delay_cnt_q = to_integer(unsigned(delay_duration_q(7 downto 1))) then next_state <= st_read; miso_word_cnt_d <= miso_word_cnt_q + 1; - if miso_word_cnt_q = 2 - 1 then + if miso_word_cnt_q = 2 - 1 then next_state <= st_eos; end if; end if; - end if; + end if; when st_eos => - status_done_d <= '1'; + status_done_d <= '1'; next_state <= st_idle; - when others => - status_done_d <= '1'; + when others => + status_done_d <= '1'; next_state <= st_idle; - end case; + end case; end process; ----------------------------------------------------------------------------- @@ -463,13 +463,13 @@ begin else spi_clk_cnt <= spi_clk_cnt + 1; end if; - else + else spi_clk_cnt <= (others => '0'); spi_clk_event <= '0'; spi_clk_s <= '1'; end if; - if state = st_write_delay or state = st_read_delay then + if state = st_write_delay or state = st_read_delay then spi_clk_s <= '1'; end if; end if; @@ -478,7 +478,7 @@ begin ----------------------------------------------------------------------------- -- 1 ms PULSE GENERATOR (200 MHz CLK) ----------------------------------------------------------------------------- - + ms_gen_i: process(CLK) begin if rising_edge(CLK) then @@ -486,15 +486,15 @@ begin if RST = '1' then pulse_event <= '0'; pulse_cnt <= (others => '0'); - elsif pulse_gen_en = '1' then - if pulse_cnt = 200000 - 1 then + elsif pulse_gen_en = '1' then + if pulse_cnt = 200000 - 1 then pulse_event <= '1'; pulse_cnt <= (others => '0'); else pulse_cnt <= pulse_cnt + 1; end if; - else + else pulse_event <= '0'; pulse_cnt <= (others => '0'); end if; @@ -502,7 +502,7 @@ begin end process; ----------------------------------------------------------------------------- - -- SPI BUFFER + -- SPI BUFFER ----------------------------------------------------------------------------- spi_buf_p: process(CLK) @@ -516,7 +516,7 @@ begin end process; ----------------------------------------------------------------------------- - -- REBOOT + -- REBOOT ----------------------------------------------------------------------------- boot_timeout_p : process(CLK) @@ -530,4 +530,4 @@ begin end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/cards/silicom/fb2cghh/src/comp/bmc_driver/sim/testbench.vhd b/cards/silicom/fb2cghh/src/comp/bmc_driver/sim/testbench.vhd index 071f10eae..d09eeecc8 100644 --- a/cards/silicom/fb2cghh/src/comp/bmc_driver/sim/testbench.vhd +++ b/cards/silicom/fb2cghh/src/comp/bmc_driver/sim/testbench.vhd @@ -1,4 +1,4 @@ --- testbench.vhd: Simulation file +-- testbench.vhd: Simulation file -- Copyright (C) 2022 CESNET z. s. p. o. -- Author(s): David Beneš -- @@ -9,11 +9,11 @@ USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_textio.ALL; USE ieee.numeric_std.ALL; USE std.textio.ALL; - + ENTITY TESTBENCH IS END TESTBENCH; - -ARCHITECTURE FULL OF TESTBENCH IS + +ARCHITECTURE FULL OF TESTBENCH IS --Inputs signal clk200 : std_logic; @@ -32,24 +32,24 @@ ARCHITECTURE FULL OF TESTBENCH IS --Outputs signal spi_clk : std_logic; - signal spi_nss : std_logic; - signal spi_mosi : std_logic; + signal spi_nss : std_logic; + signal spi_mosi : std_logic; signal bmc_mi_ardy : std_logic; signal bmc_mi_drd : std_logic_vector(32 - 1 downto 0); - signal bmc_mi_drdy : std_logic; + signal bmc_mi_drdy : std_logic; + + - - -- Clock period definitions constant clk_period250 : time := 4 ns; constant clk_period200 : time := 5 ns; signal miso_data : std_logic_vector(15 downto 0):= x"F0F0"; - + BEGIN - + -- Instantiate the Unit Under Test (UUT) - + uut_i: entity work.BMC_DRIVER PORT MAP( CLK => clk250, @@ -68,7 +68,7 @@ BEGIN BMC_MI_DRD => bmc_mi_drd, BMC_MI_DRDY => bmc_mi_drdy ); - + -- Clock process definitions clk250_p :process begin @@ -86,7 +86,7 @@ BEGIN clk200 <= '1'; wait for clk_period200/2; end process; - + rd_p: process begin @@ -107,7 +107,7 @@ BEGIN -- Stimulus process stim_proc: process - begin + begin rst <= '1', '0' after clk_period250*5; spi_miso <= '1'; @@ -143,7 +143,7 @@ BEGIN bmc_mi_wr <= '0'; - wait for clk_period250*100; + wait for clk_period250*100; WAIT; end process; diff --git a/cards/silicom/fb2cghh/src/comp/led_ctrl/Modules.tcl b/cards/silicom/fb2cghh/src/comp/led_ctrl/Modules.tcl index 1559c9b27..9c4c2a613 100644 --- a/cards/silicom/fb2cghh/src/comp/led_ctrl/Modules.tcl +++ b/cards/silicom/fb2cghh/src/comp/led_ctrl/Modules.tcl @@ -12,4 +12,4 @@ lappend COMPONENTS [list "open_loop" $OPEN_LOOP_BASE "FULL"] # Files -lappend MOD "$ENTITY_BASE/led_serial_ctrl.vhd" \ No newline at end of file +lappend MOD "$ENTITY_BASE/led_serial_ctrl.vhd" diff --git a/cards/silicom/fb2cghh/src/comp/led_ctrl/led_serial_ctrl.vhd b/cards/silicom/fb2cghh/src/comp/led_ctrl/led_serial_ctrl.vhd index 70293847f..92c42b65c 100644 --- a/cards/silicom/fb2cghh/src/comp/led_ctrl/led_serial_ctrl.vhd +++ b/cards/silicom/fb2cghh/src/comp/led_ctrl/led_serial_ctrl.vhd @@ -45,8 +45,8 @@ architecture FULL of LED_SERIAL_CTRL is st_idle, -- idle state, waiting for LED to change st_red, -- sending serial data to LED_SDI (red LED) st_green, -- sending serial data to LED_SDI (green LED) - st_eos -- end of sequence - ); + st_eos -- end of sequence + ); -- Control logic (FSM) signal state, next_state: t_fsm_led_ctrl := st_idle; @@ -61,14 +61,14 @@ architecture FULL of LED_SERIAL_CTRL is signal red_led_q : std_logic_vector(LED_W-1 downto 0) := (others => '0'); signal green_led_q : std_logic_vector(LED_W-1 downto 0) := (others => '0'); - -- Counter registers + -- Counter registers signal led_cnt : unsigned(CNT_W - 1 downto 0) := (others => '0'); signal led_cnt_next : unsigned(CNT_W - 1 downto 0) := (others => '0'); -- Output registers - signal led_le_d : std_logic; + signal led_le_d : std_logic; signal led_le_q : std_logic; - signal led_sdi_d : std_logic; + signal led_sdi_d : std_logic; signal led_sdi_q : std_logic; signal sdi_out_d : std_logic; signal sdi_out_q : std_logic; @@ -78,9 +78,9 @@ architecture FULL of LED_SERIAL_CTRL is --Timer related signals signal cnt : unsigned(TIMER_W - 1 downto 0) := (others => '0'); signal led_update : std_logic; - signal led_en : std_logic; - - --Timeout + signal led_en : std_logic; + + --Timeout signal timeout_cnt : unsigned(15 downto 0) := CNT_TIMEOUT; signal timeout_event : std_logic; @@ -102,24 +102,24 @@ begin ACLK => '0', ARST => '0', ADATAIN => RED_LED(i), - + --OUTPUT BCLK => CLK, BRST => RST, BDATAOUT => red_led_sync(i) ); - + green_sync_i: entity work.ASYNC_OPEN_LOOP generic map( IN_REG => false, TWO_REG => true ) port map( - --INPUT + --INPUT ACLK => '0', ARST => '0', ADATAIN => GREEN_LED(i), - + --OUTPUT BCLK => CLK, BRST => RST, @@ -132,13 +132,13 @@ begin ----------------------------------------------------------------------------- mem_p: process (clk) - begin + begin if rising_edge(clk) then if RST = '1' then state <= st_idle; - led_cnt <= (others => '0'); - green_led_q <= (others => '0'); - red_led_q <= (others => '0'); + led_cnt <= (others => '0'); + green_led_q <= (others => '0'); + red_led_q <= (others => '0'); led_sdi_q <= '0'; sdi_out_q <= '0'; led_le_q <= '0'; @@ -163,8 +163,8 @@ begin le_out_d <= led_le_q; LED_SDI <= sdi_out_q; LED_LE <= le_out_q; - - fsm_p: process(state, led_update, red_led_sync, green_led_sync, red_led_d, green_led_d, + + fsm_p: process(state, led_update, red_led_sync, green_led_sync, red_led_d, green_led_d, led_cnt, red_led_q, green_led_q, led_le_q, led_sdi_q, timeout_event) begin next_state <= state; @@ -177,18 +177,18 @@ begin case(state) is when st_idle => - if led_update = '1' then + if led_update = '1' then red_led_d <= red_led_sync; green_led_d <= green_led_sync; if (red_led_sync /= red_led_q) or (green_led_sync /= green_led_q) or timeout_event = '1' then next_state <= st_red; - end if; + end if; end if; when st_red => led_sdi_d <= red_led_q( to_integer(led_cnt)); - led_en <= '1'; + led_en <= '1'; if led_update = '1' then next_state <= st_green; @@ -213,7 +213,7 @@ begin when st_eos => led_le_d <= '1'; - if led_update = '1' then + if led_update = '1' then next_state <= st_idle; end if; @@ -241,7 +241,7 @@ begin led_update <= '1'; elsif cnt = (FREQ_DIV/2) and led_en = '1' then LED_CLK <= '1'; - elsif cnt = 0 then + elsif cnt = 0 then LED_CLK <= '0'; end if; end if; @@ -260,15 +260,15 @@ begin elsif state = st_idle then timeout_cnt <= timeout_cnt - 1; - if timeout_cnt = 0 then + if timeout_cnt = 0 then timeout_event <= '1'; timeout_cnt <= CNT_TIMEOUT; end if; - else + else timeout_event <= '0'; timeout_cnt <= CNT_TIMEOUT; end if; end if; end process; - -end architecture; \ No newline at end of file + +end architecture; diff --git a/cards/silicom/fb2cghh/src/comp/led_ctrl/sim/testbench.vhd b/cards/silicom/fb2cghh/src/comp/led_ctrl/sim/testbench.vhd index 1f9d5ddcb..84ee16926 100644 --- a/cards/silicom/fb2cghh/src/comp/led_ctrl/sim/testbench.vhd +++ b/cards/silicom/fb2cghh/src/comp/led_ctrl/sim/testbench.vhd @@ -1,4 +1,4 @@ --- testbench.vhd: Simulation file +-- testbench.vhd: Simulation file -- Copyright (C) 2022 CESNET z. s. p. o. -- Author(s): David Beneš -- @@ -9,13 +9,13 @@ USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_textio.ALL; USE ieee.numeric_std.ALL; USE std.textio.ALL; - + ENTITY TESTBENCH IS END TESTBENCH; - -ARCHITECTURE FULL OF TESTBENCH IS - +ARCHITECTURE FULL OF TESTBENCH IS + + --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '0'; @@ -29,9 +29,9 @@ ARCHITECTURE FULL OF TESTBENCH IS -- Clock period definitions constant clk_period : time := 20 ns; - + BEGIN - + -- Instantiate the Unit Under Test (UUT) uut_i: entity work.LED_SERIAL_CTRL PORT MAP ( @@ -41,7 +41,7 @@ BEGIN GREEN_LED => green_LED, LED_SDI => LED_SDI, LED_CLK => LED_CLK, - LED_LE => LED_LE + LED_LE => LED_LE ); -- Clock process definitions @@ -52,11 +52,11 @@ BEGIN clk <= '1'; wait for clk_period/2; end process; - + -- Stimulus process stim_proc: process - begin + begin RST <= '1', '0' after CLK_PERIOD*5; wait for CLK_PERIOD*5; --RST <= '0'; diff --git a/cards/silicom/fb2cghh/src/fpga.vhd b/cards/silicom/fb2cghh/src/fpga.vhd index e53e96a41..d13aec14c 100644 --- a/cards/silicom/fb2cghh/src/fpga.vhd +++ b/cards/silicom/fb2cghh/src/fpga.vhd @@ -31,7 +31,7 @@ port ( PCIE_TX_P : out std_logic_vector(PCIE_LANES -1 downto 0); PCIE_TX_N : out std_logic_vector(PCIE_LANES -1 downto 0); - -- 50 MHz external clock + -- 50 MHz external clock REFCLK : in std_logic; -- Pulse per second @@ -146,7 +146,7 @@ architecture FULL of FPGA is constant DDR_PORTS : integer := MEM_PORTS; constant DDR_ADDR_WIDTH : integer := 29; constant DDR_BYTES : integer := 9; - --These values are IP core specific ... + --These values are IP core specific ... constant DDR_AXI_ADDR_WIDTH : integer := 32; constant DDR_AXI_DATA_WIDTH : integer := 512; -- 1/4 of Memory Device interface Speed in Hz @@ -155,8 +155,8 @@ architecture FULL of FPGA is constant AMM_DATA_WIDTH : integer := 512; constant AMM_BURST_COUNT_WIDTH : integer := 8; constant AMM_ADDR_WIDTH : integer := 26; - constant REFR_PERIOD_WIDTH : integer := 32; - + constant REFR_PERIOD_WIDTH : integer := 32; + signal sysclk_ibuf : std_logic; signal sysclk_bufg : std_logic; signal sysrst_cnt : unsigned(4 downto 0) := (others => '0'); @@ -164,7 +164,7 @@ architecture FULL of FPGA is signal eth_led_g : std_logic_vector(2*4-1 downto 0); signal eth_led_r : std_logic_vector(2*4-1 downto 0); - + signal eth_refclk_p : std_logic_vector(2-1 downto 0); signal eth_refclk_n : std_logic_vector(2-1 downto 0); signal eth_rx_p : std_logic_vector(2*ETH_LANES-1 downto 0); @@ -178,7 +178,7 @@ architecture FULL of FPGA is signal qsfp_sda : std_logic_vector(2-1 downto 0) := (others => 'Z'); signal qsfp_modprs_n : std_logic_vector(2-1 downto 0); signal qsfp_int_n : std_logic_vector(2-1 downto 0); - + signal misc_in : std_logic_vector(MISC_IN_WIDTH-1 downto 0) := (others => '0'); signal misc_out : std_logic_vector(MISC_OUT_WIDTH-1 downto 0); @@ -201,17 +201,17 @@ architecture FULL of FPGA is signal boot_reset : std_logic; signal boot_clk : std_logic; - -- AXI Flash Controller - signal axi_mi_addr_s : std_logic_vector(8 - 1 downto 0); - signal axi_mi_dwr_s : std_logic_vector(32 - 1 downto 0); - signal axi_mi_wr_s : std_logic; - signal axi_mi_rd_s : std_logic; - signal axi_mi_be_s : std_logic_vector((32/8)-1 downto 0); - signal axi_mi_ardy_s : std_logic; - signal axi_mi_drd_s : std_logic_vector(32 - 1 downto 0); + -- AXI Flash Controller + signal axi_mi_addr_s : std_logic_vector(8 - 1 downto 0); + signal axi_mi_dwr_s : std_logic_vector(32 - 1 downto 0); + signal axi_mi_wr_s : std_logic; + signal axi_mi_rd_s : std_logic; + signal axi_mi_be_s : std_logic_vector((32/8)-1 downto 0); + signal axi_mi_ardy_s : std_logic; + signal axi_mi_drd_s : std_logic_vector(32 - 1 downto 0); signal axi_mi_drdy_s : std_logic; - --BMC controller + --BMC controller signal bmc_mi_addr_s : std_logic_vector(8 - 1 downto 0); signal bmc_mi_dwr_s : std_logic_vector(32 - 1 downto 0); signal bmc_mi_wr_s : std_logic; @@ -260,7 +260,7 @@ architecture FULL of FPGA is signal ddr_s_axi_rresp : slv_array_t (DDR_PORTS-1 downto 0)(1 DOWNTO 0); signal ddr_s_axi_rid : slv_array_t (DDR_PORTS-1 downto 0)(3 DOWNTO 0); signal ddr_s_axi_rdata : slv_array_t (DDR_PORTS-1 downto 0)(DDR_AXI_DATA_WIDTH-1 DOWNTO 0); - + -- DDR4A interface signal ddr4a_rst : std_logic; signal ddr4a_app_hi_pri : std_logic; @@ -273,7 +273,7 @@ architecture FULL of FPGA is signal ddr4b_app_hi_pri : std_logic; signal ddr4b_dqs_p : std_logic_vector(DDR_BYTES-1 downto 0); signal ddr4b_dqs_n : std_logic_vector(DDR_BYTES-1 downto 0); - signal ddr4b_dm : std_logic_vector(DDR_BYTES-1 downto 0); + signal ddr4b_dm : std_logic_vector(DDR_BYTES-1 downto 0); -- MEM_TESTER signals signal mem_clk : std_logic_vector(DDR_PORTS -1 downto 0); @@ -316,7 +316,7 @@ architecture FULL of FPGA is signal ddr_dqs_p : std_logic_vector(DDR_PORTS*DDR_BYTES-1 downto 0); signal ddr_dqs_n : std_logic_vector(DDR_PORTS*DDR_BYTES-1 downto 0); signal ddr_dm : std_logic_vector(DDR_PORTS*DDR_BYTES-1 downto 0); - + -- DDR IP core with AXI4 interface component DDR4_AXI port ( @@ -400,7 +400,7 @@ architecture FULL of FPGA is c0_ddr4_s_axi_ctrl_rready : in std_logic; c0_ddr4_s_axi_ctrl_rdata : out std_logic_vector(31 downto 0); c0_ddr4_s_axi_ctrl_rresp : out std_logic_vector(1 downto 0) - + ); end component; @@ -420,7 +420,7 @@ begin ddr4a_dqs_n(i*2+1) <= DDR4A_UDQS_N(i); ddr4a_dm(i*2+1) <= DDR4A_UDM(i); end generate; - + -- FB2CGHH specific (DDR_BYTES=9) ddr4a_dqs_n(DDR_BYTES-1) <= DDR4A_LDQS_N((DDR_BYTES/2)); ddr4a_dqs_p(DDR_BYTES-1) <= DDR4A_LDQS_P((DDR_BYTES/2)); @@ -526,36 +526,36 @@ begin DDR4A_ACT_N <= '0'; -- Insert differential buffers - CK_BUF: OBUFDS + CK_BUF: OBUFDS port map ( - I => '1', - O => DDR4A_CK_P(0), + I => '1', + O => DDR4A_CK_P(0), OB => DDR4A_CK_N(0) ); ldqs_buf_g: for p in 0 to ((DDR_BYTES/2)+1)-1 generate - LDQS_BUF: IOBUFDS + LDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', - IO => DDR4A_LDQS_P(p), + O => open, + I => '0', + T => '0', + IO => DDR4A_LDQS_P(p), IOB => DDR4A_LDQS_N(p) ); end generate; udqs_buf_g: for p in 0 to (DDR_BYTES/2)-1 generate - UDQS_BUF: IOBUFDS + UDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', + O => open, + I => '0', + T => '0', IO => DDR4A_UDQS_P(p), IOB => DDR4A_UDQS_N(p) ); end generate; - end generate; + end generate; ddr4b_en_g : if DDR_PORTS >= 2 generate ddr4b_rst <= sysrst; @@ -570,7 +570,7 @@ begin ddr4b_dqs_n(i*2+1) <= DDR4B_UDQS_N(i); ddr4b_dm(i*2+1) <= DDR4B_UDM(i); end generate; - + -- FB2CGHH specific (DDR_BYTES=9) ddr4b_dqs_n(DDR_BYTES-1) <= DDR4B_LDQS_N((DDR_BYTES/2)); ddr4b_dqs_p(DDR_BYTES-1) <= DDR4B_LDQS_P((DDR_BYTES/2)); @@ -676,43 +676,43 @@ begin DDR4B_ACT_N <= '0'; -- Insert differential buffers - CK_BUF: OBUFDS + CK_BUF: OBUFDS port map ( - I => '1', - O => DDR4B_CK_P(0), + I => '1', + O => DDR4B_CK_P(0), OB => DDR4B_CK_N(0) ); ldqs_buf_g: for p in 0 to ((DDR_BYTES/2)+1)-1 generate - LDQS_BUF: IOBUFDS + LDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', - IO => DDR4B_LDQS_P(p), + O => open, + I => '0', + T => '0', + IO => DDR4B_LDQS_P(p), IOB => DDR4B_LDQS_N(p) ); end generate; udqs_buf_g: for p in 0 to (DDR_BYTES/2)-1 generate - UDQS_BUF: IOBUFDS + UDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', + O => open, + I => '0', + T => '0', IO => DDR4B_UDQS_P(p), IOB => DDR4B_UDQS_N(p) ); end generate; - end generate; + end generate; ddr4bridge_g : for i in DDR_PORTS -1 downto 0 generate ddr4bridge_i : entity work.AXI2AVMM_BRIDGE port map( MEM_CLK => ddr_ui_clk(i), MEM_RST => ddr_ui_clk_sync_rst(i), - + -- DDR4_AXI interface DDR_S_AXI_AWID => ddr_s_axi_awid(i), DDR_S_AXI_AWADDR => ddr_s_axi_awaddr(i), @@ -743,7 +743,7 @@ begin DDR_S_AXI_RRESP => ddr_s_axi_rresp(i), DDR_S_AXI_RID => ddr_s_axi_rid(i), DDR_S_AXI_RDATA => ddr_s_axi_rdata(i), - + -- EMIF interface AMM_READY => mem_avmm_ready(i), AMM_READ => mem_avmm_read(i), @@ -782,7 +782,7 @@ begin PPS_OUT <= PPS_IN; -- QSFP MAPPING ------------------------------------------------------------ - eth_refclk_p <= QSFP1_REFCLK_P & QSFP0_REFCLK_P; + eth_refclk_p <= QSFP1_REFCLK_P & QSFP0_REFCLK_P; eth_refclk_n <= QSFP1_REFCLK_N & QSFP0_REFCLK_N; eth_rx_p <= QSFP1_RX_P & QSFP0_RX_P; @@ -835,16 +835,16 @@ begin BOOT_IMAGE => open, BMC_MI_ADDR => bmc_mi_addr_s, - BMC_MI_DWR => bmc_mi_dwr_s, + BMC_MI_DWR => bmc_mi_dwr_s, BMC_MI_WR => bmc_mi_wr_s, BMC_MI_RD => bmc_mi_rd_s, BMC_MI_BE => bmc_mi_be_s, BMC_MI_ARDY => bmc_mi_ardy_s, BMC_MI_DRD => bmc_mi_drd_s, BMC_MI_DRDY => bmc_mi_drdy_s, - + AXI_MI_ADDR => axi_mi_addr_s, - AXI_MI_DWR => axi_mi_dwr_s, + AXI_MI_DWR => axi_mi_dwr_s, AXI_MI_WR => axi_mi_wr_s, AXI_MI_RD => axi_mi_rd_s, AXI_MI_BE => axi_mi_be_s, @@ -864,7 +864,7 @@ begin SPI_MISO => SF2_MISO, SPI_INT => SF2_INT, - -- MI32 protocol signals + -- MI32 protocol signals BMC_MI_ADDR => bmc_mi_addr_s, BMC_MI_DWR => bmc_mi_dwr_s, BMC_MI_WR => bmc_mi_wr_s, @@ -882,8 +882,8 @@ begin SPI_CLK => axi_spi_clk, RST => boot_reset, - -- MI32 protocol - AXI_MI_ADDR => axi_mi_addr_s, + -- MI32 protocol + AXI_MI_ADDR => axi_mi_addr_s, AXI_MI_DWR => axi_mi_dwr_s, AXI_MI_WR => axi_mi_wr_s, AXI_MI_RD => axi_mi_rd_s, @@ -915,7 +915,7 @@ begin LED_CLK => QLED_CLK, LED_LE => QLED_LE ); - + -- FPGA COMMON ------------------------------------------------------------- usp_i : entity work.FPGA_COMMON generic map ( @@ -1007,7 +1007,7 @@ begin PCIE_CLK => pcie_clk, PCIE_RESET => pcie_reset, - + BOOT_MI_CLK => boot_mi_clk, BOOT_MI_RESET => boot_mi_reset, BOOT_MI_DWR => boot_mi_dwr, diff --git a/cards/silicom/fb4cgg3/constr/ddr4.xdc b/cards/silicom/fb4cgg3/constr/ddr4.xdc index 8990969bc..d34ad061e 100644 --- a/cards/silicom/fb4cgg3/constr/ddr4.xdc +++ b/cards/silicom/fb4cgg3/constr/ddr4.xdc @@ -165,7 +165,7 @@ set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports DDR4A_CK_P[*]] set_property PACKAGE_PIN BD36 [get_ports DDR4A_TEN] set_property IOSTANDARD LVCMOS12 [get_ports DDR4A_TEN] - + #DDR4B interface # Internal Clocks set_property PACKAGE_PIN C36 [get_ports DDR4B_REFCLK_P] diff --git a/cards/silicom/fb4cgg3/constr/qsfp.xdc b/cards/silicom/fb4cgg3/constr/qsfp.xdc index e96938669..bfdee8b8b 100644 --- a/cards/silicom/fb4cgg3/constr/qsfp.xdc +++ b/cards/silicom/fb4cgg3/constr/qsfp.xdc @@ -30,8 +30,8 @@ set_property PACKAGE_PIN K43 [get_ports {QSFP0_RX_P[3]}] set_property PACKAGE_PIN K44 [get_ports {QSFP0_RX_N[3]}] # QSFP port 1 - FB4CGG3 only --------------------------------------------------- -set_property PACKAGE_PIN AC36 [get_ports {QSFP1_REFCLK_P}] -set_property PACKAGE_PIN AC37 [get_ports {QSFP1_REFCLK_N}] +set_property PACKAGE_PIN AC36 [get_ports {QSFP1_REFCLK_P}] +set_property PACKAGE_PIN AC37 [get_ports {QSFP1_REFCLK_N}] create_clock -name qsfp1_refclk -period 6.206 [get_ports QSFP1_REFCLK_P] set_property PACKAGE_PIN AA40 [get_ports {QSFP1_TX_P[0]}] @@ -106,37 +106,37 @@ set_property PACKAGE_PIN AP44 [get_ports {QSFP3_RX_N[3]}] # QSFP misc - FB4CGG3/FB2CGG3 -------------------------------------------------- -set_property PACKAGE_PIN BF22 [get_ports {QSFP1_SCL}] -set_property PACKAGE_PIN BE22 [get_ports {QSFP1_SDA}] -set_property PACKAGE_PIN BE20 [get_ports {QSFP1_MODPRS_N}] -set_property PACKAGE_PIN BE21 [get_ports {QSFP1_RESET_N}] -set_property PACKAGE_PIN BD20 [get_ports {QSFP1_LPMODE}] +set_property PACKAGE_PIN BF22 [get_ports {QSFP1_SCL}] +set_property PACKAGE_PIN BE22 [get_ports {QSFP1_SDA}] +set_property PACKAGE_PIN BE20 [get_ports {QSFP1_MODPRS_N}] +set_property PACKAGE_PIN BE21 [get_ports {QSFP1_RESET_N}] +set_property PACKAGE_PIN BD20 [get_ports {QSFP1_LPMODE}] set_property PACKAGE_PIN BD21 [get_ports {QSFP1_INT_N}] -set_property PACKAGE_PIN AR23 [get_ports {QSFP0_SCL}] -set_property PACKAGE_PIN AT22 [get_ports {QSFP0_SDA}] -set_property PACKAGE_PIN AR21 [get_ports {QSFP0_MODPRS_N}] -set_property PACKAGE_PIN AT24 [get_ports {QSFP0_RESET_N}] -set_property PACKAGE_PIN AU24 [get_ports {QSFP0_LPMODE}] +set_property PACKAGE_PIN AR23 [get_ports {QSFP0_SCL}] +set_property PACKAGE_PIN AT22 [get_ports {QSFP0_SDA}] +set_property PACKAGE_PIN AR21 [get_ports {QSFP0_MODPRS_N}] +set_property PACKAGE_PIN AT24 [get_ports {QSFP0_RESET_N}] +set_property PACKAGE_PIN AU24 [get_ports {QSFP0_LPMODE}] set_property PACKAGE_PIN AT23 [get_ports {QSFP0_INT_N}] -set_property PACKAGE_PIN BC23 [get_ports {QSFP2_SCL}] -set_property PACKAGE_PIN BA23 [get_ports {QSFP2_SDA}] -set_property PACKAGE_PIN BE23 [get_ports {QSFP2_MODPRS_N}] -set_property PACKAGE_PIN BF23 [get_ports {QSFP2_RESET_N}] -set_property PACKAGE_PIN BD23 [get_ports {QSFP2_LPMODE}] +set_property PACKAGE_PIN BC23 [get_ports {QSFP2_SCL}] +set_property PACKAGE_PIN BA23 [get_ports {QSFP2_SDA}] +set_property PACKAGE_PIN BE23 [get_ports {QSFP2_MODPRS_N}] +set_property PACKAGE_PIN BF23 [get_ports {QSFP2_RESET_N}] +set_property PACKAGE_PIN BD23 [get_ports {QSFP2_LPMODE}] set_property PACKAGE_PIN BF24 [get_ports {QSFP2_INT_N}] -set_property PACKAGE_PIN BB21 [get_ports {QSFP3_SCL}] -set_property PACKAGE_PIN BB20 [get_ports {QSFP3_SDA}] +set_property PACKAGE_PIN BB21 [get_ports {QSFP3_SCL}] +set_property PACKAGE_PIN BB20 [get_ports {QSFP3_SDA}] set_property PACKAGE_PIN BA24 [get_ports {QSFP3_MODPRS_N}] -set_property PACKAGE_PIN BB22 [get_ports {QSFP3_RESET_N}] -set_property PACKAGE_PIN BC22 [get_ports {QSFP3_LPMODE}] +set_property PACKAGE_PIN BB22 [get_ports {QSFP3_RESET_N}] +set_property PACKAGE_PIN BC22 [get_ports {QSFP3_LPMODE}] set_property PACKAGE_PIN BC21 [get_ports {QSFP3_INT_N}] set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_SCL}] -set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_SDA}] +set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_SDA}] set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_MODPRS_N}] -set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_RESET_N}] -set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_LPMODE}] +set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_RESET_N}] +set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_LPMODE}] set_property IOSTANDARD LVCMOS18 [get_ports {QSFP*_INT_N}] diff --git a/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/Modules.tcl b/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/Modules.tcl index 047e2f5a4..adbf191c1 100644 --- a/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/Modules.tcl +++ b/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/Modules.tcl @@ -8,4 +8,4 @@ lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd" # Files -lappend MOD "$ENTITY_BASE/spi_flash_driver.vhd" \ No newline at end of file +lappend MOD "$ENTITY_BASE/spi_flash_driver.vhd" diff --git a/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/sim/testbench.vhd b/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/sim/testbench.vhd index d2d39f3cc..d79206684 100644 --- a/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/sim/testbench.vhd +++ b/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/sim/testbench.vhd @@ -15,7 +15,7 @@ architecture FULL of TESTBENCH is constant CLK_PERIOD : time := 4 ns; constant WORD_SIZE : natural := 16; constant TRANS_COUNT: natural := 16; - + signal clk : std_logic := '0'; signal reset : std_logic; diff --git a/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/spi_flash_driver.vhd b/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/spi_flash_driver.vhd index c16baf3d5..184f269d0 100644 --- a/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/spi_flash_driver.vhd +++ b/cards/silicom/fb4cgg3/src/comp/spi_flash_driver/spi_flash_driver.vhd @@ -57,7 +57,7 @@ architecture FULL of SPI_FLASH_DRIVER is signal rd_cnt_next : unsigned(log2(RD_CLK_TIME)-1 downto 0); signal spi_done : std_logic; signal spi_rd_data : std_logic_vector(WORD_SIZE-1 downto 0); - + signal spi_clk_reg : std_logic; signal spi_cs_n_reg : std_logic; signal spi_mosi_reg : std_logic; @@ -66,7 +66,7 @@ architecture FULL of SPI_FLASH_DRIVER is signal spi_mosi_next : std_logic; begin - + process(CLK) begin if rising_edge(CLK) then @@ -80,7 +80,7 @@ begin else -- second part of flash need more time before read rd_start_delay_reg <= X"800"; end if; - end if; + end if; end if; end process; @@ -124,7 +124,7 @@ begin end if; end if; end process; - + process (all) begin spi_fsm_nst <= spi_fsm_pst; @@ -225,7 +225,7 @@ begin wait_cnt_next <= wait_cnt_reg + 1; spi_fsm_nst <= st_read_sample; end if; - + when st_read_done => miso_reg_next <= miso_reg(miso_reg'high-1 downto 0) & SPI_MISO; spi_done <= '1'; diff --git a/cards/silicom/fb4cgg3/src/fpga.vhd b/cards/silicom/fb4cgg3/src/fpga.vhd index fde0f7729..471297b7d 100644 --- a/cards/silicom/fb4cgg3/src/fpga.vhd +++ b/cards/silicom/fb4cgg3/src/fpga.vhd @@ -194,7 +194,7 @@ architecture FULL of FPGA is signal eth_led_g : std_logic_vector(4*4-1 downto 0); signal eth_led_r : std_logic_vector(4*4-1 downto 0); - + signal eth_refclk_p : std_logic_vector(4-1 downto 0); signal eth_refclk_n : std_logic_vector(4-1 downto 0); signal eth_rx_p : std_logic_vector(4*ETH_LANES-1 downto 0); @@ -208,7 +208,7 @@ architecture FULL of FPGA is signal qsfp_sda : std_logic_vector(4-1 downto 0) := (others => 'Z'); signal qsfp_modprs_n : std_logic_vector(4-1 downto 0); signal qsfp_int_n : std_logic_vector(4-1 downto 0); - + signal misc_in : std_logic_vector(MISC_IN_WIDTH-1 downto 0) := (others => '0'); signal misc_out : std_logic_vector(MISC_OUT_WIDTH-1 downto 0); @@ -269,7 +269,7 @@ architecture FULL of FPGA is signal ddr_s_axi_rresp : slv_array_t (DDR_PORTS-1 downto 0)(1 DOWNTO 0); signal ddr_s_axi_rid : slv_array_t (DDR_PORTS-1 downto 0)(3 DOWNTO 0); signal ddr_s_axi_rdata : slv_array_t (DDR_PORTS-1 downto 0)(DDR_AXI_DATA_WIDTH-1 DOWNTO 0); - + -- DDR4A interface signal ddr4a_rst : std_logic; signal ddr4a_app_hi_pri : std_logic; @@ -282,8 +282,8 @@ architecture FULL of FPGA is signal ddr4b_app_hi_pri : std_logic; signal ddr4b_dqs_p : std_logic_vector(DDR_BYTES-1 downto 0); signal ddr4b_dqs_n : std_logic_vector(DDR_BYTES-1 downto 0); - signal ddr4b_dm : std_logic_vector(DDR_BYTES-1 downto 0); - + signal ddr4b_dm : std_logic_vector(DDR_BYTES-1 downto 0); + -- MEM_TESTER signals signal mem_avmm_ready : std_logic_vector(DDR_PORTS -1 downto 0); signal mem_avmm_read : std_logic_vector(DDR_PORTS -1 downto 0); @@ -476,30 +476,30 @@ begin DDR4A_TEN <= '0'; -- Insert differential buffers - A_CK_BUF: OBUFDS + A_CK_BUF: OBUFDS port map ( - I => '1', - O => DDR4A_CK_P(0), + I => '1', + O => DDR4A_CK_P(0), OB => DDR4A_CK_N(0) ); A_ldqs_buf_g: for p in 0 to (DDR_BYTES/2)-1 generate - LDQS_BUF: IOBUFDS + LDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', - IO => DDR4A_LDQS_P(p), + O => open, + I => '0', + T => '0', + IO => DDR4A_LDQS_P(p), IOB => DDR4A_LDQS_N(p) ); end generate; A_udqs_buf_g: for p in 0 to (DDR_BYTES/2)-1 generate - UDQS_BUF: IOBUFDS + UDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', + O => open, + I => '0', + T => '0', IO => DDR4A_UDQS_P(p), IOB => DDR4A_UDQS_N(p) ); @@ -601,30 +601,30 @@ begin DDR4B_TEN <= '0'; -- Insert differential buffers - B_CK_BUF: OBUFDS + B_CK_BUF: OBUFDS port map ( - I => '1', - O => DDR4B_CK_P(0), + I => '1', + O => DDR4B_CK_P(0), OB => DDR4B_CK_N(0) ); B_ldqs_buf_g: for p in 0 to (DDR_BYTES/2)-1 generate - LDQS_BUF: IOBUFDS + LDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', - IO => DDR4B_LDQS_P(p), + O => open, + I => '0', + T => '0', + IO => DDR4B_LDQS_P(p), IOB => DDR4B_LDQS_N(p) ); end generate; B_udqs_buf_g: for p in 0 to (DDR_BYTES/2)-1 generate - UDQS_BUF: IOBUFDS + UDQS_BUF: IOBUFDS port map ( - O => open, - I => '0', - T => '0', + O => open, + I => '0', + T => '0', IO => DDR4B_UDQS_P(p), IOB => DDR4B_UDQS_N(p) ); @@ -638,7 +638,7 @@ begin port map( MEM_CLK => ddr_ui_clk(i), MEM_RST => ddr_ui_clk_sync_rst(i), - + -- DDR4_AXI interface DDR_S_AXI_AWID => ddr_s_axi_awid(i), DDR_S_AXI_AWADDR => ddr_s_axi_awaddr(i), @@ -669,7 +669,7 @@ begin DDR_S_AXI_RRESP => ddr_s_axi_rresp(i), DDR_S_AXI_RID => ddr_s_axi_rid(i), DDR_S_AXI_RDATA => ddr_s_axi_rdata(i), - + -- EMIF interface AMM_READY => mem_avmm_ready(i), AMM_READ => mem_avmm_read(i), @@ -774,7 +774,7 @@ begin FLASH_WR_DATA => boot_wr_data, FLASH_WR_EN => boot_wr_en, FLASH_RD_DATA => boot_rd_data - ); + ); spi_flash_driver_i : entity work.SPI_FLASH_DRIVER port map ( @@ -884,7 +884,7 @@ begin PCIE_CLK => pcie_clk, PCIE_RESET => pcie_reset, - + BOOT_MI_CLK => boot_mi_clk, BOOT_MI_RESET => boot_mi_reset, BOOT_MI_DWR => boot_mi_dwr, diff --git a/cards/silicom/n6010/constr/general.qsf b/cards/silicom/n6010/constr/general.qsf index 8f2687bbb..037a76bdd 100644 --- a/cards/silicom/n6010/constr/general.qsf +++ b/cards/silicom/n6010/constr/general.qsf @@ -87,8 +87,8 @@ set_location_assignment PIN_P31 -to NCSI_RBT_NCSI_TXD[1] set_location_assignment PIN_M31 -to NCSI_RBT_NCSI_TX_EN set_location_assignment PIN_H29 -to NCSI_RBT_NCSI_RXD[0] set_location_assignment PIN_J30 -to NCSI_RBT_NCSI_RXD[1] -set_location_assignment PIN_L30 -to NCSI_RBT_NCSI_CRS_DV -set_location_assignment PIN_N30 -to NCSI_RBT_NCSI_ARB_IN +set_location_assignment PIN_L30 -to NCSI_RBT_NCSI_CRS_DV +set_location_assignment PIN_N30 -to NCSI_RBT_NCSI_ARB_IN set_location_assignment PIN_F29 -to NCSI_RBT_NCSI_ARB_OUT set_instance_assignment -name IO_STANDARD "1.2 V" -to QSPI_NCS diff --git a/cards/silicom/n6010/constr/pcie.qsf b/cards/silicom/n6010/constr/pcie.qsf index 93f253a2d..c06bf5924 100644 --- a/cards/silicom/n6010/constr/pcie.qsf +++ b/cards/silicom/n6010/constr/pcie.qsf @@ -82,7 +82,7 @@ set_location_assignment PIN_AG56 -to PCIE_TX_N[14] set_location_assignment PIN_AD53 -to PCIE_TX_N[15] # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK0 diff --git a/cards/silicom/n6010/constr/qsfp.qsf b/cards/silicom/n6010/constr/qsfp.qsf index b855cd6f4..6622e4762 100644 --- a/cards/silicom/n6010/constr/qsfp.qsf +++ b/cards/silicom/n6010/constr/qsfp.qsf @@ -52,7 +52,7 @@ set_location_assignment PIN_CY29 -to QSFP1_LED_R set_location_assignment PIN_DB29 -to QSFP1_LED_G # ============================================================================== -# Pin IO Standards & Input Termination +# Pin IO Standards & Input Termination # ============================================================================== set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to QSFP_REFCLK_156M @@ -105,4 +105,4 @@ set_instance_assignment -name SLEW_RATE 0 -to QSFP1_RESET_N set_instance_assignment -name SLEW_RATE 0 -to QSFP1_LPMODE set_instance_assignment -name SLEW_RATE 0 -to QSFP1_MODESEL_N set_instance_assignment -name SLEW_RATE 0 -to QSFP1_I2C_SCL -set_instance_assignment -name SLEW_RATE 0 -to QSFP1_I2C_SDA +set_instance_assignment -name SLEW_RATE 0 -to QSFP1_I2C_SDA diff --git a/cards/silicom/n6010/scripts/LICENSE.txt b/cards/silicom/n6010/scripts/LICENSE.txt index a9f3b6eba..c9fa9b111 100644 --- a/cards/silicom/n6010/scripts/LICENSE.txt +++ b/cards/silicom/n6010/scripts/LICENSE.txt @@ -1,4 +1,4 @@ -Copyright (c) 2022 Intel Corporation +Copyright (c) 2022 Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -16,4 +16,4 @@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. \ No newline at end of file +SOFTWARE. diff --git a/cards/silicom/n6010/scripts/build_flash.sh b/cards/silicom/n6010/scripts/build_flash.sh index 2065d09a9..f8fc7879f 100755 --- a/cards/silicom/n6010/scripts/build_flash.sh +++ b/cards/silicom/n6010/scripts/build_flash.sh @@ -27,13 +27,13 @@ FACTORY_SOF_PRESENT="0" FACTORY_HPS_SOF_PRESENT="0" GEN_TYPE="" -# This script assumes that the calling shell has already changed the CWD +# This script assumes that the calling shell has already changed the CWD # to this directory. SCRIPT=$(realpath "$0") WORK_DIR=`realpath .` LOCAL_SCRIPT_DIR=$(dirname "$SCRIPT") -# check for factory_image.sof, if not available, +# check for factory_image.sof, if not available, # copy over the ofs_fim.sof as the factory if [ -e ${WORK_DIR}/${FACTORY_HPS_SOF} ]; then echo "Using ${FACTORY_HPS_SOF} as the factory image." @@ -69,7 +69,7 @@ python3 ${LOCAL_SCRIPT_DIR}/gen_image_info_hex.py ${LOCAL_SCRIPT_DIR}/${fme_mif_ #objcopy -I binary -O ihex ${LOCAL_SCRIPT_DIR}/blank_bmc_root_hash.reversed ${LOCAL_SCRIPT_DIR}/blank_bmc_root_hash.reversed.hex ## blank sr (FIM) key - 4 bytes of FF -#python ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/blank_sr_key_programmed ${LOCAL_SCRIPT_DIR}/blank_sr_key_programmed.reversed +#python ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/blank_sr_key_programmed ${LOCAL_SCRIPT_DIR}/blank_sr_key_programmed.reversed #objcopy -I binary -O ihex blank_sr_key_programmed.reversed blank_sr_key_programmed.reversed.hex ## blank sr (FIM) root key hash - 32 bytes of FF @@ -141,7 +141,7 @@ python3 ${LOCAL_SCRIPT_DIR}/extract_bitstream.py ${WORK_DIR}/${GEN_TYPE}_pof.map python3 ${LOCAL_SCRIPT_DIR}/extract_bitstream.py ${WORK_DIR}/${GEN_TYPE}_pof.map ${WORK_DIR}/${GEN_TYPE}.bin ${WORK_DIR}/$pacsign_infile_user1 "User_Image_1" python3 ${LOCAL_SCRIPT_DIR}/extract_bitstream.py ${WORK_DIR}/${GEN_TYPE}_pof.map ${WORK_DIR}/${GEN_TYPE}.bin ${WORK_DIR}/$pacsign_infile_user2 "User_Image_2" -# -- read the image info txt string to pass to pacsign +# -- read the image info txt string to pass to pacsign value_factory=$(<${LOCAL_SCRIPT_DIR}/../${factory_image_info_text}) value_user1=$(<${LOCAL_SCRIPT_DIR}/../${user1_image_info_text}) value_user2=$(<${LOCAL_SCRIPT_DIR}/../${user2_image_info_text}) @@ -151,7 +151,7 @@ value_user2=$(<${LOCAL_SCRIPT_DIR}/../${user2_image_info_text}) # uncomment following line if mfg image is desired #python3 ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/../${GEN_TYPE}.bin ${LOCAL_SCRIPT_DIR}/../mfg_ofs_fim_reversed.bin -# -- create unsigned FIM user image for fpgasupdate tool +# -- create unsigned FIM user image for fpgasupdate tool if which PACSign &> /dev/null ; then PACSign FACTORY -y -v -t UPDATE -H openssl_manager -b ${value_factory} -i ${WORK_DIR}/$pacsign_infile_factory -o ${WORK_DIR}/$pacsign_outfile_factory PACSign SR -s 0 -y -v -t UPDATE -H openssl_manager -b ${value_factory} -i ${WORK_DIR}/$pacsign_infile_user1 -o ${WORK_DIR}/$pacsign_outfile_user1 @@ -188,4 +188,4 @@ else fi echo "Done." -exit 0 \ No newline at end of file +exit 0 diff --git a/cards/silicom/n6010/scripts/extract_bitstream.py b/cards/silicom/n6010/scripts/extract_bitstream.py index 8a84a5854..18d15cedc 100755 --- a/cards/silicom/n6010/scripts/extract_bitstream.py +++ b/cards/silicom/n6010/scripts/extract_bitstream.py @@ -10,7 +10,8 @@ import sys logging.basicConfig(level=0) -LOGGER= logging.getLogger(__name__) +LOGGER = logging.getLogger(__name__) + def main(args): pof_map = args.map_file.read().decode('utf-8') @@ -29,6 +30,7 @@ def main(args): bs = args.in_file.read(bs_len) args.out_file.write(bs) + if __name__ == '__main__': parser = argparse.ArgumentParser() diff --git a/cards/silicom/n6010/scripts/gen_image_info_hex.py b/cards/silicom/n6010/scripts/gen_image_info_hex.py index be383a3dc..7b90c24bc 100755 --- a/cards/silicom/n6010/scripts/gen_image_info_hex.py +++ b/cards/silicom/n6010/scripts/gen_image_info_hex.py @@ -11,7 +11,8 @@ import binascii logging.basicConfig(level=0) -LOGGER= logging.getLogger(__name__) +LOGGER = logging.getLogger(__name__) + def checksum_calc(address, value): int_value = int(value, 16) @@ -31,17 +32,19 @@ def checksum_calc(address, value): checksum_return = format(checksum_val, '02X') return checksum_return + def bit_reversal(value): reversed_value = "" - for i in range(0,len(value),2): # Grab two hex digits (byte) and reverse the bits. + for i in range(0, len(value), 2): # Grab two hex digits (byte) and reverse the bits. byte = value[i:i+2] - byte_int = int(byte,16) + byte_int = int(byte, 16) byte_reversed = '{:08b}'.format(byte_int)[::-1] - byte_hex = int(byte_reversed,2) + byte_hex = int(byte_reversed, 2) byte_reversed_str = format(byte_hex, '02X') reversed_value = reversed_value + byte_reversed_str return reversed_value + def main(args): address = 0x0000 mif_data = args.mif_file.read().decode('utf-8') @@ -79,7 +82,7 @@ def main(args): words = words + id_second id_second_bytes = id_second.encode() id_second_hex_bytes = binascii.hexlify(id_second_bytes) - id_second_hex = bit_reversal(str(id_second_hex_bytes, 'utf-8')) + id_second_hex = bit_reversal(str(id_second_hex_bytes, 'utf-8')) id_second_hex_front_half = id_second_hex[:16] id_second_hex_back_half = id_second_hex[16:] id_second_hex_front_half_checksum = checksum_calc(address, id_second_hex_front_half) diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/LICENSE.txt b/cards/silicom/n6010/src/comp/pmci/pmci_ip/LICENSE.txt index a9f3b6eba..c9fa9b111 100644 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/LICENSE.txt +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/LICENSE.txt @@ -1,4 +1,4 @@ -Copyright (c) 2022 Intel Corporation +Copyright (c) 2022 Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -16,4 +16,4 @@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. \ No newline at end of file +SOFTWARE. diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/avmms_2_spim_bridge_hw.tcl b/cards/silicom/n6010/src/comp/pmci/pmci_ip/avmms_2_spim_bridge_hw.tcl index 12b177cb0..5dba309a0 100644 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/avmms_2_spim_bridge_hw.tcl +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/avmms_2_spim_bridge_hw.tcl @@ -1,7 +1,7 @@ # Copyright (C) 2020 Intel Corporation. # SPDX-License-Identifier: MIT -# +# # Description # ----------------------------------------------------------------------------- # This is the _hw.tcl of Avalon Slave to SPI Master Bridge Core @@ -348,7 +348,7 @@ add_interface_port spi spim_mosi mosi Output 1 # Validate IP # ----------------------------------------------------------------------------- proc ip_validate { } { - + set csr_dwidth [ get_parameter_value CSR_DATA_WIDTH ] set dir_awidth [ get_parameter_value DIR_ADDR_WIDTH ] set dir_baddr [ get_parameter_value DIR_BASE_ADDR ] @@ -364,16 +364,16 @@ proc ip_validate { } { } else { set_parameter_value CSR_ADDR_WIDTH -1 } - + set addr_span [expr {int(4 * pow(2, $dir_awidth))}] set max_bcount [expr {int(2 * pow(2, $dir_bcount))}] - + if { $max_bcount > $addr_span } { send_message Error "Addressable bytes derived from DIR_ADDR_WIDTH is lesser than maximum burst length derived from DIR_BRST_WIDTH" send_message Info "Address width spans $addr_span bytes." send_message Info "Maximum burst count is $max_bcount bytes." } - + if { $dir_baddr == 0 } { send_message Error "'Base Address of Direct Slave Access' cannot be zero" } @@ -384,35 +384,35 @@ proc ip_validate { } { if { [expr {$dir_baddr & ($addr_span - 1)}] != 0 } { send_message Error [format "Base address 0x%X is not aligned to address range $addr_span bytes" $dir_baddr] } - + set bit_pos 31 set all_fs 0xFFFFFFFF while { ([expr {$dir_baddr & ($all_fs << $bit_pos)}] != $dir_baddr) && ($bit_pos >= 0) } { set bit_pos [expr {$bit_pos - 1}] } set_parameter_value SLV_CSR_AWIDTH $bit_pos - + if { $miso_dly > [expr {$clk_div + 1}] } { send_message Warning "MISO Capture delay is more than clock period. Please make sure master can capture MISO at this delay" } - + } # ----------------------------------------------------------------------------- # Elaborate IP # ----------------------------------------------------------------------------- proc ip_elaborate { } { - + set csr_awidth [ get_parameter_value CSR_ADDR_WIDTH ] set csr_dwidth [ get_parameter_value CSR_DATA_WIDTH ] set dir_awidth [ get_parameter_value DIR_ADDR_WIDTH ] set dir_bcount [ get_parameter_value DIR_BRST_WIDTH ] - + set_port_property avmm_csr_addr width_expr $csr_awidth set_port_property avmm_csr_rddata width_expr $csr_dwidth set_port_property avmm_csr_wrdata width_expr $csr_dwidth set_port_property avmm_csr_byteen width_expr [expr {$csr_dwidth / 8}] - + set_port_property avmm_dir_addr width_expr $dir_awidth set_port_property avmm_dir_burstcnt width_expr $dir_bcount diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/flash_burst_master/flash_burst_master.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/flash_burst_master/flash_burst_master.sv index e51564ed8..351441c8a 100644 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/flash_burst_master/flash_burst_master.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/flash_burst_master/flash_burst_master.sv @@ -4,11 +4,11 @@ // // Description //----------------------------------------------------------------------------- -// This module converts single beat (4Byte/8Byte) flash read/write requests to +// This module converts single beat (4Byte/8Byte) flash read/write requests to // page read/write requests. -// Flash’s write performance improves when 256byte page program is used instead -// of non-page program. Flash burst master aggregates contiguous 4B/8B flash -// write requests from host and requests 256byte page write request to the +// Flash’s write performance improves when 256byte page program is used instead +// of non-page program. Flash burst master aggregates contiguous 4B/8B flash +// write requests from host and requests 256byte page write request to the // flash controller to improve flash write performance. //----------------------------------------------------------------------------- @@ -30,7 +30,7 @@ module flash_burst_master #( input logic [FIFO_DEPTH_LOG2:0] read_count, input logic [FLASH_ADDR_WIDTH-1:0] flash_addr, - //AVMM slave + //AVMM slave input logic [7:0] avmm_slv_addr, input logic avmm_slv_write, input logic avmm_slv_read, @@ -39,7 +39,7 @@ module flash_burst_master #( output logic [31:0] avmm_slv_rddata, output logic avmm_slv_rddvld, output logic avmm_slv_waitreq, - + //AVMM master to flash output logic [FLASH_ADDR_WIDTH-1:0] avmm_mstr_addr, output logic avmm_mstr_write, @@ -66,7 +66,7 @@ enum { FBM_RD_REQ_BIT = 4, FBM_RD_DATA_BIT = 5, FBM_DUMMY_RD_BIT = 6 - + } fbm_state_bit; enum logic [6:0] { @@ -116,15 +116,15 @@ begin : fbm_ctrl_seq write_mode_r1 <= write_mode; read_mode_r1 <= read_mode; rsu_mode_r1 <= rsu_mode; - + if(!read_mode_r1 && read_mode && !rsu_mode || !rsu_mode_r1 && rsu_mode || !write_mode_r1 && write_mode) fifo_reset_cntr <= {RST_DEPTH+1{1'b0}}; else if(!fifo_reset_cntr[RST_DEPTH]) fifo_reset_cntr <= fifo_reset_cntr + 1'b1; - + flash_busy <= ~fbm_state[FBM_RESET_BIT] & ~fbm_state[FBM_READY_BIT]; - + if(fifo_full) fifo_dcount <= '0; else @@ -148,8 +148,8 @@ begin : fifo_wr_seq fifo_wr_data <= avmm_mstr_rddata; else fifo_wr_data <= avmm_slv_wrdata; - - if(read_mode_r1 && avmm_mstr_rddvld || (write_mode_r1 || rsu_mode_r1) && + + if(read_mode_r1 && avmm_mstr_rddvld || (write_mode_r1 || rsu_mode_r1) && !fifo_full && avmm_slv_write && !avmm_slv_waitreq) fifo_wr_req <= 1'b1; else @@ -164,7 +164,7 @@ always_comb begin : fifo_rd_comb if(read_mode_r1 && !fifo_empty && avmm_slv_read && !avmm_slv_waitreq) lsw_rd = (EN_DBG_STS == 1 && avmm_slv_addr[7]) ? 1'b0 : 1'b1; - else + else lsw_rd = 1'b0; end : fifo_rd_comb @@ -178,22 +178,22 @@ begin : fifo_rd_seq avmm_slv_rddata <= 64'd0; end else begin lsw_rd_sr <= {lsw_rd_sr[0], lsw_rd}; - + if(fbm_fifo_rd || lsw_rd) - fifo_rdreq <= 1'b1; - else - fifo_rdreq <= 1'b0; - + fifo_rdreq <= 1'b1; + else + fifo_rdreq <= 1'b0; + if((avmm_slv_read || avmm_slv_write) && !avmm_slv_waitreq) avmm_slv_waitreq <= 1'b1; else if(lsw_rd_sr == 2'd0) avmm_slv_waitreq <= 1'b0; - + if(lsw_rd_sr[1] || avmm_slv_read && !avmm_slv_waitreq && !lsw_rd) avmm_slv_rddvld <= 1'b1; else avmm_slv_rddvld <= 1'b0; - + if(lsw_rd_sr[1]) avmm_slv_rddata <= fifo_rddata; else @@ -238,7 +238,7 @@ scfifo #( ); //------------------------------------------------------------------------------ -// Flash burst master's FSM +// Flash burst master's FSM // Top "always_ff" simply switches the state of the state machine registers. // Following "always_comb" contains all of the next-state decoding logic. //------------------------------------------------------------------------------ @@ -259,17 +259,17 @@ begin : fbm_sm_comb fbm_next = FBM_RESET_ST; else fbm_next = FBM_READY_ST; - + fbm_state[FBM_READY_BIT]: //FBM_READY_ST if(rsu_mode_r1 || write_mode_r1) fbm_next = FBM_WR_WAIT_ST; else if(read_mode_r1 && !rd_complete) fbm_next = FBM_RD_REQ_ST; - + fbm_state[FBM_WR_WAIT_BIT]: //FBM_WR_WAIT_ST if(!(rsu_mode_r1 || write_mode_r1) && fifo_empty) fbm_next = FBM_DUMMY_RD_ST; - else if(!(rsu_mode_r1 || write_mode_r1) && !fifo_empty || + else if(!(rsu_mode_r1 || write_mode_r1) && !fifo_empty || fifo_full || (fifo_usedw >= 7'd64)) fbm_next = FBM_WR_REQ_ST; @@ -282,11 +282,11 @@ begin : fbm_sm_comb fbm_next = FBM_READY_ST; else fbm_next = FBM_RD_DATA_ST; - + fbm_state[FBM_RD_DATA_BIT]: //FBM_RD_DATA_ST if(beat_cntr == 7'd0) fbm_next = FBM_RD_REQ_ST; - + fbm_state[FBM_DUMMY_RD_BIT]: //FBM_DUMMY_RD_ST if(avmm_mstr_rddvld) fbm_next = FBM_READY_ST; @@ -302,7 +302,7 @@ begin : fsm_ctrl_seq avmm_mstr_addr <= STAGING_AREA_BADDR; else if(fbm_state[FBM_READY_BIT]) avmm_mstr_addr <= {flash_addr[FLASH_ADDR_WIDTH-1:2], 2'd0}; - else if ((fbm_state[FBM_WR_REQ_BIT] || fbm_state[FBM_RD_DATA_BIT]) && + else if ((fbm_state[FBM_WR_REQ_BIT] || fbm_state[FBM_RD_DATA_BIT]) && (beat_cntr == 7'd0)) avmm_mstr_addr <= avmm_mstr_addr + 9'd256; @@ -310,29 +310,29 @@ begin : fsm_ctrl_seq first_beat <= 1'b1; else first_beat <= 1'b0; - + if(fifo_reset) avmm_mstr_write <= 1'b0; else if(fbm_state[FBM_WR_REQ_BIT] && fifo_rdreq) avmm_mstr_write <= 1'b1; else if(!fbm_state[FBM_WR_REQ_BIT] || !avmm_mstr_waitreq) avmm_mstr_write <= 1'b0; - + if(fifo_reset) avmm_mstr_read <= 1'b0; else if((fbm_state[FBM_RD_REQ_BIT] || fbm_state[FBM_DUMMY_RD_BIT]) && !rd_complete) avmm_mstr_read <= 1'b1; - else if(!avmm_mstr_waitreq) + else if(!avmm_mstr_waitreq) avmm_mstr_read <= 1'b0; - + if(fbm_state[FBM_READY_BIT]) rd_cntr <= read_count; - else if(fbm_state[FBM_RD_REQ_BIT] && rd_cntr >= 7'd64) + else if(fbm_state[FBM_RD_REQ_BIT] && rd_cntr >= 7'd64) rd_cntr <= rd_cntr - 7'd64; - else if(fbm_state[FBM_RD_REQ_BIT]) + else if(fbm_state[FBM_RD_REQ_BIT]) rd_cntr <= '0; - - if (fbm_state[FBM_WR_WAIT_BIT] && (fifo_usedw >= 7'd64 || fifo_full) || + + if (fbm_state[FBM_WR_WAIT_BIT] && (fifo_usedw >= 7'd64 || fifo_full) || fbm_state[FBM_RD_REQ_BIT] && rd_cntr >= 7'd64) beat_cntr <= 7'd64; else if(fbm_state[FBM_WR_WAIT_BIT]) @@ -341,20 +341,20 @@ begin : fsm_ctrl_seq beat_cntr <= rd_cntr[6:0]; else if(fbm_state[FBM_DUMMY_RD_BIT]) beat_cntr <= 7'd1; - else if(fbm_state[FBM_WR_REQ_BIT] && avmm_mstr_write && !avmm_mstr_waitreq || + else if(fbm_state[FBM_WR_REQ_BIT] && avmm_mstr_write && !avmm_mstr_waitreq || fbm_state[FBM_RD_DATA_BIT] && avmm_mstr_rddvld) beat_cntr <= beat_cntr - 1'b1; - + if(fbm_state[FBM_RESET_BIT]) rd_complete <= 1'b0; - else if(fbm_state[FBM_RD_DATA_BIT] && (rd_cntr == {(FIFO_DEPTH_LOG2+1){1'b0}}) || + else if(fbm_state[FBM_RD_DATA_BIT] && (rd_cntr == {(FIFO_DEPTH_LOG2+1){1'b0}}) || fbm_state[FBM_DUMMY_RD_BIT]) rd_complete <= 1'b1; end : fsm_ctrl_seq always_comb -begin : fsm_ctrl_comb - if (fbm_state[FBM_WR_REQ_BIT] && (first_beat || +begin : fsm_ctrl_comb + if (fbm_state[FBM_WR_REQ_BIT] && (first_beat || avmm_mstr_write && !avmm_mstr_waitreq && beat_cntr[6:1] != 6'd0)) fbm_fifo_rd = 1'b1; else diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ctrlr.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ctrlr.sv index 9c3eb0058..c386e8957 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ctrlr.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ctrlr.sv @@ -4,10 +4,10 @@ // // Description //----------------------------------------------------------------------------- -// MCTP over PCIe VDM Controller module is used to parse MCTP over PCIe VDM +// MCTP over PCIe VDM Controller module is used to parse MCTP over PCIe VDM // TLPs and forward the MCTP payloads to MAX10’s MCTP over PCIe VDM buffer. -// Similarlly in the other direction, this module receives the MCTP payload -// from MAX10’s MCTP over PCIe VDM buffer and constructs PCIe VDM TLPs and +// Similarlly in the other direction, this module receives the MCTP payload +// from MAX10’s MCTP over PCIe VDM buffer and constructs PCIe VDM TLPs and // forwards it. //----------------------------------------------------------------------------- @@ -19,11 +19,11 @@ module mctp_pcievdm_ctrlr #( parameter MCTP_BASELINE_MTU = 16, //in DWORDs, i.e. 64/4 = 16 (should be aligned to 64bits) parameter DEBUG_REG_EN = 0, parameter DEBUG_REG_WIDTH = 8 - + )( input logic clk, input logic reset, - + //CSR i/f input logic [SS_ADDR_WIDTH-1:0] pcievdm_afu_addr, input logic pcievdm_afu_addr_vld, @@ -33,7 +33,7 @@ module mctp_pcievdm_ctrlr #( output logic [63:0] pcie_vdm_sts3_dbg, output logic [63:0] pcie_vdm_sts4_dbg, output logic [63:0] pcie_vdm_sts5_dbg, - + //Ingress AVMM slave (connected to IOFS-shell/AFU) input logic [0:0] avmm_ingr_slv_addr, input logic avmm_ingr_slv_write, @@ -53,7 +53,7 @@ module mctp_pcievdm_ctrlr #( input logic [31:0] avmm_ingr_mstr_rddata, input logic avmm_ingr_mstr_rddvld, input logic avmm_ingr_mstr_waitreq, - + //Egress AVMM slave (connected to SPI Slave) input logic [EGRS_SLV_ADDR_WIDTH-1:0] avmm_egrs_slv_addr, input logic avmm_egrs_slv_write, @@ -107,7 +107,7 @@ mctp_pcievdm_ingr #( )mctp_pcievdm_ingr_inst( .clk (clk ), .reset (reset ), - + //CSR i/f .pcievdm_mctp_eid (pcievdm_mctp_eid ), // .pcievdm_mctp_mtu_wsize (), @@ -116,7 +116,7 @@ mctp_pcievdm_ingr #( .pcie_vdm_sts2_dbg (pcie_vdm_sts2_dbg ), .pcie_vdm_sts3_dbg (pcie_vdm_sts3_dbg ), .pulse_1us (pulse_1us ), - + //Ingress AVMM slave (connected to IOFS-shell/AFU) .avmm_ingr_slv_addr (avmm_ingr_slv_addr ), .avmm_ingr_slv_write (avmm_ingr_slv_write ), @@ -152,14 +152,14 @@ mctp_pcievdm_egrs #( )mctp_pcievdm_egrs_inst( .clk (clk ), .reset (reset ), - + //CSR i/f .pcievdm_afu_addr (pcievdm_afu_addr ), .pcievdm_mctp_eid (pcievdm_mctp_eid ), .pcie_vdm_sts4_dbg (pcie_vdm_sts4_dbg ), .pcie_vdm_sts5_dbg (pcie_vdm_sts5_dbg ), .pulse_1us (pulse_1us ), - + //Egress AVMM slave (connected to SPI Slave) .avmm_egrs_slv_addr (avmm_egrs_slv_addr ), .avmm_egrs_slv_write (avmm_egrs_slv_write ), @@ -180,4 +180,4 @@ mctp_pcievdm_egrs #( .avmm_egrs_mstr_waitreq (avmm_egrs_mstr_waitreq) ); -endmodule +endmodule diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_egrs.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_egrs.sv index 9dab93d58..f86985b36 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_egrs.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_egrs.sv @@ -4,7 +4,7 @@ // // Description //----------------------------------------------------------------------------- -// MCTP over PCIe VDM Egress module receives the MCTP payload from MAX10’s MCTP +// MCTP over PCIe VDM Egress module receives the MCTP payload from MAX10’s MCTP // over PCIe VDM buffer and constructs PCIe VDM TLPs and forwards it to AFU. //----------------------------------------------------------------------------- @@ -18,14 +18,14 @@ module mctp_pcievdm_egrs #( )( input logic clk, input logic reset, - + //CSR i/f input logic [SS_ADDR_WIDTH-1:0] pcievdm_afu_addr, input logic [7:0] pcievdm_mctp_eid, output logic [63:0] pcie_vdm_sts4_dbg, output logic [63:0] pcie_vdm_sts5_dbg, input logic pulse_1us, - + //Egress AVMM slave (connected to SPI Slave) input logic [EGRS_SLV_ADDR_WIDTH-1:0] avmm_egrs_slv_addr, input logic avmm_egrs_slv_write, @@ -77,7 +77,7 @@ enum logic [8:0] { EGRS_HDR_2_ST = 9'h1 << EGRS_HDR_2_BIT , EGRS_PLOAD_ST = 9'h1 << EGRS_PLOAD_BIT , EGRS_EOP_ST = 9'h1 << EGRS_EOP_BIT , - EGRS_WAIT_ST = 9'h1 << EGRS_WAIT_BIT + EGRS_WAIT_ST = 9'h1 << EGRS_WAIT_BIT } egrs_state, egrs_next, egrs_state_r1; logic mctp_msg_rdy_reg ; @@ -127,7 +127,7 @@ logic [63:0] pcie_tlp_hdr_2 ; // [28] RW Null Source EID (1-null EID; 0-configured EID) // [29] RW PCIe VDM routing (0-route to root complex, 1-route by ID) // [31:28] R Reserved -//Egress Tx Packet Buffer - address 0x400 ~ 0x7FC +//Egress Tx Packet Buffer - address 0x400 ~ 0x7FC //----------------------------------------------------------------------------- always_ff @(posedge clk, posedge reset) begin : xmtr_reg_wr @@ -141,15 +141,15 @@ begin : xmtr_reg_wr mctp_src_eid_reg <= 8'd0; tlp_pcie_route_reg <= 3'd0; end else begin - if(avmm_egrs_slv_addr == EGRS_CNS_REG_ADDR && avmm_egrs_slv_write && + if(avmm_egrs_slv_addr == EGRS_CNS_REG_ADDR && avmm_egrs_slv_write && egrs_state[EGRS_IDLE_BIT]) begin mctp_msg_rdy_reg <= avmm_egrs_slv_wrdata[0]; mctp_msg_len_reg <= avmm_egrs_slv_wrdata[14:6]; tlp_pad_len_reg <= avmm_egrs_slv_wrdata[5:4]; end else mctp_msg_rdy_reg <= 1'b0; - - if(avmm_egrs_slv_addr == EGRS_PH_REG_ADDR && avmm_egrs_slv_write && + + if(avmm_egrs_slv_addr == EGRS_PH_REG_ADDR && avmm_egrs_slv_write && egrs_state[EGRS_IDLE_BIT]) begin tlp_trgt_id_reg <= avmm_egrs_slv_wrdata[29] ? avmm_egrs_slv_wrdata[15:0] : 16'd0; mctp_dst_eid_reg <= avmm_egrs_slv_wrdata[23:16]; @@ -157,7 +157,7 @@ begin : xmtr_reg_wr mctp_src_eid_reg <= avmm_egrs_slv_wrdata[28] ? 8'h00 : pcievdm_mctp_eid; tlp_pcie_route_reg <= avmm_egrs_slv_wrdata[29] ? 3'd2 : 3'd0; end - end + end end : xmtr_reg_wr always_ff @(posedge clk, posedge reset) @@ -179,15 +179,15 @@ end : xmtr_reg_rd always_comb begin : egrs_bfr_wr egrs_bfr_wraddr = avmm_egrs_slv_addr[EGRS_BFR_AMSB-1:0]; - egrs_bfr_wrdata = avmm_egrs_slv_wrdata; - egrs_bfr_wren = egrs_state[EGRS_IDLE_BIT] & avmm_egrs_slv_write & - avmm_egrs_slv_addr[EGRS_BFR_AMSB]; + egrs_bfr_wrdata = avmm_egrs_slv_wrdata; + egrs_bfr_wren = egrs_state[EGRS_IDLE_BIT] & avmm_egrs_slv_write & + avmm_egrs_slv_addr[EGRS_BFR_AMSB]; end : egrs_bfr_wr //----------------------------------------------------------------------------- // Egress Buffer Instantiation //----------------------------------------------------------------------------- -altera_syncram egress_buffer +altera_syncram egress_buffer ( .clock0 (clk ), .address_a (egrs_bfr_wraddr ), @@ -244,7 +244,7 @@ defparam //----------------------------------------------------------------------------- // Egress PCIe VDM TLP FSM. -// This FSM reads the MCTP payload from egress buffer and constructs MCTP over +// This FSM reads the MCTP payload from egress buffer and constructs MCTP over // PCIe VDM TLP and then forwards it to AFU . // Top "always_ff" simply switches the state of the state machine registers. // Following "always_comb" contains all of the next-state decoding logic. @@ -269,40 +269,40 @@ begin : egrs_fsm_comb egrs_next = EGRS_RESET_ST; else egrs_next = EGRS_IDLE_ST; - - egrs_state[EGRS_IDLE_BIT]: //EGRS_IDLE_ST + + egrs_state[EGRS_IDLE_BIT]: //EGRS_IDLE_ST if(mctp_msg_rdy_reg) egrs_next = EGRS_AFU_RDY_ST; - + egrs_state[EGRS_AFU_RDY_BIT]: //EGRS_AFU_RDY_ST if(avmm_egrs_mstr_rddvld && !avmm_egrs_mstr_rddata[2]) egrs_next = EGRS_SOP_ST; - egrs_state[EGRS_SOP_BIT]: //EGRS_SOP_ST + egrs_state[EGRS_SOP_BIT]: //EGRS_SOP_ST if(avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq) egrs_next = EGRS_HDR_1_ST; - egrs_state[EGRS_HDR_1_BIT]: //EGRS_HDR_1_ST + egrs_state[EGRS_HDR_1_BIT]: //EGRS_HDR_1_ST if(avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq) egrs_next = EGRS_HDR_2_ST; - egrs_state[EGRS_HDR_2_BIT]: //EGRS_HDR_2_ST + egrs_state[EGRS_HDR_2_BIT]: //EGRS_HDR_2_ST if(avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq) egrs_next = EGRS_PLOAD_ST; - egrs_state[EGRS_PLOAD_BIT]: //EGRS_PLOAD_ST + egrs_state[EGRS_PLOAD_BIT]: //EGRS_PLOAD_ST if(pkt_rd_done && avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq) egrs_next = EGRS_EOP_ST; - egrs_state[EGRS_EOP_BIT]: //EGRS_EOP_ST + egrs_state[EGRS_EOP_BIT]: //EGRS_EOP_ST if(avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq) begin if(not_last_pkt) egrs_next = EGRS_WAIT_ST; //EGRS_AFU_RDY_ST; else egrs_next = EGRS_IDLE_ST; - end - - egrs_state[EGRS_WAIT_BIT]: //EGRS_WAIT_ST + end + + egrs_state[EGRS_WAIT_BIT]: //EGRS_WAIT_ST if(pulse_1us) egrs_next = EGRS_AFU_RDY_ST; @@ -344,20 +344,20 @@ begin : egrs_bfr_rd bufr_rd_vld1 <= 1'b1; else bufr_rd_vld1 <= 1'b0; - + if(egrs_state[EGRS_IDLE_BIT]) egrs_bfr_rdaddr <= 8'd0; - else if(egrs_state[EGRS_PLOAD_BIT] && !avmm_egrs_mstr_write && + else if(egrs_state[EGRS_PLOAD_BIT] && !avmm_egrs_mstr_write && !bufr_rd_vld2 && !bufr_rd_vld3 && !pkt_rd_done) egrs_bfr_rdaddr <= egrs_bfr_rdaddr + 8'd1; - + bufr_rd_vld2 <= bufr_rd_vld1; bufr_rd_vld3 <= bufr_rd_vld2; egrs_bfr_rddata_r1 <= egrs_bfr_rddata; - + if(!egrs_state[EGRS_PLOAD_BIT]) pkt_rd_done <= 1'b0; - else if(!avmm_egrs_mstr_write && !bufr_rd_vld1 && !bufr_rd_vld2 && + else if(!avmm_egrs_mstr_write && !bufr_rd_vld1 && !bufr_rd_vld2 && !bufr_rd_vld3 && tlp_payload_len == 'd1 || tlp_payload_len == 'd0) pkt_rd_done <= 1'b1; end @@ -382,7 +382,7 @@ begin : mctp_flgs not_last_pkt <= 1'b1; else not_last_pkt <= 1'b0; - + if(egrs_state[EGRS_IDLE_BIT]) mctp_pndng_len <= mctp_msg_len_reg; else if(egrs_state[EGRS_WAIT_BIT] && !egrs_state_r1[EGRS_WAIT_BIT]) @@ -399,17 +399,17 @@ begin : mctp_flgs tlp_pad_len <= 2'd0; else if(egrs_state[EGRS_SOP_BIT]) tlp_pad_len <= tlp_pad_len_reg; - + if(egrs_state[EGRS_IDLE_BIT]) mctp_pkt_som <= 1'b1; else if (egrs_state[EGRS_PLOAD_BIT]) mctp_pkt_som <= 1'b0; - + if(egrs_state[EGRS_HDR_1_BIT] && not_last_pkt) mctp_pkt_eom <= 1'b0; else if (egrs_state[EGRS_HDR_1_BIT]) mctp_pkt_eom <= 1'b1; - + if (egrs_state[EGRS_EOP_BIT] && avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq) mctp_pkt_seq <= mctp_pkt_seq + 1'b1; end @@ -422,7 +422,7 @@ end : mctp_flgs always_comb begin : egrs_tlp_hdr pcie_tlp_len = {{(10-TLP_LEN_WIDTH){1'b0}}, tlp_payload_len}; - + pcie_tlp_hdr_1 = {8'h7F, //Byte-7 2'd0, tlp_pad_len, 4'd0, //Byte-6 16'd0, //Byte-5 & 4 @@ -430,9 +430,9 @@ begin : egrs_tlp_hdr 3'd0, TLP_NO_SNOOP_ATTR, 2'd0, pcie_tlp_len[9:8], //Byte-2 8'd0, //Byte-1 5'h0E, tlp_pcie_route_reg}; //Byte-0 - - - + + + pcie_tlp_hdr_2 = {mctp_pkt_som, mctp_pkt_eom, mctp_pkt_seq, mctp_tag_reg, //Byte-7 mctp_src_eid_reg, //Byte-6 mctp_dst_eid_reg, //Byte-5 @@ -441,7 +441,7 @@ begin : egrs_tlp_hdr 8'h1A, //Byte-2 tlp_trgt_id_reg[7:0], //Byte-1 tlp_trgt_id_reg[15:8]}; //Byte-0 - + end : egrs_tlp_hdr always_ff @(posedge clk, posedge reset) @@ -458,39 +458,39 @@ begin : egrs_avmm_mstr dly_busy_rechk <= 1'b1; else if(pulse_1us) dly_busy_rechk <= 1'b0; - + if(egrs_state[EGRS_AFU_RDY_BIT] && !egrs_state_r1[EGRS_AFU_RDY_BIT] || egrs_state[EGRS_AFU_RDY_BIT] && dly_busy_rechk && pulse_1us) avmm_egrs_mstr_read <= 1'b1; else if(!avmm_egrs_mstr_waitreq) avmm_egrs_mstr_read <= 1'b0; - + if(egrs_state[EGRS_SOP_BIT] && !egrs_state_r1[EGRS_SOP_BIT] || - egrs_state[EGRS_HDR_1_BIT] && !egrs_state_r1[EGRS_HDR_1_BIT] || + egrs_state[EGRS_HDR_1_BIT] && !egrs_state_r1[EGRS_HDR_1_BIT] || egrs_state[EGRS_HDR_2_BIT] && !egrs_state_r1[EGRS_HDR_2_BIT] || - egrs_state[EGRS_PLOAD_BIT] && bufr_rd_vld3 || + egrs_state[EGRS_PLOAD_BIT] && bufr_rd_vld3 || egrs_state[EGRS_EOP_BIT] && !egrs_state_r1[EGRS_EOP_BIT]) avmm_egrs_mstr_write <= 1'b1; else if(!avmm_egrs_mstr_waitreq) avmm_egrs_mstr_write <= 1'b0; - - if(egrs_state[EGRS_HDR_1_BIT] || egrs_state[EGRS_HDR_2_BIT] || + + if(egrs_state[EGRS_HDR_1_BIT] || egrs_state[EGRS_HDR_2_BIT] || egrs_state[EGRS_PLOAD_BIT]) avmm_egrs_mstr_addr <= {pcievdm_afu_addr[SS_ADDR_WIDTH-1:4], 4'd8}; - else + else avmm_egrs_mstr_addr <= {pcievdm_afu_addr[SS_ADDR_WIDTH-1:4], 4'd0}; - + if(egrs_state[EGRS_HDR_1_BIT]) avmm_egrs_mstr_wrdata <= pcie_tlp_hdr_1; else if(egrs_state[EGRS_HDR_2_BIT]) avmm_egrs_mstr_wrdata <= pcie_tlp_hdr_2; else if(egrs_state[EGRS_PLOAD_BIT] && bufr_rd_vld3) avmm_egrs_mstr_wrdata <= {egrs_bfr_rddata, egrs_bfr_rddata_r1}; - else if(!egrs_state[EGRS_PLOAD_BIT]) - avmm_egrs_mstr_wrdata <= {62'd0, - egrs_state[EGRS_EOP_BIT], + else if(!egrs_state[EGRS_PLOAD_BIT]) + avmm_egrs_mstr_wrdata <= {62'd0, + egrs_state[EGRS_EOP_BIT], egrs_state[EGRS_SOP_BIT]}; - + if(!egrs_state[EGRS_PLOAD_BIT]) avmm_egrs_mstr_byteen <= 8'hFF; else if(tlp_payload_len == 'd1 && bufr_rd_vld1) @@ -502,13 +502,13 @@ end : egrs_avmm_mstr //----------------------------------------------------------------------------- // Debug registers //----------------------------------------------------------------------------- -generate +generate if (DEBUG_REG_EN == 1) begin logic [DEBUG_REG_WIDTH-2:0] msg_rx_cntr_dbg_i ; logic msg_rx_of_dbg_i ; logic [DEBUG_REG_WIDTH-2:0] tlp_tx_cntr_dbg_i ; logic tlp_tx_of_dbg_i ; - + always_ff @(posedge clk, posedge reset) begin : dbg_reg if (reset) begin @@ -520,24 +520,24 @@ if (DEBUG_REG_EN == 1) begin //Total number of MCTP messages received if(mctp_msg_rdy_reg) msg_rx_cntr_dbg_i <= msg_rx_cntr_dbg_i + 1'b1; - + if(mctp_msg_rdy_reg && (&msg_rx_cntr_dbg_i)) msg_rx_of_dbg_i <= 1'b1; - + //Total number of TLPs transmitted - if(egrs_state[EGRS_EOP_BIT] && + if(egrs_state[EGRS_EOP_BIT] && avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq) tlp_tx_cntr_dbg_i <= tlp_tx_cntr_dbg_i + 1'b1; - - if(egrs_state[EGRS_EOP_BIT] && avmm_egrs_mstr_write && + + if(egrs_state[EGRS_EOP_BIT] && avmm_egrs_mstr_write && !avmm_egrs_mstr_waitreq && (&tlp_tx_cntr_dbg_i)) tlp_tx_of_dbg_i <= 1'b1; end end : dbg_reg - + assign pcie_vdm_sts4_dbg = {55'd0, egrs_state}; //[8:0] - Egress FSM state - + //[63:32] - Reserved //[31:16] - Number of MCTP message received //[15:0] - Number of TLPs transmitted diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ingr.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ingr.sv index 943d86fce..aa6a733df 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ingr.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/mctp_pcievdm_ctrlr/mctp_pcievdm_ingr.sv @@ -4,7 +4,7 @@ // // Description //----------------------------------------------------------------------------- -// MCTP over PCIe VDM Ingress module is used to parse MCTP over PCIe VDM +// MCTP over PCIe VDM Ingress module is used to parse MCTP over PCIe VDM // TLPs and forward the MCTP payloads to MAX10’s MCTP over PCIe VDM buffer. //----------------------------------------------------------------------------- @@ -18,7 +18,7 @@ module mctp_pcievdm_ingr #( )( input logic clk, input logic reset, - + //CSR i/f input logic [7:0] pcievdm_mctp_eid, // input logic [7:0] pcievdm_mctp_mtu_wsize, @@ -27,7 +27,7 @@ module mctp_pcievdm_ingr #( output logic [63:0] pcie_vdm_sts2_dbg, output logic [63:0] pcie_vdm_sts3_dbg, input logic pulse_1us, - + //Ingress AVMM slave (connected to IOFS-shell/AFU) input logic [0:0] avmm_ingr_slv_addr, input logic avmm_ingr_slv_write, @@ -95,7 +95,7 @@ enum logic [5:0] { TX_CHK_BUSY_ST = 6'h1 << TX_CHK_BUSY_BIT, TX_WR_PLOAD_ST = 6'h1 << TX_WR_PLOAD_BIT, TX_WR_HDR_ST = 6'h1 << TX_WR_HDR_BIT , - TX_WR_CTRL_ST = 6'h1 << TX_WR_CTRL_BIT + TX_WR_CTRL_ST = 6'h1 << TX_WR_CTRL_BIT } tx_state, tx_next, tx_state_r1; logic ingr_pkt_wr8 ; @@ -181,19 +181,19 @@ begin : ingr_avmm flow_ctrl_eop <= 1'b0; ingr_pkt_wr8 <= 1'b0; ingr_pkt_wr4 <= 1'b0; - end - + end + ingr_pkt_wr8_r1 <= ingr_pkt_wr8 & rx_state[RX_PLOAD_BIT]; - + if(avmm_ingr_slv_write && !avmm_ingr_slv_waitreq && avmm_ingr_slv_addr) ingr_wrdata_r1 <= avmm_ingr_slv_wrdata; - + if (avmm_ingr_slv_read && !avmm_ingr_slv_waitreq) avmm_ingr_slv_rddvld <= 1'b1; else avmm_ingr_slv_rddvld <= 1'b0; - - if (avmm_ingr_slv_write && !avmm_ingr_slv_waitreq || + + if (avmm_ingr_slv_write && !avmm_ingr_slv_waitreq || rx_state[RX_PLOAD_BIT] && tlp_payload_len[TLP_LEN_WIDTH-1:2] == 'd0 && // (ingr_pkt_wr4 || ingr_pkt_wr8 || ingr_pkt_wr8_r1)) (ingr_pkt_wr4 || ingr_pkt_wr8)) @@ -244,32 +244,32 @@ begin : rx_fsm_comb rx_next = RX_RESET_ST; else rx_next = RX_IDLE_ST; - + rx_state[RX_IDLE_BIT]: //RX_IDLE_ST if (flow_ctrl_sop && ingr_bfr_wrpage == ingr_bfr_rdpage) rx_next = RX_HDR_1_ST; - + rx_state[RX_HDR_1_BIT]: //RX_HDR_1_ST - if(ingr_bfr_wrpage != ingr_bfr_rdpage || ingr_pkt_wr8 && + if(ingr_bfr_wrpage != ingr_bfr_rdpage || ingr_pkt_wr8 && (!tlp_hdr1_match1 || !tlp_hdr1_match2 || !tlp_hdr1_match3 || !tlp_hdr1_len_ok)) rx_next = RX_IDLE_ST; else if(ingr_pkt_wr8) rx_next = RX_HDR_2_ST; - + rx_state[RX_HDR_2_BIT]: //RX_HDR_2_ST if (flow_ctrl_sop) rx_next = RX_HDR_1_ST; else if(ingr_pkt_wr8 && !tlp_hdr2_vndrid_match) rx_next = RX_IDLE_ST; - else if(ingr_pkt_wr8) begin - if(mctp_hdr_match && dest_eid_match && - !pkt_flag_seq_mis && !multipkt_deid_mis && !multipkt_seid_mis && + else if(ingr_pkt_wr8) begin + if(mctp_hdr_match && dest_eid_match && + !pkt_flag_seq_mis && !multipkt_deid_mis && !multipkt_seid_mis && !multipkt_tag_mis && !multipkt_len_mis) rx_next = RX_PLOAD_ST; else rx_next = RX_DISCARD_ST; end - + rx_state[RX_PLOAD_BIT]: //RX_PLOAD_ST if (flow_ctrl_sop) rx_next = RX_HDR_1_ST; @@ -277,7 +277,7 @@ begin : rx_fsm_comb rx_next = RX_DISCARD_ST; else if (tlp_payload_len == 'd0 || tlp_payload_len == 'd1 && ingr_pkt_wr4) rx_next = RX_EOP_ST; - + rx_state[RX_EOP_BIT]: //RX_EOP_ST if (flow_ctrl_sop) rx_next = RX_HDR_1_ST; @@ -285,11 +285,11 @@ begin : rx_fsm_comb rx_next = RX_IDLE_ST; else if(ingr_pkt_wr8 || ingr_pkt_wr4) rx_next = RX_DISCARD_ST; - + rx_state[RX_DISCARD_BIT]: //RX_DISCARD_ST if (flow_ctrl_sop) rx_next = RX_HDR_1_ST; - else + else rx_next = RX_IDLE_ST; endcase end : rx_fsm_comb @@ -316,35 +316,35 @@ begin : tlp_hdr_parse (avmm_ingr_slv_wrdata[2:0] == 3'b010 || //Type[2:0] == 3'b010 (Route by ID) // avmm_ingr_slv_wrdata[2:0] == 3'b000 || //Type[2:0] == 3'b000 (route to RC) avmm_ingr_slv_wrdata[2:0] == 3'b011) && //Type[2:0] == 3'b011 (Broadcast from RC) - avmm_ingr_slv_wrdata[15:14] == 2'b0) //R/T9 == 1'b0 && TC[2] == 1'b0 + avmm_ingr_slv_wrdata[15:14] == 2'b0) //R/T9 == 1'b0 && TC[2] == 1'b0 tlp_hdr1_match1 <= 1'b1; else tlp_hdr1_match1 <= 1'b0; - - if(avmm_ingr_slv_wrdata[13:8] == 6'h00 && //TC[1:0] == 2'b00 && T8/Attr/LN/TH == 4'h0 + + if(avmm_ingr_slv_wrdata[13:8] == 6'h00 && //TC[1:0] == 2'b00 && T8/Attr/LN/TH == 4'h0 //avmm_ingr_slv_wrdata[23] can be anything avmm_ingr_slv_wrdata[22] == 1'b0 && //EP == 1'b0 (avmm_ingr_slv_wrdata[21:20] == 2'b00 || //Attr == 2'b00 or 2'b01 avmm_ingr_slv_wrdata[21:20] == 2'b01) && //Attr == 2'b00 or 2'b01 avmm_ingr_slv_wrdata[19:18] == 2'b00) //R/AT == 2'b00 tlp_hdr1_match2 <= 1'b1; - else + else tlp_hdr1_match2 <= 1'b0; - + if(avmm_ingr_slv_wrdata[51:48] == 4'h0 && //MCTP VDM code == 4'h0 avmm_ingr_slv_wrdata[63:56] == 8'h7F) //Message Code Vendor Defined == 8'h7F tlp_hdr1_match3 <= 1'b1; - else + else tlp_hdr1_match3 <= 1'b0; - + //Length should be a non-zero value which is less than or equal to Baseline MTU size if(avmm_ingr_slv_wrdata[17:16] == 2'h0 && - avmm_ingr_slv_wrdata[31:24] != 8'h0 && + avmm_ingr_slv_wrdata[31:24] != 8'h0 && avmm_ingr_slv_wrdata[31:24] <= MCTP_BASELINE_MTU) tlp_hdr1_len_ok <= 1'b1; - else + else tlp_hdr1_len_ok <= 1'b0; - + if(avmm_ingr_slv_wrdata[23:16] == 8'h1A && avmm_ingr_slv_wrdata[31:24] == 8'hB4) //Vendor ID == 16'h1AB4(DMTF) tlp_hdr2_vndrid_match <= 1'b1; else @@ -358,7 +358,7 @@ begin : tlp_hdr_parse tlp_routing <= ~ingr_wrdata_r1[0]; end else if(rx_state[RX_PLOAD_BIT] && ingr_pkt_wr8) tlp_payload_len <= tlp_payload_len - 2'd2; - + end end : tlp_hdr_parse @@ -388,28 +388,28 @@ begin : mctp_hdr_parse if(//avmm_ingr_slv_wrdata[31:28] == 4'h0 && //MCTP header reserved avmm_ingr_slv_wrdata[35:32] == MCTP_HDR_VERSION) //MCTP header version mctp_hdr_match <= 1'b1; - else + else mctp_hdr_match <= 1'b0; - + if(avmm_ingr_slv_wrdata[47:40] == pcievdm_mctp_eid || //Our EID avmm_ingr_slv_wrdata[47:40] == 8'h00 || //Null EID avmm_ingr_slv_wrdata[47:40] == 8'hFF) //Broadcast EID dest_eid_match <= 1'b1; - else + else dest_eid_match <= 1'b0; - + //Latch multipacket flag if SOM = 1 & EOM = 0; deassert when EOM = 1 if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && ingr_wrdata_r1[62]) multipkt_prgrs <= 1'b0; else if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && ingr_wrdata_r1[63]) multipkt_prgrs <= 1'b1; - + //Multipacket message dropped indication if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && ingr_wrdata_r1[63]) // || !multipkt_prgrs) multipkt_drop <= 1'b0; else if(multipkt_prgrs && rx_state[RX_DISCARD_BIT]) multipkt_drop <= 1'b1; - + //Latch MCTP header parameters for first packet of multipacket if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && ingr_wrdata_r1[63]) begin multipkt_deid <= ingr_wrdata_r1[47:40]; @@ -417,25 +417,25 @@ begin : mctp_hdr_parse multipkt_tag <= ingr_wrdata_r1[59:56]; multipkt_len <= tlp_payload_len; end - + //Multipacket Dest EID miss for middle and last packets if(!avmm_ingr_slv_wrdata[63] && multipkt_deid != avmm_ingr_slv_wrdata[47:40]) multipkt_deid_mis <= 1'b1; - else + else multipkt_deid_mis <= 1'b0; - - //Multipacket Source EID miss for middle and last packets + + //Multipacket Source EID miss for middle and last packets if(!avmm_ingr_slv_wrdata[63] && multipkt_seid != avmm_ingr_slv_wrdata[55:48]) multipkt_seid_mis <= 1'b1; else multipkt_seid_mis <= 1'b0; - + //Multipacket Tag miss for middle and last packets if(!avmm_ingr_slv_wrdata[63] && multipkt_tag != avmm_ingr_slv_wrdata[59:56]) multipkt_tag_mis <= 1'b1; else multipkt_tag_mis <= 1'b0; - + //In multipacket sequence, middle pkt length should be same as that of first pkt //last pkt length should be less than or equal to first pkt length //middle packets should not have padding bytes (i.e. DWORD aligned) @@ -444,24 +444,24 @@ begin : mctp_hdr_parse avmm_ingr_slv_wrdata[62] && tlp_payload_len > multipkt_len || !avmm_ingr_slv_wrdata[62] && tlp_pad_len != 2'd0)) multipkt_len_mis <= 1'b1; - else + else multipkt_len_mis <= 1'b0; - + //Latch packet sequence and flags - if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && tlp_hdr2_vndrid_match) begin + if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && tlp_hdr2_vndrid_match) begin mctp_hdr_flag <= ingr_wrdata_r1[63:62]; - + if(ingr_wrdata_r1[63]) mctp_hdr_pkt_seq <= ingr_wrdata_r1[61:60] + 1'b1; else mctp_hdr_pkt_seq <= mctp_hdr_pkt_seq + 1'b1; end - + //Flag or packet sequence error when // 1) Unexpected middle/last packets when not in mutlipacket sequence // 2) Multipacket packet sequencer is not modulo 4 increment value // 3) Multipacket middle/last drop due to previous drops of packet in the same sequence - // if(rx_state[RX_HDR_2_BIT] && avmm_ingr_slv_write && + // if(rx_state[RX_HDR_2_BIT] && avmm_ingr_slv_write && if(!avmm_ingr_slv_wrdata[63] && (!multipkt_prgrs || multipkt_drop || multipkt_prgrs && mctp_hdr_pkt_seq != avmm_ingr_slv_wrdata[61:60])) pkt_flag_seq_mis <= 1'b1; @@ -494,7 +494,7 @@ begin : ingr_param_latch if(mctp_hdr_flag[0]) begin mctp_msg_msb_len <= ingr_bfr_wrofst; // - 1'b1; mctp_msg_lsb_len <= tlp_pad_len; - mctp_deid_latch <= (multipkt_deid == 8'h00) ? 2'd0 : + mctp_deid_latch <= (multipkt_deid == 8'h00) ? 2'd0 : (multipkt_deid == 8'hFF) ? 2'd1 : 2'd2; mctp_seid_latch <= multipkt_seid; mctp_tag_latch <= multipkt_tag; @@ -502,7 +502,7 @@ begin : ingr_param_latch mctp_multipkt <= (mctp_hdr_flag == 2'd1) ? 1'b1 : 1'b0; end end -end : ingr_param_latch +end : ingr_param_latch //----------------------------------------------------------------------------- @@ -520,20 +520,20 @@ begin : ingr_bfr_wr ingr_bfr_wrdata <= ingr_wrdata_r1[31:0]; else if(ingr_pkt_wr8_r1) ingr_bfr_wrdata <= ingr_wrdata_r1[63:32]; - + if(rx_state[RX_PLOAD_BIT] && (ingr_pkt_wr8 || ingr_pkt_wr4 || ingr_pkt_wr8_r1)) ingr_bfr_wren <= 1'b1; else ingr_bfr_wren <= 1'b0; - + //Reset buffer write offset for every packet with SOM=1 if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && ingr_wrdata_r1[63]) ingr_bfr_wrofst <= 9'd0; else if(ingr_bfr_wren) ingr_bfr_wrofst <= ingr_bfr_wrofst + 1'b1; - + //Flip page to indicate message receive successfull (once per pkt @ EOM=1) - if(rx_state[RX_EOP_BIT] && flow_ctrl_eop && mctp_hdr_flag[0] && + if(rx_state[RX_EOP_BIT] && flow_ctrl_eop && mctp_hdr_flag[0] && ingr_bfr_wrofst <= 9'd256) ingr_bfr_wrpage <= ~ingr_bfr_wrpage; end @@ -545,7 +545,7 @@ assign ingr_bfr_wraddr = ingr_bfr_wrofst[7:0]; //----------------------------------------------------------------------------- // Ingress Buffer Instantiation //----------------------------------------------------------------------------- -altera_syncram ingress_buffer +altera_syncram ingress_buffer ( .clock0 (clk ), .address_a (ingr_bfr_wraddr ), @@ -615,7 +615,7 @@ begin : tx_fsm_seq end else begin tx_state <= tx_next; tx_state_r1 <= tx_state; - end + end end : tx_fsm_seq always_comb @@ -627,27 +627,27 @@ begin : tx_fsm_comb tx_next = TX_RESET_ST; else tx_next = TX_IDLE_ST; - + tx_state[TX_IDLE_BIT]: //TX_IDLE_ST if(!afu_addr_rdy && pcievdm_afu_addr_vld) tx_next = TX_WR_CTRL_ST; else if (ingr_bfr_wrpage != ingr_bfr_rdpage) tx_next = TX_CHK_BUSY_ST; - + tx_state[TX_CHK_BUSY_BIT]: //TX_CHK_BUSY_ST if(avmm_ingr_mstr_rddvld && !avmm_ingr_mstr_rddata[4]) tx_next = TX_WR_PLOAD_ST; - + tx_state[TX_WR_PLOAD_BIT]: //TX_WR_PLOAD_ST // if(ingr_bfr_rdofst == ingr_bfr_last_ofst) // && !avmm_ingr_mstr_waitreq && avmm_ingr_mstr_write) if(ingr_bfr_rddone && !avmm_ingr_mstr_waitreq && avmm_ingr_mstr_write) tx_next = TX_WR_HDR_ST; - tx_state[TX_WR_HDR_BIT]: //TX_WR_HDR_ST + tx_state[TX_WR_HDR_BIT]: //TX_WR_HDR_ST if(!avmm_ingr_mstr_waitreq && avmm_ingr_mstr_write) tx_next = TX_WR_CTRL_ST; - tx_state[TX_WR_CTRL_BIT]: //TX_WR_CTRL_ST + tx_state[TX_WR_CTRL_BIT]: //TX_WR_CTRL_ST if(!avmm_ingr_mstr_waitreq && avmm_ingr_mstr_write) tx_next = TX_IDLE_ST; endcase @@ -670,33 +670,33 @@ begin : ingr_bfr_rd end else begin //ingr_bfr_last_ofst <= mctp_msg_msb_len - 1'b1; - //if(tx_state[TX_WR_PLOAD_BIT] && ingr_bfr_rdofst != ingr_bfr_last_ofst && + //if(tx_state[TX_WR_PLOAD_BIT] && ingr_bfr_rdofst != ingr_bfr_last_ofst && // !avmm_ingr_mstr_waitreq && avmm_ingr_mstr_write) // && !ingr_bfr_rddone) if(ingr_bfr_rdofst == (mctp_msg_msb_len - 1'b1)) ingr_bfr_rddone <= 1'b1; - else + else ingr_bfr_rddone <= 1'b0; - + if(!tx_state[TX_WR_PLOAD_BIT]) ingr_bfr_rdofst <= 9'd0; else if(!ingr_bfr_rddone && !avmm_ingr_mstr_waitreq && avmm_ingr_mstr_write) ingr_bfr_rdofst <= ingr_bfr_rdofst + 1'b1; - + if(!ingr_bfr_rddone & ~avmm_ingr_mstr_waitreq & avmm_ingr_mstr_write) ingr_bfr_rden <= 1'b1; else ingr_bfr_rden <= 1'b0; - + ingr_bfr_rden_r1 <= ingr_bfr_rden; - + //Flip page to indicate message read from ingress buffer - if(tx_state[TX_WR_CTRL_BIT] && mctp_pkt_avlbl && + if(tx_state[TX_WR_CTRL_BIT] && mctp_pkt_avlbl && !avmm_ingr_mstr_waitreq && avmm_ingr_mstr_write) ingr_bfr_rdpage <= ~ingr_bfr_rdpage; - + if(tx_state[TX_WR_PLOAD_BIT] && (!tx_state_r1[TX_WR_PLOAD_BIT] || ingr_bfr_rden_r1)) ingr_bfr_rdvld <= 1'b1; - else + else ingr_bfr_rdvld <= 1'b0; end end : ingr_bfr_rd @@ -719,57 +719,57 @@ begin : ingr_tx_avmm dly_busy_rechk_cntr <= {TX_BUSY_DLY_W{1'b0}}; mctp_pkt_avlbl <= 1'b0; end else begin - if(tx_state[TX_WR_PLOAD_BIT] && ingr_bfr_rdvld || + if(tx_state[TX_WR_PLOAD_BIT] && ingr_bfr_rdvld || tx_state[TX_WR_HDR_BIT] && !tx_state_r1[TX_WR_HDR_BIT] || tx_state[TX_WR_CTRL_BIT] && !tx_state_r1[TX_WR_CTRL_BIT]) avmm_ingr_mstr_write <= 1'b1; else if(!avmm_ingr_mstr_waitreq) avmm_ingr_mstr_write <= 1'b0; - + if(!tx_state[TX_CHK_BUSY_BIT] || avmm_ingr_mstr_read) dly_busy_rechk <= 1'b0; else if(avmm_ingr_mstr_rddvld && avmm_ingr_mstr_rddata[4]) dly_busy_rechk <= 1'b1; - + if(!dly_busy_rechk) dly_busy_rechk_cntr <= {TX_BUSY_DLY_W{1'b0}}; else if(pulse_1us) dly_busy_rechk_cntr <= dly_busy_rechk_cntr - 1'b1; - + if(tx_state[TX_CHK_BUSY_BIT] && !tx_state_r1[TX_CHK_BUSY_BIT] || //avmm_ingr_mstr_rddvld && !avmm_ingr_mstr_rddata[4]) //no delay dly_busy_rechk && dly_busy_rechk_cntr == 'd1 && pulse_1us) avmm_ingr_mstr_read <= 1'b1; else if(!avmm_ingr_mstr_waitreq) avmm_ingr_mstr_read <= 1'b0; - + if(tx_state[TX_WR_PLOAD_BIT]) avmm_ingr_mstr_addr <= M10_INGR_PKT_BFR_ADDR; else if(tx_state[TX_WR_HDR_BIT]) avmm_ingr_mstr_addr <= M10_INGR_PH_REG_ADDR; - else + else avmm_ingr_mstr_addr <= M10_INGR_CNS_REG_ADDR; - + if(tx_state[TX_WR_PLOAD_BIT]) avmm_ingr_mstr_burstcnt <= mctp_msg_msb_len; - else + else avmm_ingr_mstr_burstcnt <= 'd1; - + if(tx_state[TX_WR_HDR_BIT]) mctp_pkt_avlbl <= 1'b1; else if(!tx_state[TX_WR_CTRL_BIT]) mctp_pkt_avlbl <= 1'b0; - + if(tx_state[TX_WR_PLOAD_BIT]) avmm_ingr_mstr_wrdata <= ingr_bfr_rddata; else if(tx_state[TX_WR_HDR_BIT]) avmm_ingr_mstr_wrdata <= {mctp_deid_latch, //[31:30] Dest EID - tlp_routing_latch, //[29] PCIe TLP route + tlp_routing_latch, //[29] PCIe TLP route mctp_multipkt, //[28] Multipacket message mctp_tag_latch, //[27:24] {TO_bit, Message_tag} mctp_seid_latch, //[23:8] Source EID tlp_pci_req_id_latch};//[15:0] PCIe Req ID - else + else avmm_ingr_mstr_wrdata <= {12'd0, //[31:20] Reserved 1'd0, mctp_msg_msb_len, mctp_msg_lsb_len, //[19:8] Rx packet size 3'd0, //[7:3] Reserved @@ -784,7 +784,7 @@ end : ingr_tx_avmm //----------------------------------------------------------------------------- // Debug registers //----------------------------------------------------------------------------- -generate +generate if (DEBUG_REG_EN == 1) begin logic [DEBUG_REG_WIDTH-2:0] tlp_rcvd_cntr_dbg_i ; logic tlp_rcvd_of_dbg_i ; @@ -805,7 +805,7 @@ if (DEBUG_REG_EN == 1) begin logic ingr_bfr_rdpage_r1 ; logic [DEBUG_REG_WIDTH-2:0] vld_msg_tx_cntr_dbg_i ; logic vld_msg_tx_of_dbg_i ; - + always_ff @(posedge clk, posedge reset) begin : dbg_reg if (reset) begin @@ -832,61 +832,61 @@ if (DEBUG_REG_EN == 1) begin //Total number of VDM TLP's received if(flow_ctrl_eop) tlp_rcvd_cntr_dbg_i <= tlp_rcvd_cntr_dbg_i + 1'b1; - + if(flow_ctrl_eop && (&tlp_rcvd_cntr_dbg_i)) tlp_rcvd_of_dbg_i <= 1'b1; - + //Total number of TLP's due to receiver (i.e. this module) busy - if(rx_state[RX_IDLE_BIT] && flow_ctrl_sop && + if(rx_state[RX_IDLE_BIT] && flow_ctrl_sop && ingr_bfr_wrpage != ingr_bfr_rdpage || rx_state[RX_HDR_1_BIT] && ingr_bfr_wrpage != ingr_bfr_rdpage) b2b_drop_dbg_i <= 1'b1; else b2b_drop_dbg_i <= 1'b0; - + if(b2b_drop_dbg_i) b2b_drop_cntr_dbg_i <= b2b_drop_cntr_dbg_i + 1'b1; - + if(b2b_drop_dbg_i && (&b2b_drop_cntr_dbg_i)) b2b_drop_of_dbg_i <= 1'b1; - + //Number of TLP's received with TLP header mismatch - if(rx_state[RX_HDR_1_BIT] && ingr_pkt_wr8 && (!tlp_hdr1_match1 || + if(rx_state[RX_HDR_1_BIT] && ingr_pkt_wr8 && (!tlp_hdr1_match1 || !tlp_hdr1_match2 || !tlp_hdr1_match3 || !tlp_hdr1_len_ok) || rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && !tlp_hdr2_vndrid_match) tlp_hdr_mis_dbg_i <= 1'b1; else tlp_hdr_mis_dbg_i <= 1'b0; - + if(tlp_hdr_mis_dbg_i) tlp_hdr_mis_cntr_dbg_i <= tlp_hdr_mis_cntr_dbg_i + 1'b1; - + if(tlp_hdr_mis_dbg_i && (&tlp_hdr_mis_cntr_dbg_i)) tlp_hdr_mis_of_dbg_i <= 1'b1; - - //Number of TLP's received with MCTP header version or Destination EID + + //Number of TLP's received with MCTP header version or Destination EID //or MCTP header flag/seq mismatch - if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && + if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && (!mctp_hdr_match || !dest_eid_match)) mctp_hdr_mis_cntr_dbg_i <= mctp_hdr_mis_cntr_dbg_i + 1'b1; - - if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && (&mctp_hdr_mis_cntr_dbg_i) && + + if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && (&mctp_hdr_mis_cntr_dbg_i) && (!mctp_hdr_match || !dest_eid_match)) mctp_hdr_mis_of_dbg_i <= 1'b1; - + //Number of TLP's received with multipacket error if(rx_state[RX_HDR_2_BIT] && ingr_pkt_wr8 && (pkt_flag_seq_mis || multipkt_deid_mis || multipkt_seid_mis || multipkt_tag_mis || multipkt_len_mis)) multipkt_mis_dbg_i <= 1'b1; - else + else multipkt_mis_dbg_i <= 1'b0; - + if(multipkt_mis_dbg_i) multipkt_mis_cntr_dbg_i <= multipkt_mis_cntr_dbg_i + 1'b1; if(multipkt_mis_dbg_i && (&multipkt_mis_cntr_dbg_i)) multipkt_mis_of_dbg_i <= 1'b1; - + //Number of valid MCTP messages received ingr_bfr_wrpage_r1 <= ingr_bfr_wrpage; if(ingr_bfr_wrpage != ingr_bfr_wrpage_r1) @@ -894,7 +894,7 @@ if (DEBUG_REG_EN == 1) begin if(ingr_bfr_wrpage != ingr_bfr_wrpage_r1 && (&vld_msg_rx_cntr_dbg_i)) vld_msg_rx_of_dbg_i <= 1'b1; - + //Number of valid MCTP messages received ingr_bfr_rdpage_r1 <= ingr_bfr_rdpage; if(ingr_bfr_rdpage_r1 != ingr_bfr_rdpage) @@ -904,22 +904,22 @@ if (DEBUG_REG_EN == 1) begin vld_msg_tx_of_dbg_i <= 1'b1; end end : dbg_reg - + assign pcie_vdm_sts1_dbg = {49'd0, ingr_bfr_rdpage, //[14] - Ingress read page tx_state, //[13:8] - Ingress transmitter FSM state ingr_bfr_wrpage, //[7] - Ingress write page rx_state}; //[6:0] - Ingress receiver FSM state - + //[63:48] - Total number of TLPs received counter //[47:32] - Back to back message drop counter //[31:16] - TLP header mismatch counter //[15:0] - MCTP header mismatch counter - assign pcie_vdm_sts2_dbg = {tlp_rcvd_of_dbg_i, {(16-DEBUG_REG_WIDTH){1'b0}}, tlp_rcvd_cntr_dbg_i, - b2b_drop_of_dbg_i, {(16-DEBUG_REG_WIDTH){1'b0}}, b2b_drop_cntr_dbg_i, - tlp_hdr_mis_of_dbg_i, {(16-DEBUG_REG_WIDTH){1'b0}}, tlp_hdr_mis_cntr_dbg_i, + assign pcie_vdm_sts2_dbg = {tlp_rcvd_of_dbg_i, {(16-DEBUG_REG_WIDTH){1'b0}}, tlp_rcvd_cntr_dbg_i, + b2b_drop_of_dbg_i, {(16-DEBUG_REG_WIDTH){1'b0}}, b2b_drop_cntr_dbg_i, + tlp_hdr_mis_of_dbg_i, {(16-DEBUG_REG_WIDTH){1'b0}}, tlp_hdr_mis_cntr_dbg_i, mctp_hdr_mis_of_dbg_i, {(16-DEBUG_REG_WIDTH){1'b0}}, mctp_hdr_mis_cntr_dbg_i}; - + //[63:48] - Reserved //[47:32] - Multipacket error counter //[31:16] - Valid MCTP messages received counter diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/ncsi_ctrlr/ncsi_ctrlr.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/ncsi_ctrlr/ncsi_ctrlr.sv index 95383c2c2..a7239bdcf 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/ncsi_ctrlr/ncsi_ctrlr.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/ncsi_ctrlr/ncsi_ctrlr.sv @@ -5,9 +5,9 @@ // Description //----------------------------------------------------------------------------- // NCSI controller controls the NCSI RBT interface. The NCSI control traffic -// received from host is forwarded to PMCI-Nios and pass through taffic to AFU's -// packet filter block. Similarly, the control traffic from PMCI-Nios and pass -// through traffic from AFU's packet filter is muxed and forwarded to host over +// received from host is forwarded to PMCI-Nios and pass through taffic to AFU's +// packet filter block. Similarly, the control traffic from PMCI-Nios and pass +// through traffic from AFU's packet filter is muxed and forwarded to host over // RBT interface. //----------------------------------------------------------------------------- @@ -32,4 +32,4 @@ assign ncsi_rxd = ncsi_txd; assign ncsi_crs_dv = ncsi_tx_en; assign ncsi_arb_out = ncsi_arb_in; -endmodule +endmodule diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pmci_csr/pmci_csr.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pmci_csr/pmci_csr.sv index 4abf2d6b6..fd31c0f0f 100644 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pmci_csr/pmci_csr.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pmci_csr/pmci_csr.sv @@ -16,11 +16,11 @@ module pmci_csr #( parameter PCIEVDM_AFU_ADDR = 21'h42000, parameter QSFPA_CTRL_ADDR = 21'h12000, parameter QSFPB_CTRL_ADDR = 21'h13000, - + parameter QSPI_BAUDRATE = 5'd2, //SPI Clock Baud-rate Register of flash controller - //Valid values 0x2 -> /4, 0x3 -> /6 & 0x4 -> /8, + //Valid values 0x2 -> /4, 0x3 -> /6 & 0x4 -> /8, parameter FLASH_MFC = 1'b0, //Flash device manufacturer 0 -> Micron, 1 -> Macronix - + parameter END_OF_LIST = 1'b0, //DFH End of List parameter NEXT_DFH_OFFSET = 24'h20000,//Next DFH Offset parameter FEAT_VER = 4'h1, //DFH Feature Revision @@ -38,7 +38,7 @@ module pmci_csr #( output logic [63:0] host_avmm_slv_rddata, output logic host_avmm_slv_rddvld, output logic host_avmm_slv_waitreq, - + //PMCI Nios AVMM slave input logic [2:0] pnios_avmm_slv_addr, input logic pnios_avmm_slv_write, @@ -47,7 +47,7 @@ module pmci_csr #( output logic [31:0] pnios_avmm_slv_rddata, output logic pnios_avmm_slv_rddvld, output logic pnios_avmm_slv_waitreq, - + //MAX10 Nios AVMM slave input logic [1:0] mnios_avmm_slv_addr, input logic mnios_avmm_slv_write, @@ -56,7 +56,7 @@ module pmci_csr #( output logic [31:0] mnios_avmm_slv_rddata, output logic mnios_avmm_slv_rddvld, output logic mnios_avmm_slv_waitreq, - + //Flash burst master interface output logic write_mode, output logic read_mode, @@ -75,17 +75,17 @@ module pmci_csr #( input logic [63:0] pcie_vdm_sts3_dbg, input logic [63:0] pcie_vdm_sts4_dbg, input logic [63:0] pcie_vdm_sts5_dbg, - + //PXeboot OptionROM module interface output logic pxeboot_rd_start, input logic [31:0] pxeboot_status, - + //SEU IP interface input logic seu_sys_error, input logic [63:0] seu_avst_sink_data, input logic seu_avst_sink_vld, output logic seu_avst_sink_rdy, - + //MAX10-PMCI extra pins (temporary assignment) input logic fpga_usr_100m, input logic fpga_m10_hb, @@ -97,7 +97,7 @@ module pmci_csr #( localparam PMCI_DBG_MODE = 0; localparam PMCI_RTL_VERSION = 16'h22; localparam PMCI_DFH_FTYPE = 4'h3; //DFH Feature Type -localparam PMCI_DFH_RSVD = 19'h0; //DFH Reserved +localparam PMCI_DFH_RSVD = 19'h0; //DFH Reserved localparam TIME_CNTR_1_VAL = 10'd998; //10us counter localparam TIME_CNTR_2_VAL = 10'd399; //4ms counter @@ -168,7 +168,7 @@ always_comb begin : ss_baddr_comb pcievdm_afu_addr = PCIEVDM_AFU_ADDR; pcievdm_afu_addr_vld = 1'b1; //if this is not OK then delay until DFH read detect - + pcie_ss_addr = PCIE_SS_ADDR; hssi_ss_addr = HSSI_SS_ADDR; qsfpa_ctrl_addr = QSFPA_CTRL_ADDR; @@ -191,7 +191,7 @@ begin : host_csr_wr read_mode <= host_avmm_slv_wrdata[1]; read_count <= host_avmm_slv_wrdata[16+:10]; end - + if (host_avmm_slv_addr == 5'h8 && host_avmm_slv_byteen[7:4] == 4'hF) flash_addr <= host_avmm_slv_wrdata[32+:FLASH_ADDR_WIDTH]; end @@ -205,7 +205,7 @@ begin : host_csr_comb pmci_dfh_reg[39:16] = NEXT_DFH_OFFSET; pmci_dfh_reg[15:12] = FEAT_VER; pmci_dfh_reg[11:0] = FEAT_ID; - + fbm_ctrl_sts_reg[0] = write_mode; fbm_ctrl_sts_reg[1] = read_mode; fbm_ctrl_sts_reg[2] = flash_busy; @@ -216,14 +216,14 @@ begin : host_csr_comb fbm_ctrl_sts_reg[31:26] = '0; fbm_ctrl_sts_reg[32+:FLASH_ADDR_WIDTH] = flash_addr; fbm_ctrl_sts_reg[63:32+FLASH_ADDR_WIDTH] = '0; - + pmci_error_reg[0] = m10_seu_err_sync; pmci_error_reg[1] = fpga_seu_error; pmci_error_reg[2] = m10_nios_stuck; pmci_error_reg[3] = pmci_nios_stuck; pmci_error_reg[4] = seu_sys_error; pmci_error_reg[63:5] = '0; - + end : host_csr_comb //----------------------------------------------------------------------------- @@ -236,10 +236,10 @@ begin : host_csr_rd_seq host_avmm_slv_rddata <= 64'd0; end else if (host_avmm_slv_read && !host_avmm_slv_waitreq) begin host_avmm_slv_rddvld <= 1'b1; - + case (host_avmm_slv_addr) 5'h0 : host_avmm_slv_rddata <= pmci_dfh_reg; - + 5'h8 : host_avmm_slv_rddata <= fbm_ctrl_sts_reg; 5'h9 : host_avmm_slv_rddata <= pmci_error_reg; 5'hA : host_avmm_slv_rddata <= {32'd0, pxeboot_status}; @@ -251,7 +251,7 @@ begin : host_csr_rd_seq 5'h1E : host_avmm_slv_rddata <= fbm_dbg_sts_reg; 5'h1F : host_avmm_slv_rddata <= {32'd0, pmci_fw_version, PMCI_RTL_VERSION}; default : host_avmm_slv_rddata <= 64'hBAADBEEF_DEADBEEF; - endcase + endcase end else begin host_avmm_slv_rddvld <= 1'b0; end @@ -272,13 +272,13 @@ begin : pnios_csr_wr end else if (pnios_avmm_slv_write && !pnios_avmm_slv_waitreq) begin if (pnios_avmm_slv_addr == 3'h0) pmci_fw_version <= pnios_avmm_slv_wrdata[31:16]; - + if (pnios_avmm_slv_addr == 3'h1) fpga_therm_shdn_i <= pnios_avmm_slv_wrdata[0]; - + if (pnios_avmm_slv_addr == 3'h2) pmci_nios_hb <= pnios_avmm_slv_wrdata[0]; - + if (pnios_avmm_slv_addr == 3'h3) pnios_flsh_cfg_done <= pnios_avmm_slv_wrdata[0]; end @@ -334,7 +334,7 @@ begin : mnios_csr_wr end else begin if (mnios_avmm_slv_write && !mnios_avmm_slv_waitreq && mnios_avmm_slv_addr == 2'h1) rsu_mode <= mnios_avmm_slv_wrdata[0]; - + if (mnios_avmm_slv_write && !mnios_avmm_slv_waitreq && mnios_avmm_slv_addr == 2'h2) pcievdm_mctp_eid <= mnios_avmm_slv_wrdata[7:0]; end @@ -387,14 +387,14 @@ begin : time_pulse_seq time_cntr_1 <= 10'd0; else time_cntr_1 <= time_cntr_1 + 1'b1; - + time_tick_1 <= (time_cntr_1 == TIME_CNTR_1_VAL) ? 1'b1 : 1'b0; if(time_tick_2) time_cntr_2 <= 10'd0; else if(time_tick_1) time_cntr_2 <= time_cntr_2 + 1'b1; - + time_tick_2 <= (time_tick_1 && time_cntr_2 == TIME_CNTR_2_VAL) ? 1'b1 : 1'b0; end end : time_pulse_seq @@ -412,12 +412,12 @@ begin : nios_hb_mon end else begin m10_nios_hb_r1 <= m10_nios_hb; pmci_nios_hb_r1 <= pmci_nios_hb; - + if(m10_nios_hb_r1 != m10_nios_hb) m10_nhb_timer <= {(M10_NHB_TO_BIT+1){1'b0}}; else if(time_tick_2 && !m10_nios_stuck) m10_nhb_timer <= m10_nhb_timer + 1'b1; - + if(pmci_nios_hb_r1 != pmci_nios_hb) pmci_nhb_timer <= {(PMCI_NHB_TO_BIT+1){1'b0}}; else if(time_tick_2 && !pmci_nios_stuck) @@ -431,7 +431,7 @@ assign pmci_nios_stuck = pmci_nhb_timer[PMCI_NHB_TO_BIT]; //----------------------------------------------------------------------------- // PXEBoot Option ROM start reading flash indication. -// Start PXEboot Option ROM flash reading after flash controller is initialized +// Start PXEboot Option ROM flash reading after flash controller is initialized // and after 10us after PMCI is out of reset. //----------------------------------------------------------------------------- always_ff @(posedge clk, posedge reset) @@ -460,21 +460,21 @@ begin : dbg_flsh_wr_time flsh_wr_mode <= 1'b1; else if(!flash_busy) flsh_wr_mode <= 1'b0; - + if ((write_mode || rsu_mode) && !flsh_wr_mode) rst_time_cntr <= 1'b1; else rst_time_cntr <= 1'b0; - + if (rst_time_cntr) dbg_flsh_wr_tmr1 <= 10'd0; else if(flsh_wr_mode && time_tick_2) dbg_flsh_wr_tmr1 <= dbg_flsh_wr_tmr1 + 1'b1; - - if(!rst_time_cntr && flsh_wr_mode && time_tick_2 && + + if(!rst_time_cntr && flsh_wr_mode && time_tick_2 && dbg_flsh_wr_tmr1 == 10'h3FF) incr_time_cntr2 <= 1'b1; - else + else incr_time_cntr2 <= 1'b0; if (rst_time_cntr) @@ -496,4 +496,4 @@ begin fbm_dbg_sts_reg[63:24] = '0; end -endmodule +endmodule diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pxeboot_optrom/pxeboot_optrom.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pxeboot_optrom/pxeboot_optrom.sv index 2c4c9c26c..a0f757e5d 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pxeboot_optrom/pxeboot_optrom.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/pxeboot_optrom/pxeboot_optrom.sv @@ -5,8 +5,8 @@ // Description //----------------------------------------------------------------------------- // This module acts as a OptionROM of the PXEboot flow. -// This module reads the OptionROM contents from FPGA flash on every -// configuration and stores it in the internal buffer. Host BIOS will read +// This module reads the OptionROM contents from FPGA flash on every +// configuration and stores it in the internal buffer. Host BIOS will read // this buffer for OptionROM contents. //----------------------------------------------------------------------------- @@ -29,7 +29,7 @@ module pxeboot_optrom #( output logic [63:0] avmm_slv_rddata, output logic avmm_slv_rddvld, output logic avmm_slv_waitreq, - + //AVMM master to flash output logic [FLASH_ADDR_WIDTH-1:0] avmm_mstr_addr, output logic avmm_mstr_read, @@ -48,7 +48,7 @@ localparam DIS_OPTROM = "YES"; //Disable PXEboot OROM logic & buffer = YES //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ // PXEboot OptionROM Enabled //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -generate +generate if (DIS_OPTROM == "NO") begin //------------------------------------------------------------------------------ // Internal Declarations @@ -59,7 +59,7 @@ enum { OPTROM_RD_REQ_BIT = 2, OPTROM_RD_DATA_BIT = 3, OPTROM_RD_DONE_BIT = 4 - + } optrom_state_bit; enum logic [4:0] { @@ -80,7 +80,7 @@ logic orom_rden_r2; //------------------------------------------------------------------------------ -// Option ROM copying FSM +// Option ROM copying FSM // Top "always_ff" simply switches the state of the state machine registers. // Following "always_comb" contains all of the next-state decoding logic. //------------------------------------------------------------------------------ @@ -101,7 +101,7 @@ begin : optrom_sm_comb optrom_next = OPTROM_RESET_ST; else optrom_next = OPTROM_READY_ST; - + optrom_state[OPTROM_READY_BIT]: //OPTROM_READY_ST if(pxeboot_rd_start) optrom_next = OPTROM_RD_REQ_ST; @@ -111,11 +111,11 @@ begin : optrom_sm_comb optrom_next = OPTROM_RD_DONE_ST; else optrom_next = OPTROM_RD_DATA_ST; - + optrom_state[OPTROM_RD_DATA_BIT]: //OPTROM_RD_DATA_ST if(flsh_rd_offset[7:2] == 6'd63 && avmm_mstr_rddvld) optrom_next = OPTROM_RD_REQ_ST; - + optrom_state[OPTROM_RD_DONE_BIT]: //OPTROM_RD_DONE_ST optrom_next = OPTROM_RD_DONE_ST; endcase @@ -136,20 +136,20 @@ begin : fsm_ctrl_seq flsh_rd_offset <= OPTROM_AREA_BADDR; else if (optrom_state[OPTROM_RD_DATA_BIT] && avmm_mstr_rddvld) flsh_rd_offset <= flsh_rd_offset + 3'd4; - + if(optrom_state[OPTROM_RD_REQ_BIT] && !rd_complete) avmm_mstr_read <= 1'b1; - else if(!avmm_mstr_waitreq) + else if(!avmm_mstr_waitreq) avmm_mstr_read <= 1'b0; - - if(optrom_state[OPTROM_RD_DATA_BIT] && avmm_mstr_rddvld && + + if(optrom_state[OPTROM_RD_DATA_BIT] && avmm_mstr_rddvld && (flsh_rd_offset[OPTROM_AWID+1:2] == OPTROM_DW_SIZE-1)) rd_complete <= 1'b1; end end : fsm_ctrl_seq always_comb -begin : fsm_ctrl_comb +begin : fsm_ctrl_comb //avmm_mstr_addr = OPTROM_AREA_BADDR; avmm_mstr_addr[FLASH_ADDR_WIDTH-1:OPTROM_AWID+2] = OPTROM_AREA_BADDR >> (OPTROM_AWID+2); avmm_mstr_addr[OPTROM_AWID+1:0] = flsh_rd_offset; @@ -216,7 +216,7 @@ defparam //------------------------------------------------------------------------------ // HOst OptionROM reading //------------------------------------------------------------------------------ -assign orom_addr_range = (HOST_RDADDR_WIDTH == OPTROM_AWID+2) ? 1'b1 : +assign orom_addr_range = (HOST_RDADDR_WIDTH == OPTROM_AWID+2) ? 1'b1 : ~(|avmm_slv_addr[HOST_RDADDR_WIDTH-4:OPTROM_AWID-1]); always_ff @(posedge clk, posedge reset) @@ -231,14 +231,14 @@ begin : host_rd orom_rden_r1 <= 1'b1; else orom_rden_r1 <= 1'b0; - + orom_rden_r2 <= orom_rden_r1; - + if(!orom_addr_range && avmm_slv_read || orom_rden_r2) avmm_slv_rddvld <= 1'b1; else avmm_slv_rddvld <= 1'b0; - + if(orom_rden_r2) avmm_slv_rddata <= orom_rddata; else @@ -253,7 +253,7 @@ assign avmm_slv_waitreq = 1'b0; // PXEboot OptionROM status //------------------------------------------------------------------------------ always_comb -begin : orom_sts +begin : orom_sts pxeboot_status[31:16+OPTROM_AWID] = '0; pxeboot_status[16+:OPTROM_AWID] = flsh_rd_offset[OPTROM_AWID+1:2]; pxeboot_status[15:13] = '0; @@ -273,12 +273,12 @@ end else begin assign avmm_mstr_addr = '0; assign avmm_mstr_read = '0; assign avmm_mstr_burstcnt = '0; - + always_ff @(posedge clk, posedge reset) begin : host_rd if(reset) avmm_slv_rddvld <= 1'b0; - else + else avmm_slv_rddvld <= avmm_slv_read; end : host_rd end diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_bytes_to_packets.v b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_bytes_to_packets.v index 21e80968e..f5120a721 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_bytes_to_packets.v +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_bytes_to_packets.v @@ -7,10 +7,10 @@ `timescale 1ns / 100ps module altera_avalon_st_bytes_to_packets -//if ENCODING ==0, CHANNEL_WIDTH must be 8 +//if ENCODING ==0, CHANNEL_WIDTH must be 8 //else CHANNEL_WIDTH can be from 0 to 127 #( parameter CHANNEL_WIDTH = 8, - parameter ENCODING = 0 ) + parameter ENCODING = 0 ) ( // Interface: clk input clk, @@ -23,7 +23,7 @@ module altera_avalon_st_bytes_to_packets output reg out_startofpacket, output reg out_endofpacket, - // Interface: ST in + // Interface: ST in output reg in_ready, input in_valid, input [7: 0] in_data @@ -36,8 +36,8 @@ module altera_avalon_st_bytes_to_packets reg received_esc, received_channel, received_varchannel; wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char; - // data out mux. - // we need it twice (data & channel out), so use a wire here + // data out mux. + // we need it twice (data & channel out), so use a wire here wire [7:0] data_out; // --------------------------------------------------------------------- @@ -53,7 +53,7 @@ module altera_avalon_st_bytes_to_packets generate if (CHANNEL_WIDTH == 0) begin - // Synchorous block -- reset and registers + // Synchorous block -- reset and registers always @(posedge clk or negedge reset_n) begin if (!reset_n) begin received_esc <= 0; @@ -73,7 +73,7 @@ if (CHANNEL_WIDTH == 0) begin if (out_ready & out_valid) begin out_startofpacket <= 0; out_endofpacket <= 0; - end + end end end end @@ -93,12 +93,12 @@ if (CHANNEL_WIDTH == 0) begin out_valid = 1; if (sop_char | eop_char | escape_char | channel_char) out_valid = 0; end - out_data = data_out; + out_data = data_out; end end else begin assign varchannelesc_char = in_data[7]; - // Synchorous block -- reset and registers + // Synchorous block -- reset and registers always @(posedge clk or negedge reset_n) begin if (!reset_n) begin received_esc <= 0; @@ -128,7 +128,7 @@ end else begin if (out_ready & out_valid) begin out_startofpacket <= 0; out_endofpacket <= 0; - end + end end end end @@ -139,21 +139,21 @@ end else begin out_valid = 0; if ((out_ready | ~out_valid) && in_valid) begin out_valid = 1; - if (received_esc) begin + if (received_esc) begin if (received_channel | received_varchannel) out_valid = 0; end else begin if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0; end end - out_data = data_out; + out_data = data_out; end -end +end endgenerate // Channel block generate -if (CHANNEL_WIDTH == 0) begin +if (CHANNEL_WIDTH == 0) begin always @(posedge clk) begin out_channel <= 'h0; end @@ -174,7 +174,7 @@ end else if (CHANNEL_WIDTH < 8) begin end end -end else begin +end else begin always @(posedge clk or negedge reset_n) begin if (!reset_n) begin out_channel <= 'h0; @@ -193,7 +193,7 @@ end else begin end end end - + end endgenerate diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_packets_to_bytes.v b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_packets_to_bytes.v index 36eaf5989..984ff8fca 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_packets_to_bytes.v +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/altera_avalon_st_packets_to_bytes.v @@ -7,10 +7,10 @@ `timescale 1ns / 100ps module altera_avalon_st_packets_to_bytes -//if ENCODING ==0, CHANNEL_WIDTH must be 8 +//if ENCODING ==0, CHANNEL_WIDTH must be 8 //else CHANNEL_WIDTH can be from 0 to 127 #( parameter CHANNEL_WIDTH = 8, - parameter ENCODING = 0) + parameter ENCODING = 0) ( // Interface: clk input clk, @@ -126,16 +126,16 @@ if( CHANNEL_WIDTH > 0) begin end end else begin // Sending out MSB=0, last 7 bits of Channel - if (channel_needs_esc) begin - channel_needs_esc <= 0; + if (channel_needs_esc) begin + channel_needs_esc <= 0; out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20; end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]}; sent_channel <= 1; end end else begin - if (channel_needs_esc) begin - channel_needs_esc <= 0; - out_data <= in_channel ^ 8'h20; + if (channel_needs_esc) begin + channel_needs_esc <= 0; + out_data <= in_channel ^ 8'h20; end else out_data <= in_channel; sent_channel <= 1; end @@ -237,7 +237,7 @@ assign need_channel = (need_sop); end end end - + always @* begin in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc) & (~need_sop | sent_sop) diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/avmms_2_spim_bridge.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/avmms_2_spim_bridge.sv index e2111ca38..4693d6990 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/avmms_2_spim_bridge.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/custom_ip/spi_master/avmms_2_spim_bridge.sv @@ -6,11 +6,11 @@ //----------------------------------------------------------------------------- // This SPI master converts Avalon-MM to SPI transactions which are compatible // with 'SPI Slave to Avalon Master Bridge Core' from Quartus Platform Designer. -// This SPI master has two Avalon-MM slave interfaces through which it receives -// commands from the master. One of them implements a mailbox register for -// indirect access of CSR registers from SPI slave and other implements direct -// bridge between burst capable Avalon-MM to SPI. -// Host system can use this IP paired with 'SPI Slave to Avalon Master Bridge +// This SPI master has two Avalon-MM slave interfaces through which it receives +// commands from the master. One of them implements a mailbox register for +// indirect access of CSR registers from SPI slave and other implements direct +// bridge between burst capable Avalon-MM to SPI. +// Host system can use this IP paired with 'SPI Slave to Avalon Master Bridge // Core' to access slave's memory mapped registers. //----------------------------------------------------------------------------- @@ -38,7 +38,7 @@ module avmms_2_spim_bridge #( output logic [CSR_DATA_WIDTH-1:0] avmm_csr_rddata, output logic avmm_csr_rddvld, output logic avmm_csr_waitreq, - + input logic [DIR_ADDR_WIDTH-1:0] avmm_dir_addr, input logic avmm_dir_write, input logic avmm_dir_read, @@ -90,17 +90,17 @@ enum logic [9:0] { } spim_state, spim_next; logic [2:0] cmd_reg; -logic [SLV_CSR_AWIDTH-1:0] addr_reg; +logic [SLV_CSR_AWIDTH-1:0] addr_reg; logic [31:0] wrdata_reg; logic [31:0] rddata_reg; -logic [31:0] ctrl_reg; -logic [31:0] ctrl_reg_rd; -logic [31:0] sts0_reg_rd; -logic [31:0] sts1_reg_rd; -logic [31:0] sts2_reg_rd; -logic ack_trans; -logic first_beat; -logic read_latch; +logic [31:0] ctrl_reg; +logic [31:0] ctrl_reg_rd; +logic [31:0] sts0_reg_rd; +logic [31:0] sts1_reg_rd; +logic [31:0] sts2_reg_rd; +logic ack_trans; +logic first_beat; +logic read_latch; logic fifo_in_sop; logic fifo_in_eop; logic fifo_in_valid; @@ -181,7 +181,7 @@ function automatic logic[31:0] csr_reg_write ( end else begin if (reg_addr[0]) csr_reg_write = (csr_addr == reg_addr[2:1] && csr_ben[7:4] == 4'hF) ? csr_data[63:32]: reg_cur_data ; - else + else csr_reg_write = (csr_addr == reg_addr[2:1] && csr_ben[3:0] == 4'hF) ? csr_data[31:0] : reg_cur_data ; end return csr_reg_write; @@ -224,7 +224,7 @@ end : csr_wr generate if (SPI_DEBUG_EN == 1) begin - + always_ff @(posedge clk, posedge reset) begin : ctrl_reg_wr if(reset) begin @@ -236,18 +236,18 @@ begin ctrl_reg <= csr_reg_write(3'h4, ctrl_reg, avmm_csr_addr, avmm_csr_wrdata, avmm_csr_byteen); end end : ctrl_reg_wr - - always_comb + + always_comb begin : dbg_en_rd_comb ctrl_reg_rd = {16'd0, ctrl_reg[15:0]}; sts0_reg_rd = {6'd0, dbg_to_state, dbg_wrd_pndng, dbg_txn_error}; sts1_reg_rd = {8'd0, dbg_wrresp_pkt, 6'd0, spim_state}; sts2_reg_rd = dbg_wrresp; - end : dbg_en_rd_comb - + end : dbg_en_rd_comb + end else begin //SPI_DEBUG_EN == 0 - - always_comb + + always_comb begin : dbg_dis_rd_comb ctrl_reg[31:16] = 16'd0; ctrl_reg[15:8] = MISO_CAPT_DLY; @@ -256,8 +256,8 @@ end else begin //SPI_DEBUG_EN == 0 sts0_reg_rd = 32'hDEADBEEF; sts1_reg_rd = 32'hDEADBEEF; sts2_reg_rd = 32'hDEADBEEF; - end : dbg_dis_rd_comb - + end : dbg_dis_rd_comb + end endgenerate @@ -298,7 +298,7 @@ end else begin //CSR_DATA_WIDTH == 64 end else if (avmm_csr_read && !avmm_csr_waitreq) begin avmm_csr_rddvld <= 1'b1; case (avmm_csr_addr) - 2'h0 : avmm_csr_rddata <= {{{(32-SLV_CSR_AWIDTH){1'b0}}, addr_reg}, + 2'h0 : avmm_csr_rddata <= {{{(32-SLV_CSR_AWIDTH){1'b0}}, addr_reg}, spi_error, 28'd0 , cmd_reg}; 2'h1 : avmm_csr_rddata <= {wrdata_reg, rddata_reg}; 2'h2 : avmm_csr_rddata <= {sts0_reg_rd, ctrl_reg_rd}; @@ -338,30 +338,30 @@ begin : fifo_wr first_beat <= 1'b1; else if((avmm_dir_write || avmm_dir_read) && !avmm_dir_waitreq) first_beat <= 1'b0; - + fifo_in_sop <= first_beat; - + //use fifo_in_eop as write in progress indication - if((first_beat && avmm_dir_burstcnt == 'h1 || burst_beat == 2'h2) && + if((first_beat && avmm_dir_burstcnt == 'h1 || burst_beat == 2'h2) && !avmm_dir_waitreq && avmm_dir_write) fifo_in_eop <= 1'b1; else if(fifo_out_eop && fifo_out_valid && fifo_out_ready) fifo_in_eop <= 1'b0; - + //latch read for FSM capture if(!avmm_dir_waitreq && avmm_dir_read) read_latch <= 1'b1; else if(spim_state[SPIM_COMPLETE_BIT] && !csr_cmd && rd_cmd) read_latch <= 1'b0; - + fifo_in_valid <= ~avmm_dir_waitreq & avmm_dir_write; fifo_in_data <= avmm_dir_wrdata; - + if(first_beat && avmm_dir_write && !avmm_dir_waitreq) burst_beat <= avmm_dir_burstcnt; else if(!avmm_dir_waitreq && avmm_dir_write) burst_beat <= burst_beat - 1'b1; - + if(first_beat && !avmm_dir_waitreq) begin addr_latch <= avmm_dir_addr; brst_cnt_latch <= avmm_dir_burstcnt; @@ -401,7 +401,7 @@ spi_sc_fifo #( ); //------------------------------------------------------------------------------ -// SPI-Master packetizer FSM +// SPI-Master packetizer FSM // Top "always_ff" simply switches the state of the state machine registers. // Following "always_comb" contains all of the next-state decoding logic. //------------------------------------------------------------------------------ @@ -422,20 +422,20 @@ begin : spim_fsm_comb spim_next = SPIM_RESET_ST; else spim_next = SPIM_READY_ST; - + spim_state[SPIM_READY_BIT]: //SPIM_READY_ST if((!cmd_reg[2] && cmd_reg[1:0] != 2'd0) || fifo_in_eop || read_latch) spim_next = SPIM_START_ST; - + spim_state[SPIM_START_BIT]: //SPIM_START_ST spim_next = SPIM_CMD_ST; - + spim_state[SPIM_CMD_BIT]: //SPIM_CMD_ST if (time_out) spim_next = SPIM_COMPLETE_ST; else if(byte_cntr == 'h0) spim_next = SPIM_ADDR_ST; - + spim_state[SPIM_ADDR_BIT]: //SPIM_ADDR_ST if (time_out) spim_next = SPIM_COMPLETE_ST; @@ -443,7 +443,7 @@ begin : spim_fsm_comb spim_next = SPIM_RDDATA_ST; else if(byte_cntr == 'h0) spim_next = SPIM_WRDATA_ST; - + spim_state[SPIM_WRDATA_BIT]: //SPIM_WRDATA_ST if (time_out) spim_next = SPIM_COMPLETE_ST; @@ -451,7 +451,7 @@ begin : spim_fsm_comb spim_next = SPIM_WRRESP_ST; else if(byte_cntr[1:0] == 2'd1 && p2b_in_valid && p2b_in_ready) spim_next = SPIM_RDFIFO_ST; - + spim_state[SPIM_RDFIFO_BIT]: //SPIM_RDFIFO_ST spim_next = SPIM_WRDATA_ST; @@ -469,7 +469,7 @@ begin : spim_fsm_comb endcase end : spim_fsm_comb - + //------------------------------------------------------------------------------ // FSM control generation logic //------------------------------------------------------------------------------ @@ -491,8 +491,8 @@ begin : fsm_ctrl_seq csr_cmd <= (!cmd_reg[2] && cmd_reg[1:0] != 2'd0) ? 1'b1 : 1'b0; rd_cmd <= (~cmd_reg[2] & cmd_reg[0]) | ((cmd_reg[2] | ~cmd_reg[1]) & read_latch); end - - //Address and length of the write/read data + + //Address and length of the write/read data if(spim_state[SPIM_START_BIT]) begin cmd_mux[31:16] <= rd_cmd ? 16'h1400 : 16'h0400; cmd_mux[15:0] <= csr_cmd ? 16'h0004 : {{(14-DIR_BRST_WIDTH){1'b0}}, brst_cnt_latch, 2'd0}; @@ -505,36 +505,36 @@ begin : fsm_ctrl_seq cmd_mux[DIR_ADDR_WIDTH+1:0] <= {addr_latch, 2'd0}; end end - + if(!spim_state[SPIM_WRRESP_BIT] && !spim_state[SPIM_RDDATA_BIT]) resp_sop_rcvd <= 1'b0; else if(b2p_out_sop) resp_sop_rcvd <= 1'b1; - + if(tx_end_n || resp_sop_rcvd) resp_chk_cntr <= 2'd0; else if(b2p_out_valid) resp_chk_cntr <= resp_chk_cntr + 1'b1; - + if(!spim_state[SPIM_WRRESP_BIT] && !spim_state[SPIM_RDDATA_BIT]) no_response <= 1'b0; else if(resp_chk_cntr == 2'd3) no_response <= 1'b1; - - //Byte counter of the FSM - if(spim_state[SPIM_START_BIT] || + + //Byte counter of the FSM + if(spim_state[SPIM_START_BIT] || spim_state[SPIM_CMD_BIT] && byte_cntr == 'h0 || spim_state[SPIM_WRDATA_BIT] && p2b_in_valid && p2b_in_ready && byte_cntr == 'h1) byte_cntr <= 'h4; else if(spim_state[SPIM_ADDR_BIT] && byte_cntr == 'h0) byte_cntr <= size_mux; - else if(spim_state[SPIM_CMD_BIT] && p2b_in_ready || //&& p2b_in_valid - spim_state[SPIM_ADDR_BIT] && p2b_in_ready || //&& p2b_in_valid - spim_state[SPIM_WRDATA_BIT] && p2b_in_ready || //&& p2b_in_valid + else if(spim_state[SPIM_CMD_BIT] && p2b_in_ready || //&& p2b_in_valid + spim_state[SPIM_ADDR_BIT] && p2b_in_ready || //&& p2b_in_valid + spim_state[SPIM_WRDATA_BIT] && p2b_in_ready || //&& p2b_in_valid spim_state[SPIM_WRRESP_BIT] && resp_sop_rcvd && b2p_out_valid || spim_state[SPIM_RDDATA_BIT] && resp_sop_rcvd && b2p_out_valid) byte_cntr <= byte_cntr - 1'b1; - + //SPI transaction error (only for the Nios/Host interface i.e. for CSR based) if(spim_state[SPIM_START_BIT] && csr_cmd) spi_error <= 1'b0; @@ -561,30 +561,30 @@ begin : fsm_out_seq avmm_dir_rddata <= 32'd0; rddata_reg <= 32'd0; b2p_out_ready <= 1'b0; - avmm_dir_rddvld <= 1'b0; + avmm_dir_rddvld <= 1'b0; end else begin //Start of packet indication to P2B module if (spim_state[SPIM_START_BIT]) p2b_in_sop <= 1'b1; else if(p2b_in_ready) p2b_in_sop <= 1'b0; - + //End of packet indication to P2B module if(spim_state[SPIM_ADDR_BIT] && byte_cntr == 'h1 && rd_cmd || spim_state[SPIM_WRDATA_BIT] && byte_cntr == 'h1) p2b_in_eop <= 1'b1; else p2b_in_eop <= 1'b0; - + //Data valid indication to P2B module if(p2b_in_ready) p2b_in_valid <= 1'b0; - else if(spim_state[SPIM_CMD_BIT] || spim_state[SPIM_ADDR_BIT] || + else if(spim_state[SPIM_CMD_BIT] || spim_state[SPIM_ADDR_BIT] || spim_state[SPIM_WRDATA_BIT]) p2b_in_valid <= 1'b1; else p2b_in_valid <= 1'b0; - + //Data to P2B module if(spim_state[SPIM_CMD_BIT] || spim_state[SPIM_ADDR_BIT]) unique case (byte_cntr[1:0]) @@ -600,25 +600,25 @@ begin : fsm_out_seq 2'd2 : p2b_in_data <= csr_cmd ? wrdata_reg[2*8+:8] : fifo_out_data[2*8+:8]; 2'd1 : p2b_in_data <= csr_cmd ? wrdata_reg[3*8+:8] : fifo_out_data[3*8+:8]; endcase - + //Pop out data from FIFO //if(spim_state[SPIM_RDFIFO_BIT] || dbg_fifo_read) - if(spim_state[SPIM_WRDATA_BIT] && byte_cntr[1:0] == 2'd1 && !csr_cmd && + if(spim_state[SPIM_WRDATA_BIT] && byte_cntr[1:0] == 2'd1 && !csr_cmd && p2b_in_valid && p2b_in_ready || dbg_fifo_read) fifo_out_ready <= 1'b1; else fifo_out_ready <= 1'b0; - + //Ready indication to B2P module b2p_out_ready <= 1'b1; - + //Read response of direct AVMM slave if(spim_state[SPIM_RDDATA_BIT] && b2p_out_valid) begin avmm_dir_rddata <= {b2p_out_data, avmm_dir_rddata[31:8]}; avmm_dir_rddvld <= (!csr_cmd && byte_cntr[1:0] == 2'd1) ? 1'b1 : 1'b0; - end else + end else avmm_dir_rddvld <= 1'b0; - + //Read data register of CSR if (spim_state[SPIM_COMPLETE_BIT] && csr_cmd) begin rddata_reg <= avmm_dir_rddata; @@ -639,7 +639,7 @@ if (SPI_DEBUG_EN == 1) begin assign dbg_size_mux = {{(14-DIR_BRST_WIDTH){1'b0}}, size_mux}; - + always_ff @(posedge clk, posedge reset) begin : fsm_dbg_seq if(reset) begin @@ -661,7 +661,7 @@ begin to_cntr <= 8'd0; else if(clk_pedge) to_cntr <= to_cntr + 1'b1; - + if(to_cntr == DBG_WR_TIMEOUT) begin time_out <= 1'b1; dbg_to_state <= spim_state; @@ -671,13 +671,13 @@ begin to_cntr <= 8'd0; else if(clk_pedge) to_cntr <= to_cntr + 1'b1; - + if(to_cntr == DBG_RD_TIMEOUT) begin time_out <= 1'b1; dbg_to_state <= spim_state; end end - + //transaction error if(spim_state[SPIM_START_BIT]) begin dbg_txn_error <= 8'h0; @@ -716,7 +716,7 @@ begin dbg_txn_error[6] <= (byte_cntr == size_mux && !b2p_out_sop) ? 1'b1 : 1'b0; dbg_txn_error[7] <= (byte_cntr == 'h1 && !b2p_out_eop) ? 1'b1 : 1'b0; end - + //FIFO data pending error if(spim_state[SPIM_START_BIT]) dbg_wrd_pndng <= 8'h0; @@ -724,17 +724,17 @@ begin dbg_wrd_pndng <= dbg_wrd_pndng + 1'b1; end end : fsm_dbg_seq - + always_comb begin : fsm_dbg_comb dbg_fifo_read = spim_state[SPIM_COMPLETE_BIT] & fifo_out_valid & !fifo_out_sop; end : fsm_dbg_comb - + end else begin //SPI_DEBUG_EN == 0 assign time_out = 1'b0; assign dbg_fifo_read = 1'b0; - + end endgenerate @@ -744,7 +744,7 @@ endgenerate // 0x7A - Start of packet indication (byte following 0x7A will be first byte) // 0x7B - End of packet indication (byte following 0x7B will be last byte) // 0x7C - Channel selector (byte following 0x7C will be the channel number) -// 0x7D - Escape character +// 0x7D - Escape character //------------------------------------------------------------------------------ altera_avalon_st_packets_to_bytes #( .CHANNEL_WIDTH (8), @@ -760,11 +760,11 @@ altera_avalon_st_packets_to_bytes #( .in_endofpacket (p2b_in_eop ), .out_ready (p2b_out_ready ), .out_valid (p2b_out_valid ), - .out_data (p2b_out_data ) + .out_data (p2b_out_data ) ); //------------------------------------------------------------------------------ -// Bytes to packets IP to packetize the incoming byte stream. +// Bytes to packets IP to packetize the incoming byte stream. //------------------------------------------------------------------------------ altera_avalon_st_bytes_to_packets #( .CHANNEL_WIDTH (8), @@ -780,7 +780,7 @@ altera_avalon_st_bytes_to_packets #( .out_endofpacket (b2p_out_eop ), .in_ready (b2p_in_ready ), .in_valid (b2p_in_valid ), - .in_data (b2p_in_data ) + .in_data (b2p_in_data ) ); //------------------------------------------------------------------------------ @@ -812,13 +812,13 @@ begin : spi_ctrl_seq end else begin spim_clk <= spim_clk_r1; spim_csn <= 1'b0; - + if(clk_nedge[0]) first_sclk <= 1'b1; - + if(miso_cptr_nedge) //exclude first negedge miso_byte_en<= 1'b1; - + if(clk_cntr == 'd0) begin clk_cntr <= ctrl_reg[0+:CLK_DIV_WIDTH]; spim_clk_r1 <= ~spim_clk_r1; @@ -831,7 +831,7 @@ begin : spi_ctrl_seq end end end -end : spi_ctrl_seq +end : spi_ctrl_seq always_comb begin : spi_ctrl_comb @@ -885,7 +885,7 @@ begin : spi_mosi_seq tx_end_n <= 1'b0; end end - + //MOSI shifting if(clk_pedge) begin if(mosi_bit_cntr == 3'd7) @@ -901,7 +901,7 @@ end : spi_mosi_seq //------------------------------------------------------------------------------ // SPI master MISO decode logic // - 0x4A is used as IDLE character and is discarded -// - 0x4D is used as ESCAPE character and is also discarded and next +// - 0x4D is used as ESCAPE character and is also discarded and next // character is XORed with 0x20 //------------------------------------------------------------------------------ always_ff @(posedge clk, posedge reset) @@ -925,7 +925,7 @@ begin : spi_miso_seq miso_data_byte <= {miso_data_byte[6:0], spim_miso}; miso_bit_cntr <= miso_bit_cntr + 1'b1; end - + //SPI Rx/MISO data forwarding if(miso_bit_cntr == 3'd0 && miso_cptr_nedge && miso_byte_en) begin if(miso_data_byte == 8'h4A) begin @@ -948,7 +948,7 @@ begin : spi_miso_seq end end end -end : spi_miso_seq +end : spi_miso_seq //------------------------------------------------------------------------------ // SPI Tx/Rx disable logic. @@ -964,7 +964,7 @@ begin spi_pause_cntr <= spi_pause_cntr + 1'd1; end -always_comb +always_comb begin stop_spi = spim_state[SPIM_READY_BIT] | (~spi_pause_cntr[3] & ~tx_end_n); end diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/flash_burst_master_hw.tcl b/cards/silicom/n6010/src/comp/pmci/pmci_ip/flash_burst_master_hw.tcl index 78df4fc7d..0e6f90042 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/flash_burst_master_hw.tcl +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/flash_burst_master_hw.tcl @@ -1,7 +1,7 @@ # Copyright (C) 2020 Intel Corporation. # SPDX-License-Identifier: MIT -# +# # Description # ----------------------------------------------------------------------------- # This is the _hw.tcl of Flash Burst Master core @@ -183,7 +183,7 @@ add_interface_port avalon_master avmm_mstr_waitreq waitrequest Input 1 # ----------------------------------------------------------------------------- # Port - Avalon-MM slave (to IOFS-shell/host) -# ----------------------------------------------------------------------------- +# ----------------------------------------------------------------------------- add_interface avalon_slave avalon end set_interface_property avalon_slave addressGroup 0 set_interface_property avalon_slave addressUnits WORDS @@ -253,13 +253,13 @@ add_interface_port csr_if flash_addr flash_addr Input -1 # Validate IP # ----------------------------------------------------------------------------- proc ip_validate { } { - + set sa_baddr [ get_parameter_value STAGING_AREA_BADDR ] set fadr_width [ get_parameter_value FLASH_ADDR_WIDTH ] set fifo_depth [ get_parameter_value FIFO_DEPTH_LOG2 ] set addr_span [expr {pow(2, $fadr_width)}] - + if { $addr_span <= $sa_baddr } { send_message Error "Staging area base addres is out of bound of flash address range" } elseif {$sa_baddr < [expr {($addr_span * 3) / 4}]} { @@ -271,7 +271,7 @@ proc ip_validate { } { # Elaborate IP # ----------------------------------------------------------------------------- proc ip_elaborate { } { - + set sa_baddr [ get_parameter_value STAGING_AREA_BADDR ] set fadr_width [ get_parameter_value FLASH_ADDR_WIDTH ] set fifo_depth [ get_parameter_value FIFO_DEPTH_LOG2 ] diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/mctp_pcievdm_ctrlr_hw.tcl b/cards/silicom/n6010/src/comp/pmci/pmci_ip/mctp_pcievdm_ctrlr_hw.tcl index c1d527261..df9efd376 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/mctp_pcievdm_ctrlr_hw.tcl +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/mctp_pcievdm_ctrlr_hw.tcl @@ -1,7 +1,7 @@ # Copyright (C) 2020 Intel Corporation. # SPDX-License-Identifier: MIT -# +# # Description # ----------------------------------------------------------------------------- # This is the _hw.tcl of MCTP over PCIeVDM Controller @@ -351,7 +351,7 @@ add_interface_port csr_if pcie_vdm_sts5_dbg pcie_vdm_sts5_dbg Output 64 # Validate IP # ----------------------------------------------------------------------------- proc ip_validate { } { - + set ingrm_awidth [ get_parameter_value INGR_MSTR_ADDR_WIDTH ] set ingrm_bwidth [ get_parameter_value INGR_MSTR_BRST_WIDTH ] # set egrss_awidth [ get_parameter_value EGRS_SLV_ADDR_WIDTH ] @@ -359,7 +359,7 @@ proc ip_validate { } { set addr_span [expr {pow(2, $ingrm_awidth)}] set max_bcount [expr {2 * pow(2, $ingrm_bwidth)}] - + if { $max_bcount > $addr_span } { send_message Error "Addressable bytes are lesser than maximum burst length" send_message Info "Address width spans $addr_span bytes." @@ -371,12 +371,12 @@ proc ip_validate { } { # Elaborate IP # ----------------------------------------------------------------------------- proc ip_elaborate { } { - + set ingrm_awidth [ get_parameter_value INGR_MSTR_ADDR_WIDTH ] set ingrm_bwidth [ get_parameter_value INGR_MSTR_BRST_WIDTH ] set egrss_awidth [ get_parameter_value EGRS_SLV_ADDR_WIDTH ] set egrsm_awidth [ get_parameter_value SS_ADDR_WIDTH ] - + set_port_property avmm_ingr_mstr_addr width_expr $ingrm_awidth set_port_property avmm_ingr_mstr_burstcnt width_expr $ingrm_bwidth set_port_property avmm_egrs_slv_addr width_expr $egrss_awidth diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/ncsi_ctrlr_hw.tcl b/cards/silicom/n6010/src/comp/pmci/pmci_ip/ncsi_ctrlr_hw.tcl index 260cf452b..3b9c1c65e 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/ncsi_ctrlr_hw.tcl +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/ncsi_ctrlr_hw.tcl @@ -1,7 +1,7 @@ # Copyright (C) 2020 Intel Corporation. # SPDX-License-Identifier: MIT -# +# # Description # ----------------------------------------------------------------------------- # This is the _hw.tcl of NCSI Controller diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_csr_hw.tcl b/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_csr_hw.tcl index f3d7fd4ec..6e659758b 100644 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_csr_hw.tcl +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_csr_hw.tcl @@ -1,7 +1,7 @@ # Copyright (C) 2020 Intel Corporation. # SPDX-License-Identifier: MIT -# +# # Description # ----------------------------------------------------------------------------- # This is the _hw.tcl of PMCI CSR @@ -437,38 +437,38 @@ add_interface_port m10_if fpga_seu_error fpga_seu_error Output 1 # ----------------------------------------------------------------------------- # Port - SEU IP AvST Sink # ----------------------------------------------------------------------------- -add_interface seu_avst_sink avalon_streaming end -set_interface_property seu_avst_sink associatedClock clock -set_interface_property seu_avst_sink associatedReset reset -set_interface_property seu_avst_sink dataBitsPerSymbol 64 -set_interface_property seu_avst_sink errorDescriptor "" -set_interface_property seu_avst_sink firstSymbolInHighOrderBits true -set_interface_property seu_avst_sink maxChannel 0 -set_interface_property seu_avst_sink readyAllowance 0 -set_interface_property seu_avst_sink readyLatency 0 -set_interface_property seu_avst_sink ENABLED true -set_interface_property seu_avst_sink EXPORT_OF "" -set_interface_property seu_avst_sink PORT_NAME_MAP "" -set_interface_property seu_avst_sink CMSIS_SVD_VARIABLES "" -set_interface_property seu_avst_sink SVD_ADDRESS_GROUP "" -set_interface_property seu_avst_sink IPXACT_REGISTER_MAP_VARIABLES "" - -add_interface_port seu_avst_sink seu_avst_sink_data data Input 64 -add_interface_port seu_avst_sink seu_avst_sink_vld valid Input 1 -add_interface_port seu_avst_sink seu_avst_sink_rdy ready Output 1 +add_interface seu_avst_sink avalon_streaming end +set_interface_property seu_avst_sink associatedClock clock +set_interface_property seu_avst_sink associatedReset reset +set_interface_property seu_avst_sink dataBitsPerSymbol 64 +set_interface_property seu_avst_sink errorDescriptor "" +set_interface_property seu_avst_sink firstSymbolInHighOrderBits true +set_interface_property seu_avst_sink maxChannel 0 +set_interface_property seu_avst_sink readyAllowance 0 +set_interface_property seu_avst_sink readyLatency 0 +set_interface_property seu_avst_sink ENABLED true +set_interface_property seu_avst_sink EXPORT_OF "" +set_interface_property seu_avst_sink PORT_NAME_MAP "" +set_interface_property seu_avst_sink CMSIS_SVD_VARIABLES "" +set_interface_property seu_avst_sink SVD_ADDRESS_GROUP "" +set_interface_property seu_avst_sink IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port seu_avst_sink seu_avst_sink_data data Input 64 +add_interface_port seu_avst_sink seu_avst_sink_vld valid Input 1 +add_interface_port seu_avst_sink seu_avst_sink_rdy ready Output 1 # ----------------------------------------------------------------------------- # Port - SEU IP System Error (conduit) # ----------------------------------------------------------------------------- -add_interface seu_sys_err conduit end -set_interface_property seu_sys_err associatedClock clock -set_interface_property seu_sys_err associatedReset reset -set_interface_property seu_sys_err ENABLED true -set_interface_property seu_sys_err EXPORT_OF "" -set_interface_property seu_sys_err PORT_NAME_MAP "" -set_interface_property seu_sys_err CMSIS_SVD_VARIABLES "" -set_interface_property seu_sys_err SVD_ADDRESS_GROUP "" -set_interface_property seu_sys_err IPXACT_REGISTER_MAP_VARIABLES "" +add_interface seu_sys_err conduit end +set_interface_property seu_sys_err associatedClock clock +set_interface_property seu_sys_err associatedReset reset +set_interface_property seu_sys_err ENABLED true +set_interface_property seu_sys_err EXPORT_OF "" +set_interface_property seu_sys_err PORT_NAME_MAP "" +set_interface_property seu_sys_err CMSIS_SVD_VARIABLES "" +set_interface_property seu_sys_err SVD_ADDRESS_GROUP "" +set_interface_property seu_sys_err IPXACT_REGISTER_MAP_VARIABLES "" add_interface_port seu_sys_err seu_sys_error sys_error Input 1 @@ -476,7 +476,7 @@ add_interface_port seu_sys_err seu_sys_error sys_error Input 1 # Validate IP # ----------------------------------------------------------------------------- proc ip_validate { } { - + } @@ -484,11 +484,11 @@ proc ip_validate { } { # Elaborate IP # ----------------------------------------------------------------------------- proc ip_elaborate { } { - + set fadr_width [ get_parameter_value FLASH_ADDR_WIDTH ] set fbm_fdepth [ get_parameter_value FBM_FIFO_DEPTH ] set ssa_awidth [ get_parameter_value SS_ADDR_WIDTH ] - + set_port_property flash_addr width_expr $fadr_width set_port_property read_count width_expr [expr {$fbm_fdepth + 1}] set_port_property fifo_dcount width_expr [expr {$fbm_fdepth + 1}] diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_wrapper.sv b/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_wrapper.sv index 87bad52ae..3a7845c8b 100644 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_wrapper.sv +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/pmci_wrapper.sv @@ -1,4 +1,4 @@ - + // Copyright (C) 2020 Intel Corporation. // SPDX-License-Identifier: MIT @@ -29,37 +29,37 @@ module pmci_wrapper # ( )( // AXI clock and reset - input wire clk_csr, - input wire reset_csr, + input wire clk_csr, + input wire reset_csr, ofs_fim_axi_lite_if.slave csr_lite_slv_if, ofs_fim_axi_lite_if.master csr_lite_mst_if, - // AC FPGA - AC card BMC interface - output wire qspi_dclk, - output wire qspi_ncs, - inout wire [3:0] qspi_data, - input wire ncsi_rbt_ncsi_clk, - input wire [1:0] ncsi_rbt_ncsi_txd, - input wire ncsi_rbt_ncsi_tx_en, - output wire [1:0] ncsi_rbt_ncsi_rxd, - output wire ncsi_rbt_ncsi_crs_dv, - input wire ncsi_rbt_ncsi_arb_in, - output wire ncsi_rbt_ncsi_arb_out, - input wire m10_gpio_fpga_usr_100m, - input wire m10_gpio_fpga_m10_hb, - input wire m10_gpio_m10_seu_error, + // AC FPGA - AC card BMC interface + output wire qspi_dclk, + output wire qspi_ncs, + inout wire [3:0] qspi_data, + input wire ncsi_rbt_ncsi_clk, + input wire [1:0] ncsi_rbt_ncsi_txd, + input wire ncsi_rbt_ncsi_tx_en, + output wire [1:0] ncsi_rbt_ncsi_rxd, + output wire ncsi_rbt_ncsi_crs_dv, + input wire ncsi_rbt_ncsi_arb_in, + output wire ncsi_rbt_ncsi_arb_out, + input wire m10_gpio_fpga_usr_100m, + input wire m10_gpio_fpga_m10_hb, + input wire m10_gpio_m10_seu_error, output wire m10_gpio_fpga_therm_shdn, - output wire m10_gpio_fpga_seu_error, - output wire spi_ingress_sclk, - output wire spi_ingress_csn, - input wire spi_ingress_miso, - output wire spi_ingress_mosi, - input wire spi_egress_mosi, - input wire spi_egress_csn, - input wire spi_egress_sclk, - output wire spi_egress_miso + output wire m10_gpio_fpga_seu_error, + output wire spi_ingress_sclk, + output wire spi_ingress_csn, + input wire spi_ingress_miso, + output wire spi_ingress_mosi, + input wire spi_egress_mosi, + input wire spi_egress_csn, + input wire spi_egress_sclk, + output wire spi_egress_miso ); - + wire [2:0] slv_awsize; wire [2:0] slv_arsize; logic [7:0] axi_mstr_awid_sig; @@ -77,113 +77,112 @@ assign slv_arsize = ( csr_lite_slv_if.araddr[2] ) ? 3'b010 : // 4-byt // This arrangement will work as long as there is request vs response pair maintained. // This will not work when requests are send one after other from master before receiving the response always_ff @(posedge clk_csr) begin - if (reset_csr) + if (reset_csr) begin axi_mstr_bid_sig <= 8'b0; axi_mstr_rid_sig <= 8'b0; end - if (csr_lite_mst_if.awvalid && csr_lite_mst_if.awready) + if (csr_lite_mst_if.awvalid && csr_lite_mst_if.awready) begin axi_mstr_bid_sig <= axi_mstr_awid_sig; - end + end if (csr_lite_mst_if.arvalid && csr_lite_mst_if.arready) begin axi_mstr_rid_sig <= axi_mstr_arid_sig; end end - pmci_ss #( .pmci_csr_PCIE_SS_ADDR (pmci_csr_PCIE_SS_ADDR ), - .pmci_csr_HSSI_SS_ADDR (pmci_csr_HSSI_SS_ADDR ), - .pmci_csr_PCIEVDM_AFU_ADDR(pmci_csr_PCIEVDM_AFU_ADDR), - .pmci_csr_QSFPA_CTRL_ADDR (pmci_csr_QSFPA_CTRL_ADDR ), - .pmci_csr_QSFPB_CTRL_ADDR (pmci_csr_QSFPB_CTRL_ADDR ), - .pmci_csr_END_OF_LIST (pmci_csr_END_OF_LIST ), - .pmci_csr_NEXT_DFH_OFFSET (pmci_csr_NEXT_DFH_OFFSET ), - .pmci_csr_FEAT_VER (pmci_csr_FEAT_VER ), + pmci_ss #( .pmci_csr_PCIE_SS_ADDR (pmci_csr_PCIE_SS_ADDR ), + .pmci_csr_HSSI_SS_ADDR (pmci_csr_HSSI_SS_ADDR ), + .pmci_csr_PCIEVDM_AFU_ADDR(pmci_csr_PCIEVDM_AFU_ADDR), + .pmci_csr_QSFPA_CTRL_ADDR (pmci_csr_QSFPA_CTRL_ADDR ), + .pmci_csr_QSFPB_CTRL_ADDR (pmci_csr_QSFPB_CTRL_ADDR ), + .pmci_csr_END_OF_LIST (pmci_csr_END_OF_LIST ), + .pmci_csr_NEXT_DFH_OFFSET (pmci_csr_NEXT_DFH_OFFSET ), + .pmci_csr_FEAT_VER (pmci_csr_FEAT_VER ), .pmci_csr_FEAT_ID (pmci_csr_FEAT_ID ), - .pmci_csr_QSPI_BAUDRATE (5'd2), - .pmci_csr_FLASH_MFC (1'b0) + .pmci_csr_QSPI_BAUDRATE (5'd2), + .pmci_csr_FLASH_MFC (1'b0) ) pmci_ss ( - .axi_mstr_awid (axi_mstr_awid_sig ), - .axi_mstr_awaddr (csr_lite_mst_if.awaddr ), - .axi_mstr_awprot (csr_lite_mst_if.awprot[2:0] ), - .axi_mstr_awvalid (csr_lite_mst_if.awvalid ), - .axi_mstr_awready (csr_lite_mst_if.awready ), - .axi_mstr_wdata (csr_lite_mst_if.wdata ), - .axi_mstr_wstrb (csr_lite_mst_if.wstrb ), - .axi_mstr_wlast ( ), - .axi_mstr_wvalid (csr_lite_mst_if.wvalid ), - .axi_mstr_wready (csr_lite_mst_if.wready ), - .axi_mstr_bid (axi_mstr_bid_sig ), - .axi_mstr_bresp (csr_lite_mst_if.bresp ), - .axi_mstr_bvalid (csr_lite_mst_if.bvalid ), - .axi_mstr_bready (csr_lite_mst_if.bready ), - .axi_mstr_arid (axi_mstr_arid_sig ), - .axi_mstr_araddr (csr_lite_mst_if.araddr ), - .axi_mstr_arprot (csr_lite_mst_if.arprot ), - .axi_mstr_arvalid (csr_lite_mst_if.arvalid ), - .axi_mstr_arready (csr_lite_mst_if.arready ), - .axi_mstr_rid (axi_mstr_rid_sig ), - .axi_mstr_rdata (csr_lite_mst_if.rdata ), - .axi_mstr_rresp (csr_lite_mst_if.rresp ), - .axi_mstr_rvalid (csr_lite_mst_if.rvalid ), - .axi_mstr_rready (csr_lite_mst_if.rready ), - .axi_slave_awid (8'b0 ), - .axi_slave_awaddr (csr_lite_slv_if.awaddr ), - .axi_slave_awlen (8'b0 ), - .axi_slave_awsize (slv_awsize ), - .axi_slave_awburst (2'b0 ), - .axi_slave_awprot (csr_lite_slv_if.awprot ), - .axi_slave_awvalid (csr_lite_slv_if.awvalid ), - .axi_slave_awready (csr_lite_slv_if.awready ), - .axi_slave_wdata (csr_lite_slv_if.wdata ), - .axi_slave_wstrb (csr_lite_slv_if.wstrb ), - .axi_slave_wvalid (csr_lite_slv_if.wvalid ), - .axi_slave_wready (csr_lite_slv_if.wready ), - .axi_slave_bid ( ), - .axi_slave_bresp (csr_lite_slv_if.bresp ), - .axi_slave_bvalid (csr_lite_slv_if.bvalid ), - .axi_slave_bready (csr_lite_slv_if.bready ), - .axi_slave_arid (8'b0 ), - .axi_slave_araddr (csr_lite_slv_if.araddr ), - .axi_slave_arlen (8'b0 ), - .axi_slave_arsize (slv_arsize ), - .axi_slave_arburst (2'b0 ), - .axi_slave_arprot (csr_lite_slv_if.arprot ), - .axi_slave_arvalid (csr_lite_slv_if.arvalid ), - .axi_slave_arready (csr_lite_slv_if.arready ), - .axi_slave_rid ( ), - .axi_slave_rdata (csr_lite_slv_if.rdata ), - .axi_slave_rresp (csr_lite_slv_if.rresp ), - .axi_slave_rlast ( ), - .axi_slave_rvalid (csr_lite_slv_if.rvalid ), - .axi_slave_rready (csr_lite_slv_if.rready ), - .clk_clk (clk_csr ), - .qspi_dclk (qspi_dclk ), - .qspi_ncs (qspi_ncs ), - .qspi_data (qspi_data ), - .ncsi_rbt_ncsi_clk (ncsi_rbt_ncsi_clk ), - .ncsi_rbt_ncsi_txd (ncsi_rbt_ncsi_txd ), - .ncsi_rbt_ncsi_tx_en (ncsi_rbt_ncsi_tx_en ), - .ncsi_rbt_ncsi_rxd (ncsi_rbt_ncsi_rxd ), - .ncsi_rbt_ncsi_crs_dv (ncsi_rbt_ncsi_crs_dv ), - .ncsi_rbt_ncsi_arb_in (ncsi_rbt_ncsi_arb_in ), - .ncsi_rbt_ncsi_arb_out (ncsi_rbt_ncsi_arb_out ), - .m10_gpio_fpga_usr_100m (m10_gpio_fpga_usr_100m ), - .m10_gpio_fpga_m10_hb (m10_gpio_fpga_m10_hb ), - .m10_gpio_m10_seu_error (m10_gpio_m10_seu_error ), - .m10_gpio_fpga_therm_shdn (m10_gpio_fpga_therm_shdn ), - .m10_gpio_fpga_seu_error (m10_gpio_fpga_seu_error ), - .reset_reset (reset_csr ), - .spi_ingress_sclk (spi_ingress_sclk ), - .spi_ingress_csn (spi_ingress_csn ), - .spi_ingress_miso (spi_ingress_miso ), - .spi_ingress_mosi (spi_ingress_mosi ), + .axi_mstr_awid (axi_mstr_awid_sig ), + .axi_mstr_awaddr (csr_lite_mst_if.awaddr ), + .axi_mstr_awprot (csr_lite_mst_if.awprot[2:0] ), + .axi_mstr_awvalid (csr_lite_mst_if.awvalid ), + .axi_mstr_awready (csr_lite_mst_if.awready ), + .axi_mstr_wdata (csr_lite_mst_if.wdata ), + .axi_mstr_wstrb (csr_lite_mst_if.wstrb ), + .axi_mstr_wlast ( ), + .axi_mstr_wvalid (csr_lite_mst_if.wvalid ), + .axi_mstr_wready (csr_lite_mst_if.wready ), + .axi_mstr_bid (axi_mstr_bid_sig ), + .axi_mstr_bresp (csr_lite_mst_if.bresp ), + .axi_mstr_bvalid (csr_lite_mst_if.bvalid ), + .axi_mstr_bready (csr_lite_mst_if.bready ), + .axi_mstr_arid (axi_mstr_arid_sig ), + .axi_mstr_araddr (csr_lite_mst_if.araddr ), + .axi_mstr_arprot (csr_lite_mst_if.arprot ), + .axi_mstr_arvalid (csr_lite_mst_if.arvalid ), + .axi_mstr_arready (csr_lite_mst_if.arready ), + .axi_mstr_rid (axi_mstr_rid_sig ), + .axi_mstr_rdata (csr_lite_mst_if.rdata ), + .axi_mstr_rresp (csr_lite_mst_if.rresp ), + .axi_mstr_rvalid (csr_lite_mst_if.rvalid ), + .axi_mstr_rready (csr_lite_mst_if.rready ), + .axi_slave_awid (8'b0 ), + .axi_slave_awaddr (csr_lite_slv_if.awaddr ), + .axi_slave_awlen (8'b0 ), + .axi_slave_awsize (slv_awsize ), + .axi_slave_awburst (2'b0 ), + .axi_slave_awprot (csr_lite_slv_if.awprot ), + .axi_slave_awvalid (csr_lite_slv_if.awvalid ), + .axi_slave_awready (csr_lite_slv_if.awready ), + .axi_slave_wdata (csr_lite_slv_if.wdata ), + .axi_slave_wstrb (csr_lite_slv_if.wstrb ), + .axi_slave_wvalid (csr_lite_slv_if.wvalid ), + .axi_slave_wready (csr_lite_slv_if.wready ), + .axi_slave_bid ( ), + .axi_slave_bresp (csr_lite_slv_if.bresp ), + .axi_slave_bvalid (csr_lite_slv_if.bvalid ), + .axi_slave_bready (csr_lite_slv_if.bready ), + .axi_slave_arid (8'b0 ), + .axi_slave_araddr (csr_lite_slv_if.araddr ), + .axi_slave_arlen (8'b0 ), + .axi_slave_arsize (slv_arsize ), + .axi_slave_arburst (2'b0 ), + .axi_slave_arprot (csr_lite_slv_if.arprot ), + .axi_slave_arvalid (csr_lite_slv_if.arvalid ), + .axi_slave_arready (csr_lite_slv_if.arready ), + .axi_slave_rid ( ), + .axi_slave_rdata (csr_lite_slv_if.rdata ), + .axi_slave_rresp (csr_lite_slv_if.rresp ), + .axi_slave_rlast ( ), + .axi_slave_rvalid (csr_lite_slv_if.rvalid ), + .axi_slave_rready (csr_lite_slv_if.rready ), + .clk_clk (clk_csr ), + .qspi_dclk (qspi_dclk ), + .qspi_ncs (qspi_ncs ), + .qspi_data (qspi_data ), + .ncsi_rbt_ncsi_clk (ncsi_rbt_ncsi_clk ), + .ncsi_rbt_ncsi_txd (ncsi_rbt_ncsi_txd ), + .ncsi_rbt_ncsi_tx_en (ncsi_rbt_ncsi_tx_en ), + .ncsi_rbt_ncsi_rxd (ncsi_rbt_ncsi_rxd ), + .ncsi_rbt_ncsi_crs_dv (ncsi_rbt_ncsi_crs_dv ), + .ncsi_rbt_ncsi_arb_in (ncsi_rbt_ncsi_arb_in ), + .ncsi_rbt_ncsi_arb_out (ncsi_rbt_ncsi_arb_out ), + .m10_gpio_fpga_usr_100m (m10_gpio_fpga_usr_100m ), + .m10_gpio_fpga_m10_hb (m10_gpio_fpga_m10_hb ), + .m10_gpio_m10_seu_error (m10_gpio_m10_seu_error ), + .m10_gpio_fpga_therm_shdn (m10_gpio_fpga_therm_shdn ), + .m10_gpio_fpga_seu_error (m10_gpio_fpga_seu_error ), + .reset_reset (reset_csr ), + .spi_ingress_sclk (spi_ingress_sclk ), + .spi_ingress_csn (spi_ingress_csn ), + .spi_ingress_miso (spi_ingress_miso ), + .spi_ingress_mosi (spi_ingress_mosi ), .spi_egress_mosi_to_the_spislave_inst_for_spichain (spi_egress_mosi ), .spi_egress_nss_to_the_spislave_inst_for_spichain (spi_egress_csn ), - .spi_egress_sclk_to_the_spislave_inst_for_spichain (spi_egress_sclk ), - .spi_egress_miso_to_and_from_the_spislave_inst_for_spichain (spi_egress_miso ) - + .spi_egress_sclk_to_the_spislave_inst_for_spichain (spi_egress_sclk ), + .spi_egress_miso_to_and_from_the_spislave_inst_for_spichain (spi_egress_miso ) ); - + endmodule diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_ip/pxeboot_optrom_hw.tcl b/cards/silicom/n6010/src/comp/pmci/pmci_ip/pxeboot_optrom_hw.tcl index f168be943..26576fe37 100755 --- a/cards/silicom/n6010/src/comp/pmci/pmci_ip/pxeboot_optrom_hw.tcl +++ b/cards/silicom/n6010/src/comp/pmci/pmci_ip/pxeboot_optrom_hw.tcl @@ -1,7 +1,7 @@ # Copyright (C) 2020 Intel Corporation. # SPDX-License-Identifier: MIT -# +# # Description # ----------------------------------------------------------------------------- # This is the _hw.tcl of PXEBoot OptionROM core @@ -176,7 +176,7 @@ add_interface_port avalon_master avmm_mstr_waitreq waitrequest Input 1 # ----------------------------------------------------------------------------- # Port - Avalon-MM slave (to IOFS-shell/host) -# ----------------------------------------------------------------------------- +# ----------------------------------------------------------------------------- add_interface avalon_slave avalon end set_interface_property avalon_slave addressGroup 0 set_interface_property avalon_slave addressUnits WORDS @@ -238,18 +238,18 @@ add_interface_port csr_if pxeboot_status pxeboot_status Output 32 # Validate IP # ----------------------------------------------------------------------------- proc ip_validate { } { - + set orom_baddr [ get_parameter_value OPTROM_AREA_BADDR ] set fadr_width [ get_parameter_value FLASH_ADDR_WIDTH ] set hadr_width [ get_parameter_value HOST_RDADDR_WIDTH ] set orom_size [ get_parameter_value OPTROM_SIZE ] set addr_span [expr {pow(2, $fadr_width)}] - + if { $addr_span <= $orom_baddr } { send_message Error "Option ROM flash base addres is out of bound of flash address range. Please correct Option ROM base address or flash address width" } - + if { [expr {$orom_size * 1024}] > [expr {pow(2, $hadr_width)}] } { send_message Error "Option ROM size is out of bound of host address. Please correct Option ROM size or host address width" } @@ -259,7 +259,7 @@ proc ip_validate { } { # Elaborate IP # ----------------------------------------------------------------------------- proc ip_elaborate { } { - + set fadr_width [ get_parameter_value FLASH_ADDR_WIDTH ] set hadr_width [ get_parameter_value HOST_RDADDR_WIDTH ] diff --git a/cards/silicom/n6010/src/comp/pmci/pmci_top.vhd b/cards/silicom/n6010/src/comp/pmci/pmci_top.vhd index 4b5ead093..dfed0db46 100644 --- a/cards/silicom/n6010/src/comp/pmci/pmci_top.vhd +++ b/cards/silicom/n6010/src/comp/pmci/pmci_top.vhd @@ -31,7 +31,7 @@ entity PMCI_TOP is MI_DRD : out std_logic_vector(32-1 downto 0); MI_ARDY : out std_logic; MI_DRDY : out std_logic; - + -- ===================================================================== -- BMC interface -- ===================================================================== @@ -77,7 +77,7 @@ architecture FULL of PMCI_TOP is axi_mstr_wvalid : out std_logic; axi_mstr_wready : in std_logic; axi_mstr_bid : in std_logic_vector(8-1 downto 0); - axi_mstr_bresp : in std_logic_vector(2-1 downto 0); + axi_mstr_bresp : in std_logic_vector(2-1 downto 0); axi_mstr_bvalid : in std_logic; axi_mstr_bready : out std_logic; axi_mstr_arid : out std_logic_vector(8-1 downto 0); @@ -104,7 +104,7 @@ architecture FULL of PMCI_TOP is axi_slave_wvalid : in std_logic; axi_slave_wready : out std_logic; axi_slave_bid : out std_logic_vector(8-1 downto 0); - axi_slave_bresp : out std_logic_vector(2-1 downto 0); + axi_slave_bresp : out std_logic_vector(2-1 downto 0); axi_slave_bvalid : out std_logic; axi_slave_bready : in std_logic; axi_slave_arid : in std_logic_vector(8-1 downto 0); @@ -161,7 +161,7 @@ architecture FULL of PMCI_TOP is signal axi_mstr_wvalid : std_logic; signal axi_mstr_wready : std_logic; signal axi_mstr_bid : std_logic_vector(8-1 downto 0); - signal axi_mstr_bresp : std_logic_vector(2-1 downto 0); + signal axi_mstr_bresp : std_logic_vector(2-1 downto 0); signal axi_mstr_bvalid : std_logic; signal axi_mstr_bready : std_logic; signal axi_mstr_arid : std_logic_vector(8-1 downto 0); @@ -188,7 +188,7 @@ architecture FULL of PMCI_TOP is signal csr_wvalid : std_logic; signal csr_wready : std_logic; signal csr_bid : std_logic_vector(8-1 downto 0); - signal csr_bresp : std_logic_vector(2-1 downto 0); + signal csr_bresp : std_logic_vector(2-1 downto 0); signal csr_bvalid : std_logic; signal csr_bready : std_logic; signal csr_arid : std_logic_vector(8-1 downto 0); diff --git a/cards/silicom/n6010/src/fpga.vhd b/cards/silicom/n6010/src/fpga.vhd index b19a2f4ff..3aa527754 100644 --- a/cards/silicom/n6010/src/fpga.vhd +++ b/cards/silicom/n6010/src/fpga.vhd @@ -298,7 +298,7 @@ architecture FULL of FPGA is signal mem_clk : std_logic_vector(MEM_PORTS-1 downto 0) := (others => '0'); signal mem_rst_n : std_logic_vector(MEM_PORTS-1 downto 0) := (others => '0'); signal mem_pll_locked : std_logic_vector(MEM_PORTS-1 downto 0) := (others => '0'); - + signal mem_avmm_ready : std_logic_vector(MEM_PORTS-1 downto 0) := (others => '0'); signal mem_avmm_read : std_logic_vector(MEM_PORTS-1 downto 0); signal mem_avmm_write : std_logic_vector(MEM_PORTS-1 downto 0); @@ -307,7 +307,7 @@ architecture FULL of FPGA is signal mem_avmm_writedata : slv_array_t(MEM_PORTS-1 downto 0)(MEM_DATA_WIDTH-1 downto 0); signal mem_avmm_readdata : slv_array_t(MEM_PORTS-1 downto 0)(MEM_DATA_WIDTH-1 downto 0) := (others => (others => '0')); signal mem_avmm_readdatavalid : std_logic_vector(MEM_PORTS-1 downto 0) := (others => '0'); - + signal emif_rst_req : std_logic_vector(MEM_PORTS-1 downto 0); signal emif_rst_done : std_logic_vector(MEM_PORTS-1 downto 0) := (others => '0'); signal emif_ecc_usr_int : std_logic_vector(MEM_PORTS-1 downto 0) := (others => '0'); @@ -338,24 +338,24 @@ begin ETH_PORT_CHAN => ETH_PORT_CHAN, ETH_PORT_LEDS => 1, ETH_LANES => ETH_LANES, - + QSFP_PORTS => ETH_PORTS, QSFP_I2C_PORTS => ETH_PORTS, STATUS_LEDS => STATUS_LEDS, MISC_IN_WIDTH => MISC_IN_WIDTH, MISC_OUT_WIDTH => MISC_OUT_WIDTH, - + PCIE_ENDPOINTS => PCIE_ENDPOINTS, PCIE_ENDPOINT_TYPE => PCIE_MOD_ARCH, PCIE_ENDPOINT_MODE => PCIE_ENDPOINT_MODE, - + DMA_ENDPOINTS => DMA_ENDPOINTS, DMA_MODULES => DMA_MODULES, - + DMA_RX_CHANNELS => DMA_RX_CHANNELS/DMA_MODULES, DMA_TX_CHANNELS => DMA_TX_CHANNELS/DMA_MODULES, - + MEM_PORTS => MEM_PORTS, MEM_ADDR_WIDTH => MEM_ADDR_WIDTH, MEM_DATA_WIDTH => MEM_DATA_WIDTH, @@ -377,10 +377,10 @@ begin PCIE_RX_N => PCIE_RX_N, PCIE_TX_P => PCIE_TX_P, PCIE_TX_N => PCIE_TX_N, - + ETH_REFCLK_P => eth_refclk_p, ETH_REFCLK_N => eth_refclk_n, - + ETH_RX_P => eth_rx_p, ETH_RX_N => eth_rx_n, ETH_TX_P => eth_tx_p, @@ -421,7 +421,7 @@ begin EMIF_ECC_USR_INT => emif_ecc_usr_int, EMIF_CAL_SUCCESS => emif_cal_success, EMIF_CAL_FAIL => emif_cal_fail, - + BOOT_MI_CLK => boot_mi_clk, BOOT_MI_RESET => boot_mi_reset, BOOT_MI_DWR => boot_mi_dwr, @@ -438,7 +438,7 @@ begin ); -- QSFP MAPPING ------------------------------------------------------------ - eth_refclk_p <= QSFP_REFCLK_156M & QSFP_REFCLK_156M; + eth_refclk_p <= QSFP_REFCLK_156M & QSFP_REFCLK_156M; eth_refclk_n <= (others => '0'); -- Quartus will handle the connection itself eth_rx_p <= QSFP1_RX_P & QSFP0_RX_P; @@ -672,17 +672,17 @@ begin ddr4_cal0_i : component ddr4_calibration port map ( - calbus_read_0 => calbus_read(0), - calbus_write_0 => calbus_write(0), - calbus_address_0 => calbus_address(0), - calbus_wdata_0 => calbus_wdata(0), - calbus_rdata_0 => calbus_rdata(0), + calbus_read_0 => calbus_read(0), + calbus_write_0 => calbus_write(0), + calbus_address_0 => calbus_address(0), + calbus_wdata_0 => calbus_wdata(0), + calbus_rdata_0 => calbus_rdata(0), calbus_seq_param_tbl_0 => calbus_seq_param_tbl(0), - calbus_read_1 => calbus_read(1), - calbus_write_1 => calbus_write(1), - calbus_address_1 => calbus_address(1), - calbus_wdata_1 => calbus_wdata(1), - calbus_rdata_1 => calbus_rdata(1), + calbus_read_1 => calbus_read(1), + calbus_write_1 => calbus_write(1), + calbus_address_1 => calbus_address(1), + calbus_wdata_1 => calbus_wdata(1), + calbus_rdata_1 => calbus_rdata(1), calbus_seq_param_tbl_1 => calbus_seq_param_tbl(1), calbus_clk => calbus_clk(0) ); @@ -691,17 +691,17 @@ begin ddr4_cal1_i : component ddr4_calibration port map ( - calbus_read_0 => calbus_read(2), - calbus_write_0 => calbus_write(2), - calbus_address_0 => calbus_address(2), - calbus_wdata_0 => calbus_wdata(2), - calbus_rdata_0 => calbus_rdata(2), + calbus_read_0 => calbus_read(2), + calbus_write_0 => calbus_write(2), + calbus_address_0 => calbus_address(2), + calbus_wdata_0 => calbus_wdata(2), + calbus_rdata_0 => calbus_rdata(2), calbus_seq_param_tbl_0 => calbus_seq_param_tbl(2), - calbus_read_1 => calbus_read(3), - calbus_write_1 => calbus_write(3), - calbus_address_1 => calbus_address(3), - calbus_wdata_1 => calbus_wdata(3), - calbus_rdata_1 => calbus_rdata(3), + calbus_read_1 => calbus_read(3), + calbus_write_1 => calbus_write(3), + calbus_address_1 => calbus_address(3), + calbus_wdata_1 => calbus_wdata(3), + calbus_rdata_1 => calbus_rdata(3), calbus_seq_param_tbl_1 => calbus_seq_param_tbl(3), calbus_clk => calbus_clk(2) ); diff --git a/core/cocotb/examples/cocotb_test.py b/core/cocotb/examples/cocotb_test.py index 514d6794c..ebb9c6f6b 100644 --- a/core/cocotb/examples/cocotb_test.py +++ b/core/cocotb/examples/cocotb_test.py @@ -1,22 +1,24 @@ import cocotb -from cocotb.triggers import Timer, RisingEdge, Combine +from cocotb.triggers import Timer from ndk_core import NFBDevice import sys sys.stderr = None # disable warnings from Scapy -from scapy.all import TCP, Ether, IP, raw +from scapy.all import TCP, Ether, IP, raw # noqa sys.stderr = sys.__stderr__ + def s2b(pkt): return list(bytes(raw(pkt))) + @cocotb.test() async def cocotb_test_idcomp_invert(dut): nfb = NFBDevice(dut) await nfb.init() - mi, dma = nfb.mi[0], nfb.dma + mi = nfb.mi[0] node = [nfb._fdt.get_node(path) for path in nfb.fdt_get_compatible("netcope,idcomp")][0] mi_base = node.get_property('reg')[0] @@ -24,6 +26,7 @@ async def cocotb_test_idcomp_invert(dut): await mi.write32(mi_base, 0x12345678) assert await mi.read32(mi_base) == 0x12345678 ^ 0xFFFFFFFF + @cocotb.test() async def cocotb_test_rx_scapy_packet(dut): nfb = NFBDevice(dut) @@ -47,6 +50,7 @@ async def cocotb_test_rx_scapy_packet(dut): stats = await mac.read_stats() assert stats['received'] == 1 + @cocotb.test() async def cocotb_test_tx_scapy_packet(dut): nfb = NFBDevice(dut) @@ -63,6 +67,6 @@ def eth_tx_monitor_cb(p): await nfb.dma.tx[0].send(s2b(pkt)) await Timer(10, units='us') - + stats = await mac.read_stats() assert stats['sent'] == 1 diff --git a/core/cocotb/ndk_core/__init__.py b/core/cocotb/ndk_core/__init__.py index bcb2ea895..5af8530b4 100644 --- a/core/cocotb/ndk_core/__init__.py +++ b/core/cocotb/ndk_core/__init__.py @@ -1 +1,4 @@ from .nfbdevice import NFBDevice + + +__all__ = ["NFBDevice"] diff --git a/core/cocotb/ndk_core/nfbdevice.py b/core/cocotb/ndk_core/nfbdevice.py index d34354466..5f141cad4 100644 --- a/core/cocotb/ndk_core/nfbdevice.py +++ b/core/cocotb/ndk_core/nfbdevice.py @@ -1,6 +1,6 @@ import cocotb from cocotb.clock import Clock -from cocotb.triggers import Timer, RisingEdge, FallingEdge, Combine +from cocotb.triggers import Timer, RisingEdge, FallingEdge from cocotb.utils import get_sim_steps from cocotb import simulator @@ -21,15 +21,20 @@ from cocotbext.ofm.avst_eth.monitors import AvstEthMonitor from cocotbext.ofm.avst_eth.drivers import AvstEthDriver + class Axi4StreamMasterV(Axi4StreamMaster): _signals = {"TVALID": "VALID"} - _optional_signals = {"TREADY": "READY", "TDATA": "DATA", "TLAST": "LAST", "TKEEP" :"KEEP", "TUSER": "USER"} + _optional_signals = {"TREADY": "READY", "TDATA": "DATA", "TLAST": "LAST", "TKEEP": "KEEP", "TUSER": "USER"} + + class Axi4StreamSlaveV(Axi4StreamSlave): _signals = {"TVALID": "VALID"} - _optional_signals = {"TREADY": "READY", "TDATA": "DATA", "TLAST": "LAST", "TKEEP" :"KEEP", "TUSER": "USER"} + _optional_signals = {"TREADY": "READY", "TDATA": "DATA", "TLAST": "LAST", "TKEEP": "KEEP", "TUSER": "USER"} + + class Axi4StreamV(Axi4Stream): _signals = {"TVALID": "VALID"} - _optional_signals = {"TREADY": "READY", "TDATA": "DATA", "TLAST": "LAST", "TKEEP" :"KEEP", "TUSER": "USER"} + _optional_signals = {"TREADY": "READY", "TDATA": "DATA", "TLAST": "LAST", "TKEEP": "KEEP", "TUSER": "USER"} class NFBDevice(cocotbext.nfb.NfbDevice): @@ -37,7 +42,7 @@ class NFBDevice(cocotbext.nfb.NfbDevice): def core_instance_from_top(dut): try: core = [getattr(dut, core) for core in ["usp_i", "fpga_i", "ag_i", "cm_i"] if hasattr(dut, core)][0] - except: + except Exception: # No fpga_common instance in card, try fpga_common directly core = dut @@ -123,7 +128,7 @@ def _init_pcie(self): try: self._core = NFBDevice.core_instance_from_top(self._dut) - except: + except Exception: # No fpga_common instance in card, try fpga_common directly self._core = self._dut @@ -195,7 +200,7 @@ async def _reset(self, time=40, units="ns"): # FIXME: some strange loopback on ALVEO_U200 if self._core.USE_PCIE_CLK.value == 1: - await cocotb.triggers.FallingEdge(self._core.global_reset) + await FallingEdge(self._core.global_reset) elif hasattr(pcie_i, 'pcie_reset_status_n'): for rst in pcie_i.pcie_reset_status_n: rst.value = 0 @@ -206,9 +211,9 @@ async def _reset(self, time=40, units="ns"): raise NotImplementedError("Unknown signals for PCI/device reset") if self._core.rst_pci[0].value == 1: - await cocotb.triggers.FallingEdge(self._core.rst_pci[0]) + await FallingEdge(self._core.rst_pci[0]) - async def _pcie_cfg_ext_reg_access(self, addr, index = 0, fn = 0, sync=True, data=None): + async def _pcie_cfg_ext_reg_access(self, addr, index=0, fn=0, sync=True, data=None): pcie_i = self._core.pcie_i.pcie_core_i clk = pcie_i.pcie_hip_clk[index] @@ -217,23 +222,23 @@ async def _pcie_cfg_ext_reg_access(self, addr, index = 0, fn = 0, sync=True, dat pcie_i.cfg_ext_function[index].value = fn pcie_i.cfg_ext_register[index].value = addr >> 2 - pcie_i.cfg_ext_read[index].value = 1 if data == None else 0 - pcie_i.cfg_ext_write[index].value = 0 if data == None else 1 + pcie_i.cfg_ext_read[index].value = 1 if data is None else 0 + pcie_i.cfg_ext_write[index].value = 0 if data is None else 1 if data: pcie_i.cfg_ext_write_data[index].value = data await RisingEdge(clk) pcie_i.cfg_ext_read[index].value = 0 pcie_i.cfg_ext_write[index].value = 0 - if data == None: + if data is None: return pcie_i.cfg_ext_read_data[index].value.integer - async def _pcie_cfg_ext_reg_read(self, addr, index = 0, fn = 0, sync=True): + async def _pcie_cfg_ext_reg_read(self, addr, index=0, fn=0, sync=True): return await self._pcie_cfg_ext_reg_access(addr, index, fn, sync) - async def _pcie_cfg_ext_reg_write(self, addr, data, index = 0, fn = 0, sync=True): + async def _pcie_cfg_ext_reg_write(self, addr, data, index=0, fn=0, sync=True): await self._pcie_cfg_ext_reg_access(addr, index, fn, sync, data) - async def _read_dtb_raw(self, cap_dtb = 0x480): + async def _read_dtb_raw(self, cap_dtb=0x480): dtb_length = await self._pcie_cfg_ext_reg_read(cap_dtb + 0x0c) data = [] for i in range(dtb_length // 4): diff --git a/core/comp/app/app_uvm/env/env.sv b/core/comp/app/app_uvm/env/env.sv index 8fbb27c3f..f55e9839f 100644 --- a/core/comp/app/app_uvm/env/env.sv +++ b/core/comp/app/app_uvm/env/env.sv @@ -117,7 +117,7 @@ class env #(ETH_STREAMS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR_WIDTH, DMA_ST mfb_rx_config.active = UVM_ACTIVE; mfb_rx_config.interface_name = {"ETH_RX_MFB_", it_num}; uvm_config_db#(uvm_logic_vector_array_mfb::config_item)::set(this, {"m_eth_mfb_rx_", it_num}, "m_config", mfb_rx_config); - m_eth_mfb_rx[it] = uvm_logic_vector_array_mfb::env_rx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::create({"m_eth_mfb_rx_", it_num}, this); + m_eth_mfb_rx[it] = uvm_logic_vector_array_mfb::env_rx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::create({"m_eth_mfb_rx_", it_num}, this); // TX MFB mfb_tx_config = new(); mfb_tx_config.meta_behav = uvm_logic_vector_array_mfb::config_item::META_SOF; @@ -136,7 +136,7 @@ class env #(ETH_STREAMS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR_WIDTH, DMA_ST uvm_logic_vector_array_mfb::config_item mfb_tx_config; string it_num; it_num.itoa(it); - + //DMA m_dma_rx_config = new(); m_dma_rx_config.active = UVM_ACTIVE; @@ -331,7 +331,7 @@ class env #(ETH_STREAMS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR_WIDTH, DMA_ST end endtask - task run_eth_packet(uvm_logic_vector_array::sequencer#(MFB_ITEM_WIDTH) sqr); + task run_eth_packet(uvm_logic_vector_array::sequencer#(MFB_ITEM_WIDTH) sqr); uvm_app_core_top_agent::logic_vector_array#(MFB_ITEM_WIDTH, ETH_RX_HDR_WIDTH) seq; seq = uvm_app_core_top_agent::logic_vector_array#(MFB_ITEM_WIDTH, ETH_RX_HDR_WIDTH)::type_id::create("seq", this); forever begin @@ -352,7 +352,7 @@ class env #(ETH_STREAMS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR_WIDTH, DMA_ST end endtask - task run_dma_packet(uvm_logic_vector_array::sequencer#(MFB_ITEM_WIDTH) sqr); + task run_dma_packet(uvm_logic_vector_array::sequencer#(MFB_ITEM_WIDTH) sqr); uvm_app_core_top_agent::logic_vector_array#(MFB_ITEM_WIDTH, DMA_RX_MVB_WIDTH) seq; seq = uvm_app_core_top_agent::logic_vector_array#(MFB_ITEM_WIDTH, DMA_RX_MVB_WIDTH)::type_id::create("seq", this); forever begin diff --git a/core/comp/app/app_uvm/env/model.sv b/core/comp/app/app_uvm/env/model.sv index 742ccf7ea..d07eb922a 100644 --- a/core/comp/app/app_uvm/env/model.sv +++ b/core/comp/app/app_uvm/env/model.sv @@ -1,7 +1,7 @@ /* * file : model.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: Model create expectated output from input. + * description: Model create expectated output from input. * date : 2021 * author : Radek Iša * @@ -61,7 +61,7 @@ class packet #(WIDTH, CHANNELS, PKT_MTU, ITEM_WIDTH) extends uvm_app_core_top_ag packet_size = data.size(); msg = super.convert2string(); - msg = {msg, $sformatf("\n\tPacket form 0x%h", {discard, channel, meta, packet_size})}; + msg = {msg, $sformatf("\n\tPacket form 0x%h", {discard, channel, meta, packet_size})}; msg = {msg, $sformatf("\n\tmeta 0x%h\n\tchannel %0d\n\tpacket size %0d\n\tdiscard %b", meta, channel, packet_size, discard)}; return msg; endfunction diff --git a/core/comp/app/app_uvm/env/scoreboard.sv b/core/comp/app/app_uvm/env/scoreboard.sv index 0bf44f156..3a19a17e9 100644 --- a/core/comp/app/app_uvm/env/scoreboard.sv +++ b/core/comp/app/app_uvm/env/scoreboard.sv @@ -1,7 +1,7 @@ /* * file : scoreboard.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: scoreboard compare transactions from DUT and MODEL + * description: scoreboard compare transactions from DUT and MODEL * date : 2021 * author : Radek Iša * diff --git a/core/comp/app/app_uvm/env/scoreboard_cmp.sv b/core/comp/app/app_uvm/env/scoreboard_cmp.sv index e5cd53385..6f3c35fd2 100644 --- a/core/comp/app/app_uvm/env/scoreboard_cmp.sv +++ b/core/comp/app/app_uvm/env/scoreboard_cmp.sv @@ -1,7 +1,7 @@ /* * file : scoreboard_cmp.sv * Copyright (C) 2021 CESNET z. s. p. o. - * description: Scoreboard comparator + * description: Scoreboard comparator * date : 2021 * author : Radek Iša * diff --git a/core/comp/app/app_uvm/env/sequence.sv b/core/comp/app/app_uvm/env/sequence.sv index b3c63e424..ecb8cb867 100644 --- a/core/comp/app/app_uvm/env/sequence.sv +++ b/core/comp/app/app_uvm/env/sequence.sv @@ -1,7 +1,7 @@ /* * file : sequence.sv * Copyright (C) 2024 CESNET z. s. p. o. - * description: verification sequence + * description: verification sequence * date : 2021 * author : Radek Iša * diff --git a/core/comp/app/app_uvm/env/sequence_eth.sv b/core/comp/app/app_uvm/env/sequence_eth.sv index 71eeaf0be..5b14d4084 100644 --- a/core/comp/app/app_uvm/env/sequence_eth.sv +++ b/core/comp/app/app_uvm/env/sequence_eth.sv @@ -452,7 +452,7 @@ class sequence_search_eth #( }; constraint c_eth{ - foreach(eth_next_prot[it]) { + foreach(eth_next_prot[it]) { eth_next_prot[it] >= 0; eth_next_prot[it] < 10; } @@ -460,7 +460,7 @@ class sequence_search_eth #( }; constraint c_vlan{ - foreach(vlan_next_prot[it]) { + foreach(vlan_next_prot[it]) { vlan_next_prot[it] >= 0; vlan_next_prot[it] < 10; } @@ -468,7 +468,7 @@ class sequence_search_eth #( }; constraint c_ppp{ - foreach(ppp_next_prot[it]) { + foreach(ppp_next_prot[it]) { ppp_next_prot[it] >= 0; ppp_next_prot[it] < 10; } @@ -476,7 +476,7 @@ class sequence_search_eth #( }; constraint c_mpls{ - foreach(mpls_next_prot[it]) { + foreach(mpls_next_prot[it]) { mpls_next_prot[it] >= 0; mpls_next_prot[it] < 10; } @@ -484,7 +484,7 @@ class sequence_search_eth #( }; constraint c_ipv4{ - foreach(ipv4_next_prot[it]) { + foreach(ipv4_next_prot[it]) { ipv4_next_prot[it] >= 0; ipv4_next_prot[it] < 10; } @@ -492,7 +492,7 @@ class sequence_search_eth #( }; constraint c_ipv6{ - foreach(ipv6_next_prot[it]) { + foreach(ipv6_next_prot[it]) { ipv6_next_prot[it] >= 0; ipv6_next_prot[it] < 10; } @@ -500,7 +500,7 @@ class sequence_search_eth #( }; constraint c_proto{ - foreach(proto_next_prot[it]) { + foreach(proto_next_prot[it]) { proto_next_prot[it] >= 0; proto_next_prot[it] < 10; } diff --git a/core/comp/app/app_uvm/env/sequence_tsu.sv b/core/comp/app/app_uvm/env/sequence_tsu.sv index 7165315b3..3f6367ec5 100644 --- a/core/comp/app/app_uvm/env/sequence_tsu.sv +++ b/core/comp/app/app_uvm/env/sequence_tsu.sv @@ -1,7 +1,7 @@ /* * file : sequence.sv * Copyright (C) 2024 CESNET z. s. p. o. - * description: verification sequence + * description: verification sequence * date : 2024 * author : Radek Iša * @@ -25,14 +25,14 @@ class sequence_tsu extends uvm_common::sequence_base #(uvm_logic_vector::config_ // Generates transactions task body; - + req = uvm_logic_vector::sequence_item #(64)::type_id::create("req", m_sequencer); forever begin // Generate random request start_item(req); req.data = (time_start + $time())/1ns; - finish_item(req); + finish_item(req); end endtask diff --git a/core/comp/app/app_uvm/env/sequencer.sv b/core/comp/app/app_uvm/env/sequencer.sv index 60e47befe..85d321681 100644 --- a/core/comp/app/app_uvm/env/sequencer.sv +++ b/core/comp/app/app_uvm/env/sequencer.sv @@ -1,7 +1,7 @@ /* * file : sequencer.sv * Copyright (C) 2024 CESNET z. s. p. o. - * description: verification top sequencer + * description: verification top sequencer * date : 2021 * author : Radek Iša * diff --git a/core/comp/app/app_uvm/pkt_gen/config.py b/core/comp/app/app_uvm/pkt_gen/config.py index 6f23dc7df..7189c5022 100644 --- a/core/comp/app/app_uvm/pkt_gen/config.py +++ b/core/comp/app/app_uvm/pkt_gen/config.py @@ -8,19 +8,19 @@ # Author(s): # Radek Iša -import json def json_object_get(json, path): index = 0 - obj = json - while (index < len(path) and obj != None): + obj = json + while index < len(path) and obj is not None: obj = obj.get(path[index]) index += 1 - return obj; + return obj + class packet_config: - def __init__(self, constraints = None): + def __init__(self, constraints=None): #init values self.trill = 1 self.vlan = 4 @@ -29,17 +29,17 @@ def __init__(self, constraints = None): self.constraints = constraints - mpls_stack = self.object_get(["mpls", "stack"]); - if (mpls_stack != None): - self.mpls = int(mpls_stack.get("max")); + mpls_stack = self.object_get(["mpls", "stack"]) + if mpls_stack is not None: + self.mpls = int(mpls_stack.get("max")) - vlan_stack = self.object_get(["vlan", "stack"]); - if (vlan_stack != None): - self.vlan = int(vlan_stack.get("max")); + vlan_stack = self.object_get(["vlan", "stack"]) + if vlan_stack is not None: + self.vlan = int(vlan_stack.get("max")) - ipv6ext_stack = self.object_get(["ipv6ext", "stack"]); - if (ipv6ext_stack != None): - self.ipv6ext = int(ipv6ext.get("max")); + ipv6ext_stack = self.object_get(["ipv6ext", "stack"]) + if ipv6ext_stack is not None: + self.ipv6ext = int(ipv6ext.get("max")) def copy(self): ret = packet_config(self.constraints) @@ -47,8 +47,7 @@ def copy(self): ret.vlan = self.vlan ret.mpls = self.mpls ret.ipv6ext = self.ipv6ext - return ret; + return ret def object_get(self, path): return json_object_get(self.constraints, path) - diff --git a/core/comp/app/app_uvm/pkt_gen/layers/trill.py b/core/comp/app/app_uvm/pkt_gen/layers/trill.py index 47ea7ab03..eff88647e 100644 --- a/core/comp/app/app_uvm/pkt_gen/layers/trill.py +++ b/core/comp/app/app_uvm/pkt_gen/layers/trill.py @@ -15,6 +15,7 @@ import scapy.utils import scapy.volatile + class MyStrLenField(scapy.fields.StrLenField): __slots__ = ["rand_item"] @@ -26,7 +27,7 @@ def __init__( length_from=None, # type: Optional[Callable[[Packet], int]] max_length=None, # type: Optional[Any] ): - super(MyStrLenField, self).__init__(name, default, length_from = length_from, max_length = max_length) + super(MyStrLenField, self).__init__(name, default, length_from=length_from, max_length=max_length) def randval(self): # Randomization is move to Trill protocol. @@ -51,18 +52,18 @@ class Trill(scapy.packet.Packet): ] def do_build(self): - field_opt_length = self.opt_length; - field_data = self.data; + field_opt_length = self.opt_length + field_data = self.data if (isinstance(field_opt_length, scapy.volatile.RandNum)): - if (field_data == None): # randomize opt_length and data + if field_data is None: # randomize opt_length and data field_opt_length = field_opt_length._fix() field_data = scapy.volatile.RandBin(field_opt_length*4) else: # get length from data field_data += b"\0" * ((-len(field_data)) % 4) field_opt_length = len(field_data)/4 else: # randomize data depends on length - if (field_data == None): + if field_data is None: field_data = scapy.volatile.RandBin(field_opt_length*4) else: # Cannot randomize because all is set pass @@ -70,8 +71,8 @@ def do_build(self): if not self.explicit: self = next(iter(self)) - self.opt_length = field_opt_length; - self.data = field_data; + self.opt_length = field_opt_length + self.data = field_data pkt = self.self_build() for t in self.post_transforms: @@ -86,5 +87,3 @@ def do_build(self): scapy.packet.bind_layers(scapy.all.Ether, Trill, type=0x22f3) scapy.packet.bind_layers(scapy.all.Dot1Q, Trill, type=0x22f3) scapy.packet.bind_layers(Trill, scapy.all.Ether) - - diff --git a/core/comp/app/app_uvm/pkt_gen/parser.py b/core/comp/app/app_uvm/pkt_gen/parser.py index c79113680..e1eaa971f 100644 --- a/core/comp/app/app_uvm/pkt_gen/parser.py +++ b/core/comp/app/app_uvm/pkt_gen/parser.py @@ -9,15 +9,17 @@ # Author(s): # Radek Iša -from config import * +from config import json_object_get from layers import trill +import sys import scapy.all import scapy.utils import scapy.volatile import scapy.contrib.mpls import random -import string import ipaddress +import json + class base_node: def __init__(self, name): @@ -33,17 +35,17 @@ def protocol_next(self, config): return {} - ################################# # PAYLOAD protocols ################################# class Empty(base_node): def __init__(self): - super().__init__("Empty"); + super().__init__("Empty") + class Payload(base_node): def __init__(self): - super().__init__("Payload"); + super().__init__("Payload") def protocol_add(self, config): return scapy.all.Raw() @@ -51,13 +53,13 @@ def protocol_add(self, config): class TRILL(base_node): def __init__(self): - super().__init__("TRILL"); + super().__init__("TRILL") def protocol_add(self, config): - return trill.Trill(version = 0, res=0) + return trill.Trill(version=0, res=0) def protocol_next(self, config): - if (config.trill != 0): + if config.trill != 0: config.trill -= 1 proto = {"ETH" : 1} return proto @@ -68,7 +70,7 @@ def protocol_next(self, config): ################################# class ICMPv4(base_node): def __init__(self): - super().__init__("ICMPv4"); + super().__init__("ICMPv4") def protocol_add(self, config): return scapy.all.ICMP() @@ -76,53 +78,54 @@ def protocol_add(self, config): class ICMPv6(base_node): def __init__(self): - super().__init__("ICMPv6"); + super().__init__("ICMPv6") def protocol_add(self, config): return scapy.all.ICMPv6Unknown() + class UDP(base_node): def __init__(self): - super().__init__("UDP"); + super().__init__("UDP") def protocol_add(self, config): return scapy.all.UDP() def protocol_next(self, config): - proto = { "Empty" : 1, "Payload" : 1 } + proto = {"Empty" : 1, "Payload" : 1} cfg_obj = config.object_get([self.name, "weight"]) - if (cfg_obj != None): - proto.update(cfg_obj); + if cfg_obj is not None: + proto.update(cfg_obj) return proto class TCP(base_node): def __init__(self): - super().__init__("TCP"); + super().__init__("TCP") def protocol_add(self, config): return scapy.all.TCP() def protocol_next(self, config): - proto = { "Empty" : 1, "Payload" : 1 } - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto = {"Empty" : 1, "Payload" : 1} + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) return proto class SCTP(base_node): def __init__(self): - super().__init__("SCTP"); + super().__init__("SCTP") def protocol_add(self, config): return scapy.all.SCTP() def protocol_next(self, config): - proto = { "Empty" : 1, "Payload" : 1 } + proto = {"Empty" : 1, "Payload" : 1} cfg_obj = config.object_get([self.name, "weight"]) - if (cfg_obj != None): - proto.update(cfg_obj); + if cfg_obj is not None: + proto.update(cfg_obj) return proto @@ -131,124 +134,126 @@ def protocol_next(self, config): ################################# class IPv4(base_node): def __init__(self): - super().__init__("IPv4"); + super().__init__("IPv4") def protocol_add(self, config): - src = None; - dst = None; + src = None + dst = None - src_rand = config.object_get([self.name, "values", "src"]); - if (src_rand != None): + src_rand = config.object_get([self.name, "values", "src"]) + if src_rand is not None: val_range = random.choice(src_rand) src_min = int(val_range.get("min"), 0) src_max = int(val_range.get("max"), 0) src = str(ipaddress.IPv4Address(random.randint(src_min, src_max))) - dst_rand = config.object_get([self.name, "values", "dst"]); - if (dst_rand != None): + dst_rand = config.object_get([self.name, "values", "dst"]) + if dst_rand is not None: val_range = random.choice(dst_rand) dst_min = int(val_range.get("min"), 0) dst_max = int(val_range.get("max"), 0) dst = str(ipaddress.IPv4Address(random.randint(dst_min, dst_max))) - return scapy.all.IP(version=4, src = src, dst = dst) + return scapy.all.IP(version=4, src=src, dst=dst) def protocol_next(self, config): - proto = { "Payload" : 1, "Empty" : 1, "ICMPv4" : 1, "UDP" : 1, "TCP" : 1, "SCTP" : 1} - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto = {"Payload" : 1, "Empty" : 1, "ICMPv4" : 1, "UDP" : 1, "TCP" : 1, "SCTP" : 1} + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) return proto class IPv6Ext(base_node): def __init__(self): - super().__init__("IPv6Ext"); + super().__init__("IPv6Ext") def protocol_add(self, config): - possible_protocols = [ scapy.all.IPv6ExtHdrDestOpt(), scapy.all.IPv6ExtHdrFragment(id=random.randint(0, 2**32-1)), scapy.all.IPv6ExtHdrHopByHop(), scapy.all.IPv6ExtHdrRouting() ] + possible_protocols = [scapy.all.IPv6ExtHdrDestOpt(), scapy.all.IPv6ExtHdrFragment(id=random.randint(0, 2**32-1)), scapy.all.IPv6ExtHdrHopByHop(), scapy.all.IPv6ExtHdrRouting()] return random.choice(possible_protocols) def protocol_next(self, config): - proto = { "Payload" : 1, "Empty" : 1, "ICMPv4" : 1, "ICMPv6" : 1, "UDP" : 1, "TCP" : 1, "SCTP" : 1, "IPv6Ext" : 1} - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto = {"Payload" : 1, "Empty" : 1, "ICMPv4" : 1, "ICMPv6" : 1, "UDP" : 1, "TCP" : 1, "SCTP" : 1, "IPv6Ext" : 1} + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) # Check if it is last generated IPv6Ext - if (config.ipv6ext != 0): + if config.ipv6ext != 0: config.ipv6ext -= 1 - if (config.ipv6ext == 0): - proto["IPv6Ext"] = 0; + if config.ipv6ext == 0: + proto["IPv6Ext"] = 0 return proto class IPv6(base_node): def __init__(self): - super().__init__("IPv6"); + super().__init__("IPv6") def protocol_add(self, config): - src = None; - dst = None; + src = None + dst = None - src_rand = config.object_get([self.name, "values", "src"]); - if (src_rand != None): + src_rand = config.object_get([self.name, "values", "src"]) + if src_rand is not None: val_range = random.choice(src_rand) src_min = int(val_range.get("min"), 0) src_max = int(val_range.get("max"), 0) src = str(ipaddress.IPv6Address(random.randint(src_min, src_max))) - dst_rand = config.object_get([self.name, "values", "dst"]); - if (dst_rand != None): + dst_rand = config.object_get([self.name, "values", "dst"]) + if dst_rand is not None: val_range = random.choice(dst_rand) dst_min = int(val_range.get("min"), 0) dst_max = int(val_range.get("max"), 0) dst = str(ipaddress.IPv6Address(random.randint(dst_min, dst_max))) - return scapy.all.IPv6(version=6, src = src, dst = dst) + return scapy.all.IPv6(version=6, src=src, dst=dst) def protocol_next(self, config): - proto = { "Payload" : 1, "Empty" : 1, "ICMPv4" : 1, "ICMPv6" : 1, "UDP" : 1, "TCP" : 1, "SCTP" : 1, "IPv6Ext" : 1} - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto = {"Payload" : 1, "Empty" : 1, "ICMPv4" : 1, "ICMPv6" : 1, "UDP" : 1, "TCP" : 1, "SCTP" : 1, "IPv6Ext" : 1} + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) return proto ################################# # ETHERNET protocols ################################# + + class MPLS(base_node): def __init__(self): - super().__init__("MPLS"); + super().__init__("MPLS") def protocol_add(self, config): return scapy.contrib.mpls.MPLS() def protocol_next(self, config): - proto = {"IPv4" : 1, "IPv6" : 1, "MPLS" : 1,"Empty" : 1} - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto = {"IPv4" : 1, "IPv6" : 1, "MPLS" : 1, "Empty" : 1} + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) # Check if it is last generated MPLS - if (config.mpls != 0): + if config.mpls != 0: config.mpls -= 1 - if (config.mpls == 0): - proto["MPLS"] = 0; + if config.mpls == 0: + proto["MPLS"] = 0 return proto class PPP(base_node): def __init__(self): - super().__init__("PPP"); + super().__init__("PPP") def protocol_add(self, config): return scapy.all.PPPoE()/scapy.all.PPP() def protocol_next(self, config): proto = {"IPv4" : 1, "IPv6" : 1, "MPLS" : 1, "Empty" : 1} - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) return proto @@ -256,43 +261,43 @@ def protocol_next(self, config): class VLAN(base_node): def __init__(self): - super().__init__("VLAN"); + super().__init__("VLAN") def protocol_add(self, config): - possible_protocols = [ scapy.all.Dot1Q(), scapy.all.Dot1AD() ] + possible_protocols = [scapy.all.Dot1Q(), scapy.all.Dot1AD()] return random.choice(possible_protocols) def protocol_next(self, config): proto = {"IPv4" : 1, "IPv6" : 1, "VLAN" : 1 , "TRILL" : 1, "MPLS" : 1, "Empty" : 1, "PPP" : 1} - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) # check if it is last generated VLAN - if (config.vlan != 0): + if config.vlan != 0: config.vlan -= 1 - if (config.vlan == 0): - proto["VLAN"] = 0; - if (config.trill == 0): - proto["TRILL"] = 0; + if config.vlan == 0: + proto["VLAN"] = 0 + if config.trill == 0: + proto["TRILL"] = 0 return proto class ETH(base_node): def __init__(self): - super().__init__("ETH"); + super().__init__("ETH") def protocol_add(self, config): return scapy.all.Ether(src=scapy.volatile.RandMAC(), dst=scapy.volatile.RandMAC()) def protocol_next(self, config): proto = {"IPv4" : 1, "IPv6" : 1, "VLAN" : 1, "TRILL" : 1, "MPLS" : 1, "Empty" : 1, "PPP" : 1} - proto_weight = config.object_get([self.name, "weight"]); - if (proto_weight != None): + proto_weight = config.object_get([self.name, "weight"]) + if proto_weight is not None: proto.update(proto_weight) - if (config.trill == 0): - proto["TRILL"] = 0; + if config.trill == 0: + proto["TRILL"] = 0 return proto @@ -300,30 +305,29 @@ def protocol_next(self, config): class parser: def __init__(self, pcap_file, cfg, seed): self.protocols = {"ETH" : ETH(), "VLAN" : VLAN(), "TRILL" : TRILL(), "PPP" : PPP(), "MPLS" : MPLS(), "IPv6" : IPv6(), "IPv6Ext" : IPv6Ext(), - "IPv4" : IPv4(), "TCP" : TCP(), "UDP" : UDP(), "ICMPv6" : ICMPv6(), "ICMPv4" : ICMPv4(), "SCTP" : SCTP(), - "Payload" : Payload(), "Empty" : Empty()}; + "IPv4" : IPv4(), "TCP" : TCP(), "UDP" : UDP(), "ICMPv6" : ICMPv6(), "ICMPv4" : ICMPv4(), "SCTP" : SCTP(), + "Payload" : Payload(), "Empty" : Empty()} self.pcap_file = scapy.utils.PcapWriter(pcap_file, append=False, sync=True) self.cfg = None - if (cfg != None): + if cfg is not None: conf_file = open(cfg) json_cfg = conf_file.read() - conf_file.close(); - self.cfg = json.loads(json_cfg); + conf_file.close() + self.cfg = json.loads(json_cfg) random.seed(seed) - pkt_size_min = json_object_get(self.cfg, ["packet", "size_min"]); - if (pkt_size_min != None): + pkt_size_min = json_object_get(self.cfg, ["packet", "size_min"]) + if pkt_size_min is not None: self.pkt_size_min = pkt_size_min else: self.pkt_size_min = 60 - pkt_err_probability = json_object_get(self.cfg, ["packet", "err_probability"]); - if (pkt_err_probability != None): + pkt_err_probability = json_object_get(self.cfg, ["packet", "err_probability"]) + if pkt_err_probability is not None: self.pkt_err_probability = pkt_err_probability else: self.pkt_err_probability = 0 - def __del__(self): self.pcap_file.close() @@ -335,26 +339,23 @@ def proto_weight_get(self, dict_items): proto = [] weight = [] for key in dict_items: - proto.append(key); - weight.append(dict_items[key]); + proto.append(key) + weight.append(dict_items[key]) return (proto, weight) - def write(self, packet): packet_fuzz = scapy.packet.fuzz(packet) packet_wr = b"" try: - packet_wr = packet_fuzz.build(); - except: - packet_wr = packet.build(); + packet_wr = packet_fuzz.build() + except Exception: + packet_wr = packet.build() # GENERATE ERROR PACKETS - if (random.randint(0, 99) < self.pkt_err_probability): - packet_wr = packet_wr[0:random.randint(0,len(packet_wr))]; + if random.randint(0, 99) < self.pkt_err_probability: + packet_wr = packet_wr[0:random.randint(0, len(packet_wr))] # SET MINIMAL SIZE - if (len(packet_wr) < self.pkt_size_min): - packet_wr += b"\0" * (self.pkt_size_min -len(packet_wr)) - self.pcap_file.write(packet_wr); - - + if len(packet_wr) < self.pkt_size_min: + packet_wr += bytes(self.pkt_size_min - len(packet_wr)) + self.pcap_file.write(packet_wr) diff --git a/core/comp/app/app_uvm/pkt_gen/parser_dfs.py b/core/comp/app/app_uvm/pkt_gen/parser_dfs.py index 82cec654e..1aab3a8db 100644 --- a/core/comp/app/app_uvm/pkt_gen/parser_dfs.py +++ b/core/comp/app/app_uvm/pkt_gen/parser_dfs.py @@ -9,8 +9,9 @@ # Author(s): # Radek Iša -from config import * -from parser import * +from config import packet_config +from parser import parser as Parser + class dfs_item: def __init__(self, protocol, cfg): @@ -24,10 +25,10 @@ def __init__(self, protocol, cfg): self.protocols_next.append(it) def last(self): - return len(self.protocols_next) == 0; + return len(self.protocols_next) == 0 def next(self): - if (self.protocols_next == None or self.index >= len(self.protocols_next)): + if self.protocols_next is None or self.index >= len(self.protocols_next): return None ret = self.protocols_next[self.index] @@ -35,27 +36,27 @@ def next(self): return ret -class parser_dfs(parser): +class parser_dfs(Parser): def __init__(self, pcap_file, cfg, seed): - super().__init__(pcap_file, cfg, seed); + super().__init__(pcap_file, cfg, seed) def gen(self): next_items = [] - cfg_act = packet_config(self.cfg); - item = dfs_item(self.protocols["ETH"], cfg_act); + cfg_act = packet_config(self.cfg) + item = dfs_item(self.protocols["ETH"], cfg_act) next_items.append(item) packets = 0 - while (len(next_items) > 0): + while len(next_items) > 0: # get last item - item = next_items[-1]; + item = next_items[-1] # get next generated protocol proto_next = item.next() - if (not item.last()): - if (proto_next != None): - item_next = dfs_item(self.protocols[proto_next], item.cfg); + if not item.last(): + if proto_next is not None: + item_next = dfs_item(self.protocols[proto_next], item.cfg) next_items.append(item_next) else: #remove last index there is no next protocol @@ -67,14 +68,13 @@ def gen(self): for it in next_items: pkt_proto = it.protocol.protocol_add(it.cfg) - if (pkt_proto != None): - packet = packet/pkt_proto + if pkt_proto is not None: + packet = packet / pkt_proto #write packet self.write(packet) #remove last index del next_items[-1] - print ("PACKETS %d" % (packets)) + print("PACKETS %d" % (packets)) pass - diff --git a/core/comp/app/app_uvm/pkt_gen/parser_rand.py b/core/comp/app/app_uvm/pkt_gen/parser_rand.py index 105d9f71a..d1f76b622 100644 --- a/core/comp/app/app_uvm/pkt_gen/parser_rand.py +++ b/core/comp/app/app_uvm/pkt_gen/parser_rand.py @@ -9,12 +9,13 @@ # Author(s): # Radek Iša -from config import * -from parser import * +from config import packet_config +from parser import parser as Parser -class parser_rand(parser): + +class parser_rand(Parser): def __init__(self, pcap_file, cfg, seed, packets): - super().__init__(pcap_file, cfg, seed); + super().__init__(pcap_file, cfg, seed) self.packets = packets def gen(self): @@ -23,18 +24,17 @@ def gen(self): proto_act = self.protocols["ETH"] packet = scapy.packet.Packet() - while (proto_act != None): + while proto_act is not None: pkt_proto = proto_act.protocol_add(cfg) - if (pkt_proto != None): + if pkt_proto is not None: packet = packet/pkt_proto proto_next = proto_act.protocol_next(cfg) - if (len(proto_next) > 0): + if len(proto_next) > 0: (proto_next_indexs, proto_next_weights) = self.proto_weight_get(proto_next) protocol_next_name = random.choices(proto_next_indexs, proto_next_weights)[0] - proto_act = self.protocols.get(protocol_next_name); + proto_act = self.protocols.get(protocol_next_name) else: proto_act = None # End While self.write(packet) - diff --git a/core/comp/app/app_uvm/pkt_gen/pkt_gen.py b/core/comp/app/app_uvm/pkt_gen/pkt_gen.py index 4ed884746..9a1ae1490 100755 --- a/core/comp/app/app_uvm/pkt_gen/pkt_gen.py +++ b/core/comp/app/app_uvm/pkt_gen/pkt_gen.py @@ -9,14 +9,13 @@ # Radek Iša -from parser_rand import * -from parser_dfs import * -import scapy.utils -import string +from parser_rand import parser_rand as Parser_rand +from parser_dfs import parser_dfs as Parser_dfs import argparse import time import enum + class parse_alg(enum.Enum): noe = 'none' dfs = 'dfs' @@ -27,25 +26,26 @@ def __str__(self): @staticmethod def values(): - ret = [] - arg_list = list(parse_alg) - for it in arg_list: - ret.append(it.value); - return ret; + ret = [] + arg_list = list(parse_alg) + for it in arg_list: + ret.append(it.value) + return ret + def main(): #parse options arg_parser = argparse.ArgumentParser() arg_parser.add_argument("-f", "--file_output", type=str, - help="Set output file", required=True) + help="Set output file", required=True) arg_parser.add_argument("-p", "--packets", type=int, - help="number of generated packets", default=20) + help="number of generated packets", default=20) arg_parser.add_argument("-a", "--algorithm", type=parse_alg, - help=("parse algorithms possible values [" + ' '.join(parse_alg.values()) + "]"), default="rand") + help=("parse algorithms possible values [" + ' '.join(parse_alg.values()) + "]"), default="rand") arg_parser.add_argument("-s", "--seed", type=int, - help="set seed to random generator", default=int(time.time()*1000)) + help="set seed to random generator", default=int(time.time()*1000)) arg_parser.add_argument("-c", "--conf", type=str, - help="Configrutation of random genertor for protocols in JSON", default=None) + help="Configrutation of random genertor for protocols in JSON", default=None) args = arg_parser.parse_args() print("SEED : " + f'{args.seed}') @@ -55,12 +55,12 @@ def main(): gen = parser(args.file_output, args.conf, args.seed) if (args.algorithm == parse_alg.rand): - gen = parser_rand(args.file_output, args.conf, args.seed, args.packets) + gen = Parser_rand(args.file_output, args.conf, args.seed, args.packets) if (args.algorithm == parse_alg.dfs): - gen = parser_dfs(args.file_output, args.conf, args.seed) + gen = Parser_dfs(args.file_output, args.conf, args.seed) #run generator - gen.gen(); + gen.gen() if __name__ == "__main__": diff --git a/core/comp/app/app_uvm/top_agent/agent.sv b/core/comp/app/app_uvm/top_agent/agent.sv index cf4c10dfa..6172dfa5c 100644 --- a/core/comp/app/app_uvm/top_agent/agent.sv +++ b/core/comp/app/app_uvm/top_agent/agent.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2024 CESNET z. s. p. o. //-- Author(s): Radek Iša -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class agent #(type TR_TYPE, int unsigned ITEM_WIDTH, int unsigned META_WIDTH) extends uvm_agent; // registration of component tools diff --git a/core/comp/app/app_uvm/top_agent/config.sv b/core/comp/app/app_uvm/top_agent/config.sv index 56367d985..4d45851c2 100644 --- a/core/comp/app/app_uvm/top_agent/config.sv +++ b/core/comp/app/app_uvm/top_agent/config.sv @@ -1,4 +1,4 @@ -//-- config.sv: +//-- config.sv: //-- Copyright (C) 2024 CESNET z. s. p. o. //-- Author(s): Radek Iša diff --git a/core/comp/app/app_uvm/top_agent/driver.sv b/core/comp/app/app_uvm/top_agent/driver.sv index 628ad20c8..c58526e46 100644 --- a/core/comp/app/app_uvm/top_agent/driver.sv +++ b/core/comp/app/app_uvm/top_agent/driver.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2024 CESNET z. s. p. o. //-- Author(s): Radek Iša -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class driver#(ITEM_WIDTH, META_WIDTH) extends uvm_driver #(sequence_item#(ITEM_WIDTH, META_WIDTH)); diff --git a/core/comp/app/app_uvm/top_agent/monitor.sv b/core/comp/app/app_uvm/top_agent/monitor.sv index b32450b14..9a9e01914 100644 --- a/core/comp/app/app_uvm/top_agent/monitor.sv +++ b/core/comp/app/app_uvm/top_agent/monitor.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2024 CESNET z. s. p. o. //-- Author(s): Radek Iša -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class monitor #(type TR_TYPE, int unsigned ITEM_WIDTH, int unsigned META_WIDTH) extends uvm_monitor; diff --git a/core/comp/app/app_uvm/top_agent/pkg.sv b/core/comp/app/app_uvm/top_agent/pkg.sv index 08ed775a9..0beb8871d 100644 --- a/core/comp/app/app_uvm/top_agent/pkg.sv +++ b/core/comp/app/app_uvm/top_agent/pkg.sv @@ -1,8 +1,8 @@ -//-- pkg.sv: packet environment +//-- pkg.sv: packet environment //-- Copyright (C) 2024 CESNET z. s. p. o. //-- Author(s): Radek Iša -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause `ifndef APP_CORE_TOP_AGENT_PKG `define APP_CORE_TOP_AGENT_PKG diff --git a/core/comp/app/app_uvm/top_agent/sequence.sv b/core/comp/app/app_uvm/top_agent/sequence.sv index 7629e31ae..18cceda58 100644 --- a/core/comp/app/app_uvm/top_agent/sequence.sv +++ b/core/comp/app/app_uvm/top_agent/sequence.sv @@ -1,8 +1,8 @@ -//-- sequence.sv: create from packet transaction mfb and mvb transaction +//-- sequence.sv: create from packet transaction mfb and mvb transaction //-- Copyright (C) 2024 CESNET z. s. p. o. //-- Author(s): Radek Iša -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class sequence_base#(type TR_TYPE) extends uvm_sequence #(TR_TYPE); @@ -39,7 +39,7 @@ class sequence_base#(type TR_TYPE) extends uvm_sequence #(TR_TYPE); while(it < transactions && (state == null || !state.stopped())) begin //generat new packet start_item(req); - req.randomize() with {req.data.size() inside {[60:1500]}; }; + req.randomize() with {req.data.size() inside {[60:1500]}; }; finish_item(req); it++; @@ -77,7 +77,7 @@ class logic_vector_array#(ITEM_WIDTH, META_WIDTH) extends uvm_sequence #(uvm_log //generat new packet start_item(req); - req.data = tmp_packet.data; + req.data = tmp_packet.data; finish_item(req); end endtask @@ -120,7 +120,7 @@ class logic_vector_sequence #(ITEM_WIDTH, META_WIDTH) extends uvm_sequence #(uvm //generat new packet start_item(req); req.data = high_tr.item2meta(); - //high_tr.pack(bitstream); + //high_tr.pack(bitstream); //req.data = { >> {bitstream}}; finish_item(req); diff --git a/core/comp/app/app_uvm/top_agent/sequencer.sv b/core/comp/app/app_uvm/top_agent/sequencer.sv index 3586eae8d..4020d489f 100644 --- a/core/comp/app/app_uvm/top_agent/sequencer.sv +++ b/core/comp/app/app_uvm/top_agent/sequencer.sv @@ -1,10 +1,10 @@ -//-- sequencer.sv: packet sequencer +//-- sequencer.sv: packet sequencer //-- Copyright (C) 2024 CESNET z. s. p. o. //-- Author(s): Radek Iša -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause -//typedef uvm_sequencer#(sequence_item) sequencer; +//typedef uvm_sequencer#(sequence_item) sequencer; class sequencer #(int unsigned ITEM_WIDTH, int unsigned META_WIDTH) extends uvm_sequencer #(sequence_item #(ITEM_WIDTH, META_WIDTH)); `uvm_component_param_utils(uvm_app_core_top_agent::sequencer #(ITEM_WIDTH, META_WIDTH)) diff --git a/core/comp/app/application_ent.vhd b/core/comp/app/application_ent.vhd index c58907616..155c6c24a 100644 --- a/core/comp/app/application_ent.vhd +++ b/core/comp/app/application_ent.vhd @@ -177,7 +177,7 @@ port ( -- Unique identification number of the FPGA chip (clocked at MI_CLK) FPGA_ID : in std_logic_vector(FPGA_ID_WIDTH-1 downto 0); FPGA_ID_VLD : in std_logic; - + -- ========================================================================= -- RX ETHERNET STREAMS (clocked at APP_CLK) -- @@ -193,7 +193,7 @@ port ( ETH_RX_MVB_SRC_RDY : in std_logic_vector(ETH_STREAMS-1 downto 0); -- ETH RX MVB streams: destination ready of each MVB bus ETH_RX_MVB_DST_RDY : out std_logic_vector(ETH_STREAMS-1 downto 0); - + -- ETH RX MFB streams: data word with frames (packets) ETH_RX_MFB_DATA : in std_logic_vector(ETH_STREAMS* ETH_MFB_REGIONS*ETH_MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0); -- ETH RX MFB streams: Start Of Frame (SOF) flag for each MFB region @@ -275,7 +275,7 @@ port ( DMA_RX_MFB_SRC_RDY : out std_logic_vector(DMA_STREAMS-1 downto 0); -- DMA RX MFB streams: destination ready of each MFB bus DMA_RX_MFB_DST_RDY : in std_logic_vector(DMA_STREAMS-1 downto 0); - + -- ========================================================================= -- TX DMA STREAMS (clocked at APP_CLK) -- @@ -310,7 +310,7 @@ port ( DMA_TX_MFB_SRC_RDY : in std_logic_vector(DMA_STREAMS-1 downto 0); -- DMA TX MFB streams: destination ready of each MFB bus DMA_TX_MFB_DST_RDY : out std_logic_vector(DMA_STREAMS-1 downto 0); - + -- ===================================================================== -- Application specific signals -- ===================================================================== diff --git a/core/comp/app/biflow_simple/app_biflow_port.vhd b/core/comp/app/biflow_simple/app_biflow_port.vhd index da3755cb4..bce0c1ff0 100644 --- a/core/comp/app/biflow_simple/app_biflow_port.vhd +++ b/core/comp/app/biflow_simple/app_biflow_port.vhd @@ -32,7 +32,7 @@ port ( -- ========================================================================= CLK : in std_logic; RESET : in std_logic; - + -- ========================================================================= -- Input MFB+MVB interface -- ========================================================================= @@ -49,7 +49,7 @@ port ( IN_MFB_EOF_POS : in slv_array_t(IN_STREAMS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0); IN_MFB_SRC_RDY : in std_logic_vector(IN_STREAMS-1 downto 0); IN_MFB_DST_RDY : out std_logic_vector(IN_STREAMS-1 downto 0); - + -- ========================================================================= -- Output MFB+MVB interface -- ========================================================================= @@ -57,7 +57,7 @@ port ( OUT_MVB_VLD : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS-1 downto 0); OUT_MVB_SRC_RDY : out std_logic_vector(OUT_STREAMS-1 downto 0); OUT_MVB_DST_RDY : in std_logic_vector(OUT_STREAMS-1 downto 0); - + OUT_MFB_DATA : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0); OUT_MFB_SOF : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS-1 downto 0); OUT_MFB_EOF : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS-1 downto 0); @@ -114,7 +114,7 @@ begin port map( CLK => CLK, RESET => RESET, - + RX_MVB_DATA => IN_MVB_DATA, RX_MVB_PAYLOAD => (others => (others => '1')), RX_MVB_VLD => IN_MVB_VLD, @@ -157,7 +157,7 @@ begin port map ( CLK => CLK, RST => RESET, - + RX_DATA => fi_mfb_data(0), RX_SOF_POS => fi_mfb_sof_pos(0), RX_EOF_POS => fi_mfb_eof_pos(0), @@ -165,7 +165,7 @@ begin RX_EOF => fi_mfb_eof(0), RX_SRC_RDY => fi_mfb_src_rdy(0), RX_DST_RDY => fi_mfb_dst_rdy(0), - + TX_DATA => OUT_MFB_DATA(0), TX_SOF_POS => OUT_MFB_SOF_POS(0), TX_EOF_POS => OUT_MFB_EOF_POS(0), @@ -247,7 +247,7 @@ begin port map ( CLK => CLK, RST => RESET, - + RX_DATA => fi_mfb_data(i), RX_SOF_POS => fi_mfb_sof_pos(i), RX_EOF_POS => fi_mfb_eof_pos(i), @@ -255,7 +255,7 @@ begin RX_EOF => fi_mfb_eof(i), RX_SRC_RDY => fi_mfb_src_rdy(i), RX_DST_RDY => fi_mfb_dst_rdy(i), - + TX_DATA => OUT_MFB_DATA(i), TX_SOF_POS => OUT_MFB_SOF_POS(i), TX_EOF_POS => OUT_MFB_EOF_POS(i), diff --git a/core/comp/app/biflow_simple/app_biflow_simple.vhd b/core/comp/app/biflow_simple/app_biflow_simple.vhd index 715ccf790..1fe9f74a4 100644 --- a/core/comp/app/biflow_simple/app_biflow_simple.vhd +++ b/core/comp/app/biflow_simple/app_biflow_simple.vhd @@ -32,7 +32,7 @@ port ( -- ========================================================================= CLK : in std_logic; RESET : in std_logic; - + -- ========================================================================= -- Input MFB+MVB interface -- ========================================================================= @@ -49,7 +49,7 @@ port ( IN_MFB_EOF_POS : in slv_array_t(IN_STREAMS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0); IN_MFB_SRC_RDY : in std_logic_vector(IN_STREAMS-1 downto 0); IN_MFB_DST_RDY : out std_logic_vector(IN_STREAMS-1 downto 0); - + -- ========================================================================= -- Output MFB+MVB interface -- ========================================================================= @@ -57,7 +57,7 @@ port ( OUT_MVB_VLD : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS-1 downto 0); OUT_MVB_SRC_RDY : out std_logic_vector(OUT_STREAMS-1 downto 0); OUT_MVB_DST_RDY : in std_logic_vector(OUT_STREAMS-1 downto 0); - + OUT_MFB_DATA : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0); OUT_MFB_SOF : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS-1 downto 0); OUT_MFB_EOF : out slv_array_t(OUT_STREAMS-1 downto 0)(MFB_REGIONS-1 downto 0); @@ -182,7 +182,7 @@ begin port_out_mvb_vld(i*IN_STREAMS+j) <= port_in_mvb_vld(j*OUT_STREAMS+i); port_out_mvb_src_rdy(i*IN_STREAMS+j) <= port_in_mvb_src_rdy(j*OUT_STREAMS+i); port_in_mvb_dst_rdy(j*OUT_STREAMS+i) <= port_out_mvb_dst_rdy(i*IN_STREAMS+j); - + port_out_mfb_data(i*IN_STREAMS+j) <= port_in_mfb_data(j*OUT_STREAMS+i); port_out_mfb_sof(i*IN_STREAMS+j) <= port_in_mfb_sof(j*OUT_STREAMS+i); port_out_mfb_eof(i*IN_STREAMS+j) <= port_in_mfb_eof(j*OUT_STREAMS+i); @@ -210,7 +210,7 @@ begin port map( CLK => CLK, RESET => RESET, - + RX_MVB_DATA => port_out_mvb_data(IPO_RANGE), RX_MVB_PAYLOAD => (others => (others => '1')), RX_MVB_VLD => port_out_mvb_vld(IPO_RANGE), diff --git a/core/comp/app/biflow_simple/app_biflow_simple_top.vhd b/core/comp/app/biflow_simple/app_biflow_simple_top.vhd index 62f0be458..51f183cca 100644 --- a/core/comp/app/biflow_simple/app_biflow_simple_top.vhd +++ b/core/comp/app/biflow_simple/app_biflow_simple_top.vhd @@ -37,7 +37,7 @@ port ( -- ========================================================================= CLK : in std_logic; RESET : in std_logic; - + -- ========================================================================= -- APP2DMA PATH -- ========================================================================= @@ -56,7 +56,7 @@ port ( APP_DMA_RX_MFB_EOF_POS : in slv_array_t(APP_STREAMS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0); APP_DMA_RX_MFB_SRC_RDY : in std_logic_vector(APP_STREAMS-1 downto 0); APP_DMA_RX_MFB_DST_RDY : out std_logic_vector(APP_STREAMS-1 downto 0); - + DMA_RX_MVB_LEN : out slv_array_t(DMA_STREAMS-1 downto 0)(MFB_REGIONS*log2(DMA_RX_FRAME_SIZE_MAX+1)-1 downto 0); DMA_RX_MVB_HDR_META : out slv_array_t(DMA_STREAMS-1 downto 0)(MFB_REGIONS*DMA_HDR_META_WIDTH-1 downto 0); DMA_RX_MVB_CHANNEL : out slv_array_t(DMA_STREAMS-1 downto 0)(MFB_REGIONS*log2(DMA_RX_CHANNELS)-1 downto 0); diff --git a/core/comp/app/dma_streams_merger/app_dma_streams_merger.vhd b/core/comp/app/dma_streams_merger/app_dma_streams_merger.vhd index 14adb1afd..12e8aa32f 100644 --- a/core/comp/app/dma_streams_merger/app_dma_streams_merger.vhd +++ b/core/comp/app/dma_streams_merger/app_dma_streams_merger.vhd @@ -37,7 +37,7 @@ port ( -- ========================================================================= CLK : in std_logic; RESET : in std_logic; - + -- ========================================================================= -- APP2DMA PATH -- ========================================================================= @@ -59,7 +59,7 @@ port ( APP_DMA_RX_MFB_EOF_POS : in slv_array_t(APP_STREAMS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0); APP_DMA_RX_MFB_SRC_RDY : in std_logic_vector(APP_STREAMS-1 downto 0); APP_DMA_RX_MFB_DST_RDY : out std_logic_vector(APP_STREAMS-1 downto 0); - + -- MFB+MVB interface to DMA module (to DMA module) -- ------------------------------------------------------------------------- DMA_RX_MVB_LEN : out slv_array_t(DMA_STREAMS-1 downto 0)(MFB_REGIONS*log2(DMA_RX_FRAME_SIZE_MAX+1)-1 downto 0); @@ -98,7 +98,7 @@ port ( DMA_TX_MFB_EOF_POS : in slv_array_t(DMA_STREAMS-1 downto 0)(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0); DMA_TX_MFB_SRC_RDY : in std_logic_vector(DMA_STREAMS-1 downto 0); DMA_TX_MFB_DST_RDY : out std_logic_vector(DMA_STREAMS-1 downto 0); - + -- MFB+MVB interface to DMA module (to APP/ETH module) -- ------------------------------------------------------------------------- APP_DMA_TX_MVB_LEN : out slv_array_t(APP_STREAMS-1 downto 0)(MFB_REGIONS*log2(DMA_TX_FRAME_SIZE_MAX+1)-1 downto 0); @@ -209,7 +209,7 @@ begin port map( CLK => CLK, RESET => RESET, - + RX_MVB_DATA => app_dma_rx_mvb_data_deser, RX_MVB_PAYLOAD => app_dma_rx_mvb_payload_deser, RX_MVB_VLD => APP_DMA_RX_MVB_VLD, diff --git a/core/comp/dma/dma_mod/dma_empty_arch.vhd b/core/comp/dma/dma_mod/dma_empty_arch.vhd index 265a8064a..afb81a889 100644 --- a/core/comp/dma/dma_mod/dma_empty_arch.vhd +++ b/core/comp/dma/dma_mod/dma_empty_arch.vhd @@ -141,7 +141,7 @@ begin rx_usr_arr_mvb_vld <= RX_USR_MVB_VLD; rx_usr_arr_mvb_src_rdy <= RX_USR_MVB_SRC_RDY; RX_USR_MVB_DST_RDY <= rx_usr_arr_mvb_dst_rdy; - + rx_usr_arr_mfb_data <= RX_USR_MFB_DATA; rx_usr_arr_mfb_sof <= RX_USR_MFB_SOF; rx_usr_arr_mfb_eof <= RX_USR_MFB_EOF; @@ -236,7 +236,7 @@ begin SAME_CLK => false , MI_PIPE_EN => true , DEVICE => DEVICE - ) + ) port map( MI_CLK => MI_CLK, MI_RESET => MI_RESET, @@ -305,7 +305,7 @@ begin DMA_TX_MVB_VLD => dma_tx_usr_mvb_vld(i) , DMA_TX_MVB_SRC_RDY => dma_tx_usr_mvb_src_rdy(i) , DMA_TX_MVB_DST_RDY => dma_tx_usr_mvb_dst_rdy(i) , - + DMA_TX_MFB_DATA => dma_tx_usr_mfb_data(i) , DMA_TX_MFB_SOF => dma_tx_usr_mfb_sof(i) , DMA_TX_MFB_EOF => dma_tx_usr_mfb_eof(i) , diff --git a/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd b/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd index 10a8ddffc..727f5ecd0 100644 --- a/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd +++ b/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd @@ -385,7 +385,7 @@ begin port map( CLK => USR_CLK, RESET => USR_RESET, - + RX_DATA => rx_usr_mfb_data_res(i), RX_META => rx_usr_mfb_meta_res(i), RX_SOF => rx_usr_mfb_sof_res(i), @@ -394,7 +394,7 @@ begin RX_EOF_POS => rx_usr_mfb_eof_pos_res(i), RX_SRC_RDY => rx_usr_mfb_src_rdy_res(i), RX_DST_RDY => rx_usr_mfb_dst_rdy_res(i), - + TX_DATA => rx_usr_mfb_data_async(i), TX_META => rx_usr_mfb_meta_async(i), TX_SOF => rx_usr_mfb_sof_async(i), @@ -404,7 +404,7 @@ begin TX_SRC_RDY => rx_usr_mfb_src_rdy_async(i), TX_DST_RDY => rx_usr_mfb_dst_rdy_async(i) ); - + urs_tx_mfb_reconf_i : entity work.MFB_RECONFIGURATOR generic map( RX_REGIONS => DMA_MFB_REGIONS, @@ -424,7 +424,7 @@ begin port map( CLK => USR_CLK, RESET => USR_RESET, - + RX_DATA => tx_usr_mfb_data_async(i), RX_META => tx_usr_mfb_meta_async(i), RX_SOF => tx_usr_mfb_sof_async(i), @@ -433,7 +433,7 @@ begin RX_EOF_POS => tx_usr_mfb_eof_pos_async(i), RX_SRC_RDY => tx_usr_mfb_src_rdy_async(i), RX_DST_RDY => tx_usr_mfb_dst_rdy_async(i), - + TX_DATA => tx_usr_mfb_data_res(i), TX_META => tx_usr_mfb_meta_res(i), TX_SOF => tx_usr_mfb_sof_res(i), diff --git a/core/comp/dma/dma_mod/wrapper/dma_medusa_wrapper_arch.vhd b/core/comp/dma/dma_mod/wrapper/dma_medusa_wrapper_arch.vhd index 2c52e5388..faf53d3e6 100644 --- a/core/comp/dma/dma_mod/wrapper/dma_medusa_wrapper_arch.vhd +++ b/core/comp/dma/dma_mod/wrapper/dma_medusa_wrapper_arch.vhd @@ -329,7 +329,7 @@ begin UP_MVB_VLD => PCIE_RQ_MVB_VLD(DPE), UP_MVB_SRC_RDY => PCIE_RQ_MVB_SRC_RDY(DPE), UP_MVB_DST_RDY => PCIE_RQ_MVB_DST_RDY(DPE), - + UP_MFB_DATA => PCIE_RQ_MFB_DATA(DPE), UP_MFB_SOF => PCIE_RQ_MFB_SOF(DPE), UP_MFB_EOF => PCIE_RQ_MFB_EOF(DPE), @@ -337,12 +337,12 @@ begin UP_MFB_EOF_POS => PCIE_RQ_MFB_EOF_POS(DPE), UP_MFB_SRC_RDY => PCIE_RQ_MFB_SRC_RDY(DPE), UP_MFB_DST_RDY => PCIE_RQ_MFB_DST_RDY(DPE), - + DOWN_MVB_DATA => PCIE_RC_MVB_DATA(DPE), DOWN_MVB_VLD => PCIE_RC_MVB_VLD(DPE), DOWN_MVB_SRC_RDY => PCIE_RC_MVB_SRC_RDY(DPE), DOWN_MVB_DST_RDY => PCIE_RC_MVB_DST_RDY(DPE), - + DOWN_MFB_DATA => PCIE_RC_MFB_DATA(DPE), DOWN_MFB_SOF => PCIE_RC_MFB_SOF(DPE), DOWN_MFB_EOF => PCIE_RC_MFB_EOF(DPE), diff --git a/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl b/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl index 2787f0ae0..c7fef670a 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl +++ b/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl @@ -124,7 +124,7 @@ if { $ARCHGRP == "E_TILE"} { lappend MOD "$ENTITY_BASE/ts_demo_logic.vhd" lappend MOD "$ENTITY_BASE/network_mod_core_etile.vhd" } - + if { $ARCHGRP == "CMAC" } { lappend COMPONENTS [list "ASYNC_RESET" "$ASYNC_BASE/reset" "FULL"] lappend COMPONENTS [list "ASYNC_OPEN_LOOP" "$ASYNC_BASE/open_loop" "FULL"] diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/bridge_drp/bridge_drp.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/bridge_drp/bridge_drp.vhd index 46eac9e23..50bb8309a 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/bridge_drp/bridge_drp.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/bridge_drp/bridge_drp.vhd @@ -39,7 +39,7 @@ entity BRIDGE_DRP is ); end entity; -architecture FULL of BRIDGE_DRP is +architecture FULL of BRIDGE_DRP is signal drp_sel : std_logic_vector (DRPSEL'range); signal drpardy_vld : std_logic; signal drp_rd_sig : std_logic; @@ -54,7 +54,7 @@ begin end if; -- DRPARDY is valid one clock cycle after DRPEN at the earliest drpardy_vld <= DRPEN; - if (DRP_DRDY = '1') then + if (DRP_DRDY = '1') then drp_rd_sig <= '0'; elsif (DRPEN = '1') and (DRPWE = '0') then drp_rd_sig <= '1'; @@ -65,7 +65,7 @@ begin -- Assign WR/RD signals for Eth blocks drd_mux_p: process(all) begin - for j in 0 to MI_SEL_RANGE-1 loop + for j in 0 to MI_SEL_RANGE-1 loop if (MI_EN_MAP(j) = '1') then RECONFIG_ADDR (j) <= DRPADDR(RECONFIG_ADDR(j)'range); RECONFIG_WRITEDATA(j) <= DRPDI; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_1x400g8.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_1x400g8.vhd index 44e941827..16a476c33 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_1x400g8.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_1x400g8.vhd @@ -60,7 +60,7 @@ entity FTILE_1x400g8 is CLK_ETH_OUT : out std_logic; RESET_ETH : in std_logic; -- =================================================================== - -- ADAPTERS link up + -- ADAPTERS link up -- =================================================================== RX_LINK_UP : out std_logic; TX_LINK_UP : out std_logic; @@ -221,8 +221,8 @@ architecture FULL of FTILE_1x400g8 is -- Adress and data range constants for eth and xcvr constant MI_ADDR_WIDTH_PHY : natural := 32; constant MI_DATA_WIDTH_PHY : natural := 32; - - -- monitoring RX link state + + -- monitoring RX link state constant RX_LINK_CNT_W : natural := 27; -- eneable for drp_bridge (xcvr + eth) @@ -248,9 +248,9 @@ architecture FULL of FTILE_1x400g8 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); - -- signals for mi_sel => IP core interface + -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); signal reconfig_readdata_valid : std_logic_vector(MI_SEL_RANGE-1 downto 0); signal reconfig_read : std_logic_vector(MI_SEL_RANGE-1 downto 0); @@ -265,14 +265,14 @@ architecture FULL of FTILE_1x400g8 is signal reconfig_addr_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); signal reconfig_writedata_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_DATA_WIDTH_PHY-1 downto 0); - -- signal for Ftile interface + -- signal for Ftile interface signal ftile_rx_rst_n : std_logic; signal ftile_rx_rst_ack_n : std_logic; signal ftile_tx_lanes_stable : std_logic; signal ftile_rx_pcs_ready : std_logic; signal ftile_rx_block_lock : std_logic; signal ftile_rx_am_lock : std_logic; - signal ftile_local_fault : std_logic; -- not used + signal ftile_local_fault : std_logic; -- not used signal ftile_remote_fault : std_logic; signal ftile_rx_hi_ber : std_logic; signal ftile_rx_pcs_fully_aligned : std_logic; @@ -307,7 +307,7 @@ architecture FULL of FTILE_1x400g8 is signal mgmt_mac_loop : std_logic; signal mgmt_pcs_control : std_logic_vector(16-1 downto 0); signal mgmt_pcs_status : std_logic_vector(16-1 downto 0); - + -- For QuestaSim signal mgmt_pcs_control_dummy : std_logic_vector(15-1 downto 0); @@ -322,7 +322,7 @@ architecture FULL of FTILE_1x400g8 is signal rx_link_rst : std_logic; signal ftile_clk_out : std_logic; - + begin mgmt_i : entity work.mgmt generic map ( @@ -356,7 +356,7 @@ begin BLK_ERR_CNTR => (others => '0'), BLK_ERR_CLR => open, SCR_BYPASS => open, - PCS_RESET => mgmt_pcs_reset, --TODO + PCS_RESET => mgmt_pcs_reset, --TODO PCS_LPBCK => open, PCS_CONTROL(0) => mgmt_mac_loop, PCS_CONTROL(15 downto 1) => mgmt_pcs_control_dummy, @@ -372,7 +372,7 @@ begin PMA_LOPWR => open, PMA_LPBCK => open, PMA_REM_LPBCK => open, - PMA_RESET => mgmt_pma_reset, --TODO + PMA_RESET => mgmt_pma_reset, --TODO PMA_RETUNE => open, PMA_CONTROL => open, PMA_STATUS => (others => '0'), @@ -399,7 +399,7 @@ begin mgmt_pcs_control(15 downto 1) <= (others => '0'); mgmt_pcs_control(0) <= sync_repeater_ctrl; -- MAC loopback active -- MDIO reg 3.4001 (vendor specific PCS status/abilities) - mgmt_pcs_status(15 downto 1) <= (others => '0'); + mgmt_pcs_status(15 downto 1) <= (others => '0'); mgmt_pcs_status(0) <= '1'; -- MAC loopback ability supported drp_bridge_i : entity work.bridge_drp @@ -419,7 +419,7 @@ begin DRPARDY => drpardy, DRPDI => drpdi, DRPSEL => drpsel, - + RECONFIG_ADDR => reconfig_addr_drp, RECONFIG_READDATA_VALID => reconfig_readdata_valid, RECONFIG_READ => reconfig_read_drp, @@ -434,7 +434,7 @@ begin reconfig_readdata_valid (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => '0'); reconfig_waitrequest (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => '0'); reconfig_readdata (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => (others => '0')); - + -- monitoring RX link state process(ftile_clk_out) begin @@ -462,7 +462,7 @@ begin end process; ftile_rx_rst_n <= not rx_link_rst; - + xcvr_reconfig_inf_res_g: for xcvr in PMA_LANES-1 downto 0 generate constant IA_INDEX : natural := 1 + xcvr; @@ -524,7 +524,7 @@ begin mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate mi_ardy_phy(i) <= not reconfig_waitrequest(i); end generate; - + CLK_ETH_OUT <= ftile_clk_out; -- ========================================================================= @@ -749,4 +749,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x100g4.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x100g4.vhd index 351441bde..367e362ca 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x100g4.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x100g4.vhd @@ -73,7 +73,7 @@ entity FTILE_2x100g4 is end entity; architecture FULL of FTILE_2x100g4 is - + -- 100g2 (NRZ) component ftile_eth_2x100g is port ( @@ -169,7 +169,7 @@ architecture FULL of FTILE_2x100g4 is o_reconfig_xcvr3_waitrequest : out std_logic; -- waitrequest i_clk_pll : in std_logic := 'X' -- clk ); - end component ftile_eth_2x100g; + end component ftile_eth_2x100g; -- =================================================================== -- Constants @@ -190,8 +190,8 @@ architecture FULL of FTILE_2x100g4 is -- Adress and data range constants for eth and xcvr constant MI_ADDR_WIDTH_PHY : natural := 32; constant MI_DATA_WIDTH_PHY : natural := 32; - - -- monitoring RX link state + + -- monitoring RX link state constant RX_LINK_CNT_W : natural := 27; -- eneable for drp_bridge (xcvr + eth) @@ -217,7 +217,7 @@ architecture FULL of FTILE_2x100g4 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); @@ -234,7 +234,7 @@ architecture FULL of FTILE_2x100g4 is signal reconfig_addr_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); signal reconfig_writedata_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_DATA_WIDTH_PHY-1 downto 0); - -- signal for Ftile interface + -- signal for Ftile interface signal ftile_rx_rst_n : std_logic; signal ftile_rx_rst_ack_n : std_logic; signal ftile_tx_lanes_stable : std_logic; @@ -327,7 +327,7 @@ begin BLK_ERR_CNTR => (others => '0'), BLK_ERR_CLR => open, SCR_BYPASS => open, - PCS_RESET => mgmt_pcs_reset, --TODO + PCS_RESET => mgmt_pcs_reset, --TODO PCS_LPBCK => open, PCS_CONTROL(0) => mgmt_mac_loop, PCS_CONTROL(15 downto 1) => mgmt_pcs_control_dummy, @@ -343,7 +343,7 @@ begin PMA_LOPWR => open, PMA_LPBCK => open, PMA_REM_LPBCK => open, - PMA_RESET => mgmt_pma_reset, --TODO + PMA_RESET => mgmt_pma_reset, --TODO PMA_RETUNE => open, PMA_CONTROL => open, PMA_STATUS => (others => '0'), @@ -495,7 +495,7 @@ begin mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate mi_ardy_phy(i) <= not reconfig_waitrequest(i); end generate; - + CLK_ETH_OUT <= ftile_clk_out; -- ========================================================================= @@ -682,4 +682,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x200g4.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x200g4.vhd index b9bbbf2f0..926515c40 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x200g4.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x200g4.vhd @@ -188,7 +188,7 @@ architecture FULL of FTILE_2x200g4 is constant MI_ADDR_WIDTH_PHY : natural := 32; constant MI_DATA_WIDTH_PHY : natural := 32; - -- monitoring RX link state + -- monitoring RX link state constant RX_LINK_CNT_W : natural := 27; -- eneable for drp_bridge (xcvr + eth) @@ -214,7 +214,7 @@ architecture FULL of FTILE_2x200g4 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); @@ -239,7 +239,7 @@ architecture FULL of FTILE_2x200g4 is -- signal ftile_pll_refclk : std_logic; signal ftile_rx_block_lock : std_logic; signal ftile_rx_am_lock : std_logic; - signal ftile_local_fault : std_logic; -- not used + signal ftile_local_fault : std_logic; -- not used signal ftile_remote_fault : std_logic; signal ftile_rx_hi_ber : std_logic; signal ftile_rx_pcs_fully_aligned : std_logic; @@ -324,7 +324,7 @@ architecture FULL of FTILE_2x200g4 is BLK_ERR_CNTR => (others => '0'), BLK_ERR_CLR => open, SCR_BYPASS => open, - PCS_RESET => mgmt_pcs_reset, --TODO + PCS_RESET => mgmt_pcs_reset, --TODO PCS_LPBCK => open, PCS_CONTROL(0) => mgmt_mac_loop, PCS_CONTROL(15 downto 1) => mgmt_pcs_control_dummy, @@ -340,7 +340,7 @@ architecture FULL of FTILE_2x200g4 is PMA_LOPWR => open, PMA_LPBCK => open, PMA_REM_LPBCK => open, - PMA_RESET => mgmt_pma_reset, --TODO + PMA_RESET => mgmt_pma_reset, --TODO PMA_RETUNE => open, PMA_CONTROL => open, PMA_STATUS => (others => '0'), @@ -367,7 +367,7 @@ architecture FULL of FTILE_2x200g4 is mgmt_pcs_control(15 downto 1) <= (others => '0'); mgmt_pcs_control(0) <= sync_repeater_ctrl; -- MAC loopback active -- MDIO reg 3.4001 (vendor specific PCS status/abilities) - mgmt_pcs_status(15 downto 1) <= (others => '0'); + mgmt_pcs_status(15 downto 1) <= (others => '0'); mgmt_pcs_status(0) <= '1'; -- MAC loopback ability supported drp_bridge_i : entity work.bridge_drp @@ -492,7 +492,7 @@ architecture FULL of FTILE_2x200g4 is mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate mi_ardy_phy(i) <= not reconfig_waitrequest(i); end generate; - + CLK_ETH_OUT <= ftile_clk_out; -- ========================================================================= @@ -679,4 +679,4 @@ architecture FULL of FTILE_2x200g4 is ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x40g4.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x40g4.vhd index 7c57b483d..026702bbd 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x40g4.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x40g4.vhd @@ -60,7 +60,7 @@ entity FTILE_2x40g4 is CLK_ETH_OUT : out std_logic; RESET_ETH : in std_logic; -- =================================================================== - -- ADAPTERS link up + -- ADAPTERS link up -- =================================================================== RX_LINK_UP : out std_logic; TX_LINK_UP : out std_logic; @@ -73,7 +73,7 @@ entity FTILE_2x40g4 is end entity; architecture FULL of FTILE_2x40g4 is - + component ftile_eth_2x40g is port ( i_clk_tx : in std_logic := 'X'; -- clk @@ -166,7 +166,7 @@ architecture FULL of FTILE_2x40g4 is i_tx_pause : in std_logic := 'X'; -- i_tx_pause o_rx_pause : out std_logic -- o_rx_pause ); - end component ftile_eth_2x40g; + end component ftile_eth_2x40g; -- =================================================================== -- Constants @@ -188,7 +188,7 @@ architecture FULL of FTILE_2x40g4 is constant MI_ADDR_WIDTH_PHY : natural := 32; constant MI_DATA_WIDTH_PHY : natural := 32; - -- monitoring RX link state + -- monitoring RX link state constant RX_LINK_CNT_W : natural := 27; -- eneable for drp_bridge (xcvr + eth) @@ -214,9 +214,9 @@ architecture FULL of FTILE_2x40g4 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); - -- signals for mi_sel => IP core interface + -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); signal reconfig_readdata_valid : std_logic_vector(MI_SEL_RANGE-1 downto 0); signal reconfig_read : std_logic_vector(MI_SEL_RANGE-1 downto 0); @@ -231,7 +231,7 @@ architecture FULL of FTILE_2x40g4 is signal reconfig_addr_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); signal reconfig_writedata_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_DATA_WIDTH_PHY-1 downto 0); - -- signal for Ftile interface + -- signal for Ftile interface signal ftile_rx_rst_n : std_logic; signal ftile_rx_rst_ack_n : std_logic; signal ftile_tx_lanes_stable : std_logic; @@ -290,7 +290,7 @@ architecture FULL of FTILE_2x40g4 is signal rx_link_rst : std_logic; signal ftile_clk_out : std_logic; - + begin mgmt_i : entity work.mgmt generic map ( @@ -324,7 +324,7 @@ begin BLK_ERR_CNTR => (others => '0'), BLK_ERR_CLR => open, SCR_BYPASS => open, - PCS_RESET => mgmt_pcs_reset, --TODO + PCS_RESET => mgmt_pcs_reset, --TODO PCS_LPBCK => open, PCS_CONTROL(0) => mgmt_mac_loop, PCS_CONTROL(15 downto 1) => mgmt_pcs_control_dummy, @@ -340,7 +340,7 @@ begin PMA_LOPWR => open, PMA_LPBCK => open, PMA_REM_LPBCK => open, - PMA_RESET => mgmt_pma_reset, --TODO + PMA_RESET => mgmt_pma_reset, --TODO PMA_RETUNE => open, PMA_CONTROL => open, PMA_STATUS => (others => '0'), @@ -367,7 +367,7 @@ begin mgmt_pcs_control(15 downto 1) <= (others => '0'); mgmt_pcs_control(0) <= sync_repeater_ctrl; -- MAC loopback active -- MDIO reg 3.4001 (vendor specific PCS status/abilities) - mgmt_pcs_status(15 downto 1) <= (others => '0'); + mgmt_pcs_status(15 downto 1) <= (others => '0'); mgmt_pcs_status(0) <= '1'; -- MAC loopback ability supported drp_bridge_i : entity work.bridge_drp @@ -430,7 +430,7 @@ begin end process; ftile_rx_rst_n <= not rx_link_rst; - + xcvr_reconfig_inf_res_g: for xcvr in PMA_LANES-1 downto 0 generate constant IA_INDEX : natural := 1 + xcvr; @@ -458,7 +458,7 @@ begin reconfig_writedata (IA_INDEX) <= init_writedata when init_busy = '1' else reconfig_writedata_drp (IA_INDEX); - + init_done_g: if (xcvr = 0) generate init_ready(0) <= ftile_tx_lanes_stable; else generate @@ -493,7 +493,7 @@ begin mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate mi_ardy_phy(i) <= not reconfig_waitrequest(i); end generate; - + CLK_ETH_OUT <= ftile_clk_out; -- ========================================================================= @@ -680,4 +680,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_4x100g2.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_4x100g2.vhd index 0290b4bed..2388bbcd9 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_4x100g2.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_4x100g2.vhd @@ -158,7 +158,7 @@ architecture FULL of FTILE_4x100g2 is -- constants for IP core setup constant NUM_LANES : natural := 20; constant PMA_LANES : natural := 2; - constant ETH_PORT_CHAN : natural := 1; + constant ETH_PORT_CHAN : natural := 1; constant SPEED : natural := 100; constant SPEED_CAP : std_logic_vector(15 downto 0) := X"0200"; constant DEVICE : string := "AGILEX"; @@ -172,7 +172,7 @@ architecture FULL of FTILE_4x100g2 is constant MI_ADDR_WIDTH_PHY : natural := 32; constant MI_DATA_WIDTH_PHY : natural := 32; - -- monitoring RX link state + -- monitoring RX link state constant RX_LINK_CNT_W : natural := 27; -- eneable for drp_bridge (xcvr + eth) @@ -198,9 +198,9 @@ architecture FULL of FTILE_4x100g2 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); - -- signals for mi_sel => IP core interface + -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); signal reconfig_readdata_valid : std_logic_vector(MI_SEL_RANGE-1 downto 0); signal reconfig_read : std_logic_vector(MI_SEL_RANGE-1 downto 0); @@ -215,7 +215,7 @@ architecture FULL of FTILE_4x100g2 is signal reconfig_addr_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); signal reconfig_writedata_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_DATA_WIDTH_PHY-1 downto 0); - -- signal for Ftile interface + -- signal for Ftile interface signal ftile_rx_rst_n : std_logic; signal ftile_rx_rst_ack_n : std_logic; signal ftile_tx_lanes_stable : std_logic; @@ -274,7 +274,7 @@ architecture FULL of FTILE_4x100g2 is signal rx_link_rst : std_logic; signal ftile_clk_out : std_logic; - + begin mgmt_i : entity work.mgmt generic map ( @@ -351,7 +351,7 @@ begin mgmt_pcs_control(15 downto 1) <= (others => '0'); mgmt_pcs_control(0) <= sync_repeater_ctrl; -- MAC loopback active -- MDIO reg 3.4001 (vendor specific PCS status/abilities) - mgmt_pcs_status(15 downto 1) <= (others => '0'); + mgmt_pcs_status(15 downto 1) <= (others => '0'); mgmt_pcs_status(0) <= '1'; -- MAC loopback ability supported drp_bridge_i : entity work.bridge_drp @@ -476,7 +476,7 @@ begin mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate mi_ardy_phy(i) <= not reconfig_waitrequest(i); end generate; - + CLK_ETH_OUT <= ftile_clk_out; -- ========================================================================= @@ -645,4 +645,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x10g1.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x10g1.vhd index cf63b16c9..68183a9f7 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x10g1.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x10g1.vhd @@ -187,7 +187,7 @@ architecture FULL of FTILE_8x10g1 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); @@ -297,7 +297,7 @@ begin BLK_ERR_CNTR => (others => '0'), BLK_ERR_CLR => open, SCR_BYPASS => open, - PCS_RESET => mgmt_pcs_reset, --TODO + PCS_RESET => mgmt_pcs_reset, --TODO PCS_LPBCK => open, PCS_CONTROL(0) => mgmt_mac_loop, PCS_CONTROL(15 downto 1) => mgmt_pcs_control_dummy, @@ -313,7 +313,7 @@ begin PMA_LOPWR => open, PMA_LPBCK => open, PMA_REM_LPBCK => open, - PMA_RESET => mgmt_pma_reset, --TODO + PMA_RESET => mgmt_pma_reset, --TODO PMA_RETUNE => open, PMA_CONTROL => open, PMA_STATUS => (others => '0'), @@ -605,7 +605,7 @@ begin OUT_MAC_READY => ftile_tx_mac_ready ); - + ftile_tx_mux: process(all) begin if sync_repeater_ctrl = '1' then @@ -624,4 +624,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x25g1.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x25g1.vhd index c1f5c8588..fe8df1db2 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x25g1.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x25g1.vhd @@ -163,7 +163,7 @@ architecture FULL of FTILE_8x25g1 is -- Adress and data range constants for eth and xcvr constant MI_ADDR_WIDTH_PHY : natural := 32; -- not sure constant MI_DATA_WIDTH_PHY : natural := 32; - + -- monitoring RX link state constant RX_LINK_CNT_W : natural := 27; @@ -172,7 +172,7 @@ architecture FULL of FTILE_8x25g1 is -- eneable for drp_bridge (xcvr + eth) constant MI_EN_MAP : std_logic_vector(16-1 downto 0) := "0000000000000011"; - + -- constant for segments for macseg_loop size constant SEGMENTS_LOOP : natural := 1; @@ -190,7 +190,7 @@ architecture FULL of FTILE_8x25g1 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); @@ -300,7 +300,7 @@ begin BLK_ERR_CNTR => (others => '0'), BLK_ERR_CLR => open, SCR_BYPASS => open, - PCS_RESET => mgmt_pcs_reset, --TODO + PCS_RESET => mgmt_pcs_reset, --TODO PCS_LPBCK => open, PCS_CONTROL(0) => mgmt_mac_loop, PCS_CONTROL(15 downto 1) => mgmt_pcs_control_dummy, @@ -316,7 +316,7 @@ begin PMA_LOPWR => open, PMA_LPBCK => open, PMA_REM_LPBCK => open, - PMA_RESET => mgmt_pma_reset, --TODO + PMA_RESET => mgmt_pma_reset, --TODO PMA_RETUNE => open, PMA_CONTROL => open, PMA_STATUS => (others => '0'), @@ -343,7 +343,7 @@ begin mgmt_pcs_control(15 downto 1) <= (others => '0'); mgmt_pcs_control(0) <= sync_repeater_ctrl; -- MAC loopback active -- MDIO reg 3.4001 (vendor specific PCS status/abilities) - mgmt_pcs_status(15 downto 1) <= (others => '0'); + mgmt_pcs_status(15 downto 1) <= (others => '0'); mgmt_pcs_status(0) <= '1'; -- MAC loopback ability supported drp_bridge_i : entity work.bridge_drp @@ -363,7 +363,7 @@ begin DRPARDY => drpardy, DRPDI => drpdi, DRPSEL => drpsel, - + RECONFIG_ADDR => reconfig_addr_drp, RECONFIG_READDATA_VALID => reconfig_readdata_valid, RECONFIG_READ => reconfig_read_drp, @@ -626,4 +626,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x50g1.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x50g1.vhd index c129c4ee0..fb3777b1e 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x50g1.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x50g1.vhd @@ -150,7 +150,7 @@ architecture FULL of FTILE_8x50g1 is -- constants for IP core setup constant NUM_LANES : natural := 4; constant PMA_LANES : natural := 1; - constant ETH_PORT_CHAN : natural := 1; + constant ETH_PORT_CHAN : natural := 1; constant SPEED : natural := 50; constant SPEED_CAP : std_logic_vector(15 downto 0) := X"0008"; constant DEVICE : string := "AGILEX"; @@ -190,7 +190,7 @@ architecture FULL of FTILE_8x50g1 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); @@ -343,7 +343,7 @@ begin mgmt_pcs_control(15 downto 1) <= (others => '0'); mgmt_pcs_control(0) <= sync_repeater_ctrl; -- MAC loopback active -- MDIO reg 3.4001 (vendor specific PCS status/abilities) - mgmt_pcs_status(15 downto 1) <= (others => '0'); + mgmt_pcs_status(15 downto 1) <= (others => '0'); mgmt_pcs_status(0) <= '1'; -- MAC loopback ability supported drp_bridge_i : entity work.bridge_drp @@ -433,7 +433,7 @@ begin reconfig_writedata (IA_INDEX) <= init_writedata when init_busy = '1' else reconfig_writedata_drp (IA_INDEX); - + init_done_g: if (xcvr = 0) generate init_ready(0) <= ftile_tx_lanes_stable; else generate @@ -468,7 +468,7 @@ begin mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate mi_ardy_phy(i) <= not reconfig_waitrequest(i); end generate; - + CLK_ETH_OUT <= ftile_clk_out; -- ========================================================================= @@ -628,4 +628,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_2x100g4.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_2x100g4.vhd index 7e65aad46..6356fca5c 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_2x100g4.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_2x100g4.vhd @@ -281,7 +281,7 @@ architecture FULL of FTILE_MULTIRATE_ETH_2x100G4 is ); end component ftile_multirate_eth_1x100g; - -- Dynamic reconfiguration controller for the multirate IP + -- Dynamic reconfiguration controller for the multirate IP component dr_ctrl is port ( i_csr_clk : in std_logic := 'X'; -- clk @@ -478,7 +478,7 @@ begin BLK_ERR_CNTR => (others => '0'), BLK_ERR_CLR => open, SCR_BYPASS => open, - PCS_RESET => mgmt_pcs_reset, --TODO + PCS_RESET => mgmt_pcs_reset, --TODO PCS_LPBCK => open, PCS_CONTROL(0) => mgmt_mac_loop, PCS_CONTROL(15 downto 1) => mgmt_pcs_control_dummy, @@ -494,7 +494,7 @@ begin PMA_LOPWR => open, PMA_LPBCK => open, PMA_REM_LPBCK => open, - PMA_RESET => mgmt_pma_reset, --TODO + PMA_RESET => mgmt_pma_reset, --TODO PMA_RETUNE => open, PMA_CONTROL => open, PMA_STATUS => (others => '0'), @@ -521,7 +521,7 @@ begin mgmt_pcs_control(15 downto 1) <= (others => '0'); mgmt_pcs_control(0) <= sync_repeater_ctrl; -- MAC loopback active -- MDIO reg 3.4001 (vendor specific PCS status/abilities) - mgmt_pcs_status(15 downto 1) <= (others => '0'); + mgmt_pcs_status(15 downto 1) <= (others => '0'); mgmt_pcs_status(0) <= '1'; -- MAC loopback ability supported drp_bridge_i : entity work.bridge_drp @@ -616,7 +616,7 @@ begin reconfig_writedata (IA_INDEX) <= init_writedata when init_busy = '1' else reconfig_writedata_drp (IA_INDEX); - + init_done_g: if (xcvr = 0) generate init_ready(0) <= ftile_tx_lanes_stable; else generate @@ -989,4 +989,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_8x25g1_8x10g1.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_8x25g1_8x10g1.vhd index de24b8a0e..080c5fda3 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_8x25g1_8x10g1.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_8x25g1_8x10g1.vhd @@ -67,7 +67,7 @@ entity FTILE_MULTIRATE_ETH_8x25G1_8x10G1 is CLK_ETH_OUT : out std_logic; RESET_ETH : in std_logic; -- =================================================================== - -- ADAPTERS link up + -- ADAPTERS link up -- =================================================================== RX_LINK_UP : out std_logic; TX_LINK_UP : out std_logic; @@ -155,7 +155,7 @@ architecture FULL of FTILE_MULTIRATE_ETH_8x25G1_8x10G1 is ); end component ftile_multirate_eth_1x25g_1x10g; - -- Dynamic reconfiguration controller for the multirate IP + -- Dynamic reconfiguration controller for the multirate IP component dr_ctrl is port ( i_csr_clk : in std_logic := 'X'; -- clk @@ -199,7 +199,7 @@ architecture FULL of FTILE_MULTIRATE_ETH_8x25G1_8x10G1 is -- constants for IP core setup constant NUM_LANES : natural := 1; constant PMA_LANES : natural := 1; - constant ETH_PORT_CHAN : natural := 1; + constant ETH_PORT_CHAN : natural := 1; constant SPEED : natural := 25; constant SPEED_CAP : std_logic_vector(15 downto 0) := X"0800"; constant DEVICE : string := "AGILEX"; @@ -212,7 +212,7 @@ architecture FULL of FTILE_MULTIRATE_ETH_8x25G1_8x10G1 is ---- Adress and data range constants for eth and xcvr constant MI_ADDR_WIDTH_PHY : natural := 32; constant MI_DATA_WIDTH_PHY : natural := 32; - + -- monitoring RX link state constant RX_LINK_CNT_W : natural := 27; @@ -233,7 +233,7 @@ architecture FULL of FTILE_MULTIRATE_ETH_8x25G1_8x10G1 is signal drpaddr : std_logic_vector(MI_ADDR_WIDTH_PHY-1 downto 0); signal drpardy : std_logic; signal drpdi : std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0); - signal drpsel : std_logic_vector(4-1 downto 0); + signal drpsel : std_logic_vector(4-1 downto 0); -- signals for mi_sel => IP core interface signal reconfig_addr : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_ADDR_WIDTH_PHY-1 downto 0); @@ -251,7 +251,7 @@ architecture FULL of FTILE_MULTIRATE_ETH_8x25G1_8x10G1 is signal reconfig_writedata_drp : slv_array_t (MI_SEL_RANGE-1 downto 0)(MI_DATA_WIDTH_PHY-1 downto 0); signal reconfig_waitrequest_drp : std_logic_vector(MI_SEL_RANGE-1 downto 0) := (others => '0'); - -- signal for Ftile interface + -- signal for Ftile interface signal ftile_rx_rst_n : std_logic; signal ftile_rx_rst_ack_n : std_logic; signal ftile_tx_lanes_stable : std_logic; @@ -516,7 +516,7 @@ begin mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate reconfig_waitrequest_drp(i) <= not reconfig_waitrequest(i); end generate; - + CLK_ETH_OUT <= ftile_clk_out; -- ========================================================================= -- DR_CTRL @@ -708,4 +708,4 @@ begin ftile_tx_mac_valid <= TX_MACSI_ADAPT_VALID; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd index 1e12df4f9..95a4c1b65 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd @@ -30,7 +30,7 @@ port ( IN_MAC_ERROR : in slv_array_t (CHANNELS-1 downto 0)(ERROR_WIDTH -1 downto 0); IN_MAC_STATUS : in slv_array_t (CHANNELS-1 downto 0)(STATUS_WIDTH -1 downto 0); IN_MAC_VALID : in std_logic_vector (CHANNELS-1 downto 0); - + -- OUTPUT OUT_MAC_DATA : out slv_array_t (CHANNELS-1 downto 0)(DATA_WIDTH -1 downto 0); OUT_MAC_INFRAME : out slv_array_t (CHANNELS-1 downto 0)(INFRAME_WIDTH -1 downto 0); diff --git a/core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.rst b/core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.rst index 166c8873a..742c962ba 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.rst +++ b/core/comp/eth/network_mod/comp/network_mod_core/doc/f-tile_multirate_ip.rst @@ -1,9 +1,9 @@ .. _ndk_f-tile_multirate: -F-Tile Multirate IP +F-Tile Multirate IP =================== -Implemented IP cores +Implemented IP cores -------------------- Right now, you can use two designs with Multirate IP. These designs have optimized parameters, so you do not need to change anything. @@ -13,7 +13,7 @@ If you want to make a build with Multirate IP, check the ``Makefile`` file for a Build tips ---------- -The first step is to make a build. If an error during the build occurs, here are a few tips to help you to fix them. +The first step is to make a build. If an error during the build occurs, here are a few tips to help you to fix them. If you have a problem during the build with Timing analysis and it seems that it could be because of asynchronous clk signals, look into the ``timing.sdc`` file. There is the declaration of asynchronous clocks for both Multirate IP cores. If you have a problem with the Profile ID setup for Dynamic Reconfiguration, look into ``multirate.qsf``. There is the declaration of profiles for both types of IP cores (100G and 25G) and it is set by its setup (the order of profiles when the IP was generated). These assignments allow you to set the order of all profiles (from 0 to ...) for all IP cores. If you have other problems, look into Intel's documentation: :ref:`Intel F-Tile Ethernet Multirate Intel FPGA IP User Guide ` and :ref:`Intel F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide `. diff --git a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_cmac.vhd b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_cmac.vhd index 3585a65cc..8089eefc4 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_cmac.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_cmac.vhd @@ -451,7 +451,7 @@ architecture CMAC of NETWORK_MOD_CORE is signal cmac_rx_pcsl_number : std_logic_vector(NUM_LANES*5-1 downto 0); signal cmac_rx_synced : std_logic_vector(NUM_LANES-1 downto 0); signal mgmt_pma_loopback : std_logic; - signal mgmt_pma_rem_loopback : std_logic; + signal mgmt_pma_rem_loopback : std_logic; signal mgmt_pcs_rev_loopback : std_logic; signal mgmt_pma_reset : std_logic; signal mgmt_gt_precursor : std_logic_vector(32-1 downto 0); @@ -580,9 +580,9 @@ begin SPEED => ETH_PORT_SPEED, SPEED_CAP => SPEED_CAP, RSFEC_ABLE => '1', - PMA_PRECURSOR_INIT => X"000" & GTY_TX_EQ(3*20-1 downto 2*20), + PMA_PRECURSOR_INIT => X"000" & GTY_TX_EQ(3*20-1 downto 2*20), PMA_POSTCURSOR_INIT => X"000" & GTY_TX_EQ(2*20-1 downto 1*20), - PMA_DRIVE_INIT => X"000" & GTY_TX_EQ(1*20-1 downto 0*20), + PMA_DRIVE_INIT => X"000" & GTY_TX_EQ(1*20-1 downto 0*20), DEVICE => DEVICE ) port map ( @@ -619,7 +619,7 @@ begin -- PMA & PMD status/control PMA_LOPWR => open, PMA_LPBCK => mgmt_pma_loopback, - PMA_REM_LPBCK => mgmt_pma_rem_loopback, + PMA_REM_LPBCK => mgmt_pma_rem_loopback, PMA_RESET => mgmt_pma_reset, PMA_RETUNE => open, PMA_CONTROL => open, @@ -649,7 +649,7 @@ begin -- FEC PCS stats FEC_TX_BIP => (others => '0'), FEC_TX_LANE_MAP => X"0013001200110010000f000e000d000c000b000a0009000800070006000500040003000200010000", - FEC_TX_BLK_LOCK => (others => '1'), + FEC_TX_BLK_LOCK => (others => '1'), FEC_TX_ALGN_STAT => (others => '1'), -- DRP interface DRPCLK => MI_CLK_PHY, @@ -965,10 +965,10 @@ begin cmac_clk_322m <= cmac_gt_tx_clk_322m; CLK_ETH <= cmac_clk_322m; - + -- CMAC reset cmac_rst_async <= RESET_ETH or (not (and cmac_gt_pwrgood)); - + cmac_rst_322m_i : entity work.ASYNC_RESET generic map ( TWO_REG => false, @@ -985,10 +985,10 @@ begin cmac_gt_loopback <= "010010010010" when (mgmt_pma_loopback = '1') else -- Near end PMA loopback "100100100100" when (mgmt_pma_rem_loopback = '1') or (mgmt_pcs_rev_loopback = '1') else -- Far end PMA loopback "000000000000"; -- Normal operation - - -- Disable polarity swaps when loopback is active + + -- Disable polarity swaps when loopback is active gt_rxpolarity <= (others => '0') when cmac_gt_loopback(1) = '1' else LANE_RX_POLARITY; - gt_txpolarity <= (others => '0') when cmac_gt_loopback(1) = '1' else LANE_TX_POLARITY; + gt_txpolarity <= (others => '0') when cmac_gt_loopback(1) = '1' else LANE_TX_POLARITY; rxpol_g: for i in LANE_RX_POLARITY'range generate rxpol_sync_i : entity work.ASYNC_OPEN_LOOP @@ -1100,12 +1100,12 @@ begin gt_rxrate => (others => '0'), gt_txpolarity => cmac_gt_txpolarity, gt_txinhibit => (others => '0'), - -- - gt_txdiffctrl => mgmt_gt_txdiffctrl(19 downto 0), + -- + gt_txdiffctrl => mgmt_gt_txdiffctrl(19 downto 0), gt_txpostcursor => mgmt_gt_postcursor(19 downto 0), gt_txprecursor => mgmt_gt_precursor(19 downto 0), -- - gt_txprbsforceerr => (others => '0'), + gt_txprbsforceerr => (others => '0'), gt_eyescandataerror => open, gt_txbufstatus => open, gt_rxdfelpmreset => (others => '0'), diff --git a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd index 5e6bff64f..086a18c0e 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd @@ -34,7 +34,7 @@ generic( LANES : natural := 8; -- Type of used IP core -- Options: "EHIP=0" , "F-Tile" ; - -- "EHIP>=1", "F-Tile_Multirate"; + -- "EHIP>=1", "F-Tile_Multirate"; EHIP_TYPE : natural := 0; -- ===================================================================== -- MFB configuration: @@ -88,8 +88,8 @@ port( QSFP_TX_N : out std_logic_vector(LANES-1 downto 0); -- QSFP XCVR TX Data -- ===================================================================== - -- Link control/status - -- ===================================================================== + -- Link control/status + -- ===================================================================== -- REPEATER_CTRL : in std_logic_vector(1 downto 0); -- PORT_ENABLED : out std_logic; RX_LINK_UP : out std_logic_vector(ETH_PORT_CHAN-1 downto 0); @@ -114,7 +114,7 @@ port( TSU_TS_NS : in std_logic_vector(64-1 downto 0); TSU_TS_DV : in std_logic; - + -- ===================================================================== -- TX interface (Packets received from Ethernet, for transmit to MFB) -- ===================================================================== diff --git a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd index fb59b1a59..b43ef3198 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd @@ -264,7 +264,7 @@ architecture FULL of NETWORK_MOD_CORE is in_refclk_fgt_0 => QSFP_REFCLK_P ); - -- devide input data to x lines serial lines + -- devide input data to x lines serial lines qsfp_rx_p_sig <= slv_array_deser(QSFP_RX_P, ETH_PORT_CHAN); qsfp_rx_n_sig <= slv_array_deser(QSFP_RX_N, ETH_PORT_CHAN); QSFP_TX_P <= slv_array_ser(qsfp_tx_p_sig); @@ -277,7 +277,7 @@ architecture FULL of NETWORK_MOD_CORE is ftile_1x400g8_g : if ((ETH_PORT_SPEED = 400) and (EHIP_TYPE = 0)) generate eth_ip_g : for i in ETH_PORT_CHAN-1 downto 0 generate - FTILE_1x400g8_i: entity work.FTILE_1x400G8 + FTILE_1x400g8_i: entity work.FTILE_1x400G8 port map( MI_RESET_PHY => MI_RESET_PHY , MI_CLK_PHY => MI_CLK_PHY , @@ -326,7 +326,7 @@ architecture FULL of NETWORK_MOD_CORE is ftile_2x200g4_g : if ((ETH_PORT_SPEED = 200) and (EHIP_TYPE = 0)) generate eth_ip_g : for i in ETH_PORT_CHAN-1 downto 0 generate - ftile_2x200g4_i: entity work.FTILE_2x200g4 + ftile_2x200g4_i: entity work.FTILE_2x200g4 port map( MI_RESET_PHY => MI_RESET_PHY , MI_CLK_PHY => MI_CLK_PHY , @@ -375,7 +375,7 @@ architecture FULL of NETWORK_MOD_CORE is ftile_4x100g2_g : if (((ETH_PORT_SPEED = 100) and (EHIP_TYPE = 0)) and (ETH_PORT_CHAN = 4)) generate eth_ip_g : for i in ETH_PORT_CHAN-1 downto 0 generate - FTILE_4x100g2_i: entity work.FTILE_4x100g2 + FTILE_4x100g2_i: entity work.FTILE_4x100g2 port map( MI_RESET_PHY => MI_RESET_PHY , MI_CLK_PHY => MI_CLK_PHY , @@ -465,7 +465,7 @@ architecture FULL of NETWORK_MOD_CORE is RX_LINK_UP => RX_LINK_UP(i), TX_LINK_UP => TX_LINK_UP(i), - + FTILE_PLL_CLK => ftile_pll_clk, FTILE_PLL_REFCLK => ftile_pll_refclk ); @@ -523,7 +523,7 @@ architecture FULL of NETWORK_MOD_CORE is -- generic for 50G 1 line F-Tile IP core 8 times for one card ftile_8x50g1_g : if ((ETH_PORT_SPEED = 50) and (EHIP_TYPE = 0)) generate eth_ip_g : for i in ETH_PORT_CHAN-1 downto 0 generate - FTILE_8x50g1_i: entity work.FTILE_8x50g1 + FTILE_8x50g1_i: entity work.FTILE_8x50g1 port map( MI_RESET_PHY => MI_RESET_PHY , MI_CLK_PHY => MI_CLK_PHY , @@ -571,7 +571,7 @@ architecture FULL of NETWORK_MOD_CORE is -- generic for 40G 4 line F-Tile IP core 2 times for one card ftile_2x40g4_g : if ((ETH_PORT_SPEED = 40) and (EHIP_TYPE = 0)) generate eth_ip_g : for i in ETH_PORT_CHAN-1 downto 0 generate - FTILE_2x40g4_i: entity work.FTILE_2x40g4 + FTILE_2x40g4_i: entity work.FTILE_2x40g4 port map( MI_RESET_PHY => MI_RESET_PHY , MI_CLK_PHY => MI_CLK_PHY , @@ -620,7 +620,7 @@ architecture FULL of NETWORK_MOD_CORE is ftile_8x25g1_g : if ((ETH_PORT_SPEED = 25) and (EHIP_TYPE = 0)) generate eth_ip_g : for i in ETH_PORT_CHAN-1 downto 0 generate - FTILE_8x25g1_i: entity work.FTILE_8x25g1 + FTILE_8x25g1_i: entity work.FTILE_8x25g1 port map( MI_RESET_PHY => MI_RESET_PHY , MI_CLK_PHY => MI_CLK_PHY , @@ -721,7 +721,7 @@ architecture FULL of NETWORK_MOD_CORE is ftile_8x10g1_g : if ((ETH_PORT_SPEED = 10) and (EHIP_TYPE = 0)) generate eth_ip_g : for i in ETH_PORT_CHAN-1 downto 0 generate - FTILE_8x10g1_i: entity work.FTILE_8x10g1 + FTILE_8x10g1_i: entity work.FTILE_8x10g1 port map( MI_RESET_PHY => MI_RESET_PHY , MI_CLK_PHY => MI_CLK_PHY , diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/network_mod_logic.vhd b/core/comp/eth/network_mod/comp/network_mod_logic/network_mod_logic.vhd index a200baa68..a75af577a 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/network_mod_logic.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_logic/network_mod_logic.vhd @@ -237,12 +237,12 @@ architecture FULL of NETWORK_MOD_LOGIC is begin - assert (ETH_STREAMS = ETH_PORT_CHAN or ETH_STREAMS = 1) - report "NETWORK_MOD_LOGIC: ETH_STREAMS must be equal to 1 or ETH_PORT_CHAN!" + assert (ETH_STREAMS = ETH_PORT_CHAN or ETH_STREAMS = 1) + report "NETWORK_MOD_LOGIC: ETH_STREAMS must be equal to 1 or ETH_PORT_CHAN!" severity failure; - assert ((ETH_STREAMS = ETH_PORT_CHAN and ETH_MAC_BYPASS = True) or (ETH_MAC_BYPASS = False)) - report "NETWORK_MOD_LOGIC: ETH_MAC_BYPASS is supported only when ETH_STREAMS = ETH_PORT_CHAN!" + assert ((ETH_STREAMS = ETH_PORT_CHAN and ETH_MAC_BYPASS = True) or (ETH_MAC_BYPASS = False)) + report "NETWORK_MOD_LOGIC: ETH_MAC_BYPASS is supported only when ETH_STREAMS = ETH_PORT_CHAN!" severity failure; mi_splitter_g: if not ETH_MAC_BYPASS generate @@ -272,7 +272,7 @@ begin RX_ARDY => MI_ARDY , RX_DRD => MI_DRD , RX_DRDY => MI_DRDY , - + TX_DWR => mi_split_dwr , TX_MWR => open , TX_ADDR => mi_split_addr , @@ -286,7 +286,7 @@ begin else generate MI_ARDY <= MI_RD or MI_WR; MI_DRDY <= MI_RD; - MI_DRD <= X"DEADCAFE"; + MI_DRD <= X"DEADCAFE"; end generate; -- ========================================================================= @@ -300,7 +300,7 @@ begin split_addr_arr (r) <= eth_hdr_tx_port_arr(r)(max(1,log2(ETH_PORT_CHAN))-1 downto 0); end generate; split_addr <= slv_array_ser(split_addr_arr); - + -- Split one ETH_STREAM into ETH_CHANNELS for each TX MAC Lite mfb_splitter_tree_i : entity work.MFB_SPLITTER_SIMPLE_GEN generic map( diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals.fdo b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals.fdo index 8e041ead5..ceae2ab00 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals.fdo +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals.fdo @@ -10,11 +10,11 @@ proc all {NAME PATH} { } proc rx {NAME PATH} { - add wave -divider "$NAME" + add wave -divider "$NAME" add_wave "-noupdate -hex" $PATH/RX_* } proc tx {NAME PATH} { - add wave -divider "$NAME" + add wave -divider "$NAME" add_wave "-noupdate -hex" $PATH/TX_* } diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals_sig.fdo b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals_sig.fdo index 86c866578..f76844ef4 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals_sig.fdo +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/signals_sig.fdo @@ -1,4 +1,4 @@ -# signal_sig.fdo : Include file with signals +# signal_sig.fdo : Include file with signals # Copyright (C) 2022 CESNET z. s. p. o. # Author(s): Daniel Kondys diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/dut.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/dut.sv index e8dc6a216..7fc24debc 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/dut.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/dut.sv @@ -1,8 +1,8 @@ -// dut.sv: Design under test +// dut.sv: Design under test // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause import test::*; @@ -166,6 +166,6 @@ module DUT ( assign mvb_vld[j] = VHDL_DUT_U.rx_g[j].rx_mac_g.rx_mac_i.s_stin_valid; end endgenerate - + endmodule diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/env.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/env.sv index fc856a801..b2d54f042 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/env.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/env.sv @@ -2,7 +2,7 @@ // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause class env_base #(USER_REGIONS, USER_REGION_SIZE, CORE_REGIONS, CORE_REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH, USER_MVB_WIDTH, ETH_CHANNELS, RX_MAC_LITE_REGIONS) extends uvm_env; diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/model.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/model.sv index ad6f31d97..6d67ebc20 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/model.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/model.sv @@ -2,7 +2,7 @@ // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause class model_data#(ITEM_WIDTH, META_WIDTH) extends uvm_common::sequence_item; `uvm_object_param_utils(net_mod_logic_env::model_data#(ITEM_WIDTH, META_WIDTH)) @@ -127,7 +127,7 @@ class model #(CHANNELS, ITEM_WIDTH, META_WIDTH, HDR_WIDTH) extends uvm_component task run_phase(uvm_phase phase); for (int unsigned ch = 0; ch < CHANNELS; ch++) begin - fork + fork automatic int unsigned index = ch; rx_run(index); join_none; diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/pkg.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/pkg.sv index 794fec9e3..c1a67258f 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/pkg.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/pkg.sv @@ -2,7 +2,7 @@ // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause `ifndef NET_MOD_LOGIC_ENV_SV `define NET_MOD_LOGIC_ENV_SV @@ -23,4 +23,4 @@ package net_mod_logic_env; endpackage -`endif \ No newline at end of file +`endif diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/reg_seq.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/reg_seq.sv index 0adcd190c..cfa255d20 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/reg_seq.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/reg_seq.sv @@ -24,4 +24,4 @@ class sequence_simple #(ETH_CHANNELS) extends uvm_sequence; #(100); end endtask -endclass \ No newline at end of file +endclass diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/registers.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/registers.sv index 3cd8d74ac..5606d1ada 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/registers.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/registers.sv @@ -30,8 +30,8 @@ class mac_control extends uvm_reg; 0 , // Value on reset 1 , // Can the value be reset? 0 , // Can the value be randomized? - 0 // Does the field occupy an entire byte lane? + 0 // Does the field occupy an entire byte lane? ); - + endfunction endclass diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/scoreboard.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/scoreboard.sv index bbec4ada7..136184c12 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/scoreboard.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/scoreboard.sv @@ -32,7 +32,7 @@ class model_input_fifo#(ITEM_WIDTH, META_WIDTH) extends uvm_component; function new(string name, uvm_component parent = null); super.new(name, parent); - analysis_export_data = new("analysis_export_data", this); + analysis_export_data = new("analysis_export_data", this); analysis_export_meta = new("analysis_export_meta", this); port = new("port", this); endfunction @@ -107,7 +107,7 @@ class scoreboard #(CHANNELS, REGIONS, ITEM_WIDTH, META_WIDTH, HDR_WIDTH, RX_MAC_ // TX path uvm_analysis_export #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) tx_input_data; uvm_analysis_export #(uvm_logic_vector::sequence_item #(META_WIDTH)) tx_input_meta; - protected model_input_fifo#(ITEM_WIDTH, META_WIDTH) tx_input; + protected model_input_fifo#(ITEM_WIDTH, META_WIDTH) tx_input; uvm_analysis_export #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) tx_out[CHANNELS]; //comparesrs diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/sequencer.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/sequencer.sv index ad59d4cf3..d4137c8f0 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/sequencer.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/env/sequencer.sv @@ -1,8 +1,8 @@ -// sequencer.sv: Virtual sequencer +// sequencer.sv: Virtual sequencer // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause class virt_sequencer#(ITEM_WIDTH, META_WIDTH) extends uvm_sequencer; `uvm_component_param_utils(virt_sequencer#(ITEM_WIDTH, META_WIDTH)) diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/testbench.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/testbench.sv index 904147023..e9efd35d4 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/testbench.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/testbench.sv @@ -2,7 +2,7 @@ // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause import uvm_pkg::*; `include "uvm_macros.svh" diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/pkg.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/pkg.sv index edd8eeac1..ea91cb726 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/pkg.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/pkg.sv @@ -2,7 +2,7 @@ // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause `ifndef SPLITTER_SIMPLE_TEST_SV `define SPLITTER_SIMPLE_TEST_SV diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/test.sv b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/test.sv index bc07eb694..0f8b8b002 100644 --- a/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/test.sv +++ b/core/comp/eth/network_mod/comp/network_mod_logic/uvm/tbench/tests/test.sv @@ -2,7 +2,7 @@ // Copyright (C) 2022 CESNET z. s. p. o. // Author(s): Daniel Kondys -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause class ex_test extends uvm_test; @@ -121,7 +121,7 @@ class ex_test extends uvm_test; user_tx_seq(phase); //Run MFB RX (USER) sequence - m_vseq = virt_seq #(ITEM_WIDTH, META_WIDTH, ETH_CHANNELS)::type_id::create("m_vseq"); + m_vseq = virt_seq #(ITEM_WIDTH, META_WIDTH, ETH_CHANNELS)::type_id::create("m_vseq"); m_vseq.randomize(); m_vseq.start(m_env.m_user_rx_mfb_env.m_sequencer); diff --git a/core/comp/eth/network_mod/network_mod.vhd b/core/comp/eth/network_mod/network_mod.vhd index 9258cfe1a..d32761ae8 100644 --- a/core/comp/eth/network_mod/network_mod.vhd +++ b/core/comp/eth/network_mod/network_mod.vhd @@ -1,4 +1,4 @@ --- network_mod.vhd: this is the top component of the Network module; +-- network_mod.vhd: this is the top component of the Network module; -- it contains MI splitter(s) and one or more of the -- Network module cores (based on mode of the ethernet -- port) which is connected to a pair of MAC lites (RX + TX). @@ -53,7 +53,7 @@ architecture FULL of NETWORK_MOD is -- ========================================================================= -- CONSTANTS -- ========================================================================= - constant EHIP_TYPE : natural := EHIP_PORT_TYPE(0); -- Define type of used IP core + constant EHIP_TYPE : natural := EHIP_PORT_TYPE(0); -- Define type of used IP core constant REGIONS_CORE : natural := tsel(ETH_PORT_SPEED(0) = 400, 2, 1); -- TODO: support different speeds/number of channels for each port constant REGION_SIZE_CORE : natural := region_size_core_f; @@ -428,8 +428,8 @@ begin -- ===================================================================== -- Network Module Core - -- ===================================================================== - network_mod_core_i: entity work.NETWORK_MOD_CORE + -- ===================================================================== + network_mod_core_i: entity work.NETWORK_MOD_CORE generic map ( ETH_PORT_SPEED => ETH_PORT_SPEED(p), ETH_PORT_CHAN => ETH_PORT_CHAN (p), @@ -565,7 +565,7 @@ begin if (asfifox_ts_dv_n(p) = '0') then synced_ts_ns(p) <= asfifox_ts_ns(p); end if; - + synced_ts_dv(p) <= (not asfifox_ts_dv_n(p)) or (asfifox_ts_last_vld(p) and not asfifox_ts_timeout(p)(TS_TIMEOUT_W-1)); diff --git a/core/comp/eth/network_mod/network_mod_ent.vhd b/core/comp/eth/network_mod/network_mod_ent.vhd index 7a5bf9669..60e251570 100644 --- a/core/comp/eth/network_mod/network_mod_ent.vhd +++ b/core/comp/eth/network_mod/network_mod_ent.vhd @@ -19,7 +19,7 @@ generic( ETH_CORE_ARCH : string := "E_TILE"; -- ===================================================================== -- Network ports configuration: - -- ===================================================================== + -- ===================================================================== ETH_PORTS : natural := 2; -- max 2 (MI address space limit) -- Number ETH streams, must be equal to ETH_PORTS or ETH_PORTS*ETH_PORT_CHAN! ETH_STREAMS : natural := ETH_PORTS; @@ -66,7 +66,7 @@ generic( -- ===================================================================== MI_DATA_WIDTH : natural := 32; MI_ADDR_WIDTH : natural := 32; - + MI_DATA_WIDTH_PHY : natural := 32; MI_ADDR_WIDTH_PHY : natural := 32; @@ -111,7 +111,7 @@ port( ETH_TX_N : out std_logic_vector(ETH_PORTS*LANES-1 downto 0); -- ===================================================================== -- QSFP Control - -- ===================================================================== + -- ===================================================================== QSFP_I2C_SCL : inout std_logic_vector(QSFP_I2C_PORTS-1 downto 0) := (others => 'Z'); QSFP_I2C_SDA : inout std_logic_vector(QSFP_I2C_PORTS-1 downto 0) := (others => 'Z'); QSFP_I2C_SDA_I : in std_logic_vector(QSFP_I2C_PORTS-1 downto 0) := (others => '1'); @@ -130,7 +130,7 @@ port( -- ===================================================================== -- Link control/status - runs on CLK_ETH - -- ===================================================================== + -- ===================================================================== -- REPEATER_CTRL : in std_logic_vector(ETH_PORTS*2-1 downto 0); -- PORT_ENABLED : out std_logic_vector(ETH_PORTS-1 downto 0); ACTIVITY_RX : out std_logic_vector(ETH_PORTS*ETH_PORT_CHAN(0)-1 downto 0); diff --git a/core/comp/eth/network_mod/qsfp_ctrl.vhd b/core/comp/eth/network_mod/qsfp_ctrl.vhd index 8c7b53002..366fe38d5 100644 --- a/core/comp/eth/network_mod/qsfp_ctrl.vhd +++ b/core/comp/eth/network_mod/qsfp_ctrl.vhd @@ -48,7 +48,7 @@ port ( QSFP_I2C_SDA_OE : out std_logic_vector(QSFP_I2C_PORTS-1 downto 0); -- Select which QSFP port is targetting during MI read/writes MI_QSFP_SEL : in std_logic_vector(max(log2(QSFP_PORTS)-1, 0) downto 0); - -- MI32 interface - + -- MI32 interface - MI_CLK_PHY : in std_logic; MI_RESET_PHY : in std_logic; MI_DWR_PHY : in std_logic_vector(31 downto 0); @@ -58,7 +58,7 @@ port ( MI_BE_PHY : in std_logic_vector( 3 downto 0); MI_DRD_PHY : out std_logic_vector(31 downto 0); MI_ARDY_PHY : out std_logic; - MI_DRDY_PHY : out std_logic + MI_DRDY_PHY : out std_logic ); end entity; @@ -67,7 +67,7 @@ architecture full of qsfp_ctrl is constant QSFP_RST_W : natural := 20; constant QSFP_STATUS_W : natural := 8; - signal i2c_mi_wr : std_logic; + signal i2c_mi_wr : std_logic; signal i2c_qsfp_scl_o : std_logic; signal i2c_qsfp_scl_oen : std_logic; signal i2c_qsfp_sda_o : std_logic; @@ -93,7 +93,7 @@ architecture full of qsfp_ctrl is signal fpc_conf_st : unsigned(2-1 downto 0); signal fpc_conf_st_reg : unsigned(2-1 downto 0); signal sleep_timer : unsigned(25-1 downto 0); - + signal trans_ctrl : std_logic_vector(3*QSFP_PORTS-1 downto 0); signal qsfp_modsel_r : std_logic_vector(QSFP_PORTS-1 downto 0) := (0 => '1', others => '0'); signal qsfp_i2c_scl_in : std_logic_vector(QSFP_I2C_PORTS-1 downto 0); @@ -101,19 +101,19 @@ architecture full of qsfp_ctrl is signal qsfp_i2c_sda_in : std_logic_vector(QSFP_I2C_PORTS-1 downto 0); signal qsfp_i2c_sda_int : std_logic; signal qsfp_status : std_logic_vector(QSFP_PORTS*QSFP_STATUS_W-1 downto 0); - - signal qsfp_mi_sel_i : natural; - + + signal qsfp_mi_sel_i : natural; + signal qsfp_modprs_n_sync : std_logic_vector(QSFP_PORTS-1 downto 0); signal qsfp_modprs_n_sync2 : std_logic_vector(QSFP_PORTS-1 downto 0); signal qsfp_insert_detect : std_logic_vector(QSFP_PORTS-1 downto 0); signal qsfp_rst_start : std_logic_vector(QSFP_PORTS-1 downto 0); signal qsfp_rst_timer : u_array_t (QSFP_PORTS-1 downto 0)(QSFP_RST_W-1 downto 0); - + begin - + qsfp_mi_sel_i <= to_integer(unsigned(MI_QSFP_SEL)); - + gen_qsfp_status: for i in 0 to QSFP_PORTS-1 generate qsfp_status((i+1)*QSFP_STATUS_W-1 downto i*QSFP_STATUS_W) <= TX_READY(i) & QSFP_RESET_N(i) & QSFP_INT_N(i) & QSFP_MODPRS_N(i) & trans_ctrl((i+1)*3-1 downto i*3) & '1'; end generate; @@ -125,7 +125,7 @@ begin MI_DRDY_PHY <= '0'; MI_DRD_PHY <= (others => '0'); -- Read from I2C controller or from QSFP status reg - if (MI_RD_PHY = '1') then + if (MI_RD_PHY = '1') then MI_DRDY_PHY <= '1'; if (MI_ADDR_PHY(3 downto 2) = "00") then -- I2C reg 0x00 MI_DRD_PHY <= i2c_qsfp_drd(31 downto 0); @@ -139,7 +139,7 @@ begin end process mi_regs_rd_p; MI_ARDY_PHY <= (MI_RD_PHY or MI_WR_PHY) and fpc_fsm_done; - + -- ---------------------------------------------------------------------------- -- QSFP I2C control and management ------------------------------------------------------------------------------- @@ -164,18 +164,18 @@ begin if (MI_ADDR_PHY(3 downto 2) = "11") then -- 0x1C - QSFP control reg trans_ctrl(qsfp_mi_sel_i*3+2 downto qsfp_mi_sel_i*3) <= MI_DWR_PHY(3 downto 1); end if; - + -- Turn on module select on targeted QSFP qsfp_modsel_r <= (others => '0'); qsfp_modsel_r(qsfp_mi_sel_i) <= '1'; end if; - + if RST = '1' then for i in 0 to QSFP_PORTS-1 loop trans_ctrl(3*i+2 downto 3*i) <= "001"; end loop; end if; - + end if; end process i2c_regs_wr_p; @@ -325,7 +325,7 @@ begin fpc_fsm_done <= '1'; end generate; - -- QSFP28 I2C controller + -- QSFP28 I2C controller i2c_qsfp_i : entity work.i2c_master_top generic map ( PRER_INIT => X"0271" -- 250MHz CLK -> 100KHz SCL @@ -403,7 +403,7 @@ begin ---------------------------------------------------------------------------- -- QSFP reset logic ---------------------------------------------------------------------------- - + qsfp_rst_g: for i in 0 to QSFP_PORTS-1 generate -- TODO glitch filtering on the QSFP_MODPRS_N signal sync_qsfp_modprs_n_i: entity work.ASYNC_OPEN_LOOP @@ -445,9 +445,9 @@ begin end if; end process; end generate; - + ---------------------------------------------------------------------------- - -- Assign outputs + -- Assign outputs ---------------------------------------------------------------------------- qsfp_outs_g: for i in 0 to QSFP_PORTS-1 generate @@ -457,5 +457,5 @@ begin QSFP_MODSEL_N(i) <= not qsfp_modsel_r(i); end generate; QSFP_I2C_DIR <= (others => not i2c_qsfp_sda_oen); -- I2C bus direction: 0 = QSFP -> FPGA, 1 = FPGA -> QSFP - + end architecture; diff --git a/core/comp/eth/network_mod/readme.rst b/core/comp/eth/network_mod/readme.rst index 83d29a5f0..b84c1050d 100644 --- a/core/comp/eth/network_mod/readme.rst +++ b/core/comp/eth/network_mod/readme.rst @@ -80,4 +80,4 @@ It is necessary to test all supported Ethernet IP architectures (E-Tile, CMAC,.. Entity Docs ^^^^^^^^^^^ -.. vhdl:autoentity:: NETWORK_MOD \ No newline at end of file +.. vhdl:autoentity:: NETWORK_MOD diff --git a/core/comp/eth/network_mod/sw/ftile.py b/core/comp/eth/network_mod/sw/ftile.py index 3b305fcf7..d94501bf1 100644 --- a/core/comp/eth/network_mod/sw/ftile.py +++ b/core/comp/eth/network_mod/sw/ftile.py @@ -3,8 +3,8 @@ FTILE_RSFEC_BASES = {25: 0x6000, 50: 0x6200, 100: 0x6600, 200: 0x6E00, 400: 0x7E00} # See https://www.intel.com/content/www/us/en/docs/programmable/683023/22-2/ethernet-hard-ip-core-csrs.html -FTILE_ETH_BASES = {10: 0x1000, 25: 0x1000, 50: 0x2000, 40: 0x3000, 100: 0x3000, 200: 0x4000, 400: 0x5000, 0: 0x3000 } -ETH_LANES = {10: 1, 25: 1, 50: 4, 40: 4, 100: 20, 200: 8, 400: 16, 0: 4} +FTILE_ETH_BASES = {10: 0x1000, 25: 0x1000, 50: 0x2000, 40: 0x3000, 100: 0x3000, 200: 0x4000, 400: 0x5000, 0: 0x3000} +ETH_LANES = {10: 1, 25: 1, 50: 4, 40: 4, 100: 20, 200: 8, 400: 16, 0: 4} FEC_NONE = 0 FEC_FIRECODE = 1 FEC_CL91 = 2 @@ -14,54 +14,57 @@ def drp_read(regs, reg, page=0, verbose=False): - reg = reg >> 2 - cmd = (page << 4) + 0 - # Write DRP address - regs.write32(0x18014,reg) - # Set page & start the operation - regs.write32(0x18018, cmd) - # Get the result - time.sleep(0.001) - val = regs.read32(0x18010) - if verbose: - print('Reading reg {:08x}, page {:d}, cmd {:08x}, value {:08x}'.format(reg, page, cmd, val)) - return val + reg = reg >> 2 + cmd = (page << 4) + 0 + # Write DRP address + regs.write32(0x18014, reg) + # Set page & start the operation + regs.write32(0x18018, cmd) + # Get the result + time.sleep(0.001) + val = regs.read32(0x18010) + if verbose: + print('Reading reg {:08x}, page {:d}, cmd {:08x}, value {:08x}'.format(reg, page, cmd, val)) + return val + def drp_write(comp, reg, val, page=0): - reg = reg >> 2 - cmd = (page << 4) + 1 - # Write value - comp.write32(0x18010,val) - # Write DRP address - comp.write32(0x18014,reg) - # Set page & start the operation - #print('Writing reg {:08x}, cmd {:08x}'.format(reg, cmd)) - comp.write32(0x18018, cmd) - time.sleep(0.001) # !!!!!!!!!!!!!!! + reg = reg >> 2 + cmd = (page << 4) + 1 + # Write value + comp.write32(0x18010, val) + # Write DRP address + comp.write32(0x18014, reg) + # Set page & start the operation + #print('Writing reg {:08x}, cmd {:08x}'.format(reg, cmd)) + comp.write32(0x18018, cmd) + time.sleep(0.001) # !!!!!!!!!!!!!!! + def drp_read_drc(regs, reg, page=0, verbose=False): - cmd = (page << 4) + 0 - # Write DRP address - regs.write32(0x18014,reg) - # Set page & start the operation - regs.write32(0x18018, cmd) - # Get the result - time.sleep(0.001) - val = regs.read32(0x18010) - if verbose: - print('Reading reg {:08x}, page {:d}, cmd {:08x}, value {:08x}'.format(reg, page, cmd, val)) - return val + cmd = (page << 4) + 0 + # Write DRP address + regs.write32(0x18014, reg) + # Set page & start the operation + regs.write32(0x18018, cmd) + # Get the result + time.sleep(0.001) + val = regs.read32(0x18010) + if verbose: + print('Reading reg {:08x}, page {:d}, cmd {:08x}, value {:08x}'.format(reg, page, cmd, val)) + return val + def drp_write_drc(comp, reg, val, page=0): - cmd = (page << 4) + 1 - # Write value - comp.write32(0x18010,val) - # Write DRP address - comp.write32(0x18014,reg) - # Set page & start the operation - #print('Writing reg {:08x}, cmd {:08x}'.format(reg, cmd)) - comp.write32(0x18018, cmd) - time.sleep(0.001) # !!!!!!!!!!!!!!! + cmd = (page << 4) + 1 + # Write value + comp.write32(0x18010, val) + # Write DRP address + comp.write32(0x18014, reg) + # Set page & start the operation + #print('Writing reg {:08x}, cmd {:08x}'.format(reg, cmd)) + comp.write32(0x18018, cmd) + time.sleep(0.001) # !!!!!!!!!!!!!!! def bit(val, b): @@ -70,17 +73,18 @@ def bit(val, b): """ return (val & (2**b)) >> b + def bits(val, start, count): """ Return value of bits val[start:start+count] """ - hi_bit = start + count + # hi_bit = start + count return (val >> start) & ((1 << count) - 1) class ftile_rsfec(): # For base addresses see https://www.intel.com/content/www/us/en/docs/programmable/683023/22-1/fec-and-transceiver-control-and-status.html - def __init__(self, pcsregs, base=0x7e00, lanes = 16, mode=FEC_CL134): + def __init__(self, pcsregs, base=0x7e00, lanes=16, mode=FEC_CL134): self.base = base self.comp = pcsregs self.page = 0 @@ -95,11 +99,11 @@ def read(self, reg, lane=0): def read64(self, reg, lane=0): # Get offset to PCS lane - addr = self.base + lane * 0x200 + reg + addr = self.base + lane * 0x200 + reg #print('Reading lane {} reg {:08x}, addr {:08x}'.format(lane, reg, addr)) lo = drp_read(self.comp, addr, 0) hi = drp_read(self.comp, addr+4, 0) - return (hi<<32)+lo + return (hi << 32) + lo def write(self, reg, val, lane=0): # Get offset to PCS lane @@ -114,8 +118,9 @@ def clear_stats(self): for lane in range(0, self.lanes): self.write(0x1e0, 0x10, lane) + class ftile_pma(): - def __init__(self, pcsregs, lanes = 8): + def __init__(self, pcsregs, lanes=8): self.comp = pcsregs self.lanes = lanes @@ -128,15 +133,15 @@ def write(self, reg, val, lane=0): def cpi_request(self, data, option, lane, opcode): # See https://www.intel.com/content/www/us/en/docs/programmable/683872/22-4-4-3-0/fgt-attribute-access-method.html - # Get transceiver index - index = self.read(0xffffc, lane) ## !!!! Not working after design boot !!! Why??????????????????????????????????????????????????????????????? + # Get transceiver index + index = self.read(0xffffc, lane) # !!!! Not working after design boot !!! Why??????????????????????????????????????????????????????????????? print(f'Phy lane readout {index:08x}') index &= 0x00000003 val = (data << 16) + (option << 12) + (index << 8) + (opcode) print(f'CPI req {lane}, phy lane {index}, value {val:08x}') self.write(0x9003c, val, lane) # poll 0x90040 until bit 14 = 0 and bit 15 = option[3] - ref = 0x8000 if (option&0x8) else 0x0000 + ref = 0x8000 if (option & 0x8) else 0x0000 readout = self.read(0x90040, lane) print(f'CPI status: {readout:08x}') while (readout & 0xC000) != ref: @@ -146,9 +151,9 @@ def cpi_request(self, data, option, lane, opcode): def set_pma_loop(self, enable): val = 0x6 if enable else 0x0 for lane in range(self.lanes): - self.cpi_request(val,0xA, lane, 0x40) - self.cpi_request(val,0x2, lane, 0x40) - + self.cpi_request(val, 0xA, lane, 0x40) + self.cpi_request(val, 0x2, lane, 0x40) + def set_lane_media_mode(self, lane, media=0x14): # See ttk_helper_ftile.tcl self.cpi_request(data=media, option=0xA, lane=lane, opcode=0x64) @@ -160,26 +165,25 @@ def set_mode(self, mode=0x14): self.set_lane_media_mode(lane, mode) - class ftile_pcs(): - def __init__(self, pcsregs, base, lanes = 20): + def __init__(self, pcsregs, base, lanes=20): self.base = base self.comp = pcsregs self.lanes = lanes def read(self, reg): - # Get offset to PCS + # Get offset to PCS addr = self.base + (reg - 0x1000) val = drp_read(self.comp, addr, 0) #print('Reading PCS reg {:08x}, addr {:08x}, value = {:08x}'.format(reg, addr, val)) return val def read64(self, reg): - # Get offset to PCS + # Get offset to PCS addr = self.base + (reg - 0x1000) lo = drp_read(self.comp, addr, 0) hi = drp_read(self.comp, addr+4, 0) - return (hi<<32)+lo + return (hi << 32) + lo def write(self, reg, val): addr = self.base + (reg - 0x1000) @@ -196,7 +200,7 @@ def clear_stats(self): # Reset TX stats self.write(0x1274, 1) self.write(0x1274, 0) - + class ftile_eth(): @@ -208,17 +212,17 @@ def __init__(self, pcsregs): self.modulation = 'PAM-4' if bit(config, 9) else 'NRZ' speed = bits(config, 5, 3) self.speed = \ - 10 if speed == 0 else\ - 25 if speed == 1 else\ - 40 if speed == 2 else\ - 50 if speed == 3 else\ + 10 if speed == 0 else\ + 25 if speed == 1 else\ + 40 if speed == 2 else\ + 50 if speed == 3 else\ 100 if speed == 4 else\ 200 if speed == 5 else\ 400 if speed == 6 else\ 0 # Assign PMA self.pma = ftile_pma(pcsregs, self.lanes) - # Assign PCS + # Assign PCS pcsbase = FTILE_ETH_BASES[self.speed] pcslanes = ETH_LANES[self.speed] self.pcs = ftile_pcs(pcsregs, pcsbase, pcslanes) @@ -228,7 +232,7 @@ def __init__(self, pcsregs): fec_base = 0 if self.speed in FTILE_RSFEC_BASES: fec_base = FTILE_RSFEC_BASES[self.speed] - if fec_mode: + if fec_mode: self.rsfec = ftile_rsfec(pcsregs, fec_base, self.speed//25, fec_mode) self.print_config() @@ -237,7 +241,7 @@ def print_config(self): fec_mode = bits(config, 10, 3) fec_base = 0 if self.speed in FTILE_RSFEC_BASES: - fec_base = FTILE_RSFEC_BASES[self.speed] + fec_base = FTILE_RSFEC_BASES[self.speed] print(f'\nEth init: config = {config:08x}, speed = {self.speed}, modulation : {self.modulation}, lanes = {self.lanes}, rsfec mode = "{FEC_MODE_STR[fec_mode]}", base = {fec_base:04x}') def read(self, reg): @@ -247,7 +251,7 @@ def read(self, reg): def read64(self, reg): lo = drp_read(self.comp, addr, 0) hi = drp_read(self.comp, addr+4, 0) - return (hi<<32)+lo + return (hi << 32) + lo def write(self, reg, val): # Get offset to PCS lane @@ -256,14 +260,14 @@ def write(self, reg, val): def set_rxreset(self): self.write(0x108, 4) - + def clr_rxreset(self): self.write(0x108, 0) def set_reset(self): self.write(0x108, 6) time.sleep(0.5) - + def clr_reset(self): self.write(0x108, 0) time.sleep(0.5) @@ -274,12 +278,12 @@ def pma_loopback(self, enable): self.clr_rxreset() time.sleep(0.1) + dev = nfb.open(path='0') nodes = dev.fdt_get_compatible("netcope,pcsregs") -eths = [] +eths = [] for i, node in enumerate(nodes): comp = dev.comp_open(node) eth = ftile_eth(comp) eths.append(eth) - diff --git a/core/comp/eth/network_mod/sw/profile_swap.py b/core/comp/eth/network_mod/sw/profile_swap.py index 7c4cf6957..8b7afec8b 100644 --- a/core/comp/eth/network_mod/sw/profile_swap.py +++ b/core/comp/eth/network_mod/sw/profile_swap.py @@ -17,24 +17,24 @@ p_mi_bus = 11 # Create the parser -args = argparse.ArgumentParser(description = "Multirate config setup Tool") +args = argparse.ArgumentParser(description="Multirate config setup Tool") # Add an argument -args.add_argument("-s_ch","--start_channel", type=int, required=False, help="start channel for profile swap default value is 0", default=0) -args.add_argument("-ch","--channels", type=int, required=True, help="num. of channels to be changed (depends on type of used IP_core)") -args.add_argument("-s_p","--start_profile", type=int, required=False,help="which profile is used right now", default=1) -args.add_argument("-e_p","--end_profile", type=int, required=True,help="which profile you want to use as next") -args.add_argument("-sp","--speed", type=str, required=True,help="speed of used IP_Core you can use \n'2x100G-4'\n'8x25G-1'", default="8x25G-1") -args.add_argument("-d","--device", type=int, required=True,help="Choose device, in which you have implemented design", default=0) +args.add_argument("-s_ch", "--start_channel", type=int, required=False, help="start channel for profile swap default value is 0", default=0) +args.add_argument("-ch", "--channels", type=int, required=True, help="num. of channels to be changed (depends on type of used IP_core)") +args.add_argument("-s_p", "--start_profile", type=int, required=False, help="which profile is used right now", default=1) +args.add_argument("-e_p", "--end_profile", type=int, required=True, help="which profile you want to use as next") +args.add_argument("-sp", "--speed", type=str, required=True, help="speed of used IP_Core you can use \n'2x100G-4'\n'8x25G-1'", default="8x25G-1") +args.add_argument("-d", "--device", type=int, required=True, help="Choose device, in which you have implemented design", default=0) arguments = args.parse_args() # ========================= -# Definition of parameters +# Definition of parameters # ========================= # for start channel you need to count from 0 it is beacose first IP core is declarated on channel 0 # for channels you need to remember that total number of channels + start channel must be smaller or equal as number of channels that means for example -# for 100GE is correct combination start channel = 0 and channels = 2 and +# for 100GE is correct combination start channel = 0 and channels = 2 and # for 100GE is wrong combination start channel = 1 and channels = 2 beacose there are only 2 IP cores and this combination means there must be 3 or more IP cores -# start profile represent current profile which is used default for our IP cores is profile 1 also dont forget if you change profile start profile must be last used profile +# start profile represent current profile which is used default for our IP cores is profile 1 also dont forget if you change profile start profile must be last used profile # end profile represent profile, which you want to set as new profile for use look for range of profile numbers for each IP core or use value of profile_difs # speed represent speed of Reconfiguration IP (default IP used in build) so if you use 10G variant form 25G IP core you need still for profile swap use 25G IP core declaration @@ -56,14 +56,14 @@ exit() if arguments.start_profile <= 0 or arguments.start_profile >= 3: print("There are not that many start_profiles, only 2 \n1\n2") - exit() + exit() if arguments.end_profile <= 0 or arguments.end_profile >= 3: print("There are not that many end_profiles, only 2 \n1\n2") - exit() + exit() # inicialization profiles_difs = 2 eth_channels = 2 - FEC_TYPE = [2,0] + FEC_TYPE = [2, 0] FEC = FEC_TYPE[arguments.end_profile - 1] profile_sel = 0 Eth_25G_10G = 0 @@ -86,9 +86,9 @@ # inicialization profiles_difs = 4 eth_channels = 8 - FEC_TYPE = [0,2,3,0] + FEC_TYPE = [0, 2, 3, 0] FEC = FEC_TYPE[arguments.end_profile - 1] - ETH_SPEED = [0,0,0,1] + ETH_SPEED = [0, 0, 0, 1] Eth_25G_10G = ETH_SPEED[arguments.end_profile - 1] profile_sel = 0 @@ -98,12 +98,12 @@ exit() # generator for full list of profiles, devices, components -for j in range (profiles_difs): +for j in range(profiles_difs): PROFILES_GROUPS.append([]) - for i in range (eth_channels): + for i in range(eth_channels): device_v.append(i) component.append(i) - PROFILES_GROUPS[j].append(j + i*profiles_difs+1 ) + PROFILES_GROUPS[j].append(j + i*profiles_difs+1) # initial initialization + line opening dev = nfb.open(path=str(arguments.device)) @@ -113,7 +113,7 @@ comp = [] # initialization to open eth channels -for i in range (eth_channels): +for i in range(eth_channels): node.append(nodes[component[i]]) comp.append(dev.comp_open(node[i])) @@ -135,16 +135,16 @@ # This process is repeated value of parameter cahnnels times # MAIN LOOP -for i in range (arguments.channels): +for i in range(arguments.channels): # print old config before swap - print ("\nold config is:") + print("\nold config is:") eth = ftile.ftile_eth(comp[arguments.start_channel + i]) # wait for moment when dr_controler is ready for switching profile - val = ftile.drp_read_drc(comp[0], 0x0, p_mi_bus) + val = ftile.drp_read_drc(comp[0], 0x0, p_mi_bus) while val != 2: print("It is not yet possible to switch a profile, wait\n") - val = ftile.drp_read_drc(comp[0], 0x0, p_mi_bus) + val = ftile.drp_read_drc(comp[0], 0x0, p_mi_bus) # dr_controler is ready, reset eth line for setup eth.set_reset() @@ -173,5 +173,5 @@ eth.clr_reset() # print new set config after swap - print ("\nnew config is:") + print("\nnew config is:") eth = ftile.ftile_eth(comp[arguments.start_channel + i]) diff --git a/core/comp/eth/network_mod/uvm/signals_sig.fdo b/core/comp/eth/network_mod/uvm/signals_sig.fdo index 47100d048..6d0aee04d 100644 --- a/core/comp/eth/network_mod/uvm/signals_sig.fdo +++ b/core/comp/eth/network_mod/uvm/signals_sig.fdo @@ -1,8 +1,8 @@ -# signal_sig.fdo : Include file with signals +# signal_sig.fdo : Include file with signals # Copyright (C) 2022 CESNET z. s. p. o. # Author(s): Daniel Kříž -# SPDX-License-Identifier: BSD-3-Clause +# SPDX-License-Identifier: BSD-3-Clause set ETH_PORTS 2 diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/model.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/model.sv index a9593f485..cee9a7b6e 100644 --- a/core/comp/eth/network_mod/uvm/tbench/base/env/model.sv +++ b/core/comp/eth/network_mod/uvm/tbench/base/env/model.sv @@ -1,4 +1,4 @@ -//-- model.sv: model +//-- model.sv: model //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Radek Iša @@ -33,7 +33,7 @@ class drop_cbs #(string ETH_CORE_ARCH, int unsigned ETH_PORT_SPEED) extends uvm_ $cast(c_data, data); {pkt_eof, pkt_drop} = c_data.data; - + for (int unsigned it = 0; it < RESIZED_REGIONS; it++) begin if (pkt_eof[it] == 1) begin queue.push_back(pkt_drop[it]); @@ -61,7 +61,7 @@ class model #(string ETH_CORE_ARCH, int unsigned ETH_PORTS, int unsigned ETH_POR uvm_analysis_port #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) usr_tx_data[ETH_PORTS]; uvm_analysis_port #(uvm_logic_vector::sequence_item#(ETH_RX_HDR_WIDTH)) usr_tx_hdr[ETH_PORTS]; - //SYNCHRONIZATION + //SYNCHRONIZATION protected drop_cbs #(ETH_CORE_ARCH, ETH_PORT_SPEED[0]) drop_sync[ETH_PORTS][]; protected int unsigned eth_recv[ETH_PORTS]; @@ -253,7 +253,7 @@ class model #(string ETH_CORE_ARCH, int unsigned ETH_PORTS, int unsigned ETH_POR hdr_out = uvm_logic_vector::sequence_item#(1)::type_id::create("hdr_out", this); hdr_out.start[$sformatf("USR_RX[%0d]", index)] = $time(); hdr_out.tag = "ETH_TX"; - hdr_out.data = 1'b0; + hdr_out.data = 1'b0; data_out = data; //data_out = uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)::type_id::create("data_out", this); diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/reg_sequence.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/reg_sequence.sv index 1eb9c7df1..0272d298c 100644 --- a/core/comp/eth/network_mod/uvm/tbench/base/env/reg_sequence.sv +++ b/core/comp/eth/network_mod/uvm/tbench/base/env/reg_sequence.sv @@ -27,7 +27,7 @@ class read_rx_counters#(RX_MAC_COUNT) extends uvm_sequence; logic [64-1:0] frames_512_1023_addr; logic [64-1:0] frames_1024_1518_addr; logic [64-1:0] frames_over_1518_addr; - logic [64-1:0] frames_below_64_addr; + logic [64-1:0] frames_below_64_addr; function new(string name = "mi_sequence"); super.new(name); @@ -184,7 +184,7 @@ class read_rx_counters#(RX_MAC_COUNT) extends uvm_sequence; regmodel.rfc.frames_65_127_h_addr.read(status, data); frames_65_127_addr[64-1:32] = data; end - + begin uvm_status_e status; uvm_reg_data_t data; diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/regmodel.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/regmodel.sv index 9679f666d..f0191d82a 100644 --- a/core/comp/eth/network_mod/uvm/tbench/base/env/regmodel.sv +++ b/core/comp/eth/network_mod/uvm/tbench/base/env/regmodel.sv @@ -50,7 +50,7 @@ class reg_model_port#(ETH_CHANNELS) extends uvm_reg_block; `uvm_object_param_utils(uvm_network_mod_env::reg_model_port#(ETH_CHANNELS)) rand reg_model_channel channel[ETH_CHANNELS]; - + function new(string name = "reg_model_port"); super.new(name, build_coverage(UVM_NO_COVERAGE)); endfunction diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard.sv index ebac6ba8d..96eff2092 100644 --- a/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard.sv +++ b/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard.sv @@ -1,4 +1,4 @@ -//-- scoreboard.sv: scoreboard +//-- scoreboard.sv: scoreboard //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Radek Iša @@ -76,7 +76,7 @@ class scoreboard #(ETH_CORE_ARCH, ETH_PORTS, int unsigned ETH_PORT_SPEED[ETH_POR // Create base components of environment. function void build_phase(uvm_phase phase); for (int unsigned it = 0; it < ETH_PORTS; it++) begin - m_eth_tx_data[it] = uvm_common::comparer_ordered#(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH))::type_id::create($sformatf("m_eth_tx_data_%0d", it), this); + m_eth_tx_data[it] = uvm_common::comparer_ordered#(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH))::type_id::create($sformatf("m_eth_tx_data_%0d", it), this); m_eth_tx_hdr [it] = uvm_common::comparer_ordered#(uvm_logic_vector::sequence_item#(1))::type_id::create($sformatf("m_eth_tx_hdr_%0d", it), this); m_usr_tx_data[it] = uvm_common::comparer_ordered#(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH))::type_id::create($sformatf("m_usr_tx_data_%0d", it), this); diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard_cmp.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard_cmp.sv index 7ee258bb1..e32d327cb 100644 --- a/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard_cmp.sv +++ b/core/comp/eth/network_mod/uvm/tbench/base/env/scoreboard_cmp.sv @@ -1,4 +1,4 @@ -//-- scoreboard_cmp.sv: scoreboard +//-- scoreboard_cmp.sv: scoreboard //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Radek Iša @@ -47,7 +47,7 @@ class comparer_tx_hdr #(int unsigned ITEM_WIDTH) extends uvm_common::comparer_ba {dut_timestamp, dut_timestamp_vld, dut_mac_hit, dut_mac_hit_vld, dut_multicast, dut_broadcast, dut_error_mac, dut_error_crc, dut_error_max_tu, dut_error_min_tu, dut_error_frame, dut_error, dut_port, dut_length} = tr_dut.data; {model_timestamp, model_timestamp_vld, model_mac_hit, model_mac_hit_vld, model_multicast, model_broadcast, model_error_mac, model_error_crc, model_error_max_tu, model_error_min_tu, model_error_frame, model_error, model_port, model_length} = tr_model.data; - ret &= dut_length === model_length ; + ret &= dut_length === model_length ; ret &= dut_port === model_port ; ret &= dut_error === model_error ; ret &= dut_error_frame === model_error_frame ; @@ -60,7 +60,7 @@ class comparer_tx_hdr #(int unsigned ITEM_WIDTH) extends uvm_common::comparer_ba ret &= dut_mac_hit_vld === model_mac_hit_vld ; ret &= (model_mac_hit_vld === 1'b0 || dut_mac_hit === model_mac_hit); ret &= dut_timestamp_vld === model_timestamp_vld; - ret &= (model_timestamp_vld === 1'b0 || dut_timestamp === model_timestamp); + ret &= (model_timestamp_vld === 1'b0 || dut_timestamp === model_timestamp); return ret; endfunction @@ -85,20 +85,20 @@ class comparer_tx_hdr #(int unsigned ITEM_WIDTH) extends uvm_common::comparer_ba {model_timestamp, model_timestamp_vld, model_mac_hit, model_mac_hit_vld, model_multicast, model_broadcast, model_error_mac, model_error_crc, model_error_max_tu, model_error_min_tu, model_error_frame, model_error, model_port, model_length} = tr.data; msg = tr.time2string(); - msg = {msg, $sformatf("\n\tlength [%0d]" , model_length)}; - msg = {msg, $sformatf("\n\tport [%0d]" , model_port)}; - msg = {msg, $sformatf("\n\terror [0x%h]", model_error)}; - msg = {msg, $sformatf("\n\terror frame [0x%h]", model_error_frame)}; - msg = {msg, $sformatf("\n\terror min MTU [0x%h]", model_error_min_tu)}; - msg = {msg, $sformatf("\n\terror max MTU [0x%h]", model_error_max_tu)}; - msg = {msg, $sformatf("\n\terror CRC [0x%h]", model_error_crc)}; - msg = {msg, $sformatf("\n\terror MAC [0x%h]", model_error_mac)}; - msg = {msg, $sformatf("\n\tbroadcast [0x%h]", model_broadcast)}; - msg = {msg, $sformatf("\n\tmulticast [0x%h]", model_multicast)}; - msg = {msg, $sformatf("\n\tMAC HIT VLD [0x%h]", model_mac_hit_vld)}; - msg = {msg, $sformatf("\n\t\tMAC HIT [0x%h]", model_mac_hit)}; - msg = {msg, $sformatf("\n\ttimestamp VLD [0x%h]", model_timestamp_vld)}; - msg = {msg, $sformatf("\n\t\ttimestamp [0x%h]", model_timestamp)}; + msg = {msg, $sformatf("\n\tlength [%0d]" , model_length)}; + msg = {msg, $sformatf("\n\tport [%0d]" , model_port)}; + msg = {msg, $sformatf("\n\terror [0x%h]", model_error)}; + msg = {msg, $sformatf("\n\terror frame [0x%h]", model_error_frame)}; + msg = {msg, $sformatf("\n\terror min MTU [0x%h]", model_error_min_tu)}; + msg = {msg, $sformatf("\n\terror max MTU [0x%h]", model_error_max_tu)}; + msg = {msg, $sformatf("\n\terror CRC [0x%h]", model_error_crc)}; + msg = {msg, $sformatf("\n\terror MAC [0x%h]", model_error_mac)}; + msg = {msg, $sformatf("\n\tbroadcast [0x%h]", model_broadcast)}; + msg = {msg, $sformatf("\n\tmulticast [0x%h]", model_multicast)}; + msg = {msg, $sformatf("\n\tMAC HIT VLD [0x%h]", model_mac_hit_vld)}; + msg = {msg, $sformatf("\n\t\tMAC HIT [0x%h]", model_mac_hit)}; + msg = {msg, $sformatf("\n\ttimestamp VLD [0x%h]", model_timestamp_vld)}; + msg = {msg, $sformatf("\n\t\ttimestamp [0x%h]", model_timestamp)}; return msg; endfunction @@ -122,20 +122,20 @@ class comparer_tx_hdr #(int unsigned ITEM_WIDTH) extends uvm_common::comparer_ba {dut_timestamp, dut_timestamp_vld, dut_mac_hit, dut_mac_hit_vld, dut_multicast, dut_broadcast, dut_error_mac, dut_error_crc, dut_error_max_tu, dut_error_min_tu, dut_error_frame, dut_error, dut_port, dut_length} = tr.data; msg = tr.time2string(); - msg = {msg, $sformatf("\n\tlength [%0d]" , dut_length)}; - msg = {msg, $sformatf("\n\tport [%0d]" , dut_port)}; - msg = {msg, $sformatf("\n\terror [0x%h]", dut_error)}; - msg = {msg, $sformatf("\n\terror frame [0x%h]", dut_error_frame)}; - msg = {msg, $sformatf("\n\terror min MTU [0x%h]", dut_error_min_tu)}; - msg = {msg, $sformatf("\n\terror max MTU [0x%h]", dut_error_max_tu)}; - msg = {msg, $sformatf("\n\terror CRC [0x%h]", dut_error_crc)}; - msg = {msg, $sformatf("\n\terror MAC [0x%h]", dut_error_mac)}; - msg = {msg, $sformatf("\n\tbroadcast [0x%h]", dut_broadcast)}; - msg = {msg, $sformatf("\n\tmulticast [0x%h]", dut_multicast)}; - msg = {msg, $sformatf("\n\tMAC HIT VLD [0x%h]", dut_mac_hit_vld)}; - msg = {msg, $sformatf("\n\t\tMAC HIT [0x%h]", dut_mac_hit)}; - msg = {msg, $sformatf("\n\ttimestamp VLD [0x%h]", dut_timestamp_vld)}; - msg = {msg, $sformatf("\n\t\ttimestamp [0x%h]", dut_timestamp)}; + msg = {msg, $sformatf("\n\tlength [%0d]" , dut_length)}; + msg = {msg, $sformatf("\n\tport [%0d]" , dut_port)}; + msg = {msg, $sformatf("\n\terror [0x%h]", dut_error)}; + msg = {msg, $sformatf("\n\terror frame [0x%h]", dut_error_frame)}; + msg = {msg, $sformatf("\n\terror min MTU [0x%h]", dut_error_min_tu)}; + msg = {msg, $sformatf("\n\terror max MTU [0x%h]", dut_error_max_tu)}; + msg = {msg, $sformatf("\n\terror CRC [0x%h]", dut_error_crc)}; + msg = {msg, $sformatf("\n\terror MAC [0x%h]", dut_error_mac)}; + msg = {msg, $sformatf("\n\tbroadcast [0x%h]", dut_broadcast)}; + msg = {msg, $sformatf("\n\tmulticast [0x%h]", dut_multicast)}; + msg = {msg, $sformatf("\n\tMAC HIT VLD [0x%h]", dut_mac_hit_vld)}; + msg = {msg, $sformatf("\n\t\tMAC HIT [0x%h]", dut_mac_hit)}; + msg = {msg, $sformatf("\n\ttimestamp VLD [0x%h]", dut_timestamp_vld)}; + msg = {msg, $sformatf("\n\t\ttimestamp [0x%h]", dut_timestamp)}; return msg; endfunction endclass diff --git a/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv b/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv index 6f65c4eda..949eb6385 100644 --- a/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv +++ b/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv @@ -147,7 +147,7 @@ class virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIO rx_stats.start(null); tx_stats.start(null); join - + `uvm_info(this.get_full_name(), $sformatf("RX channel %s base [%0d]\n\tSTATS trfc %0d cfc %0d dfc %0d bodfc %0d oroc %0d\n", m_sequencer.get_full_name(), it, rx_stats.trfc, rx_stats.cfc, rx_stats.dfc, rx_stats.bodfc, rx_stats.oroc), UVM_LOW); @@ -319,7 +319,7 @@ class virt_sequence_simple #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM task pre_body(); super.pre_body(); - + for (int unsigned it = 0; it < ETH_PORTS; it++) begin virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH) cast_virt_sequence_port; assert($cast(cast_virt_sequence_port, port[it])) @@ -408,7 +408,7 @@ class virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_W `uvm_object_param_utils(uvm_network_mod_e_tile_env::virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)) protected uvm_logic_vector_array::config_sequence eth_rx_seq_cfg[ETH_PORTS]; - + function new(string name = "virt_sequence_stop"); super.new(name); endfunction diff --git a/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv b/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv index bee26aba1..7f2e58b1a 100644 --- a/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv +++ b/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv @@ -82,7 +82,7 @@ module testbench; // CONFIGURE and RUN VERIFICATION initial begin automatic uvm_root m_root; - automatic virtual reset_if vif_rst_eth[ETH_PORTS] = rst_eth; + automatic virtual reset_if vif_rst_eth[ETH_PORTS] = rst_eth; automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, ETH_TX_HDR_WIDTH) vif_usr_rx [ETH_PORTS] = usr_rx; automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) vif_usr_tx_data[ETH_PORTS] = usr_tx_data; automatic virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) vif_usr_tx_hdr [ETH_PORTS] = usr_tx_hdr; @@ -104,7 +104,7 @@ module testbench; uvm_config_db#(virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) )::set(null, "", $sformatf("vif_usr_tx_hdr_%0d", it) , vif_usr_tx_hdr[it]); uvm_config_db#(virtual avst_if #(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 6))::set(null, "", $sformatf("vif_eth_rx_%0d", it) , vif_eth_rx[it]); - uvm_config_db#(virtual avst_if #(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 1))::set(null, "", $sformatf("vif_eth_tx_%0d", it) , vif_eth_tx[it]); + uvm_config_db#(virtual avst_if #(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 1))::set(null, "", $sformatf("vif_eth_tx_%0d", it) , vif_eth_tx[it]); end uvm_config_db#(virtual mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH))::set(null, "", "vif_mi" , mi); uvm_config_db#(virtual mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH))::set(null, "", "vif_mi_phy", mi_phy); @@ -244,6 +244,6 @@ module testbench; .tsu (tsu) ); - + endmodule diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv index c3af200d4..3425096be 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv @@ -100,7 +100,7 @@ class env #( cfg_eth_tx.interface_name = $sformatf("vif_eth_tx_%0d", it); uvm_config_db #(uvm_logic_vector_array_intel_mac_seg::config_item)::set(this, $sformatf("m_eth_tx_%0d", it), "m_config", cfg_eth_tx); m_eth_tx[it] = uvm_logic_vector_array_intel_mac_seg::env_tx #(SEGMENTS)::type_id::create($sformatf("m_eth_tx_%0d", it), this); - + m_tx_error_trimmer[it] = tx_error_trimmer::type_id::create($sformatf("m_tx_error_trimmer_%0d", it), this); end endfunction diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv index 9512b31b8..e3210d39f 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv @@ -15,7 +15,7 @@ class virt_sequence_port #( int unsigned BLOCK_SIZE, int unsigned ETH_PORT_CHAN, - + int unsigned MI_DATA_WIDTH, int unsigned MI_ADDR_WIDTH ) extends uvm_network_mod_env::virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH); @@ -158,7 +158,7 @@ class virt_sequence_port #( rx_stats.start(null); tx_stats.start(null); join - + `uvm_info(this.get_full_name(), $sformatf("RX channel %s base [%0d]\n\tSTATS trfc %0d cfc %0d dfc %0d bodfc %0d oroc %0d\n", m_sequencer.get_full_name(), it, rx_stats.trfc, rx_stats.cfc, rx_stats.dfc, rx_stats.bodfc, rx_stats.oroc), UVM_LOW); @@ -221,7 +221,7 @@ endclass class virt_sequence_port_stop #( int unsigned ETH_TX_HDR_WIDTH, int unsigned ETH_RX_HDR_WIDTH, - + int unsigned ITEM_WIDTH, int unsigned REGIONS, int unsigned REGION_SIZE, @@ -354,7 +354,7 @@ class virt_sequence_simple #( task pre_body(); super.pre_body(); - + for (int unsigned it = 0; it < ETH_PORTS; it++) begin virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH) cast_virt_sequence_port; assert($cast(cast_virt_sequence_port, port[it])) @@ -443,7 +443,7 @@ class virt_sequence_stop #( int unsigned ETH_PORTS, int unsigned ETH_TX_HDR_WIDTH, int unsigned ETH_RX_HDR_WIDTH, - + int unsigned ITEM_WIDTH, int unsigned REGIONS, int unsigned REGION_SIZE, @@ -457,7 +457,7 @@ class virt_sequence_stop #( `uvm_object_param_utils(uvm_network_mod_f_tile_env::virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)) protected uvm_logic_vector_array::config_sequence eth_rx_seq_cfg[ETH_PORTS]; - + function new(string name = "virt_sequence_stop"); super.new(name); endfunction diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequencer_port.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequencer_port.sv index e1e0980d1..9e69e74ba 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequencer_port.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequencer_port.sv @@ -7,14 +7,14 @@ class sequencer_port #( int unsigned ETH_TX_HDR_WIDTH, int unsigned ETH_RX_HDR_WIDTH, - + int unsigned ITEM_WIDTH, int unsigned REGIONS, int unsigned REGION_SIZE, int unsigned BLOCK_SIZE, - + int unsigned ETH_PORT_CHAN, - + int unsigned MI_DATA_WIDTH, int unsigned MI_ADDR_WIDTH ) extends uvm_network_mod_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH); diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv index b14b164fd..00d3bac30 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv @@ -80,7 +80,7 @@ module testbench; // CONFIGURE and RUN VERIFICATION initial begin automatic uvm_root m_root; - automatic virtual reset_if vif_rst_eth[ETH_PORTS] = rst_eth; + automatic virtual reset_if vif_rst_eth[ETH_PORTS] = rst_eth; automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, ETH_TX_HDR_WIDTH) vif_usr_rx [ETH_PORTS] = usr_rx; automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) vif_usr_tx_data[ETH_PORTS] = usr_tx_data; automatic virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) vif_usr_tx_hdr [ETH_PORTS] = usr_tx_hdr; @@ -102,7 +102,7 @@ module testbench; uvm_config_db#(virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) )::set(null, "", $sformatf("vif_usr_tx_hdr_%0d", it) , vif_usr_tx_hdr[it]); uvm_config_db#(virtual intel_mac_seg_if #(SEGMENTS))::set(null, "", $sformatf("vif_eth_rx_%0d", it) , vif_eth_rx[it]); - uvm_config_db#(virtual intel_mac_seg_if #(SEGMENTS))::set(null, "", $sformatf("vif_eth_tx_%0d", it) , vif_eth_tx[it]); + uvm_config_db#(virtual intel_mac_seg_if #(SEGMENTS))::set(null, "", $sformatf("vif_eth_tx_%0d", it) , vif_eth_tx[it]); end uvm_config_db#(virtual mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH))::set(null, "", "vif_mi" , mi); uvm_config_db#(virtual mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH))::set(null, "", "vif_mi_phy", mi_phy); @@ -243,6 +243,6 @@ module testbench; .tsu (tsu) ); - + endmodule diff --git a/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv b/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv index 2ad0fdadd..d7ecf55ba 100644 --- a/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv +++ b/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv @@ -24,7 +24,7 @@ class speed #( typedef uvm_component_registry#(test::speed #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH), "test::speed") type_id; localparam time timeout_max = 200us; - + uvm_network_mod_env::env #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH) m_env; // ------------------------------------------------------------------------ diff --git a/core/comp/eth/network_mod/uvm/ver_settings.py b/core/comp/eth/network_mod/uvm/ver_settings.py index 588df280e..baf6bae16 100644 --- a/core/comp/eth/network_mod/uvm/ver_settings.py +++ b/core/comp/eth/network_mod/uvm/ver_settings.py @@ -180,4 +180,4 @@ #"4p_cmac_1x100g4_normal" : ("cmac_1x100g4", "ports_4",), #"4p_cmac_1x100g4_small" : ("cmac_1x100g4", "ports_4", "small_packets",), }, -} \ No newline at end of file +} diff --git a/core/comp/misc/boot_ctrl/DevTree.tcl b/core/comp/misc/boot_ctrl/DevTree.tcl index e7075ad0f..a6212ba24 100644 --- a/core/comp/misc/boot_ctrl/DevTree.tcl +++ b/core/comp/misc/boot_ctrl/DevTree.tcl @@ -5,10 +5,10 @@ # SPDX-License-Identifier: BSD-3-Clause # 1. base - base address on MI bus -# 2. type - type of card +# 2. type - type of card proc dts_boot_controller {base type} { set ret "" - + append ret "boot_controller {" append ret "compatible = \"netcope,boot_controller\";" append ret "reg = <$base 8>;" diff --git a/core/comp/misc/boot_ctrl/boot_ctrl.vhd b/core/comp/misc/boot_ctrl/boot_ctrl.vhd index 4a1f3b342..ff415bf34 100644 --- a/core/comp/misc/boot_ctrl/boot_ctrl.vhd +++ b/core/comp/misc/boot_ctrl/boot_ctrl.vhd @@ -15,7 +15,7 @@ entity BOOT_CTRL is generic( -- ICAP WBSTAR register value (see UG570) for boot image 0 (Xilinx Only): -- [31:30] = RS[1:0] pin value on next warm boot in BPI mode. The default is 00. - -- [29] = RS[1:0] pins 3-state enable: + -- [29] = RS[1:0] pins 3-state enable: -- 0 = 3-state enabled (RS[1:0] disabled) (default) -- 1 = 3-state disabled (RS[1:0] enabled) -- [28:0] = START_ADDR: Next bitstream start address. @@ -23,11 +23,11 @@ entity BOOT_CTRL is ICAP_WBSTAR0 : std_logic_vector(31 downto 0) := X"00000000"; -- ICAP WBSTAR register value (see UG570) for boot image 1 (Xilinx Only): -- [31:30] = RS[1:0] pin value on next warm boot in BPI mode. The default is 00. - -- [29] = RS[1:0] pins 3-state enable: + -- [29] = RS[1:0] pins 3-state enable: -- 0 = 3-state enabled (RS[1:0] disabled) (default) -- 1 = 3-state disabled (RS[1:0] enabled) -- [28:0] = START_ADDR: Next bitstream start address. - -- The default start address is address zero. + -- The default start address is address zero. ICAP_WBSTAR1 : std_logic_vector(31 downto 0) := X"01002000"; -- FPGA device (ULTRASCALE, AGILEX,...) DEVICE : string := "ULTRASCALE"; @@ -35,7 +35,7 @@ entity BOOT_CTRL is BOOT_TYPE : natural := 2; -- BOOT timeout width in bites BOOT_TIMEOUT_W : natural := 26 - ); + ); port( -- ===================================================================== -- MAIN MI slave interface (MI_CLK) @@ -107,7 +107,7 @@ architecture FULL of BOOT_CTRL is constant MI_BOOT_PORTS : natural := 2; constant MI_BOOT_ADDR_BASE : slv_array_t(MI_BOOT_PORTS-1 downto 0)(32-1 downto 0) := ( 0 => X"0000_0000", -- BMC - 1 => X"0000_2100"); -- AXI Quad SPI + 1 => X"0000_2100"); -- AXI Quad SPI constant MASK :std_logic_vector(32 -1 downto 0):=(8 => '1', others => '0'); -- MI ASYNC @@ -212,7 +212,7 @@ begin port map( CLK => BOOT_CLK, RESET => BOOT_RESET, - + RX_DWR => mi_sync_dwr, RX_ADDR => mi_sync_addr, RX_BE => mi_sync_be, @@ -221,7 +221,7 @@ begin RX_ARDY => mi_sync_ardy, RX_DRD => mi_sync_drd, RX_DRDY => mi_sync_drdy, - + TX_DWR => mi_split_dwr, TX_ADDR => mi_split_addr, TX_BE => mi_split_be, @@ -289,13 +289,13 @@ begin when others => mi_boot_drd <= (others => '0'); end case; mi_boot_drdy <= mi_boot_rd; - + if (BOOT_RESET = '1') then mi_boot_drdy <= '0'; end if; end if; end process; - + mi_wr_p : process(BOOT_CLK) begin if rising_edge(BOOT_CLK) then @@ -313,17 +313,17 @@ begin boot_cmd <= '1'; boot_img <= not flash_wr_data_reg(0); end if; - + when others => null; - end case; + end case; end if; - + if (BOOT_RESET = '1') then boot_cmd <= '0'; end if; end if; end process; - + boot_timeout_p : process(BOOT_CLK) begin if rising_edge(BOOT_CLK) then @@ -334,7 +334,7 @@ begin end if; end if; end process; - + BOOT_REQUEST <= boot_cmd and (boot_timeout(BOOT_TIMEOUT_W-1)); BOOT_IMAGE <= boot_img; end generate; @@ -376,8 +376,8 @@ begin icap_di_swap_g: for i in 0 to 3 generate icap_di_swap_g2: for j in 0 to 7 generate icap_di_swap((i*8)+j) <= icap_di_orig((i*8)+(7-j)); - end generate; - end generate; + end generate; + end generate; ICAP_RDWRB <= '0'; ICAP_DI <= icap_di_swap; @@ -386,5 +386,5 @@ begin ICAP_RDWRB <= '0'; ICAP_DI <= (others => '0'); end generate; - + end architecture; diff --git a/core/comp/misc/boot_ctrl/sim/testbench.vhd b/core/comp/misc/boot_ctrl/sim/testbench.vhd index f3f03eb6a..23b7676b1 100644 --- a/core/comp/misc/boot_ctrl/sim/testbench.vhd +++ b/core/comp/misc/boot_ctrl/sim/testbench.vhd @@ -1,4 +1,4 @@ --- testbench.vhd: Simulation file +-- testbench.vhd: Simulation file -- Copyright (C) 2024 CESNET z. s. p. o. -- Author(s): Jakub Cabal -- @@ -9,11 +9,11 @@ USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_textio.ALL; USE ieee.numeric_std.ALL; USE std.textio.ALL; - + ENTITY TESTBENCH IS END TESTBENCH; - -ARCHITECTURE FULL OF TESTBENCH IS + +ARCHITECTURE FULL OF TESTBENCH IS signal mi_clk : std_logic; signal mi_reset : std_logic; @@ -56,9 +56,9 @@ ARCHITECTURE FULL OF TESTBENCH IS constant PERIOD_MI_CLK : time := 5 ns; constant PERIOD_BOOT_CLK : time := 10 ns; - + BEGIN - + -- Instantiate the Unit Under Test (UUT) uut_i: entity work.BOOT_CTRL generic map( @@ -110,7 +110,7 @@ BEGIN BMC_MI_DRD => bmc_mi_drd, BMC_MI_DRDY => bmc_mi_drdy ); - + process begin mi_clk <= '0'; @@ -126,10 +126,10 @@ BEGIN boot_clk <= '1'; wait for PERIOD_BOOT_CLK/2; end process; - + process - begin - icap_avail <= '0'; + begin + icap_avail <= '0'; boot_reset <= '1', '0' after PERIOD_BOOT_CLK*3; wait for 3*PERIOD_BOOT_CLK; icap_avail <= '1'; diff --git a/core/comp/misc/sdm_ctrl/sdm_ctrl_arch.vhd b/core/comp/misc/sdm_ctrl/sdm_ctrl_arch.vhd index 5fc8372d8..38d98ba8e 100644 --- a/core/comp/misc/sdm_ctrl/sdm_ctrl_arch.vhd +++ b/core/comp/misc/sdm_ctrl/sdm_ctrl_arch.vhd @@ -395,7 +395,7 @@ begin MI_DRD => MI_DRD, MI_ARDY => MI_ARDY, MI_DRDY => MI_DRDY, - + AVMM_ADDRESS => avmm_addr, AVMM_WRITE => avmm_wr, AVMM_READ => avmm_rd, diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/pcie_adapter.vhd b/core/comp/pcie/pcie_mod/comp/pcie_adapter/pcie_adapter.vhd index 303a67ae7..1d14ddfb1 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/pcie_adapter.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/pcie_adapter.vhd @@ -177,7 +177,7 @@ entity PCIE_ADAPTER is -- ===================================================================== -- AXI Requester Request (RQ) Interface - Xilinx FPGA Only - -- + -- -- See Xilinx PG213 (UltraScale+ Devices Integrated Block for PCI Express). -- ===================================================================== RQ_AXI_DATA : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); @@ -337,7 +337,7 @@ begin cq_mfb_meta_g: for i in 0 to CQ_MFB_REGIONS-1 generate cq_mfb_meta_arr(i)(PCIE_CQ_META_HEADER) <= (others => '0'); cq_mfb_meta_arr(i)(PCIE_CQ_META_PREFIX) <= (others => '0'); - cq_mfb_meta_arr(i)(PCIE_CQ_META_BAR) <= (others => '0'); + cq_mfb_meta_arr(i)(PCIE_CQ_META_BAR) <= (others => '0'); cq_mfb_meta_arr(i)(PCIE_CQ_META_FBE) <= cq_fbe((i+1)*PCIE_META_FBE_W-1 downto i*PCIE_META_FBE_W); cq_mfb_meta_arr(i)(PCIE_CQ_META_LBE) <= cq_lbe((i+1)*PCIE_META_LBE_W-1 downto i*PCIE_META_LBE_W); cq_mfb_meta_arr(i)(PCIE_CQ_META_TPH_PRESENT_O) <= cq_tph_present(i); @@ -365,7 +365,7 @@ begin RX_AXI_TUSER => RC_AXI_USER, RX_AXI_TVALID => RC_AXI_VALID, RX_AXI_TREADY => RC_AXI_READY, - + TX_MFB_DATA => RC_MFB_DATA, TX_MFB_SOF => RC_MFB_SOF, TX_MFB_EOF => RC_MFB_EOF, @@ -488,8 +488,8 @@ begin TX_AVST_HDR => AVST_UP_HDR, TX_AVST_PREFIX => AVST_UP_PREFIX, TX_AVST_SOP => AVST_UP_SOP, - TX_AVST_EOP => AVST_UP_EOP, - TX_AVST_ERROR => AVST_UP_ERROR, + TX_AVST_EOP => AVST_UP_EOP, + TX_AVST_ERROR => AVST_UP_ERROR, TX_AVST_VALID => AVST_UP_VALID, TX_AVST_READY => AVST_UP_READY, -- DOWN stream credits - R-TILE only @@ -564,17 +564,17 @@ begin cq_mfb_meta_arr(i)(PCIE_CQ_META_TPH_ST_TAG) <= (others => '0'); end generate; - rc_mfb_meta_g: for i in 0 to RC_MFB_REGIONS-1 generate + rc_mfb_meta_g: for i in 0 to RC_MFB_REGIONS-1 generate rc_mfb_meta_arr(i)(PCIE_RC_META_HEADER) <= cblk_rc_mfb_meta_arr(i)(96-1 downto 0); rc_mfb_meta_arr(i)(PCIE_RC_META_PREFIX) <= cblk_rc_mfb_meta_arr(i)(128-1 downto 96); end generate; - cc_mfb_meta_g: for i in 0 to CC_MFB_REGIONS-1 generate + cc_mfb_meta_g: for i in 0 to CC_MFB_REGIONS-1 generate cblk_cc_mfb_meta_arr(i)(96-1 downto 0) <= cc_mfb_meta_arr(i)(PCIE_CC_META_HEADER); cblk_cc_mfb_meta_arr(i)(128-1 downto 96) <= cc_mfb_meta_arr(i)(PCIE_CC_META_PREFIX); end generate; - rq_mfb_meta_g: for i in 0 to RQ_MFB_REGIONS-1 generate + rq_mfb_meta_g: for i in 0 to RQ_MFB_REGIONS-1 generate cblk_rq_mfb_meta_arr(i)(PCIE_RQ_META_HEADER) <= rq_mfb_meta_arr(i)(PCIE_RQ_META_HEADER); cblk_rq_mfb_meta_arr(i)(PCIE_RQ_META_PREFIX) <= rq_mfb_meta_arr(i)(PCIE_RQ_META_PREFIX); end generate; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/signals_sig.fdo b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/signals_sig.fdo index 2cb411990..1ac10c4eb 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/signals_sig.fdo +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/signals_sig.fdo @@ -1,4 +1,4 @@ -# signal_sig.fdo : Include file with signals +# signal_sig.fdo : Include file with signals # Copyright (C) 2022 CESNET z. s. p. o. # Author: Daniel Kříž # diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv index 0f5514c4d..42224f1e6 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv @@ -1,4 +1,4 @@ -//-- dut.sv: Design under test +//-- dut.sv: Design under test //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz @@ -124,7 +124,7 @@ module DUT ( // ===================================================================== .AVST_DOWN_SEG (CQ_MFB_REGIONS), - .AVST_UP_SEG (CC_MFB_REGIONS) + .AVST_UP_SEG (CC_MFB_REGIONS) ) VHDL_DUT_U ( .PCIE_CLK (CLK), .PCIE_RESET (RST), @@ -233,7 +233,7 @@ module DUT ( // ===================================================================== // AXI Requester Request (RQ) Interface - Xilinx FPGA Only - // + // // See Xilinx PG213 (UltraScale+ Devices Integrated Block for PCI Express). // ===================================================================== .RQ_AXI_DATA (rq_axi.TDATA), diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/agent.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/agent.sv index 4dc8fe270..53642edb2 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/agent.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/agent.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause // This is AVST credit control rx agent, which declares basic components. class agent_rx extends uvm_agent; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/config.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/config.sv index f60fe5ba1..83cc7b513 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/config.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/config.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class config_sequence extends uvm_object; // configuration of probability of rdy signal in percentige diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/driver.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/driver.sv index 9e1d8f141..8fd169087 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/driver.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/driver.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause // Driver of AVST credit control rx interface class driver_rx extends uvm_driver #(sequence_item); diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/interface.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/interface.sv index 406c88fb4..ceabe50eb 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/interface.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/interface.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause // Definition of AVST credit control interface. interface crdt_if (input logic CLK); diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/monitor.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/monitor.sv index 5a97b7419..4913a522e 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/monitor.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/monitor.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause // Definition of AVST credit control monitor class monitor extends uvm_monitor; @@ -18,7 +18,7 @@ class monitor extends uvm_monitor; // ------------------------------------------------------------------------ // Reference to the virtual interface virtual crdt_if.monitor vif; - + // ------------------------------------------------------------------------ // Analysis port used to send transactions to all connected components. uvm_analysis_port #(sequence_item) analysis_port; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/pkg.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/pkg.sv index 36f77941a..44686aeb9 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/pkg.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/pkg.sv @@ -2,16 +2,16 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause `ifndef CRDT_PKG `define CRDT_PKG package uvm_crdt; - + `include "uvm_macros.svh" import uvm_pkg::*; - + `include "config.sv" `include "sequence_item.sv" `include "sequencer.sv" diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence.sv index e98abd156..a22e26149 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class sequence_simple extends uvm_common::sequence_base #(config_sequence, sequence_item); `uvm_object_utils(uvm_crdt::sequence_simple) diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence_item.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence_item.sv index a57ea6498..06999f70b 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence_item.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequence_item.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class sequence_item extends uvm_sequence_item; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequencer.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequencer.sv index d359057c5..9e8d7fe36 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequencer.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/crdt_agent/sequencer.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class sequencer extends uvm_sequencer #(uvm_crdt::sequence_item); // ------------------------------------------------------------------------ diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/generator.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/generator.sv index e7da69d75..e64d1b2f2 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/generator.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/generator.sv @@ -90,4 +90,4 @@ class generator #(ITEM_WIDTH, META_WIDTH, SIDE, ENDPOINT_TYPE, PCIE_T) extends u end endtask -endclass \ No newline at end of file +endclass diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_base.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_base.sv index d606cface..d1182b93b 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_base.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_base.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kříž -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class model_base #(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W) extends uvm_component; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_intel.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_intel.sv index 5315242db..5760f38f6 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_intel.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_intel.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class model_intel #(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AVST_DOWN_META_W, AVST_UP_META_W, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W, ENDPOINT_TYPE) extends model_base #(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W); @@ -88,7 +88,7 @@ extends model_base #(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC rw = solve_type(tlp_type); rws.push_back(rw); - if (rw == 1'b0) begin + if (rw == 1'b0) begin tr_mfb_cq_meta_out = uvm_logic_vector::sequence_item #(CQ_MFB_META_W)::type_id::create("tr_mfb_cq_meta_out", this); tr_mfb_cq_meta_out.data = '0; tr_mfb_cq_meta_out.data = {tr_avst_down_meta_in.data[163-1 : 160], tr_avst_down_meta_in.data[160-1 : 128], tr_avst_down_meta_in.data[32-1 : 0], tr_avst_down_meta_in.data[64-1 : 32], tr_avst_down_meta_in.data[96-1 : 64], tr_avst_down_meta_in.data[128-1 : 96]}; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_xilinx.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_xilinx.sv index cfba048b9..4cde9b3cc 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_xilinx.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/model_xilinx.sv @@ -2,13 +2,13 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kříž -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause -class model_xilinx #(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AXI_CQUSER_WIDTH, AXI_CCUSER_WIDTH, AXI_RCUSER_WIDTH, AXI_RQUSER_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W) +class model_xilinx #(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AXI_CQUSER_WIDTH, AXI_CCUSER_WIDTH, AXI_RCUSER_WIDTH, AXI_RQUSER_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W) extends model_base #(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W); `uvm_component_param_utils(uvm_pcie_adapter::model_xilinx#(CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AXI_CQUSER_WIDTH, AXI_CCUSER_WIDTH, AXI_RCUSER_WIDTH, AXI_RQUSER_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W)) - + // Model inputs uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item #(CQ_MFB_ITEM_WIDTH)) axi_cq_data_in; uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item #(RC_MFB_ITEM_WIDTH)) axi_rc_data_in; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/monitor.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/monitor.sv index 031dbc883..452ccab23 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/monitor.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/monitor.sv @@ -2,7 +2,7 @@ //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author(s): Daniel Kriz -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class monitor #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH) extends uvm_monitor; `uvm_component_param_utils(uvm_pcie_adapter::monitor #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH)) diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/pkg.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/pkg.sv index 5529665da..8d3a5b61e 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/pkg.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/pkg.sv @@ -8,7 +8,7 @@ `define PCIE_ADAPTER_ENV_SV package uvm_pcie_adapter; - + `include "uvm_macros.svh" import uvm_pkg::*; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/sequence.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/sequence.sv index 355acabdb..9def07ff7 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/sequence.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/env/sequence.sv @@ -204,4 +204,4 @@ class crdt_sequence#(CC_MFB_REGIONS, CC_MFB_REGION_SIZE, CC_MFB_BLOCK_SIZE, CC_M end end endtask -endclass \ No newline at end of file +endclass diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/pkg.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/pkg.sv index 8a782b6aa..35e88d787 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/pkg.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/pkg.sv @@ -98,6 +98,6 @@ package test; `include "sequence_xilinx.sv" `include "sequence_intel.sv" `include "test.sv" - + endpackage `endif diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/sequence_xilinx.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/sequence_xilinx.sv index b76dde275..2b5bc708a 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/sequence_xilinx.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/sequence_xilinx.sv @@ -154,12 +154,12 @@ class sequence_xilinx#(CQ_MFB_REGIONS, CC_MFB_REGIONS, RQ_MFB_REGIONS, RC_MFB_RE run_axi_cq_data(); run_axi_rc_data(); run_mfb_rq_data(); - forever begin + forever begin m_mfb_rq_meta_sq.randomize(); m_mfb_rq_meta_sq.start(p_sequencer.m_rq_mfb_meta_sqr); end run_mfb_cc_data(); - forever begin + forever begin m_mfb_cc_meta_sq.randomize(); m_mfb_cc_meta_sq.start(p_sequencer.m_cc_mfb_meta_sqr); end diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/test.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/test.sv index 6cb948c04..f53af4f78 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/test.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/tests/test.sv @@ -1,8 +1,8 @@ -//-- test.sv: Verification test +//-- test.sv: Verification test //-- Copyright (C) 2023 CESNET z. s. p. o. //-- Author: Daniel Kříž -//-- SPDX-License-Identifier: BSD-3-Clause +//-- SPDX-License-Identifier: BSD-3-Clause class r_tile_mfb_seq #(CQ_MFB_REGIONS, CC_MFB_REGIONS, RQ_MFB_REGIONS, RC_MFB_REGIONS, CQ_MFB_REGION_SIZE, CC_MFB_REGION_SIZE, RQ_MFB_REGION_SIZE, RC_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, CC_MFB_BLOCK_SIZE, RQ_MFB_BLOCK_SIZE, RC_MFB_BLOCK_SIZE, CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AVST_DOWN_META_W, AVST_UP_META_W, AXI_CQUSER_WIDTH, AXI_CCUSER_WIDTH, AXI_RCUSER_WIDTH, AXI_RQUSER_WIDTH, AXI_DATA_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W, PCIE_MPS_DW) extends test::sequence_intel#(CQ_MFB_REGIONS, CC_MFB_REGIONS, RQ_MFB_REGIONS, RC_MFB_REGIONS, CQ_MFB_REGION_SIZE, CC_MFB_REGION_SIZE, RQ_MFB_REGION_SIZE, RC_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, CC_MFB_BLOCK_SIZE, RQ_MFB_BLOCK_SIZE, RC_MFB_BLOCK_SIZE, CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AVST_DOWN_META_W, AVST_UP_META_W, AXI_CQUSER_WIDTH, AXI_CCUSER_WIDTH, AXI_RCUSER_WIDTH, AXI_RQUSER_WIDTH, AXI_DATA_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W, PCIE_MPS_DW); `uvm_object_param_utils(test::r_tile_mfb_seq#(CQ_MFB_REGIONS, CC_MFB_REGIONS, RQ_MFB_REGIONS, RC_MFB_REGIONS, CQ_MFB_REGION_SIZE, CC_MFB_REGION_SIZE, RQ_MFB_REGION_SIZE, RC_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, CC_MFB_BLOCK_SIZE, RQ_MFB_BLOCK_SIZE, RC_MFB_BLOCK_SIZE, CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AVST_DOWN_META_W, AVST_UP_META_W, AXI_CQUSER_WIDTH, AXI_CCUSER_WIDTH, AXI_RCUSER_WIDTH, AXI_RQUSER_WIDTH, AXI_DATA_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W, PCIE_MPS_DW)) @@ -52,7 +52,7 @@ class ex_test extends uvm_test; task run_seq_rx(uvm_phase phase); sequence_base m_vseq; - if (IS_INTEL_DEV) + if (IS_INTEL_DEV) if (ENDPOINT_TYPE == "R_TILE") m_vseq = r_tile_mfb_seq #(CQ_MFB_REGIONS, CC_MFB_REGIONS, RQ_MFB_REGIONS, RC_MFB_REGIONS, CQ_MFB_REGION_SIZE, CC_MFB_REGION_SIZE, RQ_MFB_REGION_SIZE, RC_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, CC_MFB_BLOCK_SIZE, RQ_MFB_BLOCK_SIZE, RC_MFB_BLOCK_SIZE, CQ_MFB_ITEM_WIDTH, CC_MFB_ITEM_WIDTH, RQ_MFB_ITEM_WIDTH, RC_MFB_ITEM_WIDTH, AVST_DOWN_META_W, AVST_UP_META_W, AXI_CQUSER_WIDTH, AXI_CCUSER_WIDTH, AXI_RCUSER_WIDTH, AXI_RQUSER_WIDTH, AXI_DATA_WIDTH, RQ_MFB_META_W, RC_MFB_META_W, CQ_MFB_META_W, CC_MFB_META_W, PCIE_MPS_DW)::type_id::create("m_vseq"); else diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/ver_settings.py b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/ver_settings.py index 53fb0dcdb..37d778712 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/ver_settings.py +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/ver_settings.py @@ -152,7 +152,7 @@ "RQ_MFB_BLOCK_SIZE" : "8" , "RQ_MFB_ITEM_WIDTH" : "32" , }, - "_combinations_" : ( + "_combinations_" : ( (), # Works the same as '("default",),' as the "default" is applied in every combination # ("ultrascale_256", ), ("ultrascale_512", ), @@ -163,4 +163,4 @@ ("agilex_dev" ,"r_tile" ,), ("agilex_dev" ,"r_tile", "intel_256",), ), -} \ No newline at end of file +} diff --git a/core/comp/pcie/pcie_mod/comp/pcie_cii2cfg/pcie_cii2cfg_ext.vhd b/core/comp/pcie/pcie_mod/comp/pcie_cii2cfg/pcie_cii2cfg_ext.vhd index 20c7999d9..66f62202e 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_cii2cfg/pcie_cii2cfg_ext.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_cii2cfg/pcie_cii2cfg_ext.vhd @@ -38,7 +38,7 @@ entity PCIE_CII2CFG_EXT is end entity; architecture FULL of PCIE_CII2CFG_EXT is - + signal pcie_cii_req_reg : std_logic; signal pcie_cii_wr_reg : std_logic; signal pcie_cii_addr_reg : std_logic_vector(9 downto 0); diff --git a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_empty.vhd b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_empty.vhd index ab1ac6537..8bb99ec8f 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_empty.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_empty.vhd @@ -24,7 +24,7 @@ begin PCIE_EXT_TAG_EN <= (others => '0'); PCIE_10B_TAG_REQ_EN <= (others => '0'); PCIE_RCB_SIZE <= (others => '0'); - + PCIE_USER_CLK <= (others => '0'); PCIE_USER_RESET <= (others => (others => '0')); diff --git a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd index dadc3926a..5e48eeae9 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd @@ -75,7 +75,7 @@ entity PCIE_CORE is PCIE_SYSRST_N : in std_logic_vector(PCIE_CONS-1 downto 0); -- nINIT_DONE output of the Reset Release Intel Stratix 10 FPGA IP INIT_DONE_N : in std_logic; - + -- ===================================================================== -- PCIe serial interface -- ===================================================================== diff --git a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ptile.vhd b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ptile.vhd index 94c26407e..579803831 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ptile.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ptile.vhd @@ -387,7 +387,7 @@ architecture PTILE of PCIE_CORE is ninit_done : in std_logic := 'X' -- ninit_done ); end component ptile_pcie_2x8; - + constant VSEC_BASE_ADDRESS : integer := 16#D00#; constant PCIE_EPS_INST : natural := tsel(ENDPOINT_MODE=0,PCIE_CONS,2*PCIE_CONS); @@ -569,7 +569,7 @@ begin -- PCIE IP CORE -- ========================================================================= - pcie_core_g : for i in 0 to PCIE_CONS-1 generate + pcie_core_g : for i in 0 to PCIE_CONS-1 generate pcie_core_1x16_g : if ENDPOINT_MODE = 0 generate pcie_core_i : component ptile_pcie_1x16 port map ( @@ -744,7 +744,7 @@ begin p0_cii_addr_o => pcie_cii_addr(i*2), -- .addr p0_cii_wr_o => pcie_cii_wr(i*2), -- .write p0_cii_override_din_i => pcie_cii_override_din(i*2), -- .override_din - + p1_rx_st_ready_i => pcie_avst_down_ready(i*2+1), -- p0_rx_st.ready p1_rx_st_sop_o => pcie_avst_down_sop(i*2+1), -- .startofpacket p1_rx_st_eop_o => pcie_avst_down_eop(i*2+1), -- .endofpacket @@ -903,7 +903,7 @@ begin port map ( PCIE_CLK => pcie_clk(i), PCIE_RESET => pcie_rst(i)(0), - + AVST_DOWN_DATA => pcie_avst_down_data(i), AVST_DOWN_HDR => pcie_avst_down_hdr(i), AVST_DOWN_PREFIX => pcie_avst_down_prefix(i), @@ -913,7 +913,7 @@ begin AVST_DOWN_BAR_RANGE => pcie_avst_down_bar_range(i), AVST_DOWN_VALID => pcie_avst_down_valid(i), AVST_DOWN_READY => pcie_avst_down_ready(i), - + AVST_UP_DATA => pcie_avst_up_data(i), AVST_UP_HDR => pcie_avst_up_hdr(i), AVST_UP_PREFIX => pcie_avst_up_prefix(i), @@ -922,7 +922,7 @@ begin AVST_UP_ERROR => pcie_avst_up_error(i), AVST_UP_VALID => pcie_avst_up_valid(i), AVST_UP_READY => pcie_avst_up_ready(i), - + CRDT_DOWN_INIT_DONE => '0', CRDT_DOWN_UPDATE => open, CRDT_DOWN_CNT_PH => open, @@ -931,7 +931,7 @@ begin CRDT_DOWN_CNT_PD => open, CRDT_DOWN_CNT_NPD => open, CRDT_DOWN_CNT_CPLD => open, - + CRDT_UP_INIT_DONE => '0', CRDT_UP_UPDATE => (others => '0'), CRDT_UP_CNT_PH => (others => '0'), @@ -940,7 +940,7 @@ begin CRDT_UP_CNT_PD => (others => '0'), CRDT_UP_CNT_NPD => (others => '0'), CRDT_UP_CNT_CPLD => (others => '0'), - + CQ_AXI_DATA => (others => '0'), CQ_AXI_USER => (others => '0'), CQ_AXI_LAST => '0', @@ -968,7 +968,7 @@ begin RQ_AXI_KEEP => open, RQ_AXI_VALID => open, RQ_AXI_READY => '0', - + CQ_MFB_DATA => CQ_MFB_DATA(i), CQ_MFB_META => CQ_MFB_META(i), CQ_MFB_SOF => CQ_MFB_SOF(i), diff --git a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd index 4bcce288f..52be0415f 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd @@ -432,7 +432,7 @@ architecture RTILE of PCIE_CORE is pin_perst_n_o : out std_logic -- reset_n ); end component rtile_pcie_1x16; - + constant VSEC_BASE_ADDRESS : integer := 16#D00#; constant PCIE_HIPS : natural := tsel(ENDPOINT_MODE=0,PCIE_ENDPOINTS,PCIE_ENDPOINTS/2); constant MAX_PAYLOAD_SIZE : natural := 512; @@ -507,7 +507,7 @@ architecture RTILE of PCIE_CORE is signal crdt_up_cnt_pd : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); signal crdt_up_cnt_npd : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); signal crdt_up_cnt_cpld : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); - + signal crdt_down_init_done : std_logic_vector(PCIE_ENDPOINTS-1 downto 0); signal crdt_down_update : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(6-1 downto 0); signal crdt_down_cnt_ph : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(2-1 downto 0); @@ -1007,7 +1007,7 @@ begin pcie_adapter_g : for i in 0 to PCIE_ENDPOINTS-1 generate --TODO insert pcie function to HDR - + -- Global valid created as OR data and header valids pcie_avst_down_valid(i) <= pcie_avst_down_dvalid(i) or pcie_avst_down_hvalid(i); @@ -1066,7 +1066,7 @@ begin port map ( PCIE_CLK => pcie_clk(i), PCIE_RESET => pcie_rst(i)(0), - + AVST_DOWN_DATA => pcie_avst_down_data(i), AVST_DOWN_HDR => pcie_avst_down_hdr(i), AVST_DOWN_PREFIX => pcie_avst_down_prefix(i), @@ -1076,7 +1076,7 @@ begin AVST_DOWN_BAR_RANGE => pcie_avst_down_bar_range(i), AVST_DOWN_VALID => pcie_avst_down_valid(i), AVST_DOWN_READY => pcie_avst_down_ready(i), - + AVST_UP_DATA => pcie_avst_up_data(i), AVST_UP_HDR => pcie_avst_up_hdr(i), AVST_UP_PREFIX => pcie_avst_up_prefix(i), @@ -1085,7 +1085,7 @@ begin AVST_UP_ERROR => pcie_avst_up_error(i), AVST_UP_VALID => pcie_avst_up_valid(i), AVST_UP_READY => pcie_avst_up_ready(i), - + CRDT_DOWN_INIT_DONE => crdt_down_init_done(i), CRDT_DOWN_UPDATE => crdt_down_update(i), CRDT_DOWN_CNT_PH => crdt_down_cnt_ph(i), @@ -1094,7 +1094,7 @@ begin CRDT_DOWN_CNT_PD => crdt_down_cnt_pd(i), CRDT_DOWN_CNT_NPD => crdt_down_cnt_npd(i), CRDT_DOWN_CNT_CPLD => crdt_down_cnt_cpld(i), - + CRDT_UP_INIT_DONE => crdt_up_init_done(i), CRDT_UP_UPDATE => crdt_up_update(i), CRDT_UP_CNT_PH => crdt_up_cnt_ph(i), @@ -1103,7 +1103,7 @@ begin CRDT_UP_CNT_PD => crdt_up_cnt_pd(i), CRDT_UP_CNT_NPD => crdt_up_cnt_npd(i), CRDT_UP_CNT_CPLD => crdt_up_cnt_cpld(i), - + CQ_AXI_DATA => (others => '0'), CQ_AXI_USER => (others => '0'), CQ_AXI_LAST => '0', @@ -1131,7 +1131,7 @@ begin RQ_AXI_KEEP => open, RQ_AXI_VALID => open, RQ_AXI_READY => '0', - + CQ_MFB_DATA => CQ_MFB_DATA(i), CQ_MFB_META => CQ_MFB_META(i), CQ_MFB_SOF => CQ_MFB_SOF(i), @@ -1196,7 +1196,7 @@ begin PCIE_DCRDT_UP_INIT_ACK => pcie_dcrdt_up_init_ack(i), PCIE_DCRDT_UP_UPDATE => pcie_dcrdt_up_update(i), PCIE_DCRDT_UP_UPDATE_CNT => pcie_dcrdt_up_update_cnt(i), - + PCIE_HCRDT_DW_INIT => pcie_hcrdt_dw_init(i), PCIE_HCRDT_DW_INIT_ACK => pcie_hcrdt_dw_init_ack(i), PCIE_HCRDT_DW_UPDATE => pcie_hcrdt_dw_update(i), diff --git a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_usp.vhd b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_usp.vhd index ed41995e5..104d46906 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_usp.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_usp.vhd @@ -151,7 +151,7 @@ architecture USP of PCIE_CORE is end loop; return mi_addr_base; end function; - + -- Address bases for all Debug Probes and Event Counters in a single Endpoint function mi_addr_base_dbg_f return slv_array_t is variable mi_addr_base : slv_array_t(1+DBG_EVENTS-1 downto 0)(MI_WIDTH-1 downto 0); @@ -481,7 +481,7 @@ architecture USP of PCIE_CORE is signal pcie_clk : std_logic_vector(PCIE_ENDPOINTS-1 downto 0); signal pcie_rst_async : std_logic_vector(PCIE_ENDPOINTS-1 downto 0); signal pcie_rst : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(RESET_WIDTH+1-1 downto 0); - + signal cfg_rcb_status : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(3 downto 0); signal cfg_max_payload : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(1 downto 0); signal cfg_max_read_req : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(2 downto 0); @@ -631,7 +631,7 @@ architecture USP of PCIE_CORE is signal eve_ph : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); signal eve_pd : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); signal eve_nph : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); - signal eve_npd : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); + signal eve_npd : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); signal eve_ph_reg : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); signal eve_pd_reg : slv_array_t(PCIE_ENDPOINTS-1 downto 0)(4-1 downto 0); @@ -1342,7 +1342,7 @@ begin port map ( PCIE_CLK => pcie_clk(i), PCIE_RESET => pcie_rst(i)(0), - + AVST_DOWN_DATA => (others => '0'), AVST_DOWN_HDR => (others => '0'), AVST_DOWN_PREFIX => (others => '0'), @@ -1352,7 +1352,7 @@ begin AVST_DOWN_BAR_RANGE => (others => '0'), AVST_DOWN_VALID => (others => '0'), AVST_DOWN_READY => open, - + AVST_UP_DATA => open, AVST_UP_HDR => open, AVST_UP_PREFIX => open, @@ -1361,7 +1361,7 @@ begin AVST_UP_ERROR => open, AVST_UP_VALID => open, AVST_UP_READY => '0', - + CRDT_DOWN_INIT_DONE => '0', CRDT_DOWN_UPDATE => open, CRDT_DOWN_CNT_PH => open, @@ -1370,7 +1370,7 @@ begin CRDT_DOWN_CNT_PD => open, CRDT_DOWN_CNT_NPD => open, CRDT_DOWN_CNT_CPLD => open, - + CRDT_UP_INIT_DONE => '0', CRDT_UP_UPDATE => (others => '0'), CRDT_UP_CNT_PH => (others => '0'), @@ -1379,7 +1379,7 @@ begin CRDT_UP_CNT_PD => (others => '0'), CRDT_UP_CNT_NPD => (others => '0'), CRDT_UP_CNT_CPLD => (others => '0'), - + CQ_AXI_DATA => pcie_cq_axi_data(i), CQ_AXI_USER => pcie_cq_axi_user(i), CQ_AXI_LAST => pcie_cq_axi_last(i), @@ -1407,7 +1407,7 @@ begin RQ_AXI_KEEP => pcie_rq_axi_keep(i), RQ_AXI_VALID => pcie_rq_axi_valid(i), RQ_AXI_READY => pcie_rq_axi_ready(i), - + CQ_MFB_DATA => CQ_MFB_DATA(i), CQ_MFB_META => CQ_MFB_META(i), CQ_MFB_SOF => CQ_MFB_SOF(i), diff --git a/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_dw_fsm.vhd b/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_dw_fsm.vhd index 5fb57afcd..a24baf5f7 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_dw_fsm.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_dw_fsm.vhd @@ -39,7 +39,7 @@ begin end if; end if; end process; - + process (all) begin crdt_dw_fsm_nst <= crdt_dw_fsm_pst; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_logic.vhd b/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_logic.vhd index cf0912d0f..f6f4b7e37 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_logic.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_logic.vhd @@ -36,7 +36,7 @@ entity PCIE_CRDT_LOGIC is PCIE_DCRDT_UP_INIT_ACK : out std_logic_vector(2 downto 0); PCIE_DCRDT_UP_UPDATE : in std_logic_vector(2 downto 0); PCIE_DCRDT_UP_UPDATE_CNT : in std_logic_vector(11 downto 0); - + PCIE_HCRDT_DW_INIT : out std_logic_vector(2 downto 0); PCIE_HCRDT_DW_INIT_ACK : in std_logic_vector(2 downto 0); PCIE_HCRDT_DW_UPDATE : out std_logic_vector(2 downto 0); @@ -62,7 +62,7 @@ entity PCIE_CRDT_LOGIC is CRDT_UP_CNT_PD : out std_logic_vector(4-1 downto 0); CRDT_UP_CNT_NPD : out std_logic_vector(4-1 downto 0); CRDT_UP_CNT_CPLD : out std_logic_vector(4-1 downto 0); - + -- In init phase the receiver must set the total number of credits using -- incremental credit updates. The user logic only waits for -- CRDT_DOWN_INIT_DONE to be high. diff --git a/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_up_fsm.vhd b/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_up_fsm.vhd index 4c9d385f2..fb237a47b 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_up_fsm.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_crdt/pcie_crdt_up_fsm.vhd @@ -37,7 +37,7 @@ begin end if; end if; end process; - + process (all) begin crdt_up_fsm_nst <= crdt_up_fsm_pst; diff --git a/core/comp/pcie/pcie_mod/comp/pcie_ctrl/pcie_ctrl.vhd b/core/comp/pcie/pcie_mod/comp/pcie_ctrl/pcie_ctrl.vhd index 26ce250d2..64f13b2ed 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_ctrl/pcie_ctrl.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_ctrl/pcie_ctrl.vhd @@ -105,7 +105,7 @@ entity PCIE_CTRL is -- -- PTC ENABLE: MFB+MVB bus for transferring RQ PTC-DMA transactions. -- MFB+MVB bus is clocked at DMA_CLK. - -- PTC DISABLE: MFB bus only for transferring RQ PCIe transactions + -- PTC DISABLE: MFB bus only for transferring RQ PCIe transactions -- (format according to the PCIe IP used). Compared to the standard MFB -- specification, it does not allow gaps (SRC_RDY=0) inside transactions -- and requires that the first transaction in a word starts at byte 0. @@ -147,7 +147,7 @@ entity PCIE_CTRL is -- -- PTC ENABLE: MFB+MVB bus for transferring RC PTC-DMA transactions. -- MFB+MVB bus is clocked at DMA_CLK. - -- PTC DISABLE: MFB bus only for transferring RC PCIe transactions + -- PTC DISABLE: MFB bus only for transferring RC PCIe transactions -- (format according to the PCIe IP used). Compared to the standard MFB -- specification, it does not allow gaps (SRC_RDY=0) inside transactions -- and requires that the first transaction in a word starts at byte 0. @@ -394,7 +394,7 @@ begin pcie_rq_mfb_prefix_arr <= slv_array_deser(pcie_rq_mfb_prefix,RQ_MFB_REGIONS); pcie_rq_mfb_be_arr <= slv_array_deser(pcie_rq_mfb_be,RQ_MFB_REGIONS); - rq_mfb_meta_g: for i in 0 to RQ_MFB_REGIONS-1 generate + rq_mfb_meta_g: for i in 0 to RQ_MFB_REGIONS-1 generate pcie_rq_mfb_meta_arr(i)(PCIE_RQ_META_HEADER) <= pcie_rq_mfb_hdr_arr(i); pcie_rq_mfb_meta_arr(i)(PCIE_RQ_META_PREFIX) <= pcie_rq_mfb_prefix_arr(i); pcie_rq_mfb_meta_arr(i)(PCIE_RQ_META_FBE) <= pcie_rq_mfb_be_arr(i)(PCIE_META_FBE_W-1 downto 0); @@ -405,7 +405,7 @@ begin pcie_rc_mfb_meta_arr <= slv_array_deser(PCIE_RC_MFB_META,RC_MFB_REGIONS); - rc_mfb_meta_g: for i in 0 to RC_MFB_REGIONS-1 generate + rc_mfb_meta_g: for i in 0 to RC_MFB_REGIONS-1 generate pcie_rc_mfb_hdr_arr(i) <= pcie_rc_mfb_meta_arr(i)(PCIE_RC_META_HEADER); pcie_rc_mfb_prefix_arr(i) <= pcie_rc_mfb_meta_arr(i)(PCIE_RC_META_PREFIX); end generate; @@ -506,7 +506,7 @@ begin DMA_RC_MVB_SRC_RDY <= (others => '0'); PCIE_RQ_MFB_DATA <= DMA_RQ_MFB_DATA(0); - PCIE_RQ_MFB_META <= DMA_RQ_MFB_META(0); + PCIE_RQ_MFB_META <= DMA_RQ_MFB_META(0); PCIE_RQ_MFB_SOF <= DMA_RQ_MFB_SOF(0); PCIE_RQ_MFB_EOF <= DMA_RQ_MFB_EOF(0); PCIE_RQ_MFB_SOF_POS <= DMA_RQ_MFB_SOF_POS(0); @@ -515,7 +515,7 @@ begin DMA_RQ_MFB_DST_RDY(0) <= PCIE_RQ_MFB_DST_RDY; DMA_RC_MFB_DATA(0) <= PCIE_RC_MFB_DATA; - DMA_RC_MFB_META(0) <= PCIE_RC_MFB_META; + DMA_RC_MFB_META(0) <= PCIE_RC_MFB_META; DMA_RC_MFB_SOF(0) <= PCIE_RC_MFB_SOF; DMA_RC_MFB_EOF(0) <= PCIE_RC_MFB_EOF; DMA_RC_MFB_SOF_POS(0) <= PCIE_RC_MFB_SOF_POS; @@ -556,7 +556,7 @@ begin port map( CLK => PCIE_CLK, RST => PCIE_RESET(3), - + RX_MFB_SEL => pcie_cq_mfb_sel, RX_MFB_DATA => PCIE_CQ_MFB_DATA, RX_MFB_META => PCIE_CQ_MFB_META, @@ -566,7 +566,7 @@ begin RX_MFB_EOF_POS => PCIE_CQ_MFB_EOF_POS, RX_MFB_SRC_RDY => PCIE_CQ_MFB_SRC_RDY, RX_MFB_DST_RDY => PCIE_CQ_MFB_DST_RDY, - + TX0_MFB_DATA => mtc_fifo_mfb_data, TX0_MFB_META => mtc_fifo_mfb_meta, TX0_MFB_SOF => mtc_fifo_mfb_sof, @@ -575,7 +575,7 @@ begin TX0_MFB_EOF_POS => mtc_fifo_mfb_eof_pos, TX0_MFB_SRC_RDY => mtc_fifo_mfb_src_rdy, TX0_MFB_DST_RDY => mtc_fifo_mfb_dst_rdy, - + TX1_MFB_DATA => DMA_CQ_MFB_DATA(0), TX1_MFB_META => DMA_CQ_MFB_META(0), TX1_MFB_SOF => DMA_CQ_MFB_SOF(0), @@ -599,7 +599,7 @@ begin port map( CLK => PCIE_CLK, RST => PCIE_RESET(4), - + RX_MFB0_DATA => mtc_cc_mfb_data, RX_MFB0_META => mtc_cc_mfb_meta, RX_MFB0_SOF => mtc_cc_mfb_sof, @@ -608,7 +608,7 @@ begin RX_MFB0_EOF_POS => mtc_cc_mfb_eof_pos, RX_MFB0_SRC_RDY => mtc_cc_mfb_src_rdy, RX_MFB0_DST_RDY => mtc_cc_mfb_dst_rdy, - + RX_MFB1_DATA => DMA_CC_MFB_DATA(0), RX_MFB1_META => DMA_CC_MFB_META(0), RX_MFB1_SOF => DMA_CC_MFB_SOF(0), @@ -617,7 +617,7 @@ begin RX_MFB1_EOF_POS => DMA_CC_MFB_EOF_POS(0), RX_MFB1_SRC_RDY => DMA_CC_MFB_SRC_RDY(0), RX_MFB1_DST_RDY => DMA_CC_MFB_DST_RDY(0), - + TX_MFB_DATA => PCIE_CC_MFB_DATA, TX_MFB_META => PCIE_CC_MFB_META, TX_MFB_SOF => PCIE_CC_MFB_SOF, @@ -681,7 +681,7 @@ begin BAR4_BASE_ADDR => BAR4_BASE_ADDR, BAR5_BASE_ADDR => BAR5_BASE_ADDR, EXP_ROM_BASE_ADDR => EXP_ROM_BASE_ADDR, - + ENDPOINT_TYPE => ENDPOINT_TYPE, DEVICE => DEVICE ) @@ -802,7 +802,7 @@ begin -- Common interface CLK => MI_CLK, RESET => MI_RESET, - + -- Input MI interface IN_DWR => mi_sync_dwr, IN_ADDR => mi_sync_addr, @@ -812,7 +812,7 @@ begin IN_DRD => mi_sync_drd, IN_ARDY => mi_sync_ardy, IN_DRDY => mi_sync_drdy, - + -- Output MI interface OUT_DWR => MI_DWR, OUT_ADDR => MI_ADDR, diff --git a/core/comp/pcie/pcie_mod/pcie_top.vhd b/core/comp/pcie/pcie_mod/pcie_top.vhd index b3101ed01..cd1a9fcf1 100644 --- a/core/comp/pcie/pcie_mod/pcie_top.vhd +++ b/core/comp/pcie/pcie_mod/pcie_top.vhd @@ -126,7 +126,7 @@ entity PCIE is -- -- PTC ENABLE: MFB+MVB bus for transferring RQ PTC-DMA transactions. -- MFB+MVB bus is clocked at DMA_CLK. - -- PTC DISABLE: MFB bus only for transferring RQ PCIe transactions + -- PTC DISABLE: MFB bus only for transferring RQ PCIe transactions -- (format according to the PCIe IP used). Compared to the standard MFB -- specification, it does not allow gaps (SRC_RDY=0) inside transactions -- and requires that the first transaction in a word starts at byte 0. @@ -151,7 +151,7 @@ entity PCIE is -- -- PTC ENABLE: MFB+MVB bus for transferring RC PTC-DMA transactions. -- MFB+MVB bus is clocked at DMA_CLK. - -- PTC DISABLE: MFB bus only for transferring RC PCIe transactions + -- PTC DISABLE: MFB bus only for transferring RC PCIe transactions -- (format according to the PCIe IP used). Compared to the standard MFB -- specification, it does not allow gaps (SRC_RDY=0) inside transactions -- and requires that the first transaction in a word starts at byte 0. @@ -243,15 +243,15 @@ architecture FULL of PCIE is variable pcie_mfb_regions : natural; begin pcie_mfb_regions := MFB_REGIONS; - + -- PTC conversion if ((not PTC_DISABLE)) then if (PCIE_ENDPOINT_TYPE="P_TILE" and PCIE_ENDPOINT_MODE = 1) then - -- 256b PTC-DMA stream to 512b PCIe stream + -- 256b PTC-DMA stream to 512b PCIe stream pcie_mfb_regions := pcie_mfb_regions/2; end if; if (PCIE_ENDPOINT_TYPE="R_TILE" and PCIE_ENDPOINT_MODE = 0) then - -- 512b PTC-DMA stream to 1024b PCIe stream + -- 512b PTC-DMA stream to 1024b PCIe stream pcie_mfb_regions := pcie_mfb_regions*2; end if; end if; @@ -385,7 +385,7 @@ begin PCIE_SYSCLK_N => PCIE_SYSCLK_N, PCIE_SYSRST_N => PCIE_SYSRST_N, INIT_DONE_N => INIT_DONE_N, - + PCIE_RX_P => PCIE_RX_P, PCIE_RX_N => PCIE_RX_N, PCIE_TX_P => PCIE_TX_P, diff --git a/core/comp/pcie/pcie_mod/uvm/dtb_pack.vhd b/core/comp/pcie/pcie_mod/uvm/dtb_pack.vhd index 07b114dd2..afb5a2187 100644 --- a/core/comp/pcie/pcie_mod/uvm/dtb_pack.vhd +++ b/core/comp/pcie/pcie_mod/uvm/dtb_pack.vhd @@ -17,4 +17,4 @@ package dtb_pkg is end package dtb_pkg; package body dtb_pkg is -end dtb_pkg; \ No newline at end of file +end dtb_pkg; diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/dma/driver.sv b/core/comp/pcie/pcie_mod/uvm/tbench/dma/driver.sv index 50c69faca..c3574bb6e 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/dma/driver.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/dma/driver.sv @@ -1,4 +1,4 @@ -// driver.sv: +// driver.sv: // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša @@ -22,7 +22,7 @@ class driver extends uvm_driver#(uvm_dma::sequence_item_rq); task run_phase(uvm_phase phase); - + assert(uvm_config_db #(req_fifo#(uvm_logic_vector_array::sequence_item#(32))) ::get(this, "", "fifo_rq_mfb_data", fifo_rq_mfb_data)) else begin `uvm_fatal(this.get_full_name(), "\n\tCannot get mfb data"); @@ -43,7 +43,7 @@ class driver extends uvm_driver#(uvm_dma::sequence_item_rq); seq_item_port.get_next_item(req); dma_data = uvm_logic_vector_array::sequence_item#(32)::type_id::create("dma_data", this); - dma_hdr = uvm_logic_vector::sequence_item#(DMA_UPHDR_WIDTH_W)::type_id::create("dma_hdr", this); + dma_hdr = uvm_logic_vector::sequence_item#(DMA_UPHDR_WIDTH_W)::type_id::create("dma_hdr", this); dma_data.data = new[req.data.size()](req.data); dma_hdr.data = {req.hdr.relaxed, req.hdr.pasidvld, req.hdr.pasid, req.hdr.vfid, req.hdr.global_id, diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/dma/env.sv b/core/comp/pcie/pcie_mod/uvm/tbench/dma/env.sv index e57d4e95a..787396cd7 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/dma/env.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/dma/env.sv @@ -1,6 +1,6 @@ // env.sv: Verification environment dma // Copyright (C) 2024 CESNET z. s. p. o. -// Author(s): Radek Iša +// Author(s): Radek Iša // SPDX-License-Identifier: BSD-3-Clause @@ -27,7 +27,7 @@ class env#( uvm_reset::sync_cbs reset_sync; protected monitor m_monitor; - protected driver m_driver; + protected driver m_driver; protected uvm_logic_vector_array_mfb::env_rx #(RQ_REGIONS, RQ_REGION_SIZE, RQ_BLOCK_SIZE, RQ_ITEM_WIDTH, RQ_META_WIDTH) m_rq_mfb_env; protected uvm_logic_vector_mvb::env_rx #(RQ_REGIONS, DMA_UPHDR_WIDTH) m_rq_mvb_env; diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/dma/monitor.sv b/core/comp/pcie/pcie_mod/uvm/tbench/dma/monitor.sv index e06893da6..0bc1798dc 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/dma/monitor.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/dma/monitor.sv @@ -1,4 +1,4 @@ -// monitor.sv : Convert dma to mvb and mfb +// monitor.sv : Convert dma to mvb and mfb // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša @@ -28,7 +28,7 @@ class monitor extends uvm_monitor; rq_analysis_port = new("rq_analysis_port", this); rc_analysis_port = new("rc_analysis_port", this); endfunction - + task run_rq(); uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) tr_data; uvm_logic_vector::sequence_item#(sv_dma_bus_pack::DMA_UPHDR_WIDTH) tr_meta; @@ -84,13 +84,13 @@ class monitor extends uvm_monitor; rc_mvb.get(meta); rc_mfb.get(data); - {unit_id, tag, completed, length} = meta.data; + {unit_id, tag, completed, length} = meta.data; dma_rc = uvm_dma::sequence_item_rc::type_id::create("dma_rc", this); - dma_rc.length = length; - dma_rc.completed = completed; - dma_rc.tag = tag; - dma_rc.unit_id = unit_id; - dma_rc.data = data.data; + dma_rc.length = length; + dma_rc.completed = completed; + dma_rc.tag = tag; + dma_rc.unit_id = unit_id; + dma_rc.data = data.data; rc_analysis_port.write(dma_rc); end diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence.sv b/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence.sv index d891281d9..f5f27c15f 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence.sv @@ -1,4 +1,4 @@ -// sequence.sv: +// sequence.sv: // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša @@ -25,7 +25,7 @@ endclass class sequence_void#(type T_TYPE) extends uvm_sequence #(T_TYPE); `uvm_object_param_utils(uvm_dma::sequence_void#(T_TYPE)) - req_fifo#(T_TYPE) fifo; + req_fifo#(T_TYPE) fifo; // Constructor - creates new instance of this class function new(string name = "sequence_mfb_data"); @@ -34,7 +34,7 @@ class sequence_void#(type T_TYPE) extends uvm_sequence #(T_TYPE); task body(); assert(uvm_config_db #(req_fifo#(T_TYPE))::get(m_sequencer, "", "fifo", fifo)) else begin - `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo"); + `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo"); end; forever begin diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence_item.sv b/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence_item.sv index c19176a03..d0067fa66 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence_item.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequence_item.sv @@ -1,6 +1,6 @@ // sequence_item.sv // Copyright (C) 2024 CESNET z. s. p. o. -// Author(s): Radek Iša +// Author(s): Radek Iša // SPDX-License-Identifier: BSD-3-Clause diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequencer.sv b/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequencer.sv index 15d93e4fe..8c392d4ff 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequencer.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/dma/sequencer.sv @@ -1,6 +1,6 @@ -// sequencer.sv : +// sequencer.sv : // Copyright (C) 2024 CESNET z. s. p. o. -// Author(s): Radek Iša +// Author(s): Radek Iša // SPDX-License-Identifier: BSD-3-Clause @@ -63,12 +63,12 @@ class sequencer extends uvm_sequencer #(sequence_item_rq); task run_phase(uvm_phase phase); uvm_dma::sequence_item_rc resp; - forever begin + forever begin fifo_rsp.get(resp); if (resp.completed == 1) begin - info.tag_remove(resp.unit_id, resp.tag); + info.tag_remove(resp.unit_id, resp.tag); end - end + end endtask endclass diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/dut.sv b/core/comp/pcie/pcie_mod/uvm/tbench/dut.sv index 95955d7c7..aeb6b0bc8 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/dut.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/dut.sv @@ -1,4 +1,4 @@ -// dut.sv: Design under test +// dut.sv: Design under test // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Daniel Kriz @@ -284,7 +284,7 @@ module DUT ( // // PTC ENABLE: MFB+MVB bus for transferring RQ PTC-DMA transactions. // MFB+MVB bus is clocked at DMA_CLK. - // PTC DISABLE: MFB bus only for transferring RQ PCIe transactions + // PTC DISABLE: MFB bus only for transferring RQ PCIe transactions // (format according to the PCIe IP used). Compared to the standard MFB // specification, it does not allow gaps (SRC_RDY=0) inside transactions // and requires that the first transaction in a word starts at byte 0. @@ -309,7 +309,7 @@ module DUT ( // // PTC ENABLE: MFB+MVB bus for transferring RC PTC-DMA transactions. // MFB+MVB bus is clocked at DMA_CLK. - // PTC DISABLE: MFB bus only for transferring RC PCIe transactions + // PTC DISABLE: MFB bus only for transferring RC PCIe transactions // (format according to the PCIe IP used). Compared to the standard MFB // specification, it does not allow gaps (SRC_RDY=0) inside transactions // and requires that the first transaction in a word starts at byte 0. diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/env.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/env.sv index dfc853e0d..641889bb6 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/env.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/env.sv @@ -174,7 +174,7 @@ class env #( function void connect_phase(uvm_phase phase); for (int unsigned cons = 0; cons < PCIE_CONS; cons++) begin for (int unsigned pcie_logic = 0; pcie_logic < PCIE_ENDPOINTS/PCIE_CONS; pcie_logic++) begin - const int unsigned pcie = cons*PCIE_ENDPOINTS/PCIE_CONS + pcie_logic; + const int unsigned pcie = cons*PCIE_ENDPOINTS/PCIE_CONS + pcie_logic; //PCIE CONNECT m_pcie_env[pcie].rc_analysis_port.connect(m_scoreboard.pcie_rc[pcie]); m_pcie_env[pcie].cq_analysis_port.connect(m_scoreboard.pcie_cq[pcie]); diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/model_base.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/model_base.sv index 80f0442e8..5faf8b8ff 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/model_base.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/model_base.sv @@ -2,7 +2,7 @@ // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause class model #(REGIONS, PCIE_ENDPOINTS, DMA_PORTS, ITEM_WIDTH) extends uvm_component; diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/model_mtc.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/model_mtc.sv index b5a612c74..e784678c7 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/model_mtc.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/model_mtc.sv @@ -1,6 +1,6 @@ -// model_mtc.sv: Model of mtc +// model_mtc.sv: Model of mtc // Copyright (C) 2024 CESNET z. s. p. o. -// Author(s): Radek Iša +// Author(s): Radek Iša // SPDX-License-Identifier: BSD-3-Clause diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/model_ptc.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/model_ptc.sv index 7b900f55f..55e3d6ba5 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/model_ptc.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/model_ptc.sv @@ -1,6 +1,6 @@ // model_ptc.sv: Model of ptc // Copyright (C) 2024 CESNET z. s. p. o. -// Author(s): Radek Iša +// Author(s): Radek Iša // SPDX-License-Identifier: BSD-3-Clause @@ -178,7 +178,7 @@ class model_ptc#(RQ_REGIONS, DMA_PORTS, ITEM_WIDTH) extends uvm_component; protected uvm_pcie_top::tag_register#(PTC_TAG_WIDTH) tags; protected int unsigned rq_transactions[DMA_PORTS]; protected int unsigned rc_transactions; - protected model_ptc_config cfg; + protected model_ptc_config cfg; function new(string name, uvm_component parent = null); super.new(name, parent); @@ -295,14 +295,14 @@ class model_ptc#(RQ_REGIONS, DMA_PORTS, ITEM_WIDTH) extends uvm_component; rsp_tr.data = rq_tr.hdr.type_ide == 1'b1 ? rq_tr.data : {}; rsp_tr.requester_id = {8'b0, rq_tr.hdr.vfid}; tags.get_dma2pcie(rq_tr.hdr.type_ide, dma, rq_tr.hdr.tag, rq_tr.hdr.unitid, rsp_tr.tag); - case(rq_tr.hdr.lastib) + case(rq_tr.hdr.lastib) 0 : rsp_tr.lbe = 4'b1111; 1 : rsp_tr.lbe = 4'b0111; 2 : rsp_tr.lbe = 4'b0011; 3 : rsp_tr.lbe = 4'b0001; default : rsp_tr.lbe = 'x; endcase - case(rq_tr.hdr.firstib) + case(rq_tr.hdr.firstib) 0 : rsp_tr.fbe = 4'b1111; 1 : rsp_tr.fbe = 4'b1110; 2 : rsp_tr.fbe = 4'b1100; diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/scoreboard.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/scoreboard.sv index f93ce20f9..cfe63d5d9 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/scoreboard.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/scoreboard.sv @@ -1,6 +1,6 @@ // scoreboard.sv: Scoreboard for verification // Copyright (C) 2024 CESNET z. s. p. o. -// Author: Radek Iša +// Author: Radek Iša // SPDX-License-Identifier: BSD-3-Clause diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence.sv index 199bd253d..dd780d345 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence.sv @@ -9,21 +9,21 @@ class sequence_base #( RC_MFB_REGION_SIZE, RC_MFB_BLOCK_SIZE, RC_MFB_META_W, - + CQ_MFB_REGIONS, CQ_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, CQ_MFB_META_W, - + RQ_MFB_META_W, CC_MFB_REGIONS, CC_MFB_REGION_SIZE, CC_MFB_BLOCK_SIZE, CC_MFB_META_W, - + ITEM_WIDTH, - DMA_PORTS, PCIE_CONS, PCIE_ENDPOINTS) extends uvm_sequence; + DMA_PORTS, PCIE_CONS, PCIE_ENDPOINTS) extends uvm_sequence; `uvm_object_param_utils(uvm_pcie_top::sequence_base#(RC_MFB_REGIONS, RC_MFB_REGION_SIZE, RC_MFB_BLOCK_SIZE, RC_MFB_META_W, CQ_MFB_REGIONS, CQ_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, CQ_MFB_META_W, RQ_MFB_META_W, CC_MFB_REGIONS, CC_MFB_REGION_SIZE, CC_MFB_BLOCK_SIZE, CC_MFB_META_W, ITEM_WIDTH, DMA_PORTS, PCIE_CONS, PCIE_ENDPOINTS)) @@ -191,7 +191,7 @@ class sequence_base #( run_cq(index_pcie, index_dma); join_none end - run_pcie(index_pcie); + run_pcie(index_pcie); run_mi(index_pcie); join_none end diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_dma_rq.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_dma_rq.sv index 3ed329e8e..fa74b7163 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_dma_rq.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_dma_rq.sv @@ -47,8 +47,8 @@ class sequence_dma_rq#(DMA_PORTS) extends uvm_sequence#(uvm_dma::sequence_item_r req.hdr.firstib inside {0}; req.hdr.lastib inside {0}; req.hdr.length > 0; - (req.hdr.type_ide == 1) -> req.hdr.length <= MAX_PAYLOAD_SIZE; - (req.hdr.type_ide == 0) -> req.hdr.length <= MAX_REQUEST_SIZE; + (req.hdr.type_ide == 1) -> req.hdr.length <= MAX_PAYLOAD_SIZE; + (req.hdr.type_ide == 0) -> req.hdr.length <= MAX_REQUEST_SIZE; }) else begin `uvm_fatal(m_sequencer.get_full_name(), "\n\tsequence_dma_rq cannot randomize"); end diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_mi.sv b/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_mi.sv index 761efb2c0..f0d6f1325 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_mi.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_mi.sv @@ -44,11 +44,11 @@ class mi_cc_sequence #(MI_DATA_WIDTH, MI_ADDR_WIDTH) extends uvm_mi::sequence_ma get_response(rsp); - if (req.ardy == 1'b1 && rsp.rd == 1'b1) begin + if (req.ardy == 1'b1 && rsp.rd == 1'b1) begin read_active++; read_cnt++; end - if (req.ardy == 1'b1 && rsp.wr == 1'b1) begin + if (req.ardy == 1'b1 && rsp.wr == 1'b1) begin write_cnt++; end save_request(); diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/driver.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/driver.sv index 35d8a4011..e5572946e 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/driver.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/driver.sv @@ -1,4 +1,4 @@ -// driver.sv: pcie driver +// driver.sv: pcie driver // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/fce.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/fce.sv index c662d7266..f915f9561 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/fce.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/fce.sv @@ -1,4 +1,4 @@ -// fce.sv: pcie function to simplify manipulation +// fce.sv: pcie function to simplify manipulation // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/header.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/header.sv index bc5787733..e5f8da462 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/header.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/header.sv @@ -1,6 +1,6 @@ -// header.sv: PCIE header +// header.sv: PCIE header // Copyright (C) 2024 CESNET z. s. p. o. -// Author(s): Radek Iša +// Author(s): Radek Iša // SPDX-License-Identifier: BSD-3-Clause diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/meter.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/meter.sv index 6e08af9a4..71b0e7942 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/meter.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/meter.sv @@ -1,8 +1,8 @@ // meter.sv: measure pcie statistic // Copyright (C) 2024 CESNET z. s. p. o. -// Author(s): Radek Iša +// Author(s): Radek Iša -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause @@ -182,7 +182,7 @@ class stats extends uvm_component; msg = {msg, $sformatf("\n\tCC DATA:\n\t\tMIN : %0.2f (%0.2f b) \n\t\tMAX : %0.2f (%0.2f b)\n\t\tAVG STD_DEV : %0.2f %0.2f (%0.2f b %0.2f b)\n", min, min*KOEF, max, max*KOEF, avg, std_dev, avg*KOEF, std_dev*KOEF)}; cc_speed.count(min, max, avg, std_dev); msg = {msg, $sformatf("\tCC SPEED :\n\t\tMIN : %0.2f Gb/s \n\t\tMAX : %0.2f Gb/s\n\t\tAVG STD_DEV : %0.2f Gb/s %0.2f Gb/s\n", min*KOEF, max*KOEF, avg*KOEF, std_dev*KOEF)}; - `uvm_info(this.get_full_name(), msg, UVM_LOW); + `uvm_info(this.get_full_name(), msg, UVM_LOW); end endtask diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/monitor.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/monitor.sv index d25c925f8..e76272f52 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/monitor.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/monitor.sv @@ -1,4 +1,4 @@ -// monitor.sv: pcie monitor +// monitor.sv: pcie monitor // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/pkg.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/pkg.sv index fd2f1bb8a..42ea8ccf0 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/pkg.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/pkg.sv @@ -1,6 +1,6 @@ // pkg.sv: Package for pcie // Copyright (C) 2024 CESNET z. s. p. o. -// Author: Radek Iša +// Author: Radek Iša // SPDX-License-Identifier: BSD-3-Clause @@ -8,7 +8,7 @@ `define PCIE_ENV_SV package uvm_pcie; - + `include "uvm_macros.svh" import uvm_pkg::*; diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/transaction_info.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/transaction_info.sv index f90fc44c1..fa711f8c8 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie/transaction_info.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie/transaction_info.sv @@ -20,7 +20,7 @@ class transaction_info extends uvm_component; task run_phase(uvm_phase phase); - + forever begin wait (fifo_cc.used() != 0 || fifo_rq.used() != 0); diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_extend/pkg.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_extend/pkg.sv index fe493a6c1..a6c42bc39 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_extend/pkg.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_extend/pkg.sv @@ -1,6 +1,6 @@ // pkg.sv: Package for pcie // Copyright (C) 2024 CESNET z. s. p. o. -// Author: Radek Iša +// Author: Radek Iša // SPDX-License-Identifier: BSD-3-Clause diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/monitor.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/monitor.sv index 0bc433ece..0c3a3c8ae 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/monitor.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/monitor.sv @@ -1,4 +1,4 @@ -// monitor.sv: pcie monitor +// monitor.sv: pcie monitor // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/pkg.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/pkg.sv index b929ba1b5..4139e0932 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/pkg.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/pkg.sv @@ -1,6 +1,6 @@ // pkg.sv: Package for pcie convet intel to pcie // Copyright (C) 2024 CESNET z. s. p. o. -// Author: Radek Iša +// Author: Radek Iša // SPDX-License-Identifier: BSD-3-Clause diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/sequence.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/sequence.sv index a8c5eb55a..58ede7af8 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/sequence.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel/sequence.sv @@ -32,7 +32,7 @@ class sequence_data extends uvm_sequence #(uvm_logic_vector_array::sequence_item task body(); assert(uvm_config_db #(req_fifo#(uvm_pcie::header))::get(m_sequencer, "", "seq_fifo", fifo)) else begin - `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo data"); + `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo data"); end; forever begin @@ -67,7 +67,7 @@ class sequence_meta#(META_WIDTH_DOWN) extends uvm_sequence #(uvm_logic_vector::s localparam int unsigned BAR_RANGE_WIDTH = 3; - req_fifo#(uvm_pcie::header) fifo; + req_fifo#(uvm_pcie::header) fifo; // Constructor - creates new instance of this class function new(string name = "sequence_rc"); @@ -77,7 +77,7 @@ class sequence_meta#(META_WIDTH_DOWN) extends uvm_sequence #(uvm_logic_vector::s task body(); assert(uvm_config_db #(req_fifo#(uvm_pcie::header))::get(m_sequencer, "", "seq_fifo", fifo)) else begin - `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo data"); + `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo data"); end; forever begin diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel_r_tile/env.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel_r_tile/env.sv index b9be17235..f2433527f 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel_r_tile/env.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_intel_r_tile/env.sv @@ -87,7 +87,7 @@ class env #(CQ_MFB_REGIONS, CQ_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, AVST_DOWN_MET m_transaction_approver = transaction_approver::type_id::create("m_transaction_approver", this); m_valuer = valuer #(AVST_UP_META_W)::type_id::create("m_valuer", this); m_balance_splitter = balance_splitter::type_id::create("m_balance_splitter", this); - + // THE CURRENT IMPLEMENTATION OF PCIE-TOP DOES NOT TAKE INTO ACCOUNT UP-SIDE CREDITS SENT FROM VERIFICATION // UNCOMMENT BELOW IF YOU WANT TO ENABLE CHECKING OF THIS FEATURE // m_transaction_checker = transaction_checker #(CC_MFB_REGIONS, CC_MFB_REGION_SIZE, CC_MFB_BLOCK_SIZE, ITEM_WIDTH, AVST_UP_META_W, 3)::type_id::create("m_transaction_checker", this); @@ -158,7 +158,7 @@ class env #(CQ_MFB_REGIONS, CQ_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, AVST_DOWN_MET uvm_pcie_intel::sequence_data seq_data; uvm_pcie_intel::sequence_meta #(AVST_DOWN_META_W) seq_meta; uvm_avst::sequence_lib_tx #(CC_MFB_REGIONS, CC_MFB_REGION_SIZE, CC_MFB_BLOCK_SIZE, ITEM_WIDTH, AVST_UP_META_W) seq_up_rdy; - + for (int unsigned i = 0; i < 3; i++) begin m_crdt_up_hdr_sequence_init [i] = uvm_avst_crdt::sequence_rx_initializing_hdr::type_id::create($sformatf("m_crdt_up_hdr_sequence_init_%0d", i)); m_crdt_up_data_sequence_init[i] = uvm_avst_crdt::sequence_rx_initializing_data::type_id::create($sformatf("m_crdt_up_data_sequence_init_%0d", i)); @@ -218,7 +218,7 @@ class env #(CQ_MFB_REGIONS, CQ_MFB_REGION_SIZE, CQ_MFB_BLOCK_SIZE, AVST_DOWN_MET for (int unsigned i = 0; i < 3; i++) begin fork int unsigned j = i; - + forever begin assert(m_crdt_up_hdr_sequence_returning[j].randomize()); m_crdt_up_hdr_sequence_returning[j].start(m_avst_crdt_up_hdr[j].m_sequencer); diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/fce.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/fce.sv index 81d34e902..8df9b99a5 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/fce.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/fce.sv @@ -1,6 +1,6 @@ // fce.sv: convert function xilinx to pcie // Copyright (C) 2024 CESNET z. s. p. o. -// Author: Radek Iša +// Author: Radek Iša // SPDX-License-Identifier: BSD-3-Clause diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/monitor.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/monitor.sv index 6b4f1964a..84ab52823 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/monitor.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/monitor.sv @@ -1,4 +1,4 @@ -// monitor.sv: pcie monitor +// monitor.sv: pcie monitor // Copyright (C) 2024 CESNET z. s. p. o. // Author(s): Radek Iša diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/pkg.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/pkg.sv index 6c473e2b4..ede3f0754 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/pkg.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/pkg.sv @@ -1,6 +1,6 @@ // pkg.sv: Package for pcie convet xilinx to pcie // Copyright (C) 2024 CESNET z. s. p. o. -// Author: Radek Iša +// Author: Radek Iša // SPDX-License-Identifier: BSD-3-Clause @@ -8,7 +8,7 @@ `define PCIE_XILINX_ENV_SV package uvm_pcie_xilinx; - + `include "uvm_macros.svh" import uvm_pkg::*; diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/sequence.sv b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/sequence.sv index 87c6026da..2ddd17794 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/sequence.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/pcie_xilinx/sequence.sv @@ -23,7 +23,7 @@ endclass class sequence_rc extends uvm_sequence #(uvm_logic_vector_array::sequence_item#(32)); `uvm_object_param_utils(uvm_pcie_xilinx::sequence_rc) - req_fifo#(uvm_pcie::completer_header) fifo; + req_fifo#(uvm_pcie::completer_header) fifo; // Constructor - creates new instance of this class function new(string name = "sequence_rc"); @@ -32,7 +32,7 @@ class sequence_rc extends uvm_sequence #(uvm_logic_vector_array::sequence_item#( task body(); assert(uvm_config_db #(req_fifo#(uvm_pcie::completer_header))::get(m_sequencer, "", "seq_fifo_rc", fifo)) else begin - `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo rc"); + `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo rc"); end; forever begin @@ -58,7 +58,7 @@ class sequence_rc extends uvm_sequence #(uvm_logic_vector_array::sequence_item#( logic [32-1:0] hdr[3]; int unsigned move; - //get header from + //get header from wait(fifo.size() != 0); pcie_cc = fifo.pop_front(); @@ -89,7 +89,7 @@ class sequence_rc extends uvm_sequence #(uvm_logic_vector_array::sequence_item#( attr[0] = pcie_cc.no_snoop; r_3 = 0; - {hdr[2], hdr[1], hdr[0]} = + {hdr[2], hdr[1], hdr[0]} = {r_3, attr, tc, r_2, completer_id, tag, requester_id, r_1, poisoned, completion_status, dword_count, r_0, request_completed, locked_read_completion, byte_count, err_code, lower_addr}; @@ -102,7 +102,7 @@ endclass class sequence_cq extends uvm_sequence #(uvm_logic_vector_array::sequence_item#(32)); `uvm_object_param_utils(uvm_pcie_xilinx::sequence_cq) - req_fifo#(uvm_pcie::request_header) fifo; + req_fifo#(uvm_pcie::request_header) fifo; // Constructor - creates new instance of this class function new(string name = "sequence_cq"); @@ -112,7 +112,7 @@ class sequence_cq extends uvm_sequence #(uvm_logic_vector_array::sequence_item#( task body(); assert(uvm_config_db #(req_fifo#(uvm_pcie::request_header) )::get(m_sequencer, "", "seq_fifo_cq", fifo)) else begin - `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo cq") + `uvm_fatal(m_sequencer != null ? m_sequencer.get_full_name() : "", "\n\tCannot get fifo cq") end; forever begin diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/testbench_intel_r_tile.sv b/core/comp/pcie/pcie_mod/uvm/tbench/testbench_intel_r_tile.sv index d3001ad92..a6b0cc810 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/testbench_intel_r_tile.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/testbench_intel_r_tile.sv @@ -310,7 +310,7 @@ module testbench; assign down_hdr_init_ack[i] = avst_crdt_down_hdr[pcie_e][i].INIT_ACK; // DOWN DATA assign down_data_init_ack[i] = avst_crdt_down_data[pcie_e][i].INIT_ACK; - + // UP HDR assign avst_crdt_up_hdr[pcie_e][i].INIT_ACK = up_hdr_init_ack[i]; // UP DATA @@ -348,5 +348,5 @@ module testbench; end end endgenerate - + endmodule diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/testbench_xilinx.sv b/core/comp/pcie/pcie_mod/uvm/tbench/testbench_xilinx.sv index 19bc0b1a6..453dcd15c 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/testbench_xilinx.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/testbench_xilinx.sv @@ -230,7 +230,7 @@ module testbench; assign DUT_U.VHDL_DUT_U.pcie_core_i.cfg_rcb_status[pcie_e][0] = 1'b0; end - + endgenerate endmodule diff --git a/core/comp/pcie/pcie_mod/uvm/tbench/tests/pkg.sv b/core/comp/pcie/pcie_mod/uvm/tbench/tests/pkg.sv index 738a0a9f5..45dd2d860 100644 --- a/core/comp/pcie/pcie_mod/uvm/tbench/tests/pkg.sv +++ b/core/comp/pcie/pcie_mod/uvm/tbench/tests/pkg.sv @@ -64,7 +64,7 @@ package test; // ===================================================================== // Common configuration // ===================================================================== - // DMA ports per PCIE_ENDPOINT. Total number of dma_ports is PCIE_ENDPOINTS*DMA_PORTS + // DMA ports per PCIE_ENDPOINT. Total number of dma_ports is PCIE_ENDPOINTS*DMA_PORTS parameter DMA_PORTS = 16; // Connected PCIe endpoint type // P_TILE, R_TILE diff --git a/core/comp/pcie/pcie_mod/uvm/ver_settings.py b/core/comp/pcie/pcie_mod/uvm/ver_settings.py index f807de261..93b1b3d05 100644 --- a/core/comp/pcie/pcie_mod/uvm/ver_settings.py +++ b/core/comp/pcie/pcie_mod/uvm/ver_settings.py @@ -198,7 +198,7 @@ "dma_ports_2" : { "DMA_PORTS" : 2, }, - + "_combinations_" : { "P_TILE_512" : ("intel_p_tile_512", ), "P_TILE_256_BIF" : ("intel_p_tile_256_bif", ), diff --git a/core/doc/app.rst b/core/doc/app.rst index 87b6f71d6..7ccb964ae 100644 --- a/core/doc/app.rst +++ b/core/doc/app.rst @@ -69,7 +69,7 @@ The application sends packets to the DMA module over two buses, MVB and MFB (``D - ``MVB_CHANNEL`` - the DMA channel number - ``MVB_DISCARD`` - A discard flag (the packet is discarded on the DMA input when you set this flag to 1) -The MFB bus transfers the packet data, which may contain a user header before the payload data (e.g., an Ethernet packet). +The MFB bus transfers the packet data, which may contain a user header before the payload data (e.g., an Ethernet packet). You can determine the presence of the user header and its length from the metadata in the ``DMA_RX_MVB_HDR_META`` signal (see the previous section). The minimum allowed length of the packet data is 60B, if necessary, the application must add padding to the packet. diff --git a/core/doc/configuration.rst b/core/doc/configuration.rst index 44c47a774..e1b579ab8 100644 --- a/core/doc/configuration.rst +++ b/core/doc/configuration.rst @@ -306,7 +306,7 @@ are visible in the `*.inc.tcl` files and can be added to the array. Adding constants to the VHDL package ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ It is recommended to add card-specific constants to the ``combo_user_const`` VHDL -package in `card_const.tcl` file. The way of adding these constants was described in +package in `card_const.tcl` file. The way of adding these constants was described in the :ref:`core_config_vhdl_pkg_const` section in the documentation of NDK-CORE configuration. diff --git a/core/doc/eth.rst b/core/doc/eth.rst index 2f559c48a..8ded3ed88 100644 --- a/core/doc/eth.rst +++ b/core/doc/eth.rst @@ -396,4 +396,4 @@ Notation: NUMBER_OF_CHANNELS x SPEED - `Intel E-tile Ethernet Hard IP User Guide `_ - `Intel E-Tile Transceiver PHY User Guide `_ - `Xilinx Ultrascale+ CMAC Ethernet Hard IP User Guide `_ -- `Xilinx LBUS documentation `_ \ No newline at end of file +- `Xilinx LBUS documentation `_ diff --git a/core/doc/how_to_start.rst b/core/doc/how_to_start.rst index 837d0c9fd..0d30d3670 100644 --- a/core/doc/how_to_start.rst +++ b/core/doc/how_to_start.rst @@ -62,7 +62,7 @@ The NDK platform uses the `nfb-info tool `_ and an `API for generating read/write memory requests `_. These requests are transferred via the :ref:`MI bus ` in the NDK firmware. This memory-oriented bus is wired throughout the NDK firmware and each part has an allocated address space. The components accessible over the MI bus and their specific address spaces are described in the NDK using a :ref:`DeviceTree `. +The NDK provides the `nfb-bus tool `_ and an `API for generating read/write memory requests `_. These requests are transferred via the :ref:`MI bus ` in the NDK firmware. This memory-oriented bus is wired throughout the NDK firmware and each part has an allocated address space. The components accessible over the MI bus and their specific address spaces are described in the NDK using a :ref:`DeviceTree `. The MI bus interconnection allows easy access to implemented Control/Status Registers (CSR). Communication via the :ref:`MI bus ` is always initiated by the software via direct memory access to the PCIe device (FPGA card) memory space. The software sends a read or write PCIe transaction, which is then processed by the :ref:`MTC module ` implemented in the FPGA. The MTC module acts as a Master point on the MI bus. It translates requests from the PCIe bus to the MI bus and handles their execution. diff --git a/core/doc/testing.rst b/core/doc/testing.rst index 4c7d883d4..bec556a66 100644 --- a/core/doc/testing.rst +++ b/core/doc/testing.rst @@ -42,7 +42,7 @@ The GLS module also comes with a Python script (``/n .. code-block:: - $ python3 gls_mod.py + $ python3 gls_mod.py gls_mod.py mode [port_list] Example: gls_mod.py 1 "0,1" diff --git a/core/top/DevTree.tcl b/core/top/DevTree.tcl index 3db6db45d..a9bda9d12 100644 --- a/core/top/DevTree.tcl +++ b/core/top/DevTree.tcl @@ -75,7 +75,7 @@ proc dts_build_netcope {} { if { [llength [info procs dts_card_specific]] > 0 } { append ret [ dts_card_specific ] } - + # TSU component global TSU_ENABLE if {$TSU_ENABLE} { diff --git a/core/top/fpga_common.vhd b/core/top/fpga_common.vhd index 063b44535..1579648cb 100644 --- a/core/top/fpga_common.vhd +++ b/core/top/fpga_common.vhd @@ -38,7 +38,7 @@ generic ( PLL_OUT3_DIV : natural := 12; -- Switch CLK_GEN ref clock to clk_pci, default SYSCLK - USE_PCIE_CLK : boolean := false; + USE_PCIE_CLK : boolean := false; -- Number of PCIe connectors present on board PCIE_CONS : natural := 1; @@ -106,7 +106,7 @@ generic ( MEM_REFR_PERIOD_WIDTH : natural := 32; MEM_DEF_REFR_PERIOD : integer := 0; AMM_FREQ_KHZ : natural := 0; - + STATUS_LEDS : natural := 2; MISC_IN_WIDTH : natural := 0; MISC_OUT_WIDTH : natural := 0; @@ -462,7 +462,7 @@ architecture FULL of FPGA_COMMON is signal clk_dma : std_logic; signal clk_dma_x2 : std_logic; signal clk_app : std_logic; - + signal rst_pci : std_logic_vector(PCIE_ENDPOINTS-1 downto 0); signal rst_eth_phy : std_logic_vector(ETH_PORTS-1 downto 0); signal rst_eth_streams : std_logic_vector(ETH_STREAMS-1 downto 0); @@ -638,22 +638,22 @@ architecture FULL of FPGA_COMMON is signal boot_request : std_logic; signal boot_image : std_logic; - signal axi_mi_addr_s : std_logic_vector(8 - 1 downto 0); - signal axi_mi_dwr_s : std_logic_vector(32 - 1 downto 0); - signal axi_mi_wr_s : std_logic; - signal axi_mi_rd_s : std_logic; + signal axi_mi_addr_s : std_logic_vector(8 - 1 downto 0); + signal axi_mi_dwr_s : std_logic_vector(32 - 1 downto 0); + signal axi_mi_wr_s : std_logic; + signal axi_mi_rd_s : std_logic; signal axi_mi_be_s : std_logic_vector((32/8)-1 downto 0) := (others => '0'); - signal axi_mi_ardy_s : std_logic; - signal axi_mi_drd_s : std_logic_vector(32 - 1 downto 0); + signal axi_mi_ardy_s : std_logic; + signal axi_mi_drd_s : std_logic_vector(32 - 1 downto 0); signal axi_mi_drdy_s : std_logic; - signal bmc_mi_addr_s : std_logic_vector(8 - 1 downto 0); - signal bmc_mi_dwr_s : std_logic_vector(32 - 1 downto 0); - signal bmc_mi_wr_s : std_logic; - signal bmc_mi_rd_s : std_logic; + signal bmc_mi_addr_s : std_logic_vector(8 - 1 downto 0); + signal bmc_mi_dwr_s : std_logic_vector(32 - 1 downto 0); + signal bmc_mi_wr_s : std_logic; + signal bmc_mi_rd_s : std_logic; signal bmc_mi_be_s : std_logic_vector((32/8)-1 downto 0) := (others => '0'); - signal bmc_mi_ardy_s : std_logic; - signal bmc_mi_drd_s : std_logic_vector(32 - 1 downto 0); + signal bmc_mi_ardy_s : std_logic; + signal bmc_mi_drd_s : std_logic_vector(32 - 1 downto 0); signal bmc_mi_drdy_s : std_logic; -- clk_gen reference clock @@ -815,7 +815,7 @@ begin DMA_CLK => clk_dma, DMA_RESET => rst_dma(0), - + DMA_RQ_MFB_DATA => dma_rq_mfb_data, DMA_RQ_MFB_META => dma_rq_mfb_meta, DMA_RQ_MFB_SOF => dma_rq_mfb_sof, @@ -888,29 +888,29 @@ begin cdc_pcie_up_dma_i: entity work.ASYNC_OPEN_LOOP generic map ( IN_REG => true, - TWO_REG => false - ) + TWO_REG => false + ) port map( ACLK => clk_pci(i), BCLK => clk_dma, ARST => '0', BRST => '0', - ADATAIN => pcie_link_up(i), - BDATAOUT => dma_pcie_link_up(i) + ADATAIN => pcie_link_up(i), + BDATAOUT => dma_pcie_link_up(i) ); cdc_pcie_up_app_i: entity work.ASYNC_OPEN_LOOP generic map ( IN_REG => true, - TWO_REG => false - ) + TWO_REG => false + ) port map( ACLK => clk_pci(i), BCLK => clk_app, ARST => '0', BRST => '0', - ADATAIN => pcie_link_up(i), - BDATAOUT => app_pcie_link_up(i) + ADATAIN => pcie_link_up(i), + BDATAOUT => app_pcie_link_up(i) ); cdc_pcie_fpga_id_i: entity work.ASYNC_OPEN_LOOP_SMD @@ -1301,7 +1301,7 @@ begin CLK_USER_X2 => clk_usr_x2, CLK_USER_X3 => clk_usr_x3, CLK_USER_X4 => clk_usr_x4, - + RESET_USER => rst_usr_x1, RESET_USER_X2 => rst_usr_x2, RESET_USER_X3 => rst_usr_x3, @@ -1423,7 +1423,7 @@ begin HBM_AXI_AWPROT => HBM_AXI_AWPROT, HBM_AXI_AWQOS => HBM_AXI_AWQOS, HBM_AXI_AWUSER => HBM_AXI_AWUSER, - + HBM_AXI_WDATA => HBM_AXI_WDATA, HBM_AXI_WDATA_PARITY => HBM_AXI_WDATA_PARITY, HBM_AXI_WLAST => HBM_AXI_WLAST, @@ -1438,7 +1438,7 @@ begin MEM_CLK => MEM_CLK, MEM_RST => MEM_RST, - + MEM_AVMM_READY => MEM_AVMM_READY, MEM_AVMM_READ => MEM_AVMM_READ, MEM_AVMM_WRITE => MEM_AVMM_WRITE, @@ -1451,7 +1451,7 @@ begin MEM_REFR_PERIOD => MEM_REFR_PERIOD, MEM_REFR_REQ => MEM_REFR_REQ, MEM_REFR_ACK => MEM_REFR_ACK, - + EMIF_RST_REQ => EMIF_RST_REQ, EMIF_RST_DONE => EMIF_RST_DONE, EMIF_ECC_USR_INT => EMIF_ECC_USR_INT, @@ -1621,13 +1621,13 @@ begin ETH_CLK => clk_eth_phy, SYS_CLK => clk_usr_x2, SYS_RESET => rst_usr_x2(0), - + ETH_RX_LINK_UP => eth_rx_link_up_ser, ETH_RX_ACTIVITY => eth_rx_activity_ser, ETH_TX_ACTIVITY => eth_tx_activity_ser, ETH_PORT_ENABLED => (others => '1'), ETH_MODPRS_N => eth_modprs_n, - + ETH_LED_G => ETH_LED_G, ETH_LED_R => ETH_LED_R ); diff --git a/doc/source/_ext/ndk-fpga.py b/doc/source/_ext/ndk-fpga.py index 1b8016661..21abb17ba 100644 --- a/doc/source/_ext/ndk-fpga.py +++ b/doc/source/_ext/ndk-fpga.py @@ -1,5 +1,6 @@ import os + def build_init(app): os.symlink(app.srcdir + '/../../apps', app.srcdir + '/ndk_apps') os.symlink(app.srcdir + '/../../core', app.srcdir + '/ndk_core') @@ -8,6 +9,7 @@ def build_init(app): os.symlink(app.srcdir + '/../../extra', app.srcdir + '/ndk_extra') os.symlink(app.srcdir + '/../../comp', app.srcdir + '/comp') + def build_finish(app, exception): os.remove(app.srcdir + '/ndk_apps') os.remove(app.srcdir + '/ndk_core') @@ -16,6 +18,7 @@ def build_finish(app, exception): os.remove(app.srcdir + '/ndk_extra') os.remove(app.srcdir + '/comp') + def setup(app): app.connect('builder-inited', build_init) app.connect('build-finished', build_finish) diff --git a/doc/source/app-minimal.rst b/doc/source/app-minimal.rst index 4341bb536..d3c8fd79b 100644 --- a/doc/source/app-minimal.rst +++ b/doc/source/app-minimal.rst @@ -44,11 +44,11 @@ The NDK-based Minimal application also contains :ref:`Memory Tester Mem_logger statistics: ---------------------- - write requests 33554431 - write words 134217724 - read requests 33554431 - requested words 134217724 - received words 134217724 + write requests 33554431 + write words 134217724 + read requests 33554431 + requested words 134217724 + received words 134217724 Flow: write 160.78 [Gb/s] read 161.68 [Gb/s] @@ -62,23 +62,23 @@ The NDK-based Minimal application also contains :ref:`Memory Tester max 555.00 [ns] avg 131.56 [ns] histogram [ns]: - 93.4 - 117.5 ... 12613618 - 117.5 - 141.6 ... 13893635 - 141.6 - 165.7 ... 6618217 - 503.0 - 527.1 ... 74899 - 527.1 - 551.2 ... 265549 - 551.2 - 575.3 ... 88513 + 93.4 - 117.5 ... 12613618 + 117.5 - 141.6 ... 13893635 + 141.6 - 165.7 ... 6618217 + 503.0 - 527.1 ... 74899 + 527.1 - 551.2 ... 265549 + 551.2 - 575.3 ... 88513 Errors: - zero burst count 0 - simultaneous r+w 0 + zero burst count 0 + simultaneous r+w 0 Paralel reads count: - min 0 - max 13 - avg 10.83 - 0.0 - 4.0 ... 4 - 4.0 - 8.0 ... 27238 - 8.0 - 12.0 ... 4294967295 - 12.0 - 16.0 ... 13345442 + min 0 + max 13 + avg 10.83 + 0.0 - 4.0 ... 4 + 4.0 - 8.0 ... 27238 + 8.0 - 12.0 ... 4294967295 + 12.0 - 16.0 ... 13345442 .. note:: diff --git a/doc/source/conf.py b/doc/source/conf.py index 90a16798d..3f39d97a9 100644 --- a/doc/source/conf.py +++ b/doc/source/conf.py @@ -1,13 +1,15 @@ # -- Path setup -------------------------------------------------------------- import os import sys -sys.path.append(os.path.abspath("./_ext")) -import sphinx_rtd_theme from pathlib import Path from datetime import date from git import Repo + +# path for ndk-fpga extension +sys.path.append(os.path.abspath("./_ext")) + current_year = date.today().year git_repo = Repo(search_parent_directories=True) git_branch = git_repo.active_branch.name diff --git a/doc/source/index.rst b/doc/source/index.rst index 92ff8b9e8..7ed52d61e 100644 --- a/doc/source/index.rst +++ b/doc/source/index.rst @@ -1,4 +1,4 @@ -Documentation of Minimal NDK Application +Documentation of Minimal NDK Application **************************************** **Welcome to documentation of Minimal NDK Application!** diff --git a/tests/ci/pycodestyle.sh b/tests/ci/pycodestyle.sh index 65c0b75a1..56287ca2b 100755 --- a/tests/ci/pycodestyle.sh +++ b/tests/ci/pycodestyle.sh @@ -1,3 +1,3 @@ #! /bin/sh -flake8 --extend-exclude "ver_settings.py,synth_settings.py" --statistics --extend-ignore=T201,T202,B902,F821,E501,E203,E221,E261,E265,E266 +flake8 --extend-exclude "ver_settings.py,synth_settings.py,extra/" --statistics --extend-ignore=T201,T202,B902,F821,E501,E203,E221,E261,E265,E266