Merge branch 'cabal_s10dk_ip' into 'devel'

chore(DK-DEV-1SDX-P): use IP generation using TCL for selected IPs See merge request ndk/ndk-fpga!123
CESNET · Dec 16, 2024 · 74fc4b8 · 74fc4b8
2 parents 47e15ee + 079a934
commit 74fc4b8
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Showing 7 changed files with 113 additions and 31,592 deletions.
diff --git a/cards/intel/dk-dev-1sdx-p/src/Modules.tcl b/cards/intel/dk-dev-1sdx-p/src/Modules.tcl
@@ -12,16 +12,37 @@ set FPGA_COMMON_BASE "$ARCHGRP_ARR(CORE_BASE)/top"
 
 set COMPONENTS [list [list "FPGA_COMMON" $FPGA_COMMON_BASE $ARCHGRP]]
 
+# IP components
+set IP_COMMON_TCL $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/common.tcl
+source $IP_COMMON_TCL
+
+set ARCHGRP_ARR(IP_COMMON_TCL)    $IP_COMMON_TCL
+set ARCHGRP_ARR(IP_TEMPLATE_BASE) $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/intel
+set ARCHGRP_ARR(IP_MODIFY_BASE)   $ENTITY_BASE/ip
+set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Stratix 10"
+set ARCHGRP_ARR(IP_DEVICE)        $ARCHGRP_ARR(FPGA)
+
+set PCIE_CONF [dict create 0 "1x16" 1 "2x8"]
+set PTILE_PCIE_IP_NAME "ptile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]"
+
+# see '$ARCHGRP_ARR(CORE_BASE)/src/ip/common.tcl' for more information regarding the fields
+#                         script_path    script_name       ip_comp_name     type  modify
+lappend IP_COMPONENTS [list  "misc"   "mailbox_client"   "mailbox_client_ip"  0      0]
+lappend IP_COMPONENTS [list  "misc"   "reset_release"    "reset_release_ip"   0      0]
+lappend IP_COMPONENTS [list  "pcie"   "ptile_pcie"       $PTILE_PCIE_IP_NAME  0      1]
+
+if {$ARCHGRP_ARR(VIRTUAL_DEBUG_ENABLE)} {
+    lappend IP_COMPONENTS [list "misc"  "jtag_op"        "jtag_op_ip"         0      0]
+}
+
+lappend MOD {*}[get_ip_mod_files $IP_COMPONENTS [array get ARCHGRP_ARR]]
+
 # IP sources
 set MOD "$MOD $ENTITY_BASE/ip/iopll_ip.ip"
-set MOD "$MOD $ENTITY_BASE/ip/reset_release_ip.ip"
-set MOD "$MOD $ENTITY_BASE/ip/ptile_pcie_2x8.ip"
-set MOD "$MOD $ENTITY_BASE/ip/ptile_pcie_1x16.ip"
 set MOD "$MOD $ENTITY_BASE/ip/etile_eth_4x10g.ip"
 set MOD "$MOD $ENTITY_BASE/ip/etile_eth_4x25g.ip"
 set MOD "$MOD $ENTITY_BASE/ip/etile_eth_1x100g.ip"
 set MOD "$MOD $ENTITY_BASE/ip/emif_s10dx.ip"
-set MOD "$MOD $ENTITY_BASE/ip/mailbox_client_ip.ip"
 
 # Top-level
 set MOD "$MOD $ENTITY_BASE/fpga.vhd"
diff --git a/cards/intel/dk-dev-1sdx-p/src/Quartus.inc.tcl b/cards/intel/dk-dev-1sdx-p/src/Quartus.inc.tcl
@@ -14,7 +14,14 @@ source $CORE_BASE/Quartus.inc.tcl
 # Propagating card constants to the Modules.tcl files of the underlying components.
 # The description of usage of this array is provided in the Parametrization section
 # of the NDK-CORE repository.
-set CARD_ARCHGRP(CORE_BASE) $CORE_BASE
+set CARD_ARCHGRP(CORE_BASE)          $CORE_BASE
+set CARD_ARCHGRP(IP_BUILD_DIR)       $CARD_BASE/src/ip
+set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE
+set CARD_ARCHGRP(NET_MOD_ARCH)       $NET_MOD_ARCH
+
+# select fpga name
+set CARD_FPGA                        "1SD280PT2F55E1VG"
+set CARD_ARCHGRP(FPGA)               $CARD_FPGA
 
 # make lists from associative arrays
 set CARD_ARCHGRP_L [array get CARD_ARCHGRP]
@@ -29,7 +36,7 @@ lappend HIERARCHY(COMPONENTS) \
 
 # Design parameters
 set SYNTH_FLAGS(MODULE) "FPGA"
-set SYNTH_FLAGS(FPGA)   "1SD280PT2F55E1VG"
+set SYNTH_FLAGS(FPGA)   $CARD_FPGA
 
 # QSF constraints for specific parts of the design
 set SYNTH_FLAGS(CONSTR) ""