+
+ +
+

AXIS_ASFIFOX

+
+
+ENTITY AXIS_ASFIFOX IS
+
Generics + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Generic

Type

Default

Description

TDATA_WIDTH

natural

512

Width of AXI-Stream data signal in bits.

TUSER_WIDTH

natural

64

Width of AXI-Stream user signal in bits.

FIFO_ITEMS

natural

512

FIFO depth in number of data words, must be power of two! +Minimum value is 2.

RAM_TYPE

string

“BRAM”

Select memory implementation. Options: +“LUT” - effective for shallow FIFO (approx. ITEMS <= 64), +“BRAM” - effective for deep FIFO (approx. ITEMS > 64).

FWFT_MODE

boolean

True

First Word Fall Through mode. If FWFT_MODE=True, valid data will be +ready at the ASFIFOX output without TX_AXIS_TREADY requests.

OUTPUT_REG

boolean

True

Enabled output registers allow better timing for a few flip-flops.

AFULL_OFFSET

natural

FIFO_ITEMS/2

Sets the maximum number of remaining free data words in the ASFIFOX +that triggers the RX_FIFO_AFULL signal.

AEMPTY_OFFSET

natural

FIFO_ITEMS/2

Sets the maximum number of data words stored in the ASFIFOX that +triggers the TX_FIFO_AEMPTY signal.

DEVICE

string

“AGILEX”

Target device: AGILEX, STRATIX10, ULTRASCALE,…

+Ports + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Port

Type

Mode

Description

=====

RX AXI-Stream interface (RX_CLK)

=====

=====

RX_CLK

std_logic

in

RX_RESET

std_logic

in

RX_AXIS_TDATA

std_logic_vector(TDATA_WIDTH-1 downto 0)

in

RX_AXIS_TUSER

std_logic_vector(TUSER_WIDTH-1 downto 0)

in

RX_AXIS_TKEEP

std_logic_vector(TDATA_WIDTH/8-1 downto 0)

in

RX_AXIS_TLAST

std_logic

in

RX_AXIS_TVALID

std_logic

in

RX_AXIS_TREADY

std_logic

out

RX_FIFO_AFULL

std_logic

out

RX_FIFO_STATUS

std_logic_vector(log2(FIFO_ITEMS) downto 0)

out

=====

TX AXI-Stream interface (TX_CLK)

=====

=====

TX_CLK

std_logic

in

TX_RESET

std_logic

in

TX_AXIS_TDATA

std_logic_vector(TDATA_WIDTH-1 downto 0)

out

TX_AXIS_TUSER

std_logic_vector(TUSER_WIDTH-1 downto 0)

out

TX_AXIS_TKEEP

std_logic_vector(TDATA_WIDTH/8-1 downto 0)

out

TX_AXIS_TLAST

std_logic

out

TX_AXIS_TVALID

std_logic

out

TX_AXIS_TREADY

std_logic

in

TX_FIFO_AEMPTY

std_logic

out

TX_FIFO_STATUS

std_logic_vector(log2(FIFO_ITEMS) downto 0)

out

+
+ +
+ + +
+