diff --git a/comp/nic/mac_lite/tx_mac_lite/tx_mac_lite.vhd b/comp/nic/mac_lite/tx_mac_lite/tx_mac_lite.vhd index ba11f69ee..9d842ee71 100644 --- a/comp/nic/mac_lite/tx_mac_lite/tx_mac_lite.vhd +++ b/comp/nic/mac_lite/tx_mac_lite/tx_mac_lite.vhd @@ -819,7 +819,10 @@ begin assert (tx_gap_inside_frame_dbg_reg /= '1') report "TX_MAC_LITE: Gap inside frame on TX MFB stream!" - severity failure; + severity warning; + --change severity to warning, because questa sim have problem with this assert and + --evaluate it wrongly + --severity failure; -- ========================================================================= -- STATISTICS MODULE diff --git a/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl b/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl index ba9fafaae..b16ae4617 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl +++ b/core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl @@ -98,9 +98,6 @@ if { $ARCHGRP == "F_TILE"} { lappend MOD "$ENTITY_BASE/comps/ftile/ftile_multirate_eth_2x100g4.vhd" lappend MOD "$ENTITY_BASE/comps/ftile/ftile_multirate_eth_8x25g1_8x10g1.vhd" - # Verification probe - lappend MOD "$ENTITY_BASE/comps/ftile_ver_probe/ftile_ver_probe.vhd" - lappend MOD "$ENTITY_BASE/network_mod_core_ftile.vhd" } diff --git a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd b/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd deleted file mode 100644 index 95a4c1b65..000000000 --- a/core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd +++ /dev/null @@ -1,76 +0,0 @@ --- ftile_ver_probe.vhd: A probe for verification purposes --- Copyright (C) 2024 CESNET z. s. p. o. --- Author(s): Yaroslav Marushchenko - --- SPDX-License-Identifier: BSD-3-Clause - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.type_pack.all; - -entity NETWORK_MOD_CORE_FTILE_VER_PROBE is -generic ( - CHANNELS : natural; - - DATA_WIDTH : natural; - INFRAME_WIDTH : natural; - EOP_EMPTY_WIDTH : natural; - FCS_ERROR_WIDTH : natural; - ERROR_WIDTH : natural; - STATUS_WIDTH : natural -); -port ( - -- INPUT - IN_MAC_DATA : in slv_array_t (CHANNELS-1 downto 0)(DATA_WIDTH -1 downto 0); - IN_MAC_INFRAME : in slv_array_t (CHANNELS-1 downto 0)(INFRAME_WIDTH -1 downto 0); - IN_MAC_EOP_EMPTY : in slv_array_t (CHANNELS-1 downto 0)(EOP_EMPTY_WIDTH-1 downto 0); - IN_MAC_FCS_ERROR : in slv_array_t (CHANNELS-1 downto 0)(FCS_ERROR_WIDTH-1 downto 0); - IN_MAC_ERROR : in slv_array_t (CHANNELS-1 downto 0)(ERROR_WIDTH -1 downto 0); - IN_MAC_STATUS : in slv_array_t (CHANNELS-1 downto 0)(STATUS_WIDTH -1 downto 0); - IN_MAC_VALID : in std_logic_vector (CHANNELS-1 downto 0); - - -- OUTPUT - OUT_MAC_DATA : out slv_array_t (CHANNELS-1 downto 0)(DATA_WIDTH -1 downto 0); - OUT_MAC_INFRAME : out slv_array_t (CHANNELS-1 downto 0)(INFRAME_WIDTH -1 downto 0); - OUT_MAC_EOP_EMPTY : out slv_array_t (CHANNELS-1 downto 0)(EOP_EMPTY_WIDTH-1 downto 0); - OUT_MAC_FCS_ERROR : out slv_array_t (CHANNELS-1 downto 0)(FCS_ERROR_WIDTH-1 downto 0); - OUT_MAC_ERROR : out slv_array_t (CHANNELS-1 downto 0)(ERROR_WIDTH -1 downto 0); - OUT_MAC_STATUS : out slv_array_t (CHANNELS-1 downto 0)(STATUS_WIDTH -1 downto 0); - OUT_MAC_VALID : out std_logic_vector (CHANNELS-1 downto 0) -); -end entity; - -architecture FULL of NETWORK_MOD_CORE_FTILE_VER_PROBE is - - -- Signals for verification purposes - signal mac_data : std_logic_vector (CHANNELS*DATA_WIDTH -1 downto 0); - signal mac_inframe : std_logic_vector (CHANNELS*INFRAME_WIDTH -1 downto 0); - signal mac_eop_empty : std_logic_vector (CHANNELS*EOP_EMPTY_WIDTH-1 downto 0); - signal mac_fcs_error : std_logic_vector (CHANNELS*FCS_ERROR_WIDTH-1 downto 0); - signal mac_error : std_logic_vector (CHANNELS*ERROR_WIDTH -1 downto 0); - signal mac_status : std_logic_vector (CHANNELS*STATUS_WIDTH -1 downto 0); - signal mac_valid : std_logic_vector (CHANNELS -1 downto 0); - -begin - - -- Input serialization - mac_data <= slv_array_ser(IN_MAC_DATA , CHANNELS, DATA_WIDTH ); - mac_inframe <= slv_array_ser(IN_MAC_INFRAME , CHANNELS, INFRAME_WIDTH ); - mac_eop_empty <= slv_array_ser(IN_MAC_EOP_EMPTY, CHANNELS, EOP_EMPTY_WIDTH); - mac_fcs_error <= slv_array_ser(IN_MAC_FCS_ERROR, CHANNELS, FCS_ERROR_WIDTH); - mac_error <= slv_array_ser(IN_MAC_ERROR , CHANNELS, ERROR_WIDTH ); - mac_status <= slv_array_ser(IN_MAC_STATUS , CHANNELS, STATUS_WIDTH ); - mac_valid <= IN_MAC_VALID; - - -- Output deserialization - OUT_MAC_DATA <= slv_array_deser(mac_data , CHANNELS, DATA_WIDTH ); - OUT_MAC_INFRAME <= slv_array_deser(mac_inframe , CHANNELS, INFRAME_WIDTH ); - OUT_MAC_EOP_EMPTY <= slv_array_deser(mac_eop_empty, CHANNELS, EOP_EMPTY_WIDTH); - OUT_MAC_FCS_ERROR <= slv_array_deser(mac_fcs_error, CHANNELS, FCS_ERROR_WIDTH); - OUT_MAC_ERROR <= slv_array_deser(mac_error , CHANNELS, ERROR_WIDTH ); - OUT_MAC_STATUS <= slv_array_deser(mac_status , CHANNELS, STATUS_WIDTH ); - OUT_MAC_VALID <= mac_valid; - -end architecture; diff --git a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd index b43ef3198..4e97a69f1 100644 --- a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd +++ b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd @@ -204,15 +204,6 @@ architecture FULL of NETWORK_MOD_CORE is signal ftile_rx_mac_error : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_ERROR_WIDTH -1 downto 0); signal ftile_rx_mac_status : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_STATUS_WIDTH -1 downto 0); - -- Verification probe signals - signal ver_probe_ftile_rx_mac_data : slv_array_t (ETH_PORT_CHAN-1 downto 0)(MAC_DATA_WIDTH -1 downto 0); - signal ver_probe_ftile_rx_mac_valid : std_logic_vector(ETH_PORT_CHAN-1 downto 0); - signal ver_probe_ftile_rx_mac_inframe : slv_array_t (ETH_PORT_CHAN-1 downto 0)(MAC_INFRAME_WIDTH -1 downto 0); - signal ver_probe_ftile_rx_mac_eop_empty : slv_array_t (ETH_PORT_CHAN-1 downto 0)(MAC_EOP_EMPTY_WIDTH -1 downto 0); - signal ver_probe_ftile_rx_mac_fcs_error : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_FCS_ERROR_WIDTH-1 downto 0); - signal ver_probe_ftile_rx_mac_error : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_ERROR_WIDTH -1 downto 0); - signal ver_probe_ftile_rx_mac_status : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_STATUS_WIDTH -1 downto 0); - begin mi_splitter_i : entity work.MI_SPLITTER_PLUS_GEN @@ -766,34 +757,6 @@ architecture FULL of NETWORK_MOD_CORE is end generate; end generate ftile_8x10g1_g; - verification_probe_i : entity work.NETWORK_MOD_CORE_FTILE_VER_PROBE - generic map( - CHANNELS => ETH_PORT_CHAN, - DATA_WIDTH => MAC_DATA_WIDTH, - INFRAME_WIDTH => MAC_INFRAME_WIDTH, - EOP_EMPTY_WIDTH => MAC_EOP_EMPTY_WIDTH, - FCS_ERROR_WIDTH => RX_MAC_FCS_ERROR_WIDTH, - ERROR_WIDTH => RX_MAC_ERROR_WIDTH, - STATUS_WIDTH => RX_MAC_STATUS_WIDTH - ) - port map( - IN_MAC_DATA => ftile_rx_mac_data, - IN_MAC_INFRAME => ftile_rx_mac_inframe, - IN_MAC_EOP_EMPTY => ftile_rx_mac_eop_empty, - IN_MAC_FCS_ERROR => ftile_rx_mac_fcs_error, - IN_MAC_ERROR => ftile_rx_mac_error, - IN_MAC_STATUS => ftile_rx_mac_status, - IN_MAC_VALID => ftile_rx_mac_valid, - - OUT_MAC_DATA => ver_probe_ftile_rx_mac_data, - OUT_MAC_INFRAME => ver_probe_ftile_rx_mac_inframe, - OUT_MAC_EOP_EMPTY => ver_probe_ftile_rx_mac_eop_empty, - OUT_MAC_FCS_ERROR => ver_probe_ftile_rx_mac_fcs_error, - OUT_MAC_ERROR => ver_probe_ftile_rx_mac_error, - OUT_MAC_STATUS => ver_probe_ftile_rx_mac_status, - OUT_MAC_VALID => ver_probe_ftile_rx_mac_valid - ); - adapts_g : for i in ETH_PORT_CHAN-1 downto 0 generate -- ========================================================================= -- ADAPTERS @@ -806,13 +769,13 @@ architecture FULL of NETWORK_MOD_CORE is port map( CLK => ftile_clk_out, RESET => RESET_ETH, - IN_MAC_DATA => ver_probe_ftile_rx_mac_data(i), - IN_MAC_INFRAME => ver_probe_ftile_rx_mac_inframe(i), - IN_MAC_EOP_EMPTY => ver_probe_ftile_rx_mac_eop_empty(i), - IN_MAC_FCS_ERROR => ver_probe_ftile_rx_mac_fcs_error(i), - IN_MAC_ERROR => ver_probe_ftile_rx_mac_error(i), - IN_MAC_STATUS => ver_probe_ftile_rx_mac_status(i), - IN_MAC_VALID => ver_probe_ftile_rx_mac_valid(i), + IN_MAC_DATA => ftile_rx_mac_data(i), + IN_MAC_INFRAME => ftile_rx_mac_inframe(i), + IN_MAC_EOP_EMPTY => ftile_rx_mac_eop_empty(i), + IN_MAC_FCS_ERROR => ftile_rx_mac_fcs_error(i), + IN_MAC_ERROR => ftile_rx_mac_error(i), + IN_MAC_STATUS => ftile_rx_mac_status(i), + IN_MAC_VALID => ftile_rx_mac_valid(i), OUT_MFB_DATA => TX_MFB_DATA(i), OUT_MFB_ERROR => TX_MFB_ERROR(i), OUT_MFB_SOF => TX_MFB_SOF(i), diff --git a/core/comp/eth/network_mod/uvm/tbench/base/dut.sv b/core/comp/eth/network_mod/uvm/tbench/base/dut.sv index c1d2c8cb3..b4347425b 100644 --- a/core/comp/eth/network_mod/uvm/tbench/base/dut.sv +++ b/core/comp/eth/network_mod/uvm/tbench/base/dut.sv @@ -42,6 +42,7 @@ module DUT_BASE #( string DEVICE, string BOARD )( + output wire logic CLK_ETH[ETH_PORTS], input wire logic CLK_USR, input wire logic CLK_MI, input wire logic CLK_MI_PHY, @@ -158,7 +159,7 @@ module DUT_BASE #( ) VHDL_DUT_U ( .CLK_USER (CLK_USR), - .CLK_ETH (), + .CLK_ETH (CLK_ETH), .RESET_USER (reset_user), .RESET_ETH (reset_eth), diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv index 3faa2e320..b553c35cc 100644 --- a/core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv @@ -40,9 +40,10 @@ module DUT #( int unsigned RESET_WIDTH, string DEVICE, - string BOARD + string BOARD, + time CLK_ETH_PERIOD[ETH_PORTS] )( - input wire logic CLK_ETH[ETH_PORTS], + output wire logic CLK_ETH[ETH_PORTS], input wire logic CLK_USR, input wire logic CLK_MI, input wire logic CLK_MI_PHY, @@ -97,6 +98,7 @@ module DUT #( .DEVICE (DEVICE ), .BOARD (BOARD ) ) DUT_BASE_U ( + .CLK_ETH (CLK_ETH ), .CLK_USR (CLK_USR ), .CLK_MI (CLK_MI ), .CLK_MI_PHY (CLK_MI_PHY), @@ -127,6 +129,9 @@ module DUT #( initial assert(ETH_PORT_CHAN_LOCAL == 1); wire logic [4*128-1 : 0] eth_rx_data; + logic CLK_ETH_GEN = 1'b0; + + always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH_GEN = ~CLK_ETH_GEN; // ------- // // TX side // @@ -173,7 +178,7 @@ module DUT #( // ----- // // CLK connection - initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH[eth_it]; + initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH_GEN; end endgenerate diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv index 61fc2d973..3d94b8029 100644 --- a/core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv @@ -23,7 +23,7 @@ module testbench; // ------ // logic CLK_USR = 0; - logic CLK_ETH[ETH_PORTS] = '{ETH_PORTS{1'b0}}; + logic CLK_ETH[ETH_PORTS]; logic CLK_MI = 0; logic CLK_MI_PHY = 0; logic CLK_MI_PMD = 0; @@ -168,7 +168,8 @@ module testbench; .LANE_TX_POLARITY (LANE_TX_POLARITY ), .RESET_WIDTH (RESET_WIDTH ), .DEVICE (DEVICE ), - .BOARD (BOARD ) + .BOARD (BOARD ), + .CLK_ETH_PERIOD (CLK_ETH_PERIOD ) ) DUT_U ( .CLK_ETH (CLK_ETH ), .CLK_USR (CLK_USR ), diff --git a/core/comp/eth/network_mod/uvm/tbench/e-tile/dut.sv b/core/comp/eth/network_mod/uvm/tbench/e-tile/dut.sv index 0af2e2b72..d07e18cf6 100644 --- a/core/comp/eth/network_mod/uvm/tbench/e-tile/dut.sv +++ b/core/comp/eth/network_mod/uvm/tbench/e-tile/dut.sv @@ -40,9 +40,10 @@ module DUT #( int unsigned RESET_WIDTH, string DEVICE, - string BOARD + string BOARD, + time CLK_ETH_PERIOD[ETH_PORTS] )( - input wire logic CLK_ETH[ETH_PORTS], + output wire logic CLK_ETH[ETH_PORTS], input wire logic CLK_USR, input wire logic CLK_MI, input wire logic CLK_MI_PHY, @@ -99,6 +100,7 @@ module DUT #( .DEVICE (DEVICE ), .BOARD (BOARD ) ) DUT_BASE_U ( + .CLK_ETH (CLK_ETH ), .CLK_USR (CLK_USR ), .CLK_MI (CLK_MI ), .CLK_MI_PHY (CLK_MI_PHY), @@ -126,7 +128,9 @@ module DUT #( generate; for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin logic [AVST_WIDTH*ITEM_WIDTH-1 : 0] avst_data; + logic CLK_ETH_GEN = 1'b0; + always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH_GEN = ~CLK_ETH_GEN; // RX for (genvar data_it = 0; data_it < AVST_WIDTH; data_it++) begin assign avst_data[(AVST_WIDTH -data_it)*ITEM_WIDTH-1 -: ITEM_WIDTH] = eth_rx[eth_it].DATA[(data_it+1)*ITEM_WIDTH-1 -: ITEM_WIDTH]; @@ -152,7 +156,7 @@ module DUT #( assign DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.tx_avst_ready[0] = eth_tx[eth_it].READY; // CLK - assign DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.etile_clk_out_vec[0] = CLK_ETH[eth_it]; + assign DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.etile_clk_out_vec[0] = CLK_ETH_GEN; end endgenerate diff --git a/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv b/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv index 7f2e58b1a..d28415009 100644 --- a/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv +++ b/core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv @@ -21,7 +21,7 @@ module testbench; // ------------------------------------------------------------------------------------------------------------------------------------------------------------------- // CLOCK logic CLK_USR = 0; - logic CLK_ETH[ETH_PORTS] = '{ETH_PORTS{1'b0}}; + logic CLK_ETH[ETH_PORTS]; logic CLK_MI = 0; logic CLK_MI_PHY = 0; logic CLK_MI_PMD = 0; @@ -156,7 +156,8 @@ module testbench; .LANE_TX_POLARITY (LANE_TX_POLARITY ), .RESET_WIDTH (RESET_WIDTH ), .DEVICE (DEVICE ), - .BOARD (BOARD ) + .BOARD (BOARD ), + .CLK_ETH_PERIOD (CLK_ETH_PERIOD ) ) DUT_U ( .CLK_ETH (CLK_ETH ), .CLK_USR (CLK_USR ), diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv index c221e89b1..8c62e49ae 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv @@ -40,9 +40,10 @@ module DUT #( int unsigned RESET_WIDTH, string DEVICE, - string BOARD + string BOARD, + time CLK_ETH_PERIOD[ETH_PORTS] )( - input wire logic CLK_ETH[ETH_PORTS], + output wire logic CLK_ETH[ETH_PORTS], input wire logic CLK_USR, input wire logic CLK_MI, input wire logic CLK_MI_PHY, @@ -97,6 +98,7 @@ module DUT #( .DEVICE (DEVICE ), .BOARD (BOARD ) ) DUT_BASE_U ( + .CLK_ETH (CLK_ETH), .CLK_USR (CLK_USR ), .CLK_MI (CLK_MI ), .CLK_MI_PHY (CLK_MI_PHY), @@ -123,30 +125,67 @@ module DUT #( generate; for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin - localparam int unsigned ETH_PORT_CHAN_LOCAL = ETH_PORT_CHAN[eth_it]; - initial assert(ETH_PORT_CHAN_LOCAL == 1); // TODO - - // TX connections - assign eth_tx[eth_it].DATA = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_data}}; - assign eth_tx[eth_it].INFRAME = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_inframe}}; - assign eth_tx[eth_it].EOP_EMPTY = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_eop_empty}}; - assign eth_tx[eth_it].FCS_ERROR = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_error}}; // Both have the same width - assign eth_tx[eth_it].VALID = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_valid; + initial assert(ETH_PORT_CHAN[eth_it] == 1); // TODO + + localparam int unsigned SEGMENTS = ((ETH_PORT_SPEED[eth_it] == 400) ? 16 : + (ETH_PORT_SPEED[eth_it] == 200) ? 8 : + (ETH_PORT_SPEED[eth_it] == 100) ? 4 : + (ETH_PORT_SPEED[eth_it] == 50 ) ? 2 : + (ETH_PORT_SPEED[eth_it] == 40 ) ? 2 : + (ETH_PORT_SPEED[eth_it] == 25 ) ? 1 : + (ETH_PORT_SPEED[eth_it] == 10 ) ? 1 : + 0 ); + + //logic CLK_ETH_GEN = 1'b1; // TRY 1'b1 + logic CLK_ETH_GEN = 1'b0; + wire logic [SEGMENTS*64-1:0] mac_data [ETH_PORT_CHAN[eth_it]-1:0]; + wire logic [SEGMENTS-1:0] mac_inframe [ETH_PORT_CHAN[eth_it]-1:0]; + wire logic [SEGMENTS*3-1:0] mac_eop_empty[ETH_PORT_CHAN[eth_it]-1:0]; + wire logic [SEGMENTS-1:0] mac_fcs_error[ETH_PORT_CHAN[eth_it]-1:0]; + wire logic [SEGMENTS*2-1:0] mac_error [ETH_PORT_CHAN[eth_it]-1:0]; + wire logic [SEGMENTS*3-1:0] mac_status [ETH_PORT_CHAN[eth_it]-1:0]; + wire logic [ETH_PORT_CHAN[eth_it]-1:0] mac_valid; + wire logic [ETH_PORT_CHAN[eth_it]-1:0] mac_ready; + + + //Generate internal clock + always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH_GEN = ~CLK_ETH_GEN; + + //Channel + for (genvar chan_it = 0; chan_it < ETH_PORT_CHAN[eth_it]; chan_it++) begin + // TX connections + assign eth_tx[eth_it].DATA = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_data[chan_it]; + assign eth_tx[eth_it].INFRAME = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_inframe[chan_it]; + assign eth_tx[eth_it].EOP_EMPTY = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_eop_empty[chan_it]; + assign eth_tx[eth_it].FCS_ERROR = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_error[chan_it]; // Both have the same width + assign eth_tx[eth_it].VALID = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_valid[chan_it]; + assign mac_ready[chan_it] = eth_tx[eth_it].READY; + + //for (genvar chan_it = 0; chan_it < ETH_PORT_CHAN[eth_it]; chan_it++) begin + assign mac_data[chan_it] = eth_rx[eth_it].DATA; + assign mac_inframe[chan_it] = eth_rx[eth_it].INFRAME; + assign mac_eop_empty[chan_it] = eth_rx[eth_it].EOP_EMPTY; + assign mac_fcs_error[chan_it] = eth_rx[eth_it].FCS_ERROR; + assign mac_error[chan_it] = eth_rx[eth_it].ERROR; + assign mac_status[chan_it] = eth_rx[eth_it].STATUS_DATA; + assign mac_valid[chan_it] = eth_rx[eth_it].VALID; + + //CLK generator + initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_clk_out_vec[chan_it] = CLK_ETH_GEN; + end initial begin // RX connections - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.verification_probe_i.mac_data = eth_rx[eth_it].DATA; - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.verification_probe_i.mac_inframe = eth_rx[eth_it].INFRAME; - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.verification_probe_i.mac_eop_empty = eth_rx[eth_it].EOP_EMPTY; - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.verification_probe_i.mac_fcs_error = eth_rx[eth_it].FCS_ERROR; - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.verification_probe_i.mac_error = eth_rx[eth_it].ERROR; - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.verification_probe_i.mac_status = eth_rx[eth_it].STATUS_DATA; - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.verification_probe_i.mac_valid = eth_rx[eth_it].VALID; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_rx_mac_data = mac_data; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_rx_mac_inframe = mac_inframe; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_rx_mac_eop_empty = mac_eop_empty; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_rx_mac_fcs_error = mac_fcs_error; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_rx_mac_error = mac_error; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_rx_mac_status = mac_status; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_rx_mac_valid = mac_valid; // TX READY connection - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_mac_ready[0] = eth_tx[eth_it].READY; - // CLK connection - force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_clk_out_vec[0] = CLK_ETH[eth_it]; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_mac_ready = mac_ready; end end endgenerate diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv index 3a67c73ea..00f2a1292 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv @@ -30,7 +30,7 @@ module testbench; // ------------------------------------------------------------------------------------------------------------------------------------------------------------------- // CLOCK logic CLK_USR = 0; - logic CLK_ETH[ETH_PORTS] = '{ETH_PORTS{1'b0}}; + logic CLK_ETH[ETH_PORTS]; logic CLK_MI = 0; logic CLK_MI_PHY = 0; logic CLK_MI_PMD = 0; @@ -38,10 +38,7 @@ module testbench; // ------------------------------------------------------------------------------------------------------------------------------------------------------------------- // INTERFACES reset_if rst_usr (CLK_USR); - for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin : rst_gen - reset_if rst_eth(CLK_ETH[eth_it]); - end - reset_if rst_eth[ETH_PORTS](CLK_ETH[0]); + reset_if rst_eth[ETH_PORTS](CLK_ETH); reset_if rst_mi (CLK_MI); reset_if rst_mi_phy (CLK_MI_PHY); reset_if rst_mi_pmd (CLK_MI_PMD); @@ -51,8 +48,8 @@ module testbench; intel_mac_seg_if #(SEGMENTS) eth_tx[ETH_PORTS] (CLK_ETH); mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, ETH_TX_HDR_WIDTH) usr_rx [ETH_PORTS](CLK_USR); - mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) usr_tx_data[ETH_PORTS](CLK_USR); - mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) usr_tx_hdr [ETH_PORTS](CLK_USR); + mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) usr_tx_data[ETH_PORTS](CLK_USR); + mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) usr_tx_hdr [ETH_PORTS](CLK_USR); mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH) mi(CLK_MI); mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH) mi_phy(CLK_MI_PHY); @@ -67,10 +64,7 @@ module testbench; // ------------------------------------------------------------------------------------------------------------------------------------------------------------------- // Define clock ticking - always #(CLK_USR_PERIOD/2) CLK_USR = ~CLK_USR; - for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin - always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH[eth_it] = ~CLK_ETH[eth_it]; - end + always #(CLK_USR_PERIOD/2) CLK_USR = ~CLK_USR; always #(CLK_MI_PERIOD/2) CLK_MI = ~CLK_MI ; always #(CLK_MI_PHY_PERIOD/2) CLK_MI_PHY = ~CLK_MI_PHY; always #(CLK_MI_PMD_PERIOD/2) CLK_MI_PMD = ~CLK_MI_PMD; @@ -82,10 +76,10 @@ module testbench; automatic uvm_root m_root; automatic virtual reset_if vif_rst_eth[ETH_PORTS] = rst_eth; automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, ETH_TX_HDR_WIDTH) vif_usr_rx [ETH_PORTS] = usr_rx; - automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) vif_usr_tx_data[ETH_PORTS] = usr_tx_data; - automatic virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) vif_usr_tx_hdr [ETH_PORTS] = usr_tx_hdr; - automatic virtual intel_mac_seg_if #(SEGMENTS) vif_eth_rx [ETH_PORTS] = eth_rx; - automatic virtual intel_mac_seg_if #(SEGMENTS) vif_eth_tx [ETH_PORTS] = eth_tx; + automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) vif_usr_tx_data[ETH_PORTS] = usr_tx_data; + automatic virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) vif_usr_tx_hdr [ETH_PORTS] = usr_tx_hdr; + automatic virtual intel_mac_seg_if #(SEGMENTS) vif_eth_rx [ETH_PORTS] = eth_rx; + automatic virtual intel_mac_seg_if #(SEGMENTS) vif_eth_tx [ETH_PORTS] = eth_tx; // SET INTERFACE uvm_config_db#(virtual reset_if)::set(null, "", "vif_rst_usr", rst_usr); @@ -154,7 +148,8 @@ module testbench; .LANE_TX_POLARITY (LANE_TX_POLARITY ), .RESET_WIDTH (RESET_WIDTH ), .DEVICE (DEVICE ), - .BOARD (BOARD ) + .BOARD (BOARD ), + .CLK_ETH_PERIOD (CLK_ETH_PERIOD ) ) DUT_U ( .CLK_ETH (CLK_ETH ), .CLK_USR (CLK_USR ),