diff --git a/devel/app-minimal.html b/devel/app-minimal.html index 310576060..10ac4230e 100644 --- a/devel/app-minimal.html +++ b/devel/app-minimal.html @@ -36,7 +36,7 @@ Minimal NDK Application Docs
FIFO_DEPTH
natural
2048
Number of Items in the Input packet FIFOX_MULTI (main buffer).
Number of Items in the Input MFB_FIFOX (main buffer).
DEVICE
FIFO_AF_OFFSET
10
Almost Full Offset of the input MFB_FIFOX. +States the number of Items it can accept after Almost Full is asserted.
string
“STRATIX10”
FPGA device name: ULTRASCALE, STRATIX10, AGILEX, …
=====
PAUSE_REQUEST
std_logic
out
Used to pause incomming traffic when the buffer is Almost Full.
RX inf
RX_MFB_DATA
std_logic_vector(MFB_REGIONS*MFB_REGION_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0)
in
RX_MFB_META
std_logic_vector(MFB_REGIONS*MFB_META_WIDTH-1 downto 0)
Valid with SOF.
RX_MFB_TS
std_logic_vector(MFB_REGIONS*TS_WIDTH-1 downto 0)
Timestamp valid with each SOF.
RX_MFB_SOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE))-1 downto 0)
RX_MFB_EOF_POS
std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REGION_SIZE*MFB_BLOCK_SIZE))-1 downto 0)
RX_MFB_SOF
std_logic_vector(MFB_REGIONS-1 downto 0)
RX_MFB_EOF
RX_MFB_SRC_RDY
RX_MFB_DST_RDY
TX inf
TX_MFB_DATA
TX_MFB_META
TX_MFB_SOF_POS
TX_MFB_EOF_POS
TX_MFB_SOF
TX_MFB_EOF
TX_MFB_SRC_RDY
TX_MFB_DST_RDY
Number of Items in the Packet Delayer’s RX FIFO (the main buffer).
QUEUES
BUFFER_AF_OFFSET
Almost Full Offset of the main buffer in Packet Delayers. +States the number of data words it can accept after Almost Full is asserted.
1
The number of Queues (DMA Channels).
Connect your own Time source to this port (used when the EXTERNAL_TIME_SRC generic is True).
EXTERNAL_TIME_SRC
True
PAUSE_QUEUE
std_logic_vector(QUEUES-1 downto 0)
Issues a request to pause corresponding DMA channel.
RX MFB STREAM
RX_MFB_QUEUE
std_logic_vector(MFB_REGIONS*max(1,log2(QUEUES))-1 downto 0)
ID of the packet’s DMA channel or queue.
RX_MFB_TIMESTAMP
std_logic_vector(MFB_REGIONS*TIMESTAMP_WIDTH-1 downto 0)
Timestamps are valid with each SOF.
TX MFB STREAM
MI INTERFACE
MI_DWR
std_logic_vector(MI_DATA_WIDTH-1 downto 0)
MI_ADDR
std_logic_vector(MI_ADDR_WIDTH-1 downto 0)
MI_BE
std_logic_vector(MI_DATA_WIDTH/8-1 downto 0)
Not supported!
MI_WR
MI_RD
MI_ARDY
MI_DRD
MI_DRDY