diff --git a/apps/minimal/build/ia-440i/Makefile b/apps/minimal/build/ia-440i/Makefile new file mode 100644 index 000000000..4f1cae9a5 --- /dev/null +++ b/apps/minimal/build/ia-440i/Makefile @@ -0,0 +1,43 @@ +# Makefile: Makefile for card +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# NOTE: Usage of the configuration parameters in this file is described +# in the Parametrization section of the NDK-CORE documentation. + +# Set path to top-level of NDK-FPGA repository +COMBO_BASE = ../../../.. +CARD_BASE = $(COMBO_BASE)/cards/bittware/ia-440i +APP_CONF = app_conf.tcl +OUTPUT_NAME = ia-440i-minimal + +.PHONY: all 400g1 # 100g2 25g8 10g8 + +all: 400g1 + +# TODO: add support for different ETH configurations +# 10g8: ETH_PORT_SPEED=10 +# 10g8: ETH_PORT_CHAN=4 +# 10g8: OUTPUT_NAME:=$(OUTPUT_NAME)-10g8 +# 10g8: build +# +# 25g8: ETH_PORT_SPEED=25 +# 25g8: ETH_PORT_CHAN=4 +# 25g8: OUTPUT_NAME:=$(OUTPUT_NAME)-25g8 +# 25g8: build +# +# 100g2: ETH_PORT_SPEED=100 +# 100g2: ETH_PORT_CHAN=1 +# 100g2: OUTPUT_NAME:=$(OUTPUT_NAME)-100g2 +# 100g2: build + +400g1: ETH_PORT_SPEED=400 +400g1: ETH_PORT_CHAN=1 +400g1: EHIP_PORT_TYPE=0 +400g1: OUTPUT_NAME:=$(OUTPUT_NAME)-400g1 +400g1: build + +include $(CARD_BASE)/src/card.mk diff --git a/apps/minimal/build/ia-440i/Quartus.tcl b/apps/minimal/build/ia-440i/Quartus.tcl new file mode 100644 index 000000000..c100d570b --- /dev/null +++ b/apps/minimal/build/ia-440i/Quartus.tcl @@ -0,0 +1,32 @@ +# Quartus.tcl: Quartus tcl script to compile whole FPGA design +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# NOTE: The purpose of this file is described in the Parameterization section of +# the NDK-CORE documentation. + +# ----- Setting basic synthesis options --------------------------------------- +# NDK & user constants +source $env(CARD_BASE)/src/Quartus.inc.tcl + +# Create only a Quartus project for further design flow driven from Quartus GUI +# "0" ... full design flow in command line +# "1" ... project composition only for further dedesign flow in GUI +set SYNTH_FLAGS(PROJ_ONLY) "0" + +# Associative array which is propagated to APPLICATION_CORE, add other +# parameters if necessary. +set APP_ARCHGRP(APP_CORE_ENABLE) $APP_CORE_ENABLE + +# Convert associative array to list +set APP_ARCHGRP_L [array get APP_ARCHGRP] + +# ----- Add application core to main component list --------------------------- +lappend HIERARCHY(COMPONENTS) \ + [list "APPLICATION_CORE" "$OFM_PATH/apps/minimal/top" $APP_ARCHGRP_L] + +# Call main function which handle targets +nb_main diff --git a/apps/minimal/build/ia-440i/app_conf.tcl b/apps/minimal/build/ia-440i/app_conf.tcl new file mode 100644 index 000000000..e458289f4 --- /dev/null +++ b/apps/minimal/build/ia-440i/app_conf.tcl @@ -0,0 +1,28 @@ +# app_conf.tcl: User parameters for card +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# NOTE: The detailed description of the usage of this file can be viewed in the +# Parametrizing section of the NDK-CORE documentation. + +# NOTE: Use the PCIE_CONF make parameter to select the PCIe configuration. + +# ------------------------------------------------------------------------------ +# DMA parameters: +# ------------------------------------------------------------------------------ +# The minimum number of RX/TX DMA channels for this card is 16. +set DMA_RX_CHANNELS 16 +set DMA_TX_CHANNELS 16 +# In blocking mode, packets are dropped only when the RX DMA channel is off. +# In non-blocking mode, packets are dropped whenever they cannot be sent. +set DMA_RX_BLOCKING_MODE true + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +set PROJECT_NAME "NDK_MINIMAL" +set PROJECT_VARIANT "$ETH_PORT_SPEED(0)G$ETH_PORTS" +set PROJECT_VERSION [exec cat ../../../../VERSION] diff --git a/cards/bittware/ia-440i/config/card_conf.tcl b/cards/bittware/ia-440i/config/card_conf.tcl new file mode 100644 index 000000000..b5b1cf1f8 --- /dev/null +++ b/cards/bittware/ia-440i/config/card_conf.tcl @@ -0,0 +1,85 @@ +# card_conf.tcl: User configurable for card +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# NOTE: For the detailed description of this file, visit the Parametrization section +# in the documentation of the NDK-CORE repository. + +set PROJECT_NAME "" + +# ------------------------------------------------------------------------------ +# ETH parameters: +# ------------------------------------------------------------------------------ +# Number of Ethernet ports, must match number of items in list ETH_PORTS_SPEED! +set ETH_PORTS 1 +# Speed for each one of the ETH_PORTS +# ETH_PORT_SPEED is an array where each index represents given ETH_PORT and +# each index has associated a required port speed. +# NOTE: at this moment, all ports must have same speed ! +set ETH_PORT_SPEED(0) $env(ETH_PORT_SPEED) +# Number of channels for each one of the ETH_PORTS +# ETH_PORT_CHAN is an array where each index represents given ETH_PORT and +# each index has associated a required number of channels this port has. +# NOTE: at this moment, all ports must have same number of channels ! +set ETH_PORT_CHAN(0) $env(ETH_PORT_CHAN) +# Number of lanes for each one of the ETH_PORTS +# Typical values: 4 (QSFP), 8 (QSFP-DD) +set ETH_PORT_LANES(0) 8 +# EHIP_PORT_TYPE is an array where each index represents given ETH_PORT and +# each index has associated a required type of IP core, which this port has. +# NOTE: at this moment, all ports must have same type of IP core ! +set EHIP_PORT_TYPE(0) $env(EHIP_PORT_TYPE) + +# ------------------------------------------------------------------------------ +# PCIe parameters (not all combinations work): +# ------------------------------------------------------------------------------ +# Supported combinations for this card: +# 1x PCIe Gen5 x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: default configuration) +# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 +# ------------------------------------------------------------------------------ + +# Set default PCIe configuration +set PCIE_CONF "1xGen5x16" +if { [info exist env(PCIE_CONF)] } { + set PCIE_CONF $env(PCIE_CONF) +} + +# Parsing PCIE_CONF string to list of parameters +set pcie_conf_list [ParsePcieConf $PCIE_CONF] + +# PCIe Generation: +# 4 = PCIe Gen4 (Stratix 10 with P-Tile or Agilex) +set PCIE_GEN [lindex $pcie_conf_list 1] +# PCIe endpoints: +# 1 = 1x PCIe x16 in one slot +# 2 = 2x PCIe x8 in one slot (bifurcation x8+x8) +set PCIE_ENDPOINTS [lindex $pcie_conf_list 0] +# PCIe endpoint mode: +# 0 = 1x16 lanes +# 1 = 2x8 lanes (bifurcation x8+x8) +set PCIE_ENDPOINT_MODE [lindex $pcie_conf_list 2] + +# ------------------------------------------------------------------------------ +# DMA parameters: +# ------------------------------------------------------------------------------ +# This variable can be set in COREs *.mk file or as a parameter when launching the make +set DMA_TYPE $env(DMA_TYPE) +# The minimum number of RX/TX DMA channels for this card is 16. +set DMA_RX_CHANNELS 16 +set DMA_TX_CHANNELS 16 +# In blocking mode, packets are dropped only when the RX DMA channel is off. +# In non-blocking mode, packets are dropped whenever they cannot be sent. +set DMA_RX_BLOCKING_MODE true + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +set TSU_ENABLE true + +# ------------------------------------------------------------------------------ +# DDR4 parameters: +# ------------------------------------------------------------------------------ +set MEM_PORTS 0 diff --git a/cards/bittware/ia-440i/config/card_const.tcl b/cards/bittware/ia-440i/config/card_const.tcl new file mode 100644 index 000000000..f8db85b25 --- /dev/null +++ b/cards/bittware/ia-440i/config/card_const.tcl @@ -0,0 +1,56 @@ +# card_const.tcl: Default parameters for card +# Copyright (C) 2024 CESNET, z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# WARNING: The user should not deliberately change parameters in this file. For +# the description of this file, visit the Parametrization section in the +# documentation of the NDK-CORE repostiory + +set CARD_NAME "IA-440I" +# Achitecture of Clock generator (INTEL or USP) +set CLOCK_GEN_ARCH "INTEL" +# Achitecture of PCIe module (P_TILE, R_TILE or USP) +set PCIE_MOD_ARCH "R_TILE" +# Achitecture of Network module (E_TILE, F_TILE, CMAC or EMPTY) +set NET_MOD_ARCH "F_TILE" +# Achitecture of SDM/SYSMON module +set SDM_SYSMON_ARCH "INTEL_SDM" +# Boot controller type +set BOOT_TYPE 0 +# Total number of DMA modules/streams in FW +set DMA_MODULES 1 + +# Total number of QSFP cages +set QSFP_CAGES 1 +# I2C address of each QSFP cage +set QSFP_I2C_ADDR(0) "0xA0" + +# ------------------------------------------------------------------------------ +# Checking of parameter compatibility +# ------------------------------------------------------------------------------ + +if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) || + ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1)) } { + error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE! +Allowed PCIe configurations: +- 1xGen5x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 +- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1" +} + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ + +if {$ETH_PORT_SPEED(0) == 10 || $ETH_PORT_SPEED(0) == 25 || $ETH_PORT_SPEED(0) == 40} { + # TBD lower frequency for 10GE, 40GE? + #set TSU_FREQUENCY 161132812 + # Current setup: + # 10GE, 25GE, 40GE in F-Tile + set TSU_FREQUENCY 402832031 +} else { + # 400GE, 200GE, 100GE, 50GE in F-Tile + set TSU_FREQUENCY 415039062 +} diff --git a/cards/bittware/ia-440i/constr/bmc.qsf b/cards/bittware/ia-440i/constr/bmc.qsf new file mode 100644 index 000000000..5455a8040 --- /dev/null +++ b/cards/bittware/ia-440i/constr/bmc.qsf @@ -0,0 +1,35 @@ +# bmc.qsf +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Board Management Controller (BMC) Interface +# ============================================================================== + +set_location_assignment PIN_DA17 -to FPGA_EG_SPI_SCK +set_location_assignment PIN_CY18 -to FPGA_EG_SPI_MISO +set_location_assignment PIN_CN19 -to FPGA_EG_SPI_MOSI +set_location_assignment PIN_CM20 -to FPGA_EG_SPI_PCS0 +set_location_assignment PIN_CC19 -to BMC_TO_FPGA_IRQ + +set_location_assignment PIN_CR19 -to FPGA_IG_SPI_SCK +set_location_assignment PIN_CT20 -to FPGA_IG_SPI_MISO +set_location_assignment PIN_CN21 -to FPGA_IG_SPI_MOSI +set_location_assignment PIN_CM22 -to FPGA_IG_SPI_PCS0 +set_location_assignment PIN_CG23 -to FPGA_TO_BMC_IRQ + +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to FPGA_IG_SPI_MISO +set_instance_assignment -name FAST_INPUT_REGISTER ON -to FPGA_IG_SPI_MOSI + +set_location_assignment PIN_CH24 -to BMC_IF_PRESENT_N + +# BMC_GPIO0 and BMC_GPIO1 are RESERVED for future use +# BMC_GPIO0 - General purpose output from the FPGA to the BMC +# BMC_GPIO1 - General purpose input from the BMC to the FPGA +# set_location_assignment PIN_CU21 -to BMC_GPIO0 +# set_location_assignment PIN_CV22 -to BMC_GPIO1 + +# Reset from the BMC - independent from the BMC interface +set_location_assignment PIN_CL23 -to BMC_RST_N diff --git a/cards/bittware/ia-440i/constr/general.qsf b/cards/bittware/ia-440i/constr/general.qsf new file mode 100644 index 000000000..35a63c52c --- /dev/null +++ b/cards/bittware/ia-440i/constr/general.qsf @@ -0,0 +1,53 @@ +# general.qsf +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Main device/configuration +# ============================================================================== + +set_global_assignment -name FAMILY "Agilex 7" +set_global_assignment -name DEVICE AGIB023R18A1E1V +set_global_assignment -name BOARD default +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name ENABLE_ED_CRC_CHECK ON +set_global_assignment -name MINIMUM_SEU_INTERVAL 0 +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" +set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 +set_global_assignment -name USE_CONF_DONE SDM_IO16 +set_global_assignment -name USE_INIT_DONE SDM_IO5 +set_global_assignment -name USE_PWRMGT_ALERT SDM_IO9 +set_global_assignment -name USE_HPS_COLD_RESET SDM_IO7 +set_global_assignment -name VID_OPERATION_MODE "PMBUS SLAVE" +set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 01 +set_global_assignment -name GENERATE_PR_RBF_FILE ON +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" +set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12" +set_global_assignment -name GENERATE_COMPRESSED_SOF ON + +# ============================================================================== +# Clocks +# ============================================================================== + +set_location_assignment PIN_CU19 -to SYS_CLK_100M +set_location_assignment PIN_CV20 -to "SYS_CLK_100M(n)" +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to SYS_CLK_100M +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SYS_CLK_100M + +# ============================================================================== +# LEDs +# ============================================================================== + +set_location_assignment PIN_DA19 -to USER_LED_G +set_location_assignment PIN_CY20 -to USER_LED_R + +set_instance_assignment -name IO_STANDARD "1.2 V" -to USER_LED_G +set_instance_assignment -name IO_STANDARD "1.2 V" -to USER_LED_R diff --git a/cards/bittware/ia-440i/constr/pcie.qsf b/cards/bittware/ia-440i/constr/pcie.qsf new file mode 100644 index 000000000..5d245c1c9 --- /dev/null +++ b/cards/bittware/ia-440i/constr/pcie.qsf @@ -0,0 +1,99 @@ +# pcie.qsf +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pin Locations - PCIe +# ============================================================================== + +set_location_assignment PIN_AR37 -to PCIE_REFCLK0 +set_location_assignment PIN_AT38 -to "PCIE_REFCLK0(n)" +set_location_assignment PIN_AG37 -to PCIE_REFCLK1 +set_location_assignment PIN_AH38 -to "PCIE_REFCLK1(n)" + +set_location_assignment PIN_L31 -to PCIE_SYSRST_N + +set_location_assignment PIN_AR41 -to PCIE_TX_P[0] +set_location_assignment PIN_AP44 -to PCIE_TX_P[1] +set_location_assignment PIN_AL41 -to PCIE_TX_P[2] +set_location_assignment PIN_AK44 -to PCIE_TX_P[3] +set_location_assignment PIN_AG41 -to PCIE_TX_P[4] +set_location_assignment PIN_AF44 -to PCIE_TX_P[5] +set_location_assignment PIN_AC41 -to PCIE_TX_P[6] +set_location_assignment PIN_AB44 -to PCIE_TX_P[7] +set_location_assignment PIN_W41 -to PCIE_TX_P[8] +set_location_assignment PIN_V44 -to PCIE_TX_P[9] +set_location_assignment PIN_R41 -to PCIE_TX_P[10] +set_location_assignment PIN_P44 -to PCIE_TX_P[11] +set_location_assignment PIN_L41 -to PCIE_TX_P[12] +set_location_assignment PIN_V38 -to PCIE_TX_P[13] +set_location_assignment PIN_P38 -to PCIE_TX_P[14] +set_location_assignment PIN_K38 -to PCIE_TX_P[15] + +set_location_assignment PIN_AT40 -to PCIE_TX_N[0] +set_location_assignment PIN_AN43 -to PCIE_TX_N[1] +set_location_assignment PIN_AM40 -to PCIE_TX_N[2] +set_location_assignment PIN_AJ43 -to PCIE_TX_N[3] +set_location_assignment PIN_AH40 -to PCIE_TX_N[4] +set_location_assignment PIN_AE43 -to PCIE_TX_N[5] +set_location_assignment PIN_AD40 -to PCIE_TX_N[6] +set_location_assignment PIN_AA43 -to PCIE_TX_N[7] +set_location_assignment PIN_Y40 -to PCIE_TX_N[8] +set_location_assignment PIN_U43 -to PCIE_TX_N[9] +set_location_assignment PIN_T40 -to PCIE_TX_N[10] +set_location_assignment PIN_N43 -to PCIE_TX_N[11] +set_location_assignment PIN_M40 -to PCIE_TX_N[12] +set_location_assignment PIN_U37 -to PCIE_TX_N[13] +set_location_assignment PIN_N37 -to PCIE_TX_N[14] +set_location_assignment PIN_J37 -to PCIE_TX_N[15] + +set_location_assignment PIN_AL47 -to PCIE_RX_P[0] +set_location_assignment PIN_AG47 -to PCIE_RX_P[1] +set_location_assignment PIN_AC47 -to PCIE_RX_P[2] +set_location_assignment PIN_W47 -to PCIE_RX_P[3] +set_location_assignment PIN_R47 -to PCIE_RX_P[4] +set_location_assignment PIN_L47 -to PCIE_RX_P[5] +set_location_assignment PIN_G47 -to PCIE_RX_P[6] +set_location_assignment PIN_K44 -to PCIE_RX_P[7] +set_location_assignment PIN_D46 -to PCIE_RX_P[8] +set_location_assignment PIN_F44 -to PCIE_RX_P[9] +set_location_assignment PIN_G41 -to PCIE_RX_P[10] +set_location_assignment PIN_C41 -to PCIE_RX_P[11] +set_location_assignment PIN_B38 -to PCIE_RX_P[12] +set_location_assignment PIN_F38 -to PCIE_RX_P[13] +set_location_assignment PIN_C35 -to PCIE_RX_P[14] +set_location_assignment PIN_G35 -to PCIE_RX_P[15] + +set_location_assignment PIN_AM46 -to PCIE_RX_N[0] +set_location_assignment PIN_AH46 -to PCIE_RX_N[1] +set_location_assignment PIN_AD46 -to PCIE_RX_N[2] +set_location_assignment PIN_Y46 -to PCIE_RX_N[3] +set_location_assignment PIN_T46 -to PCIE_RX_N[4] +set_location_assignment PIN_M46 -to PCIE_RX_N[5] +set_location_assignment PIN_H46 -to PCIE_RX_N[6] +set_location_assignment PIN_J43 -to PCIE_RX_N[7] +set_location_assignment PIN_C45 -to PCIE_RX_N[8] +set_location_assignment PIN_E43 -to PCIE_RX_N[9] +set_location_assignment PIN_H40 -to PCIE_RX_N[10] +set_location_assignment PIN_D40 -to PCIE_RX_N[11] +set_location_assignment PIN_A37 -to PCIE_RX_N[12] +set_location_assignment PIN_E37 -to PCIE_RX_N[13] +set_location_assignment PIN_D34 -to PCIE_RX_N[14] +set_location_assignment PIN_H34 -to PCIE_RX_N[15] + +# ============================================================================== +# Pin IO Standards & Input Termination +# ============================================================================== + +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK0 +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK1 + +set_instance_assignment -name IO_STANDARD 1.0V -to PCIE_SYSRST_N + +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_N +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_N diff --git a/cards/bittware/ia-440i/constr/qsfp.qsf b/cards/bittware/ia-440i/constr/qsfp.qsf new file mode 100644 index 000000000..05a30cfe3 --- /dev/null +++ b/cards/bittware/ia-440i/constr/qsfp.qsf @@ -0,0 +1,68 @@ +# qsfp.qsf +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pin Locations - QSFP-DD +# ============================================================================== + +# F-Tile refclk channel 3 +set_location_assignment PIN_CB38 -to QSFP_REFCLK_156M +set_location_assignment PIN_CA37 -to "QSFP_REFCLK_156M(n)" +# F-Tile refclk channel 4 +#set_location_assignment PIN_BT38 -to QSFP_REFCLK_156M +#set_location_assignment PIN_BU37 -to "QSFP_REFCLK_156M(n)" +# F-Tile refclk channel 5 +#set_location_assignment PIN_BN37 -to QSFP_REFCLK_156M +#set_location_assignment PIN_BR37 -to "QSFP_REFCLK_156M(n)" + +set_location_assignment PIN_AW41 -to QSFP_TX_P[0] +set_location_assignment PIN_BC41 -to QSFP_TX_P[1] +set_location_assignment PIN_BF44 -to QSFP_TX_P[2] +set_location_assignment PIN_BG41 -to QSFP_TX_P[3] +set_location_assignment PIN_BK44 -to QSFP_TX_P[4] +set_location_assignment PIN_BL41 -to QSFP_TX_P[5] +set_location_assignment PIN_BP44 -to QSFP_TX_P[6] +set_location_assignment PIN_BR41 -to QSFP_TX_P[7] + +set_location_assignment PIN_AY40 -to QSFP_TX_N[0] +set_location_assignment PIN_BD40 -to QSFP_TX_N[1] +set_location_assignment PIN_BE43 -to QSFP_TX_N[2] +set_location_assignment PIN_BH40 -to QSFP_TX_N[3] +set_location_assignment PIN_BJ43 -to QSFP_TX_N[4] +set_location_assignment PIN_BM40 -to QSFP_TX_N[5] +set_location_assignment PIN_BN43 -to QSFP_TX_N[6] +set_location_assignment PIN_BT40 -to QSFP_TX_N[7] + +set_location_assignment PIN_AR47 -to QSFP_RX_P[0] +set_location_assignment PIN_AV44 -to QSFP_RX_P[1] +set_location_assignment PIN_AW47 -to QSFP_RX_P[2] +set_location_assignment PIN_BB44 -to QSFP_RX_P[3] +set_location_assignment PIN_BC47 -to QSFP_RX_P[4] +set_location_assignment PIN_BG47 -to QSFP_RX_P[5] +set_location_assignment PIN_BL47 -to QSFP_RX_P[6] +set_location_assignment PIN_BR47 -to QSFP_RX_P[7] + +set_location_assignment PIN_AT46 -to QSFP_RX_N[0] +set_location_assignment PIN_AU43 -to QSFP_RX_N[1] +set_location_assignment PIN_AY46 -to QSFP_RX_N[2] +set_location_assignment PIN_BA43 -to QSFP_RX_N[3] +set_location_assignment PIN_BD46 -to QSFP_RX_N[4] +set_location_assignment PIN_BH46 -to QSFP_RX_N[5] +set_location_assignment PIN_BM46 -to QSFP_RX_N[6] +set_location_assignment PIN_BT46 -to QSFP_RX_N[7] + +# ============================================================================== +# Pin IO Standards & Input Termination +# ============================================================================== + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[*] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[*] + +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[*] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[*] + +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON diff --git a/cards/bittware/ia-440i/constr/timing.sdc b/cards/bittware/ia-440i/constr/timing.sdc new file mode 100644 index 000000000..9ac9207a1 --- /dev/null +++ b/cards/bittware/ia-440i/constr/timing.sdc @@ -0,0 +1,26 @@ +# timing.sdc: Timing constraints +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +derive_clock_uncertainty + +create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }] + +create_clock -name {SYS_CLK_100M} -period 10.000 [get_ports { SYS_CLK_100M }] +create_clock -name {PCIE_REFCLK0} -period 10.000 [get_ports { PCIE_REFCLK0 }] +create_clock -name {PCIE_REFCLK1} -period 10.000 [get_ports { PCIE_REFCLK1 }] +create_clock -name {QSFP_REFCLK_156M} -period 6.400 [get_ports { QSFP_REFCLK_156M }] + +# Cut (set_false_path) this JTAG clock from all other clocks in the design +set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] + +set MI_CLK [get_clocks cm_i|clk_gen_i|iopll_i|iopll_0_outclk3] + +# the only supported configuration so far! +set FHIP_400G_CLK [get_clocks cm_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_1x400g8_g.eth_ip_g[0].FTILE_1x400g8_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] + +# Fix hold timing issues on FHIP +set_clock_groups -asynchronous -group $MI_CLK -group $FHIP_400G_CLK diff --git a/cards/bittware/ia-440i/readme.rst b/cards/bittware/ia-440i/readme.rst new file mode 100644 index 000000000..81e13b8b0 --- /dev/null +++ b/cards/bittware/ia-440i/readme.rst @@ -0,0 +1,61 @@ +.. _card_ia-440i: + +Bittware IA-440I +---------------- + +- Card information: + - Vendor: Bittware + - Name: IA-440I + - Ethernet ports: 1x QSFP-DD + - PCIe conectors: Edge connector + - `FPGA Card Website `_ +- FPGA specification: + - FPGA part number: ``AGIB023R18A1E1V`` + - Ethernet Hard IP: F-Tile (up to 400G Ethernet) + - PCIe Hard IP: R-Tile (up to PCIe Gen5 x16) + +NDK firmware support +^^^^^^^^^^^^^^^^^^^^ + +- Ethernet cores that are supported in the NDK firmware: + - :ref:`F-Tile in the Network Module ` +- PCIe cores that are supported in the NDK firmware: + - :ref:`R-Tile in the PCIe Module ` + - See the ``/cards/bittware/ia-440i/config/card_conf.tcl`` file for supported PCIe configurations. +- Makefile targets for building the NDK firmware (valid for NDK-APP-Minimal, may vary for other apps): + - Use ``make 400g1`` command for firmware with 1x400GE (default). +- Support for booting the NDK firmware using the nfb-boot tool: + - NO. + +.. note:: + + To build the NDK firmware for this card, you must have the Intel Quartus Prime Pro installed, including a valid license. + +Boot instructions +^^^^^^^^^^^^^^^^^ + +Before you can work with the card, you will need to install Bittware's SDK and IA-440i Card Support Package (CSP) on your host system. +To be able to do that, you will also need Python 3 (version >= 3.8) present on your system, so be sure to get that first. +Next, proceed with the following steps: + +- Download the Bittware SDK and IA-440i CSP installers from the `Bittware Developer Website `_ (version 2024.2). +- Install both downloaded packages by following the instructions in the Bittware SDK and CSP Installation manual (accessible on the same website). +- Connect your IA-440i card to the host using the dedicated USB cable. + +Once this is done, you can check the card status by issuing ``bw_card_list -v``. +If everything is OK (card has been found and is available via USB), you can use the ``bw_bmc_fpga_load`` utility to manage designs for your card. + +- To get more info about the usage and available subprograms of the ``bw_bmc_fpga_load`` utility, type ``bw_bmc_fpga_load -h``. +- Use ``bw_bmc_fpga_load table`` to list all stored flash images. +- Use ``bw_bmc_fpga_load program .rbf
`` to write the image into the configuration flash on the given address. +- Use ``bw_bmc_fpga_load default .rbf`` to make your design the default boot option. +- Use ``bw_bmc_fpga_load load .rbf`` to configure the fpga with your design from the flash. +- Use ``bw_bmc_fpga_load stream .rbf`` to configure the fpga directly without writing it into the flash. + +.. note:: + + All designs stored inside the configuration flash (or directly loaded into the fpga) must be built using the same version of Quartus Prime Pro. + +.. warning:: + + So far, there are features of the nfb framework that are not yet fully supported for this card (e. g. ``nfb-eth -T`` or ``nfb-boot``). diff --git a/cards/bittware/ia-440i/src/Modules.tcl b/cards/bittware/ia-440i/src/Modules.tcl new file mode 100644 index 000000000..9cda2052e --- /dev/null +++ b/cards/bittware/ia-440i/src/Modules.tcl @@ -0,0 +1,57 @@ +# Modules.tcl: script to compile Bittware IA-440I card +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# converting input list to associative array +array set ARCHGRP_ARR $ARCHGRP + +# Paths +set FPGA_COMMON_BASE "$ARCHGRP_ARR(CORE_BASE)/top" +#set BOOT_CTRL_BASE "$OFM_PATH/core/comp/misc/boot_ctrl" + +# Components +lappend COMPONENTS [list "FPGA_COMMON" $FPGA_COMMON_BASE $ARCHGRP] +#lappend COMPONENTS [list "BOOT_CTRL" $BOOT_CTRL_BASE "FULL" ] + +# IP components +set IP_COMMON_TCL $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/common.tcl +source $IP_COMMON_TCL + +set ARCHGRP_ARR(IP_COMMON_TCL) $IP_COMMON_TCL +set ARCHGRP_ARR(IP_TEMPLATE_BASE) $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/intel +set ARCHGRP_ARR(IP_MODIFY_BASE) $ENTITY_BASE/ip +set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Agilex" +set ARCHGRP_ARR(IP_DEVICE) $ARCHGRP_ARR(FPGA) + +set PCIE_CONF [dict create 0 "1x16" 1 "2x8"] +set RTILE_PCIE_IP_NAME "rtile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" + +set ETH_CONF [dict create 400 "1x400g" ] +# TODO: 200 "2x200g" 100 [expr {$ARCHGRP_ARR(ETH_PORT_CHAN,0) == 2 ? "2x100g" : "4x100g"}] 50 "8x50g" 40 "2x40g" 25 "8x25g" 10 "8x10g" +set FTILE_ETH_IP_NAME "ftile_eth_[dict get $ETH_CONF $ARCHGRP_ARR(ETH_PORT_SPEED,0)]" + +# see '$ARCHGRP_ARR(CORE_BASE)/src/ip/common.tcl' for more information regarding the fields +# script_path script_name ip_comp_name type modify +lappend IP_COMPONENTS [list "clk" "iopll" "iopll_ip" 0 1] +lappend IP_COMPONENTS [list "misc" "mailbox_client" "mailbox_client_ip" 0 0] +lappend IP_COMPONENTS [list "misc" "reset_release" "reset_release_ip" 0 0] +lappend IP_COMPONENTS [list "pcie" "rtile_pcie" $RTILE_PCIE_IP_NAME 0 1] + +if {$ARCHGRP_ARR(VIRTUAL_DEBUG_ENABLE)} { + lappend IP_COMPONENTS [list "misc" "jtag_op" "jtag_op_ip" 0 0] +} + +if {$ARCHGRP_ARR(NET_MOD_ARCH) eq "F_TILE"} { + if {$ARCHGRP_ARR(EHIP_PORT_TYPE,0) == 0} { + lappend IP_COMPONENTS [list "clk" "ftile_pll" "ftile_pll" 0 1] + lappend IP_COMPONENTS [list "eth" "ftile_eth" $FTILE_ETH_IP_NAME 0 1] + } +} + +lappend MOD {*}[get_ip_mod_files $IP_COMPONENTS [array get ARCHGRP_ARR]] + +# Top-level +lappend MOD "$ENTITY_BASE/fpga.vhd" diff --git a/cards/bittware/ia-440i/src/Quartus.inc.tcl b/cards/bittware/ia-440i/src/Quartus.inc.tcl new file mode 100644 index 000000000..3d2b48182 --- /dev/null +++ b/cards/bittware/ia-440i/src/Quartus.inc.tcl @@ -0,0 +1,55 @@ +# Quartus.inc.tcl: Quartus.tcl include for card +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# NDK constants (populates all NDK variables from env) +source $env(CORE_BASE)/config/core_bootstrap.tcl + +# Include common card script +source $CORE_BASE/Quartus.inc.tcl + +# Propagating card constants to the Modules.tcl files of the underlying components. +# The description of usage of this array is provided in the Parametrization section +# of the NDK-CORE repository. +set CARD_ARCHGRP(CORE_BASE) $CORE_BASE +set CARD_ARCHGRP(IP_BUILD_DIR) $CARD_BASE/src/ip +set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE +set CARD_ARCHGRP(NET_MOD_ARCH) $NET_MOD_ARCH +# Second dimension because of addition of an element of another array, just for clarity. +set CARD_ARCHGRP(ETH_PORT_SPEED,0) $ETH_PORT_SPEED(0) +set CARD_ARCHGRP(ETH_PORT_CHAN,0) $ETH_PORT_CHAN(0) +set CARD_ARCHGRP(EHIP_PORT_TYPE,0) $EHIP_PORT_TYPE(0) + +# select fpga name +set CARD_FPGA "AGIB023R18A1E1V" +set CARD_ARCHGRP(FPGA) $CARD_FPGA + +# make lists from associative arrays +set CARD_ARCHGRP_L [array get CARD_ARCHGRP] +set CORE_ARCHGRP_L [array get CORE_ARCHGRP] + +# concatenate lists to be handed as a part of the ARCHGRP to the TOPLEVEL +set ARCHGRP_ALL [concat $CARD_ARCHGRP_L $CORE_ARCHGRP_L] + +# Main component +lappend HIERARCHY(COMPONENTS) \ + [list "TOPLEVEL" $CARD_BASE/src $ARCHGRP_ALL] + +# Design parameters +set SYNTH_FLAGS(MODULE) "FPGA" +set SYNTH_FLAGS(FPGA) $CARD_FPGA +set SYNTH_FLAGS(BITSTREAM) "RBF" + +# Enable Quartus Support-Logic Generation stage +set SYNTH_FLAGS(QUARTUS_TLG) 1 + +# QSF constraints for specific parts of the design +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/general.qsf" +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/bmc.qsf" +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pcie.qsf" +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/qsfp.qsf" +#lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/ddr4.qsf" +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/timing.sdc" diff --git a/cards/bittware/ia-440i/src/card.mk b/cards/bittware/ia-440i/src/card.mk new file mode 100644 index 000000000..6938c76c9 --- /dev/null +++ b/cards/bittware/ia-440i/src/card.mk @@ -0,0 +1,43 @@ +# Makefile.card: Makefile include for card +# Copyright (C) 2024 CESNET z. s. p. o. +# Author(s): Jakub Cabal +# Tomas Hak +# +# SPDX-License-Identifier: BSD-3-Clause + +# Optional parameters (can be changed in user Makefile) +############################################################################### + +# Name for output files (rootname) +# This value is set as default in SYNTH_FLAGS(OUTPUT) +OUTPUT_NAME ?= ia-440i + +USER_ENV ?= + +# Private parameters (do not change these values in user Makefile) +############################################################################### + +# Get directory of this Makefile.inc +CARD_BASE_LOCAL := $(dir $(lastword $(MAKEFILE_LIST))) +CARD_BASE ?= $(CARD_BASE_LOCAL)/.. +CORE_BASE ?= $(COMBO_BASE)/core + +# Load correct paths to build system +include $(CORE_BASE)/ndk_paths.mk + +NETCOPE_ENV = \ + OFM_PATH=$(OFM_PATH)\ + COMBO_BASE=$(COMBO_BASE)\ + FIRMWARE_BASE=$(FIRMWARE_BASE)\ + CARD_BASE=$(CARD_BASE) \ + CORE_BASE=$(CORE_BASE) \ + APP_CONF=$(APP_CONF) \ + OUTPUT_NAME=$(OUTPUT_NAME) \ + ETH_PORT_SPEED=$(ETH_PORT_SPEED) \ + ETH_PORT_CHAN=$(ETH_PORT_CHAN) \ + EHIP_PORT_TYPE=$(EHIP_PORT_TYPE) \ + DMA_TYPE=$(DMA_TYPE) \ + $(USER_ENV) + +include $(CORE_BASE)/core.mk +include $(OFM_PATH)/build/Makefile.Quartus.inc diff --git a/cards/bittware/ia-440i/src/fpga.vhd b/cards/bittware/ia-440i/src/fpga.vhd new file mode 100644 index 000000000..cc8453209 --- /dev/null +++ b/cards/bittware/ia-440i/src/fpga.vhd @@ -0,0 +1,215 @@ +-- fpga.vhd: IA-440I board top level entity and architecture +-- Copyright (C) 2024 CESNET z. s. p. o. +-- Author(s): Jakub Cabal +-- Tomas Hak +-- +-- SPDX-License-Identifier: BSD-3-Clause + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.combo_const.all; +use work.combo_user_const.all; + +use work.math_pack.all; +use work.type_pack.all; + +entity FPGA is +port ( + -- FPGA system clock + SYS_CLK_100M : in std_logic; + -- User LEDs + USER_LED_G : out std_logic; + USER_LED_R : out std_logic; + + -- ========================================================================= + -- PCIe + -- ========================================================================= + PCIE_REFCLK0 : in std_logic; + PCIE_REFCLK1 : in std_logic; + PCIE_SYSRST_N : in std_logic; + PCIE_RX_P : in std_logic_vector(16-1 downto 0); + PCIE_RX_N : in std_logic_vector(16-1 downto 0); + PCIE_TX_P : out std_logic_vector(16-1 downto 0); + PCIE_TX_N : out std_logic_vector(16-1 downto 0); + + -- ========================================================================= + -- QSFP + -- ========================================================================= + QSFP_REFCLK_156M : in std_logic; + QSFP_RX_P : in std_logic_vector(8-1 downto 0); + QSFP_RX_N : in std_logic_vector(8-1 downto 0); + QSFP_TX_P : out std_logic_vector(8-1 downto 0); + QSFP_TX_N : out std_logic_vector(8-1 downto 0); + + -- ========================================================================= + -- BMC + -- ========================================================================= + BMC_IF_PRESENT_N : out std_logic; + BMC_RST_N : in std_logic; + + FPGA_EG_SPI_SCK : out std_logic; + FPGA_EG_SPI_MISO : in std_logic; + FPGA_EG_SPI_MOSI : out std_logic; + FPGA_EG_SPI_PCS0 : out std_logic; + BMC_TO_FPGA_IRQ : in std_logic; + + FPGA_IG_SPI_SCK : in std_logic; + FPGA_IG_SPI_MISO : inout std_logic; + FPGA_IG_SPI_MOSI : in std_logic; + FPGA_IG_SPI_PCS0 : in std_logic; + FPGA_TO_BMC_IRQ : out std_logic + + -- BMC_GPIO0 : out std_logic; + -- BMC_GPIO1 : in std_logic +); +end entity; + +architecture FULL of FPGA is + + constant PCIE_LANES : natural := 16; + constant PCIE_CLKS : natural := 2; + constant PCIE_CONS : natural := 1; + constant MISC_IN_WIDTH : natural := 4; + constant MISC_OUT_WIDTH : natural := 4; + constant ETH_LANES : natural := 8; + constant DMA_MODULES : natural := ETH_PORTS; + constant DMA_ENDPOINTS : natural := tsel(PCIE_ENDPOINT_MODE=1,PCIE_ENDPOINTS,2*PCIE_ENDPOINTS); + constant STATUS_LEDS : natural := 2; -- fake, this board has only 1 status LED + + signal status_led_g : std_logic_vector(STATUS_LEDS-1 downto 0); + signal status_led_r : std_logic_vector(STATUS_LEDS-1 downto 0); + + constant BMC_IF_PRESENT : boolean := false; + + signal bmc_mi_clk : std_logic; + signal bmc_mi_reset : std_logic; + signal bmc_mi_dwr : std_logic_vector(32-1 downto 0); + signal bmc_mi_addr : std_logic_vector(32-1 downto 0); + signal bmc_mi_rd : std_logic; + signal bmc_mi_wr : std_logic; + signal bmc_mi_be : std_logic_vector(4-1 downto 0); + signal bmc_mi_drd : std_logic_vector(32-1 downto 0); + signal bmc_mi_ardy : std_logic; + signal bmc_mi_drdy : std_logic; + +begin + + cm_i : entity work.FPGA_COMMON + generic map ( + SYSCLK_PERIOD => 10.0, + USE_PCIE_CLK => false, + + PCIE_LANES => PCIE_LANES, + PCIE_CLKS => PCIE_CLKS, + PCIE_CONS => PCIE_CONS, + + ETH_CORE_ARCH => NET_MOD_ARCH, + ETH_PORTS => ETH_PORTS, + ETH_PORT_SPEED => ETH_PORT_SPEED, + ETH_PORT_CHAN => ETH_PORT_CHAN, + ETH_PORT_LEDS => 1, -- fake, this board has no ETH LEDs + ETH_LANES => ETH_LANES, + + QSFP_PORTS => 1, + QSFP_I2C_PORTS => 1, + -- QSFP_I2C_TRISTATE => ??, + + STATUS_LEDS => STATUS_LEDS, + MISC_IN_WIDTH => MISC_IN_WIDTH, + MISC_OUT_WIDTH => MISC_OUT_WIDTH, + + PCIE_ENDPOINTS => PCIE_ENDPOINTS, + PCIE_ENDPOINT_TYPE => PCIE_MOD_ARCH, + PCIE_ENDPOINT_MODE => PCIE_ENDPOINT_MODE, + + DMA_ENDPOINTS => DMA_ENDPOINTS, + DMA_MODULES => DMA_MODULES, + + DMA_RX_CHANNELS => DMA_RX_CHANNELS/DMA_MODULES, + DMA_TX_CHANNELS => DMA_TX_CHANNELS/DMA_MODULES, + + BOARD => "IA-440I", + DEVICE => "AGILEX" + ) + port map( + SYSCLK => SYS_CLK_100M, + SYSRST => '0', + + PCIE_SYSCLK_P => PCIE_REFCLK1 & PCIE_REFCLK0, + PCIE_SYSCLK_N => (others => '0'), + PCIE_SYSRST_N(0) => PCIE_SYSRST_N, + PCIE_RX_P => PCIE_RX_P, + PCIE_RX_N => PCIE_RX_N, + PCIE_TX_P => PCIE_TX_P, + PCIE_TX_N => PCIE_TX_N, + + ETH_REFCLK_P(0) => QSFP_REFCLK_156M, + ETH_REFCLK_N => (others => '0'), + ETH_RX_P => QSFP_RX_P, + ETH_RX_N => QSFP_RX_N, + ETH_TX_P => QSFP_TX_P, + ETH_TX_N => QSFP_TX_N, + + -- QSFP_MODPRS_N => ??, + -- QSFP_INT_N => ??, + + -- QSFP_I2C_SCL_I(0) => qsfp_scl, + -- QSFP_I2C_SDA_I(0) => qsfp_sda, + -- QSFP_I2C_SCL_O(0) => qsfp_scl_o, + -- QSFP_I2C_SCL_OE(0) => qsfp_scl_oe, + -- QSFP_I2C_SDA_O(0) => qsfp_sda_o, + -- QSFP_I2C_SDA_OE(0) => qsfp_sda_oe, + + -- QSFP_MODSEL_N => open, + -- QSFP_LPMODE(0) => ioexp_o(4), + -- QSFP_RESET_N(0) => ioexp_o(7), + -- QSFP_MODPRS_N => (others => ioexp_i(6)), + -- QSFP_INT_N => (others => ioexp_i(5)), + + STATUS_LED_G => status_led_g, + STATUS_LED_R => status_led_r, + + MISC_IN => (others => '0'), + MISC_OUT => open, + + BOOT_MI_CLK => bmc_mi_clk, + BOOT_MI_RESET => bmc_mi_reset, + BOOT_MI_DWR => bmc_mi_dwr, + BOOT_MI_ADDR => bmc_mi_addr, + BOOT_MI_RD => bmc_mi_rd, + BOOT_MI_WR => bmc_mi_wr, + BOOT_MI_BE => bmc_mi_be, + BOOT_MI_DRD => bmc_mi_drd, + BOOT_MI_ARDY => bmc_mi_ardy, + BOOT_MI_DRDY => bmc_mi_drdy + ); + + USER_LED_G <= status_led_g(0); + USER_LED_R <= status_led_r(0); + + bmc_if_open_g: if not BMC_IF_PRESENT generate + BMC_IF_PRESENT_N <= '1'; + end generate; + + -- TODO: custom BMC boot controller + -- boot_ctrl_i : entity work.BOOT_CTRL + -- generic map ( + -- DEVICE => DEVICE, + -- BOOT_TYPE => 3 + -- ) + -- port map ( + -- MI_CLK => boot_mi_clk, + -- MI_RESET => boot_mi_reset, + -- MI_DWR => boot_mi_dwr, + -- MI_ADDR => boot_mi_addr, + -- MI_BE => boot_mi_be, + -- MI_RD => boot_mi_rd, + -- MI_WR => boot_mi_wr, + -- MI_ARDY => boot_mi_ardy, + -- MI_DRD => boot_mi_drd, + -- MI_DRDY => boot_mi_drdy, + -- ... + +end architecture; diff --git a/cards/bittware/ia-440i/src/ip/ftile_eth.ip.tcl b/cards/bittware/ia-440i/src/ip/ftile_eth.ip.tcl new file mode 100644 index 000000000..4e702b029 --- /dev/null +++ b/cards/bittware/ia-440i/src/ip/ftile_eth.ip.tcl @@ -0,0 +1,153 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +proc do_adjust_ftile_eth_ip_1x400g {} { + set_instance_parameter_value eth_f_0 {BASE_SEC_ENABLE} {0} + set_instance_parameter_value eth_f_0 {CUSTOM_RATE_GUI} {10.3125} + set_instance_parameter_value eth_f_0 {ENABLE_ADME_GUI} {1} + set_instance_parameter_value eth_f_0 {ENABLE_IPXACT_GUI} {1} + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {400G-8} + set_instance_parameter_value eth_f_0 {OPTIMIZED_SIM_ENABLE} {0} + set_instance_parameter_value eth_f_0 {PACKING_EN_GUI} {1} + set_instance_parameter_value eth_f_0 {QUARTUS_CDC} {0} + set_instance_parameter_value eth_f_0 {RSFEC_TYPE_GUI} {3} + set_instance_parameter_value eth_f_0 {SIM_TIME} {0} + set_instance_parameter_value eth_f_0 {bk_cfg_kvcc_vreg_offset_en_val} {CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE} + set_instance_parameter_value eth_f_0 {bk_ext_ac_cap} {EXTERNAL_AC_CAP_ENABLE} + set_instance_parameter_value eth_f_0 {bk_rx_invert_p_and_n} {RX_INVERT_PN_DIS} + set_instance_parameter_value eth_f_0 {bk_rx_termination} {RXTERM_OFFSET_P0} + set_instance_parameter_value eth_f_0 {bk_tx_invert_p_and_n} {TX_INVERT_PN_DIS} + set_instance_parameter_value eth_f_0 {bk_tx_termination} {TXTERM_OFFSET_P0} + set_instance_parameter_value eth_f_0 {bk_txeq_main_tap} {41.5} + set_instance_parameter_value eth_f_0 {bk_txeq_post_tap_1} {0.0} + set_instance_parameter_value eth_f_0 {bk_txeq_post_tap_2} {0.0} + set_instance_parameter_value eth_f_0 {bk_txeq_post_tap_3} {0.0} + set_instance_parameter_value eth_f_0 {bk_txeq_post_tap_4} {0.0} + set_instance_parameter_value eth_f_0 {bk_txeq_pre_tap_1} {0.0} + set_instance_parameter_value eth_f_0 {bk_txeq_pre_tap_2} {0.0} + set_instance_parameter_value eth_f_0 {bk_txeq_pre_tap_3} {0.0} + set_instance_parameter_value eth_f_0 {bk_txout_tristate_en} {TXOUT_TRISTATE_DIS} + set_instance_parameter_value eth_f_0 {debug_counter} {0} + set_instance_parameter_value eth_f_0 {fgt_protocol_mode} {DISABLED} + set_instance_parameter_value eth_f_0 {protocol_hard_pcie_lowloss} {DISABLE} + set_instance_parameter_value eth_f_0 {rx_ac_couple_enable} {ENABLE} + set_instance_parameter_value eth_f_0 {rx_onchip_termination} {RX_ONCHIP_TERMINATION_R_2} + set_instance_parameter_value eth_f_0 {rxeq_dfe_data_tap_1} {0} + set_instance_parameter_value eth_f_0 {rxeq_hf_boost} {0} + set_instance_parameter_value eth_f_0 {rxeq_vga_gain} {0} + set_instance_parameter_value eth_f_0 {txmac_saddr_gui} {001122334455} + set_instance_parameter_value eth_f_0 {ux_txeq_main_tap} {35} + set_instance_parameter_value eth_f_0 {ux_txeq_post_tap_1} {0} + set_instance_parameter_value eth_f_0 {ux_txeq_pre_tap_1} {5} + set_instance_parameter_value eth_f_0 {ux_txeq_pre_tap_2} {0} + set_instance_parameter_value eth_f_0 {vsr_mode} {VSR_MODE_DISABLE} + + set_interface_property reconfig_xcvr_slave_1 EXPORT_OF eth_f_0.reconfig_xcvr_slave_1 + set_interface_property reconfig_xcvr_slave_2 EXPORT_OF eth_f_0.reconfig_xcvr_slave_2 + set_interface_property reconfig_xcvr_slave_3 EXPORT_OF eth_f_0.reconfig_xcvr_slave_3 + set_interface_property reconfig_xcvr_slave_4 EXPORT_OF eth_f_0.reconfig_xcvr_slave_4 + set_interface_property reconfig_xcvr_slave_5 EXPORT_OF eth_f_0.reconfig_xcvr_slave_5 + set_interface_property reconfig_xcvr_slave_6 EXPORT_OF eth_f_0.reconfig_xcvr_slave_6 + set_interface_property reconfig_xcvr_slave_7 EXPORT_OF eth_f_0.reconfig_xcvr_slave_7 +} + +proc do_adjust_ftile_eth_ip_2x200g {} { + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {200G-4} + set_instance_parameter_value eth_f_0 {PACKING_EN_GUI} {1} + set_instance_parameter_value eth_f_0 {RSFEC_TYPE_GUI} {3} + + set_interface_property reconfig_xcvr_slave_1 EXPORT_OF eth_f_0.reconfig_xcvr_slave_1 + set_interface_property reconfig_xcvr_slave_2 EXPORT_OF eth_f_0.reconfig_xcvr_slave_2 + set_interface_property reconfig_xcvr_slave_3 EXPORT_OF eth_f_0.reconfig_xcvr_slave_3 +} + +proc do_adjust_ftile_eth_ip_4x100g {} { + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {100G-2} + set_instance_parameter_value eth_f_0 {PACKING_EN_GUI} {1} + set_instance_parameter_value eth_f_0 {RSFEC_TYPE_GUI} {3} + + set_interface_property reconfig_xcvr_slave_1 EXPORT_OF eth_f_0.reconfig_xcvr_slave_1 +} + +proc do_adjust_ftile_eth_ip_2x100g {} { + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {100G-4} + set_instance_parameter_value eth_f_0 {PACKING_EN_GUI} {1} + + set_interface_property reconfig_xcvr_slave_1 EXPORT_OF eth_f_0.reconfig_xcvr_slave_1 + set_interface_property reconfig_xcvr_slave_2 EXPORT_OF eth_f_0.reconfig_xcvr_slave_2 + set_interface_property reconfig_xcvr_slave_3 EXPORT_OF eth_f_0.reconfig_xcvr_slave_3 +} + +proc do_adjust_ftile_eth_ip_8x50g {} { + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {50G-1} + set_instance_parameter_value eth_f_0 {PACKING_EN_GUI} {1} + set_instance_parameter_value eth_f_0 {RSFEC_TYPE_GUI} {3} +} + +proc do_adjust_ftile_eth_ip_2x40g {} { + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {40G-4} + set_instance_parameter_value eth_f_0 {PACKING_EN_GUI} {1} + + set_interface_property reconfig_xcvr_slave_1 EXPORT_OF eth_f_0.reconfig_xcvr_slave_1 + set_interface_property reconfig_xcvr_slave_2 EXPORT_OF eth_f_0.reconfig_xcvr_slave_2 + set_interface_property reconfig_xcvr_slave_3 EXPORT_OF eth_f_0.reconfig_xcvr_slave_3 +} + +proc do_adjust_ftile_eth_ip_8x25g {} { + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {25G-1} + set_instance_parameter_value eth_f_0 {RSFEC_TYPE_GUI} {2} +} + +proc do_adjust_ftile_eth_ip_8x10g {} { +} + + +# adjust parameters in "ftile_eth_ip" system +proc do_adjust_ftile_eth_ip {device family ipname filename adjust_proc} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + # common IP core parameters + set_instance_parameter_value eth_f_0 {DV_OVERRIDE} {1} + set_instance_parameter_value eth_f_0 {ENABLE_ETK_GUI} {1} + set_instance_parameter_value eth_f_0 {SYSPLL_RATE_GUI} {1} + set_instance_parameter_value eth_f_0 {enforce_max_frame_size_gui} {1} + set_instance_parameter_value eth_f_0 {link_fault_mode_gui} {Bidirectional} + set_instance_parameter_value eth_f_0 {rx_max_frame_size_gui} {16383} + set_instance_parameter_value eth_f_0 {rx_vlan_detection_gui} {0} + set_instance_parameter_value eth_f_0 {tx_max_frame_size_gui} {16383} + set_instance_parameter_value eth_f_0 {tx_vlan_detection_gui} {0} + + # configuration-specific parameters + $adjust_proc + + save_system $ipname +} + +proc do_nothing {} {} + +set cb do_nothing +if {$PARAMS(ETH_PORT_SPEED,0) == 400} { + set cb do_adjust_ftile_eth_ip_1x400g +} elseif {$PARAMS(ETH_PORT_SPEED,0) == 200} { + set cb do_adjust_ftile_eth_ip_2x200g +} elseif {$PARAMS(ETH_PORT_SPEED,0) == 100 && $PARAMS(ETH_PORT_CHAN,0) == 4} { + set cb do_adjust_ftile_eth_ip_4x100g +} elseif {$PARAMS(ETH_PORT_SPEED,0) == 100 && $PARAMS(ETH_PORT_CHAN,0) == 2} { + set cb do_adjust_ftile_eth_ip_2x100g +} elseif {$PARAMS(ETH_PORT_SPEED,0) == 50} { + set cb do_adjust_ftile_eth_ip_8x50g +} elseif {$PARAMS(ETH_PORT_SPEED,0) == 40} { + set cb do_adjust_ftile_eth_ip_2x40g +} elseif {$PARAMS(ETH_PORT_SPEED,0) == 25} { + set cb do_adjust_ftile_eth_ip_8x25g +} elseif {$PARAMS(ETH_PORT_SPEED,0) == 10} { + set cb do_adjust_ftile_eth_ip_8x10g +} + +do_adjust_ftile_eth_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb diff --git a/cards/bittware/ia-440i/src/ip/ftile_pll.ip.tcl b/cards/bittware/ia-440i/src/ip/ftile_pll.ip.tcl new file mode 100644 index 000000000..8e95357e1 --- /dev/null +++ b/cards/bittware/ia-440i/src/ip/ftile_pll.ip.tcl @@ -0,0 +1,58 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +# adjust parameters in "ftile_pll_ip" system +proc do_adjust_ftile_pll_ip {device family ipname filename} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + set_instance_parameter_value systemclk_f_0 {bk_cfg_kvcc_vreg_offset_en_val} {CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE} + set_instance_parameter_value systemclk_f_0 {bk_ext_ac_cap} {EXTERNAL_AC_CAP_ENABLE} + set_instance_parameter_value systemclk_f_0 {bk_rx_invert_p_and_n} {RX_INVERT_PN_DIS} + set_instance_parameter_value systemclk_f_0 {bk_rx_termination} {RXTERM_OFFSET_P0} + set_instance_parameter_value systemclk_f_0 {bk_tx_invert_p_and_n} {TX_INVERT_PN_DIS} + set_instance_parameter_value systemclk_f_0 {bk_tx_termination} {TXTERM_OFFSET_P0} + set_instance_parameter_value systemclk_f_0 {bk_txeq_main_tap} {41.5} + set_instance_parameter_value systemclk_f_0 {bk_txeq_post_tap_1} {0.0} + set_instance_parameter_value systemclk_f_0 {bk_txeq_post_tap_2} {0.0} + set_instance_parameter_value systemclk_f_0 {bk_txeq_post_tap_3} {0.0} + set_instance_parameter_value systemclk_f_0 {bk_txeq_post_tap_4} {0.0} + set_instance_parameter_value systemclk_f_0 {bk_txeq_pre_tap_1} {0.0} + set_instance_parameter_value systemclk_f_0 {bk_txeq_pre_tap_2} {0.0} + set_instance_parameter_value systemclk_f_0 {bk_txeq_pre_tap_3} {0.0} + set_instance_parameter_value systemclk_f_0 {bk_txout_tristate_en} {TXOUT_TRISTATE_DIS} + set_instance_parameter_value systemclk_f_0 {protocol_hard_pcie_lowloss} {DISABLE} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_0} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_1} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_2} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_3} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_4} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_5} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_6} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_7} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_8} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_always_active_9} {1} + set_instance_parameter_value systemclk_f_0 {refclk_fgt_output_enable_0} {1} + set_instance_parameter_value systemclk_f_0 {rx_ac_couple_enable} {ENABLE} + set_instance_parameter_value systemclk_f_0 {rx_onchip_termination} {RX_ONCHIP_TERMINATION_R_2} + set_instance_parameter_value systemclk_f_0 {rxeq_dfe_data_tap_1} {0} + set_instance_parameter_value systemclk_f_0 {rxeq_hf_boost} {0} + set_instance_parameter_value systemclk_f_0 {rxeq_vga_gain} {0} + set_instance_parameter_value systemclk_f_0 {syspll_mod_0} {ETHERNET_FREQ_830_156} + set_instance_parameter_value systemclk_f_0 {ux_txeq_main_tap} {35} + set_instance_parameter_value systemclk_f_0 {ux_txeq_post_tap_1} {0} + set_instance_parameter_value systemclk_f_0 {ux_txeq_pre_tap_1} {5} + set_instance_parameter_value systemclk_f_0 {ux_txeq_pre_tap_2} {0} + set_instance_parameter_value systemclk_f_0 {vsr_mode} {VSR_MODE_DISABLE} + + set_interface_property out_refclk_fgt_0 EXPORT_OF systemclk_f_0.out_refclk_fgt_0 + + save_system $ipname +} + +do_adjust_ftile_pll_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] diff --git a/cards/bittware/ia-440i/src/ip/iopll.ip.tcl b/cards/bittware/ia-440i/src/ip/iopll.ip.tcl new file mode 100644 index 000000000..891be1073 --- /dev/null +++ b/cards/bittware/ia-440i/src/ip/iopll.ip.tcl @@ -0,0 +1,39 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +# adjust parameters in "iopll_ip" system +proc do_adjust_iopll_ip {device family ipname filename} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {1} + set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {3} + set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {4} + set_instance_parameter_value iopll_0 {gui_extclkout_source} {C0} + set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1666.667} + set_instance_parameter_value iopll_0 {gui_multiply_factor} {12} + set_instance_parameter_value iopll_0 {gui_number_of_clocks} {4} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {400.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {300.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {200.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {2500.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {3333.333} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {5000.0} + set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {High} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_disabled} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_disabled} + set_instance_parameter_value iopll_0 {gui_user_base_address} {0} + + set_interface_property outclk1 EXPORT_OF iopll_0.outclk1 + set_interface_property outclk2 EXPORT_OF iopll_0.outclk2 + set_interface_property outclk3 EXPORT_OF iopll_0.outclk3 + + save_system $ipname +} + +do_adjust_iopll_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] diff --git a/cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl b/cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl new file mode 100644 index 000000000..827e5e9bb --- /dev/null +++ b/cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl @@ -0,0 +1,90 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +proc do_adjust_rtile_pcie_ip_1x16 {} { +} + +proc do_adjust_rtile_pcie_ip_2x8 {} { + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_0_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_1_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_enable_cii_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {26} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_class_code_hwtcl} {131072} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {0xc000} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_vendor_id_user_hwtcl} {6380} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_user_vsec_cap_enable_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_virtual_pf0_user_vsec_offset_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {design_environment} {Unknown} + set_instance_parameter_value intel_rtile_pcie_ast_0 {standard_interface_selection_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 2x8, Interface - 512 bit} + + set_interface_property p1_rx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st0 + set_interface_property p1_rx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st_misc + set_interface_property p1_rx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st1 + set_interface_property p1_tx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st_misc + set_interface_property p1_tx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st0 + set_interface_property p1_tx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st1 + set_interface_property p1_tx_ehp EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_ehp + set_interface_property p1_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_reset_status_n + set_interface_property p1_slow_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_slow_reset_status_n + set_interface_property p1_hip_status EXPORT_OF intel_rtile_pcie_ast_0.p1_hip_status + set_interface_property p1_power_mgnt EXPORT_OF intel_rtile_pcie_ast_0.p1_power_mgnt + set_interface_property p1_pld_gp EXPORT_OF intel_rtile_pcie_ast_0.p1_pld_gp + set_interface_property p1_cii EXPORT_OF intel_rtile_pcie_ast_0.p1_cii +} + +# adjust parameters in "rtile_pcie_ip" system +proc do_adjust_rtile_pcie_ip {device family ipname filename adjust_proc} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + # common IP core parameters + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_enable_cii_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {26} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_class_code_hwtcl} {131072} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {0xc000} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_vendor_id_user_hwtcl} {6380} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_user_vsec_cap_enable_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_virtual_pf0_user_vsec_offset_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {example_design_mode_hwtcl} {PIO/SRIOV} + set_instance_parameter_value intel_rtile_pcie_ast_0 {g5_pld_clkfreq_user_hwtcl} {400MHz} + set_instance_parameter_value intel_rtile_pcie_ast_0 {independent_perst_x16_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {independent_warmcold_perst_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {pipemode_sim_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {true_independent_support_mode_user_hwtcl} {0} + + # configuration-specific parameters + $adjust_proc + + set_interface_property p0_cii EXPORT_OF intel_rtile_pcie_ast_0.p0_cii + + save_system $ipname +} + +proc do_nothing {} {} + +set cb do_nothing +if {$PARAMS(PCIE_ENDPOINT_MODE) == 0} { + set cb do_adjust_rtile_pcie_ip_1x16 +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1} { + set cb do_adjust_rtile_pcie_ip_2x8 +} + +do_adjust_rtile_pcie_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb diff --git a/doc/source/index.rst b/doc/source/index.rst index ce3c1637a..ec02180e2 100644 --- a/doc/source/index.rst +++ b/doc/source/index.rst @@ -102,6 +102,7 @@ support a subset of these cards. A complete list of supported FPGA cards can be ndk_cards/silicom/fb2cghh/readme ndk_cards/silicom/n6010/readme ndk_cards/bittware/ia-420f/readme + ndk_cards/bittware/ia-440i/readme ndk_cards/amd/alveo-u200/readme ndk_cards/amd/alveo-u55c/readme ndk_cards/amd/vcu118/readme