From b05918b0417dabb5abca7126b46e2ce5a494bec4 Mon Sep 17 00:00:00 2001 From: Radek Isa Date: Tue, 3 Sep 2024 14:05:37 +0200 Subject: [PATCH] APP UVM: [MAITENANCE] Add tsu agent and interface to generate better timestamps --- app/uvm/testbench.sv | 14 +++++++++++++- app/uvm/tests/base.sv | 11 +++++++++++ app/uvm/tests/fifo.sv | 17 +++++++++++++++-- app/uvm/tests/full_speed.sv | 9 +++++++++ 4 files changed, 48 insertions(+), 3 deletions(-) diff --git a/app/uvm/testbench.sv b/app/uvm/testbench.sv index b2e01015f..cdbe0f190 100644 --- a/app/uvm/testbench.sv +++ b/app/uvm/testbench.sv @@ -71,6 +71,10 @@ module testbench; //CONFIGURE INTERFACE mi_if#(test_pkg::MI_DATA_WIDTH, test_pkg::MI_ADDR_WIDTH) config_if(MI_CLK); + //TSU INTERFACE + mvb_if #(1, 64) m_tsu (APP_CLK); + + ///////////////////////// // CLOCK GENERATION always #(test_pkg::CLK_PERIOD/2) CLK_USER_X1 = ~CLK_USER_X1; @@ -377,6 +381,11 @@ module testbench; .MEM_AVMM_READDATA (mem_readdata ), // : in std_logic_vector(MEM_PORTS*MEM_DATA_WIDTH-1 downto 0); .MEM_AVMM_READDATAVALID(mem_readdatavalid), // : in std_logic_vector(MEM_PORTS-1 downto 0); + .TSU_CLK (APP_CLK), //: in std_logic + .TSU_RESET (1'b0), //: in std_logic; + .TSU_TS_NS (m_tsu.DATA[64-1 : 0]), //: in std_logic_vector(64-1 downto 0); -- Timestamp from TSU in nanoseconds format + .TSU_TS_VLD (m_tsu.SRC_RDY & m_tsu.VLD[0]), //: in std_logic; + .EMIF_RST_REQ (), // : out std_logic_vector(MEM_PORTS-1 downto 0); .EMIF_RST_DONE (), // : in std_logic_vector(MEM_PORTS-1 downto 0); .EMIF_ECC_USR_INT (), // : in std_logic_vector(MEM_PORTS-1 downto 0); @@ -392,7 +401,7 @@ module testbench; .MI_DRD (config_if.DRD), // : out std_logic_vector(MI_DATA_WIDTH-1 downto 0); .MI_DRDY (config_if.DRDY) // : out std_logic ); - + assign m_tsu.SRC_RDY = 1'b1; app_core_property #( .ETH_STREAMS (test_pkg::ETH_STREAMS), @@ -465,6 +474,9 @@ module testbench; //CONFIGURE INF uvm_config_db#(virtual mi_if#(test_pkg::MI_DATA_WIDTH, test_pkg::MI_ADDR_WIDTH))::set(null, "", "MI_INTERFACE", config_if); + //TSU + uvm_config_db#(virtual mvb_if #(1, 64))::set(null, "", "TSU_INTERFACE", m_tsu); + ///////////////////////////////////////////// // RUN TEST m_root = uvm_root::get(); diff --git a/app/uvm/tests/base.sv b/app/uvm/tests/base.sv index 2a5011adb..e519b1607 100644 --- a/app/uvm/tests/base.sv +++ b/app/uvm/tests/base.sv @@ -103,6 +103,7 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR endtask virtual task run_phase(uvm_phase phase); + uvm_app_core::sequence_tsu tsu_seq; uvm_app_core::sequence_main#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH, MFB_ITEM_WIDTH, ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH) main_seq; uvm_app_core::sequence_stop#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH, MFB_ITEM_WIDTH, @@ -113,6 +114,7 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH)::type_id::create("main_seq", m_env.m_sequencer); stop_seq = uvm_app_core::sequence_stop#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH, MFB_ITEM_WIDTH, ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH)::type_id::create("stop_seq", m_env.m_sequencer); + phase.raise_objection(this); // RUN RESET @@ -120,6 +122,14 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR run_reset(phase); join_none; + + // RUN TSU + tsu_seq = uvm_app_core::sequence_tsu::type_id::create("tsu_seq", m_env.m_tsu.m_sequencer); + tsu_seq.randomize(); + fork + tsu_seq.start(m_env.m_tsu.m_sequencer); + join_none; + ////configure egent wait(event_reset == 1'b0); for (int unsigned it = 0; it < 3; it++) begin @@ -130,6 +140,7 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR for (int unsigned it = 0; it < 5; it++) begin assert(main_seq.randomize()) else `uvm_fatal(m_env.m_sequencer.get_full_name(), "\n\tCannot randomize main sequence"); + main_seq.time_start = tsu_seq.time_start; main_seq.start(m_env.m_sequencer); end diff --git a/app/uvm/tests/fifo.sv b/app/uvm/tests/fifo.sv index 6bb530be2..77eb8c4ab 100644 --- a/app/uvm/tests/fifo.sv +++ b/app/uvm/tests/fifo.sv @@ -145,10 +145,14 @@ class sequence_fifo#( endfunction virtual task eth_rx_sequence(int unsigned index); - uvm_app_core::sequence_eth#(2**8, 16, MFB_ITEM_WIDTH) packet_seq; + uvm_app_core::sequence_library_eth#(2**8, 16, MFB_ITEM_WIDTH) packet_seq; + uvm_app_core::config_sequence_eth seq_cfg; int unsigned it; - packet_seq = uvm_app_core::sequence_eth#(2**8, 16, MFB_ITEM_WIDTH)::type_id::create("mfb_rx_seq", p_sequencer.m_eth_rx[index]); + seq_cfg = new(); + seq_cfg.time_start = time_start; + packet_seq = uvm_app_core::sequence_library_eth#(2**8, 16, MFB_ITEM_WIDTH)::type_id::create("mfb_rx_seq", p_sequencer.m_eth_rx[index]); + packet_seq.init_sequence(seq_cfg); uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.m_eth_rx[index], "", "state", rx_status); it = 0; @@ -358,6 +362,7 @@ class fifo#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR endfunction virtual task run_phase(uvm_phase phase); + uvm_app_core::sequence_tsu tsu_seq; test::sequence_fifo#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH, MFB_ITEM_WIDTH, ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH) main_seq; test::sequence_fifo_stop#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH, MFB_ITEM_WIDTH, @@ -375,6 +380,13 @@ class fifo#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR run_reset(phase); join_none; + // RUN TSU + tsu_seq = uvm_app_core::sequence_tsu::type_id::create("tsu_seq", m_env.m_tsu.m_sequencer); + tsu_seq.randomize(); + fork + tsu_seq.start(m_env.m_tsu.m_sequencer); + join_none; + ////configure egent wait(event_reset == 1'b0); for (int unsigned it = 0; it < 2; it++) begin @@ -385,6 +397,7 @@ class fifo#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR assert(main_seq.randomize()) else `uvm_fatal(m_env.m_sequencer.get_full_name(), "\n\tCannot randomize main sequence"); main_seq.start(m_env.m_sequencer); + main_seq.time_start = tsu_seq.time_start; assert(stop_seq.randomize()) else `uvm_fatal(m_env.m_sequencer.get_full_name(), "\n\tCannot randomize main sequence"); fork diff --git a/app/uvm/tests/full_speed.sv b/app/uvm/tests/full_speed.sv index 3c719ca31..ac456a460 100644 --- a/app/uvm/tests/full_speed.sv +++ b/app/uvm/tests/full_speed.sv @@ -140,6 +140,7 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_ endfunction virtual task run_phase(uvm_phase phase); + uvm_app_core::sequence_tsu tsu_seq; test::sequence_speed#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH, MFB_ITEM_WIDTH, ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH) main_seq; uvm_app_core::sequence_stop#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH, MFB_ITEM_WIDTH, @@ -157,6 +158,13 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_ run_reset(phase); join_none; + // RUN TSU + tsu_seq = uvm_app_core::sequence_tsu::type_id::create("tsu_seq", m_env.m_tsu.m_sequencer); + tsu_seq.randomize(); + fork + tsu_seq.start(m_env.m_tsu.m_sequencer); + join_none; + ////configure egent wait(event_reset == 1'b0); for (int unsigned it = 0; it < 3; it++) begin @@ -170,6 +178,7 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_ //for (int unsigned it = 0; it < 10; it++) begin assert(main_seq.randomize()) else `uvm_fatal(m_env.m_sequencer.get_full_name(), "\n\tCannot randomize main sequence"); main_seq.start(m_env.m_sequencer); + main_seq.time_start = tsu_seq.time_start; end assert(stop_seq.randomize()) else `uvm_fatal(m_env.m_sequencer.get_full_name(), "\n\tCannot randomize main sequence");