diff --git a/comp/base/fifo/fifo_n1/Modules.tcl b/comp/base/fifo/fifo_n1/Modules.tcl deleted file mode 100644 index d57aff7bf..000000000 --- a/comp/base/fifo/fifo_n1/Modules.tcl +++ /dev/null @@ -1,29 +0,0 @@ -# Modules.tcl: Local include tcl script -# Copyright (C) 2017 CESNET -# Author: Vaclav Hummel -# -# SPDX-License-Identifier: BSD-3-Clause - -set MATH_PKG "$OFM_PATH/comp/base/pkg" - -set MOD "$MOD $ENTITY_BASE/fifo_n1_ent.vhd" -set MOD "$MOD $ENTITY_BASE/fifo_n1.vhd" - -set MUX_BASE "$OFM_PATH/comp/base/logic/mux" -set PIPE_BASE "$OFM_PATH/comp/base/misc/pipe" -set SDP_DISTMEM_BASE "$OFM_PATH/comp/base/mem/gen_lutram/compatibility" -set N_ONE_BASE "$OFM_PATH/comp/base/logic/n_one" -set BARREL_SHIFTER_BASE "$OFM_PATH/comp/base/logic/barrel_shifter" - - -set COMPONENTS [ list \ - [ list "GEN_MUX" $MUX_BASE "FULL" ] \ - [ list "GEN_MUX_ONEHOT" $MUX_BASE "FULL" ] \ - [ list "PIPE" $PIPE_BASE "FULL" ] \ - [ list "SDP_DISTMEM" $SDP_DISTMEM_BASE "behavioral" ] \ - [ list "N_ONE" $N_ONE_BASE "FULL" ] \ - [ list "BARREL_SHIFTER_GEN" $BARREL_SHIFTER_BASE "FULL" ] \ - ] - -set PACKAGES "$PACKAGES $MATH_PKG/math_pack.vhd" -set PACKAGES "$PACKAGES $MATH_PKG/type_pack.vhd" diff --git a/comp/base/fifo/fifo_n1/fifo_n1.vhd b/comp/base/fifo/fifo_n1/fifo_n1.vhd deleted file mode 100644 index c6d89e19e..000000000 --- a/comp/base/fifo/fifo_n1/fifo_n1.vhd +++ /dev/null @@ -1,686 +0,0 @@ --- fifo_n1.vhd: FIFO - m x n bit with multiple write ports --- - synchronous read/write --- Copyright (C) 2017 CESNET --- Author(s): Vaclav Hummel vaclav.hummel@cesnet.cz --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.math_pack.all; -use work.type_pack.all; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture behavioral of FIFO_N1 is - - -- Pipeline 0 signals ------------------------------------------------------ - -- Input pipe - signal pipe0_in_dst_rdy : std_logic; - signal pipe0_out_deser : std_logic_vector(WRITE_PORTS*DATA_WIDTH+WRITE_PORTS-1 downto 0); - signal pipe0_data_out_deser : std_logic_vector(WRITE_PORTS*DATA_WIDTH-1 downto 0); - signal pipe0_data_out : slv_array_t(0 to WRITE_PORTS-1)(DATA_WIDTH-1 downto 0); - signal pipe0_data_we : std_logic_vector(WRITE_PORTS-1 downto 0); - signal pipe0_out_src_rdy : std_logic; - signal pipe0_out_src_rdy_slv: std_logic_vector(0 downto 0); - signal pipe0_out_dst_rdy : std_logic; - - -- Pipeline 1 signals ------------------------------------------------------ - -- Sum of WE - signal sum_we : std_logic_vector(log2(WRITE_PORTS+1)-1 downto 0); - - -- N-one detector - signal n_one_addrs : slv_array_t(0 to WRITE_PORTS-1)(max(log2(WRITE_PORTS),1)-1 downto 0); - signal n_one_addrs_vld : std_logic_vector(WRITE_PORTS-1 downto 0); - - -- Data registers - signal reg1_sum_we : std_logic_vector(log2(WRITE_PORTS+1)-1 downto 0); - signal reg1_n_one_addrs : slv_array_t(0 to WRITE_PORTS-1)(max(log2(WRITE_PORTS),1)-1 downto 0); - signal reg1_data : slv_array_t(0 to WRITE_PORTS-1)(DATA_WIDTH-1 downto 0); - signal reg1_we : std_logic_vector(WRITE_PORTS-1 downto 0); - - -- Control registers - signal reg1_vld : std_logic; - signal reg1_empty : std_logic; - - -- Pipeline 2 signals ------------------------------------------------------ - -- Input multiplexer - signal in_mux_sel : slv_array_t(0 to WRITE_PORTS-1)(max(log2(WRITE_PORTS),1)-1 downto 0); - signal in_mux_sel_deser : std_logic_vector(WRITE_PORTS*max(log2(WRITE_PORTS),1)-1 downto 0); - signal in_mux_out : slv_array_t(0 to WRITE_PORTS-1)(DATA_WIDTH-1 downto 0); - - -- Memory WE - signal reg2_memory_we_in : std_logic_vector(WRITE_PORTS-1 downto 0); - signal reg2_memory_we_shifted : std_logic_vector(WRITE_PORTS-1 downto 0); - - -- Memory selection counter - signal memory_sel_sum : std_logic_vector(log2(2*WRITE_PORTS)-1 downto 0); - signal memory_sel_sum_ov : std_logic_vector(max(log2(WRITE_PORTS),1)-1 downto 0); - signal memory_sel_sum_ov_ext : std_logic_vector(max(log2(WRITE_PORTS+1),1)-1 downto 0); - signal cnt2_memory_sel_ov : std_logic; - - -- Data registers - signal reg2_sum_we : std_logic_vector(log2(WRITE_PORTS+1)-1 downto 0); - signal reg2_in_mux_out : slv_array_t(0 to WRITE_PORTS-1)(DATA_WIDTH-1 downto 0); - signal reg2_memory_we : std_logic_vector(WRITE_PORTS-1 downto 0); - signal cnt2_memory_sel : std_logic_vector(max(log2(WRITE_PORTS),1)-1 downto 0); - - -- Control registers - signal reg2_vld : std_logic; - signal reg2_empty : std_logic; - - -- Pipeline 3 signals ------------------------------------------------------ - -- Memory - signal cnt3_memory_wr_pointer : slv_array_t(0 to WRITE_PORTS-1)(log2(ITEMS)-1 downto 0); - signal memory_full : std_logic; - signal memory_empty : std_logic; - - -- Free space counter - signal cnt3_free_space : std_logic_vector(log2(WRITE_PORTS*ITEMS+1)-1 downto 0); - - -- Control registers - signal reg3_vld : std_logic; - signal reg3_empty : std_logic; - - -- Pipeline 4 signals ------------------------------------------------------ - -- Output data path - signal out_mux_in : slv_array_t(0 to WRITE_PORTS-1)(DATA_WIDTH-1 downto 0); - signal out_mux_sel : std_logic_vector(max(log2(WRITE_PORTS),1)-1 downto 0); - signal out_mux_out : std_logic_vector(DATA_WIDTH-1 downto 0); - - -- Read pointer - signal cnt4_memory_rd_pointer_low : std_logic_vector(max(log2(WRITE_PORTS),1)-1 downto 0); - signal cnt4_memory_rd_pointer_high : std_logic_vector(log2(ITEMS)-1 downto 0); - - -- Output pipe - signal pipe4_in_dst_rdy : std_logic; - signal pipe4_out_src_rdy : std_logic; - signal reg4_empty_slv : std_logic_vector(0 downto 0); - -begin --- ---------------------------------------------------------------------------- --- Pipeline 0 --- ---------------------------------------------------------------------------- - - fifo_n1g: if WRITE_PORTS /= 1 generate - - -- Input Pipe - pipe0_i: entity work.pipe - generic map( - DEVICE => DEVICE, - DATA_WIDTH => WRITE_PORTS*DATA_WIDTH+WRITE_PORTS, - USE_OUTREG => true, - FAKE_PIPE => not DI_PIPE - ) - port map( - -- Common interface ----------------------------------------------------- - CLK => CLK, - RESET => RESET, - - -- Input interface ------------------------------------------------------ - IN_DATA => slv_array_ser(DATA_IN, WRITE_PORTS, DATA_WIDTH) & WE, - IN_SRC_RDY => or (WE), - IN_DST_RDY => pipe0_in_dst_rdy, - - -- Output interface ----------------------------------------------------- - OUT_DATA => pipe0_out_deser, - OUT_SRC_RDY => pipe0_out_src_rdy, - OUT_DST_RDY => pipe0_out_dst_rdy - ); - - FULL <= not pipe0_in_dst_rdy; - - pipe0_data_out_deser <= pipe0_out_deser(WRITE_PORTS*DATA_WIDTH+WRITE_PORTS-1 downto WRITE_PORTS); - pipe0_data_out <= slv_array_to_deser(pipe0_data_out_deser, WRITE_PORTS, DATA_WIDTH); - pipe0_data_we <= pipe0_out_deser(WRITE_PORTS-1 downto 0); - - --- ---------------------------------------------------------------------------- --- Pipeline 1 --- ---------------------------------------------------------------------------- - - -- Sum of WE - sum_wep: process(pipe0_data_we) - variable a : unsigned(max(log2(WRITE_PORTS+1),1)-1 downto 0); - begin - a := (others => '0'); - for i in 0 to WRITE_PORTS-1 loop - a := a + unsigned(pipe0_data_we(i downto i)); - end loop; - sum_we <= std_logic_vector(a); - end process; - - -- N-one detector - n_oneg: for i in 0 to WRITE_PORTS-1 generate - n_onei: entity work.N_ONE - generic map( - --! \brief Data width of input vector - DATA_WIDTH => WRITE_PORTS - ) - port map( - - --! \name Clock & reset interface - --! -------------------------------------------------------------------------- - --! \brief Common clock - CLK => CLK, - --! \brief Common reset - RESET => RESET, - - --! \name Input vector - --! -------------------------------------------------------------------------- - D => pipe0_data_we, - - --! \name N one number - --! ------------------------------------------------------------------------- - N => std_logic_vector(to_unsigned(i, max(log2(WRITE_PORTS),1))), - - --! \name Output address - --! -------------------------------------------------------------------------- - A => n_one_addrs(i), - --! \brief Valid bit - VLD => n_one_addrs_vld(i) - - ); - end generate; - - -- Control register - reg1_vldp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - reg1_vld <= '0'; - elsif (reg1_empty = '1') then - reg1_vld <= pipe0_out_src_rdy; - end if; - end if; - end process; - - reg1_empty <= (not reg1_vld) or reg2_empty; - pipe0_out_dst_rdy <= reg1_empty; - - -- Register - reg1_sum_wep: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (reg1_empty = '1') then - reg1_sum_we <= sum_we; - end if; - end if; - end process; - - -- Register - reg1_n_one_addrsp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (reg1_empty = '1') then - reg1_n_one_addrs <= n_one_addrs; - end if; - end if; - end process; - - -- Register - reg1_data_inp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (reg1_empty = '1') then - reg1_data <= pipe0_data_out; - end if; - end if; - end process; - - -- Register - reg1_wep: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (reg1_empty = '1') then - reg1_we <= pipe0_data_we; - end if; - end if; - end process; - --- ---------------------------------------------------------------------------- --- Pipeline 2 --- ---------------------------------------------------------------------------- - -- Input multiplexer ------------------------------------------------------- - in_muxg: for i in 0 to WRITE_PORTS-1 generate - in_muxi: entity work.GEN_MUX - generic map( - DATA_WIDTH => DATA_WIDTH, - MUX_WIDTH => WRITE_PORTS - ) - port map( - DATA_IN => slv_array_ser(reg1_data, WRITE_PORTS, DATA_WIDTH), - SEL => in_mux_sel(i), - DATA_OUT => in_mux_out(i) - ); - end generate; - - -- Input multiplexer selection process - barrel_shifteri: entity work.BARREL_SHIFTER_GEN - generic map( - -- input/output data width in BLOCKs - BLOCKS => WRITE_PORTS, - -- size of one block in bits - BLOCK_SIZE => max(log2(WRITE_PORTS),1), - -- NOTE: data_width = blocks*block_size - - -- set true to shift left, false to shift right - SHIFT_LEFT => true - ) - port map( - DATA_IN => slv_array_ser(reg1_n_one_addrs, WRITE_PORTS, (max(log2(WRITE_PORTS),1))), - DATA_OUT => in_mux_sel_deser, - SEL => cnt2_memory_sel - ); - - in_mux_sel <= slv_array_to_deser(in_mux_sel_deser, WRITE_PORTS, (max(log2(WRITE_PORTS),1))); - - -- Memory WE - reg2_memory_we_ing: for i in 0 to WRITE_PORTS-1 generate - reg2_memory_we_in(i) <= '1' when (i < to_integer(unsigned(reg1_sum_we))) else - '0'; - end generate; - - barrel_shifter_wei: entity work.BARREL_SHIFTER_GEN - generic map( - -- input/output data width in BLOCKs - BLOCKS => WRITE_PORTS, - -- size of one block in bits - BLOCK_SIZE => 1, - -- NOTE: data_width = blocks*block_size - - -- set true to shift left, false to shift right - SHIFT_LEFT => true - ) - port map( - DATA_IN => reg2_memory_we_in, - DATA_OUT => reg2_memory_we_shifted, - SEL => cnt2_memory_sel - ); - - -- Control register - reg2_vldp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - reg2_vld <= '0'; - elsif (reg2_empty = '1') then - reg2_vld <= reg1_vld; - end if; - end if; - end process; - - reg2_empty <= (not reg2_vld) or reg3_empty; - - -- Memory selection counter, counter mod WRITE_PORTS - memory_sel_sum <= std_logic_vector(to_unsigned(to_integer(unsigned(cnt2_memory_sel)) + - to_integer(unsigned(reg1_sum_we)), log2(2*WRITE_PORTS))); - - memory_sel_sum_ov_ext <= std_logic_vector(unsigned(cnt2_memory_sel) + unsigned(reg1_sum_we) - to_unsigned(WRITE_PORTS, max(log2(WRITE_PORTS+1),1))); - memory_sel_sum_ov <= memory_sel_sum_ov_ext(max(log2(WRITE_PORTS),1)-1 downto 0); - - cnt2_memory_sel_ov <= '1' when (to_integer(unsigned(memory_sel_sum)) >= WRITE_PORTS) else - '0'; - - cnt2_memory_selp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt2_memory_sel <= std_logic_vector(to_unsigned(0, max(log2(WRITE_PORTS),1))); - elsif (reg2_empty = '1' and reg1_vld = '1') then - if (cnt2_memory_sel_ov = '1') then - cnt2_memory_sel <= memory_sel_sum_ov(max(log2(WRITE_PORTS),1)-1 downto 0); - else - cnt2_memory_sel <= memory_sel_sum(max(log2(WRITE_PORTS),1)-1 downto 0); - end if; - end if; - end if; - end process; - - -- Register - reg_in_mux_outp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (reg2_empty = '1') then - reg2_in_mux_out <= in_mux_out; - end if; - end if; - end process; - - -- Register - reg2_memory_wep: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (reg2_empty = '1') then - reg2_memory_we <= reg2_memory_we_shifted; - end if; - end if; - end process; - - -- Register - reg2_sum_wep: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (reg2_empty = '1') then - reg2_sum_we <= reg1_sum_we; - end if; - end if; - end process; - --- ---------------------------------------------------------------------------- --- Pipeline 3 --- ---------------------------------------------------------------------------- - - -- Memory ------------------------------------------------------------------ - memoryg: for i in 0 to WRITE_PORTS-1 generate - memoryi : entity work.SDP_DISTMEM - generic map ( - DATA_WIDTH => DATA_WIDTH, - ITEMS => ITEMS - ) - port map ( - WCLK => CLK, - ADDRA => cnt3_memory_wr_pointer(i), - DI => reg2_in_mux_out(i), - WE => reg2_memory_we(i) and reg2_vld and reg3_empty, - ADDRB => cnt4_memory_rd_pointer_high, - DOB => out_mux_in(i) - ); - end generate; - - - -- Write interface --------------------------------------------------------- - -- Free space counter - cnt3_free_spacep: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt3_free_space <= std_logic_vector(to_unsigned(WRITE_PORTS*ITEMS, log2(WRITE_PORTS*ITEMS+1))); - else - cnt3_free_space <= std_logic_vector(to_unsigned(to_integer(unsigned(cnt3_free_space)) - to_integer(unsigned(reg2_sum_we and reg2_vld and reg3_empty)) + - to_integer(unsigned(reg4_empty_slv and reg3_vld)), log2(WRITE_PORTS*ITEMS+1))); - end if; - end if; - end process; - - -- FULL signal - memory_full <= '1' when(to_integer(unsigned(cnt3_free_space)) < to_integer(unsigned(reg2_sum_we))) else - '0'; - reg3_empty <= not memory_full; - - -- AFULL signal - AFULL <= '1' when(to_integer(unsigned(cnt3_free_space)) < ALMOST_FULL_OFFSET) else - '0'; - -- EMPTY signal - memory_empty <= '1' when(to_integer(unsigned(cnt3_free_space)) = WRITE_PORTS*ITEMS) else - '0'; - reg3_vld <= not memory_empty; - -- AEMPTY signal - AEMPTY <= '1' when(to_integer(unsigned(cnt3_free_space)) > WRITE_PORTS*ITEMS-ALMOST_EMPTY_OFFSET) else - '0'; - - -- Write pointers - cnt3_memory_wr_pointerg: for i in 0 to WRITE_PORTS-1 generate - cnt3_memory_wr_pointerp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt3_memory_wr_pointer(i) <= (others => '0'); - elsif (reg2_memory_we(i) = '1' and reg2_vld = '1' and reg3_empty = '1') then - if (to_integer(unsigned(cnt3_memory_wr_pointer(i))) = ITEMS-1) then - cnt3_memory_wr_pointer(i) <= (others => '0'); - else - cnt3_memory_wr_pointer(i) <= std_logic_vector(unsigned(cnt3_memory_wr_pointer(i)) + to_unsigned(1,1)); - end if; - end if; - end if; - end process; - end generate; - --- ---------------------------------------------------------------------------- --- Pipeline 4 --- ---------------------------------------------------------------------------- - - -- Read interface ---------------------------------------------------------- - - -- Output multiplexer - out_muxi: entity work.GEN_MUX - generic map( - DATA_WIDTH => DATA_WIDTH, - MUX_WIDTH => WRITE_PORTS - ) - port map( - DATA_IN => slv_array_ser(out_mux_in, WRITE_PORTS, DATA_WIDTH), - SEL => out_mux_sel, - DATA_OUT => out_mux_out - ); - - - -- Read pointer low - cnt4_memory_rd_pointer_lowp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt4_memory_rd_pointer_low <= (others => '0'); - elsif (reg3_vld = '1' and pipe4_in_dst_rdy = '1') then - if (to_integer(unsigned(cnt4_memory_rd_pointer_low)) = WRITE_PORTS-1) then - cnt4_memory_rd_pointer_low <= (others => '0'); - else - cnt4_memory_rd_pointer_low <= std_logic_vector(unsigned(cnt4_memory_rd_pointer_low) + to_unsigned(1,1)); - end if; - end if; - end if; - end process; - - out_mux_sel <= cnt4_memory_rd_pointer_low; - - -- Read pointer high - cnt4_memory_rd_pointer_highp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt4_memory_rd_pointer_high <= (others => '0'); - elsif (reg3_vld = '1' and pipe4_in_dst_rdy = '1' and to_integer(unsigned(cnt4_memory_rd_pointer_low)) = WRITE_PORTS-1) then - if (to_integer(unsigned(cnt4_memory_rd_pointer_high)) = ITEMS-1) then - cnt4_memory_rd_pointer_high <= (others => '0'); - else - cnt4_memory_rd_pointer_high <= std_logic_vector(unsigned(cnt4_memory_rd_pointer_high) + to_unsigned(1,1)); - end if; - end if; - end if; - end process; - - -- Output Pipe - pipe4_i: entity work.pipe - generic map( - DEVICE => DEVICE, - DATA_WIDTH => DATA_WIDTH, - USE_OUTREG => true, - FAKE_PIPE => not DO_PIPE - ) - port map( - -- Common interface ----------------------------------------------------- - CLK => CLK, - RESET => RESET, - - -- Input interface ------------------------------------------------------ - IN_DATA => out_mux_out, - IN_SRC_RDY => reg3_vld, - IN_DST_RDY => pipe4_in_dst_rdy, - - -- Output interface ----------------------------------------------------- - OUT_DATA => DATA_OUT, - OUT_SRC_RDY => pipe4_out_src_rdy, - OUT_DST_RDY => RE - ); - - EMPTY <= not pipe4_out_src_rdy; - reg4_empty_slv(0) <= pipe4_in_dst_rdy; - - end generate; - - fifo_11g: if WRITE_PORTS = 1 generate - --- Input Pipe - pipe0_i: entity work.pipe - generic map( - DEVICE => DEVICE, - DATA_WIDTH => WRITE_PORTS*DATA_WIDTH+WRITE_PORTS, - USE_OUTREG => true, - FAKE_PIPE => not DI_PIPE - ) - port map( - -- Common interface ----------------------------------------------------- - CLK => CLK, - RESET => RESET, - - -- Input interface ------------------------------------------------------ - IN_DATA => slv_array_ser(DATA_IN, WRITE_PORTS, DATA_WIDTH) & WE, - IN_SRC_RDY => or (WE), - IN_DST_RDY => pipe0_in_dst_rdy, - - -- Output interface ----------------------------------------------------- - OUT_DATA => pipe0_out_deser, - OUT_SRC_RDY => pipe0_out_src_rdy, - OUT_DST_RDY => reg3_empty - ); - - pipe0_out_src_rdy_slv(0) <= pipe0_out_src_rdy; - - FULL <= not pipe0_in_dst_rdy; - - pipe0_data_out_deser <= pipe0_out_deser(WRITE_PORTS*DATA_WIDTH+WRITE_PORTS-1 downto WRITE_PORTS); - pipe0_data_out <= slv_array_to_deser(pipe0_data_out_deser, WRITE_PORTS, DATA_WIDTH); - pipe0_data_we <= pipe0_out_deser(WRITE_PORTS-1 downto 0); - --- ---------------------------------------------------------------------------- --- Pipeline 3 --- ---------------------------------------------------------------------------- - - -- Memory ------------------------------------------------------------------ - memoryg: for i in 0 to WRITE_PORTS-1 generate - memoryi : entity work.SDP_DISTMEM - generic map ( - DATA_WIDTH => DATA_WIDTH, - ITEMS => ITEMS - ) - port map ( - WCLK => CLK, - ADDRA => cnt3_memory_wr_pointer(i), - DI => pipe0_data_out(i), - WE => pipe0_out_src_rdy and reg3_empty, - ADDRB => cnt4_memory_rd_pointer_high, - DOB => out_mux_in(i) - ); - end generate; - - -- Write interface --------------------------------------------------------- - -- Free space counter - cnt3_free_spacep: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt3_free_space <= std_logic_vector(to_unsigned(WRITE_PORTS*ITEMS, log2(WRITE_PORTS*ITEMS+1))); - else - cnt3_free_space <= std_logic_vector(to_unsigned(to_integer(unsigned(cnt3_free_space)) - to_integer(unsigned(pipe0_out_src_rdy_slv and reg3_empty)) + - to_integer(unsigned(reg4_empty_slv and reg3_vld)), log2(WRITE_PORTS*ITEMS+1))); - end if; - end if; - end process; - - -- FULL signal - memory_full <= '1' when(to_integer(unsigned(cnt3_free_space)) = 0) else - '0'; - reg3_empty <= not memory_full; - - -- AFULL signal - AFULL <= '1' when(to_integer(unsigned(cnt3_free_space)) < ALMOST_FULL_OFFSET) else - '0'; - -- EMPTY signal - memory_empty <= '1' when(to_integer(unsigned(cnt3_free_space)) = WRITE_PORTS*ITEMS) else - '0'; - reg3_vld <= not memory_empty; - - -- AEMPTY signal - AEMPTY <= '1' when(to_integer(unsigned(cnt3_free_space)) > WRITE_PORTS*ITEMS-ALMOST_EMPTY_OFFSET) else - '0'; - - -- Write pointers - cnt3_memory_wr_pointerg: for i in 0 to WRITE_PORTS-1 generate - cnt3_memory_wr_pointerp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt3_memory_wr_pointer(i) <= (others => '0'); - elsif (pipe0_out_src_rdy_slv(i) = '1' and reg3_empty = '1') then - if (to_integer(unsigned(cnt3_memory_wr_pointer(i))) = ITEMS-1) then - cnt3_memory_wr_pointer(i) <= (others => '0'); - else - cnt3_memory_wr_pointer(i) <= std_logic_vector(unsigned(cnt3_memory_wr_pointer(i)) + to_unsigned(1,1)); - end if; - end if; - end if; - end process; - end generate; - --- ---------------------------------------------------------------------------- --- Pipeline 4 --- ---------------------------------------------------------------------------- - - -- Read interface ---------------------------------------------------------- - - -- Read pointer high - cnt4_memory_rd_pointer_highp: process(CLK) - begin - if (CLK'event and CLK = '1') then - if (RESET = '1') then - cnt4_memory_rd_pointer_high <= (others => '0'); - elsif (reg3_vld = '1' and pipe4_in_dst_rdy = '1') then - if (to_integer(unsigned(cnt4_memory_rd_pointer_high)) = ITEMS-1) then - cnt4_memory_rd_pointer_high <= (others => '0'); - else - cnt4_memory_rd_pointer_high <= std_logic_vector(unsigned(cnt4_memory_rd_pointer_high) + to_unsigned(1,1)); - end if; - end if; - end if; - end process; - - -- Output Pipe - pipe4_i: entity work.pipe - generic map( - DEVICE => DEVICE, - DATA_WIDTH => DATA_WIDTH, - USE_OUTREG => true, - FAKE_PIPE => not DO_PIPE - ) - port map( - -- Common interface ----------------------------------------------------- - CLK => CLK, - RESET => RESET, - - -- Input interface ------------------------------------------------------ - IN_DATA => slv_array_ser(out_mux_in, WRITE_PORTS, DATA_WIDTH), - IN_SRC_RDY => reg3_vld, - IN_DST_RDY => pipe4_in_dst_rdy, - - -- Output interface ----------------------------------------------------- - OUT_DATA => DATA_OUT, - OUT_SRC_RDY => pipe4_out_src_rdy, - OUT_DST_RDY => RE - ); - - EMPTY <= not pipe4_out_src_rdy; - reg4_empty_slv(0) <= pipe4_in_dst_rdy; - - end generate; - - -end architecture behavioral; diff --git a/comp/base/fifo/fifo_n1/fifo_n1_ent.vhd b/comp/base/fifo/fifo_n1/fifo_n1_ent.vhd deleted file mode 100644 index c26a256f8..000000000 --- a/comp/base/fifo/fifo_n1/fifo_n1_ent.vhd +++ /dev/null @@ -1,80 +0,0 @@ --- fifo_n1.vhd: FIFO_N1 - m x n bit with multiple write ports --- - synchronous read/write --- Copyright (C) 2017 CESNET --- Author(s): Vaclav Hummel vaclav.hummel@cesnet.cz --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- --- TODO: --- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.math_pack.all; -use work.type_pack.all; - --- ---------------------------------------------------------------------------- --- Description --- ---------------------------------------------------------------------------- --- Multiple write ports, single read port FIFO. Uses SDP distmem. WE may be --- set at any bit - the component always finds set WE bit at any position. LSB --- WE item is first in and first out. - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity FIFO_N1 is - generic ( - -- Number of independent write ports - WRITE_PORTS : integer := 1; - -- Set data width here - DATA_WIDTH : integer := 23; - -- Set number of items per ONE memory - -- Total size equals to WRITE_PORTS*ITEMS - ITEMS : integer := 32; - - ALMOST_FULL_OFFSET : integer := 16; - ALMOST_EMPTY_OFFSET : integer := 16; - - DI_PIPE : boolean := false; - DO_PIPE : boolean := false; - - DEVICE : string := "7SERIES" - ); - port( - -- Global clock signal - CLK : in std_logic; - -- Global reset signal - RESET : in std_logic; - - -- =============== - -- Write interface - -- =============== - - -- Data input - DATA_IN : in slv_array_t(0 to WRITE_PORTS-1)(DATA_WIDTH-1 downto 0); - -- Write request - WE : in std_logic_vector(WRITE_PORTS-1 downto 0); - -- FIFO is full - FULL : out std_logic; - -- FIFO is almost full (see ALMOST_FULL_OFFSET) - AFULL : out std_logic; - - -- =============== - -- Read interface - -- =============== - - -- Data output - DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0); - -- Read request - RE : in std_logic; - -- FIFO is empty - EMPTY : out std_logic; - -- FIFO is almost empty (see ALMOST_EMPTY_OFFSET) - AEMPTY : out std_logic - ); -end entity; diff --git a/comp/base/fifo/fifo_n1/sim/fifo_n1.fdo b/comp/base/fifo/fifo_n1/sim/fifo_n1.fdo deleted file mode 100644 index 50bbafd97..000000000 --- a/comp/base/fifo/fifo_n1/sim/fifo_n1.fdo +++ /dev/null @@ -1,25 +0,0 @@ -# fifo_n1.fdo: Functional simulation file for fifo_n1 -# Copyright (C) 2017 CESNET -# Author: Vaclav Hummel -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -set FIRMWARE_BASE "../../../../.." - -set FIFO_N1_BASE "$OFM_PATH/comp/base/fifo/fifo_n1" -set MATH_PKG_BASE "$OFM_PATH/comp/base/pkg" - -set SIG_FILE "$FIFO_N1_BASE/sim/fifo_n1_sig.fdo" -set TB_FILE "$FIFO_N1_BASE/sim/testbench.vhd" - - -set COMPONENTS [list \ - [ list "fifo_n1" $FIFO_N1_BASE "behavioral" ] \ - [ list "MATH_PKG" $MATH_PKG_BASE "MATH" ] \ -] - -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -nb_sim_run 4us diff --git a/comp/base/fifo/fifo_n1/sim/fifo_n1_sig.fdo b/comp/base/fifo/fifo_n1/sim/fifo_n1_sig.fdo deleted file mode 100644 index 49b269876..000000000 --- a/comp/base/fifo/fifo_n1/sim/fifo_n1_sig.fdo +++ /dev/null @@ -1,30 +0,0 @@ -# fifo_n1_sig.fdo : Include file with signals -# Copyright (C) 2017 CESNET -# Author: Vaclav Hummel -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -# Paths -set FIFO_N1_PATH "/testbench/uut" -set TB_PATH "/testbench" - -source "signals.fdo" - -add wave -divider "" -add wave -divider "TB internals" -add wave -divider "" -tb_internals "$TB_PATH" "" - -add wave -divider "" -add wave -divider "FIFO_N1 ports" -add wave -divider "" -fifo_n1_ports "$FIFO_N1_PATH" "" - -add wave -divider "" -add wave -divider "FIFO_N1 internals" -add wave -divider "" -fifo_n1_internals "$FIFO_N1_PATH" "" - - diff --git a/comp/base/fifo/fifo_n1/sim/signals.fdo b/comp/base/fifo/fifo_n1/sim/signals.fdo deleted file mode 100644 index f04f48b05..000000000 --- a/comp/base/fifo/fifo_n1/sim/signals.fdo +++ /dev/null @@ -1,112 +0,0 @@ -# signals.fdo : Include file with signals -# Copyright (C) 2017 CESNET -# Author: Vaclav Hummel -# -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ - -proc tb_internals { PATH GROUP } { - eval "add wave $GROUP -divider {Control signals}" - add_wave "$GROUP -noupdate -hex -label fifo_src_rdy" $PATH/fifo_src_rdy - add_wave "$GROUP -noupdate -hex -label fifo_we" $PATH/fifo_we -} - -proc fifo_n1_ports { PATH GROUP } { - eval "add wave $GROUP -divider {Synchronization}" - add_wave "$GROUP -noupdate -hex -label CLK -color yellow" $PATH/CLK - add_wave "$GROUP -noupdate -hex -label RST -color yellow" $PATH/RESET - - eval "add wave $GROUP -divider {Write interface}" - add_wave "$GROUP -noupdate -hex -label DATA_IN" $PATH/DATA_IN - add_wave "$GROUP -noupdate -hex -label WE" $PATH/WE - add_wave "$GROUP -noupdate -hex -label FULL" $PATH/FULL - add_wave "$GROUP -noupdate -hex -label AFULL" $PATH/AFULL - - eval "add wave $GROUP -divider {Read interface}" - add_wave "$GROUP -noupdate -hex -label DATA_OUT" $PATH/DATA_OUT - add_wave "$GROUP -noupdate -hex -label RE" $PATH/RE - add_wave "$GROUP -noupdate -hex -label EMPTY" $PATH/EMPTY - add_wave "$GROUP -noupdate -hex -label AEMPTY" $PATH/AEMPTY - -} - -proc fifo_n1_internals { PATH GROUP } { - - eval "add wave $GROUP -divider {Input pipe}" - add_wave "$GROUP -noupdate -hex -label pipe0_in_dst_rdy" $PATH/pipe0_in_dst_rdy - add_wave "$GROUP -noupdate -hex -label pipe0_out_deser" $PATH/pipe0_out_deser - add_wave "$GROUP -noupdate -hex -label pipe0_data_out_deser" $PATH/pipe0_data_out_deser - add_wave "$GROUP -noupdate -hex -label pipe0_data_out" $PATH/pipe0_data_out - add_wave "$GROUP -noupdate -hex -label pipe0_data_we" $PATH/pipe0_data_we - add_wave "$GROUP -noupdate -hex -label pipe0_out_src_rdy" $PATH/pipe0_out_src_rdy - add_wave "$GROUP -noupdate -hex -label pipe0_out_dst_rdy" $PATH/pipe0_out_dst_rdy - - eval "add wave $GROUP -divider {Sum of WE}" - add_wave "$GROUP -noupdate -hex -label sum_we" $PATH/sum_we - - eval "add wave $GROUP -divider {N-one detector}" - add_wave "$GROUP -noupdate -hex -label n_one_addrs" $PATH/n_one_addrs - add_wave "$GROUP -noupdate -hex -label n_one_addrs_vld" $PATH/n_one_addrs_vld - - eval "add wave $GROUP -divider {Data registers}" - add_wave "$GROUP -noupdate -hex -label reg1_sum_we" $PATH/reg1_sum_we - add_wave "$GROUP -noupdate -hex -label reg1_n_one_addrs" $PATH/reg1_n_one_addrs - add_wave "$GROUP -noupdate -hex -label reg1_data" $PATH/reg1_data - add_wave "$GROUP -noupdate -hex -label reg1_we" $PATH/reg1_we - - eval "add wave $GROUP -divider {Control registers}" - add_wave "$GROUP -noupdate -hex -label reg1_vld" $PATH/reg1_vld - add_wave "$GROUP -noupdate -hex -label reg1_empty" $PATH/reg1_empty - - eval "add wave $GROUP -divider {Input multiplexer}" - add_wave "$GROUP -noupdate -hex -label in_mux_sel" $PATH/in_mux_sel - add_wave "$GROUP -noupdate -hex -label in_mux_sel_deser" $PATH/in_mux_sel_deser - add_wave "$GROUP -noupdate -hex -label in_mux_out" $PATH/in_mux_out - - eval "add wave $GROUP -divider {Memory WE}" - add_wave "$GROUP -noupdate -hex -label reg2_memory_we_in" $PATH/reg2_memory_we_in - add_wave "$GROUP -noupdate -hex -label reg2_memory_we_shifted" $PATH/reg2_memory_we_shifted - - eval "add wave $GROUP -divider {Memory selection counter}" - add_wave "$GROUP -noupdate -hex -label memory_sel_sum" $PATH/memory_sel_sum - add_wave "$GROUP -noupdate -hex -label memory_sel_sum_ov" $PATH/memory_sel_sum_ov - add_wave "$GROUP -noupdate -hex -label cnt2_memory_sel_ov" $PATH/cnt2_memory_sel_ov - - eval "add wave $GROUP -divider {Data registers}" - add_wave "$GROUP -noupdate -hex -label reg2_sum_we" $PATH/reg2_sum_we - add_wave "$GROUP -noupdate -hex -label reg2_in_mux_out" $PATH/reg2_in_mux_out - add_wave "$GROUP -noupdate -hex -label reg2_memory_we" $PATH/reg2_memory_we - add_wave "$GROUP -noupdate -hex -label cnt2_memory_sel" $PATH/cnt2_memory_sel - - eval "add wave $GROUP -divider {Control registers}" - add_wave "$GROUP -noupdate -hex -label reg2_vld" $PATH/reg2_vld - add_wave "$GROUP -noupdate -hex -label reg2_empty" $PATH/reg2_empty - - eval "add wave $GROUP -divider {Memory}" - add_wave "$GROUP -noupdate -hex -label cnt3_memory_wr_pointer" $PATH/cnt3_memory_wr_pointer - add_wave "$GROUP -noupdate -hex -label memory_full" $PATH/memory_full - add_wave "$GROUP -noupdate -hex -label memory_empty" $PATH/memory_empty - - eval "add wave $GROUP -divider {Free space counter}" - add_wave "$GROUP -noupdate -hex -label cnt3_free_space" $PATH/cnt3_free_space - - eval "add wave $GROUP -divider {Control registers}" - add_wave "$GROUP -noupdate -hex -label reg3_vld" $PATH/reg3_vld - add_wave "$GROUP -noupdate -hex -label reg3_empty" $PATH/reg3_empty - - eval "add wave $GROUP -divider {Output data path}" - add_wave "$GROUP -noupdate -hex -label out_mux_in" $PATH/out_mux_in - add_wave "$GROUP -noupdate -hex -label out_mux_sel" $PATH/out_mux_sel - add_wave "$GROUP -noupdate -hex -label out_mux_out" $PATH/out_mux_out - - eval "add wave $GROUP -divider {Read pointer}" - add_wave "$GROUP -noupdate -hex -label cnt4_memory_rd_pointer_low" $PATH/cnt4_memory_rd_pointer_low - add_wave "$GROUP -noupdate -hex -label cnt4_memory_rd_pointer_high" $PATH/cnt4_memory_rd_pointer_high - - eval "add wave $GROUP -divider {Output pipe}" - add_wave "$GROUP -noupdate -hex -label pipe4_in_dst_rdy" $PATH/pipe4_in_dst_rdy - add_wave "$GROUP -noupdate -hex -label pipe4_out_src_rdy" $PATH/pipe4_out_src_rdy - add_wave "$GROUP -noupdate -hex -label reg4_empty_slv" $PATH/reg4_empty_slv -} - diff --git a/comp/base/fifo/fifo_n1/sim/testbench.vhd b/comp/base/fifo/fifo_n1/sim/testbench.vhd deleted file mode 100644 index 71153311f..000000000 --- a/comp/base/fifo/fifo_n1/sim/testbench.vhd +++ /dev/null @@ -1,337 +0,0 @@ --- testbench.vhd: Testbench for fifo_n1 --- Copyright (C) 2017 CESNET --- Author(s): Vaclav Hummel --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; - -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; -use work.math_pack.all; -use work.type_pack.all; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- - -entity testbench is -end entity testbench; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- - -architecture behavioral of testbench is - - -- Constants declaration --------------------------------------------------- - -- Synchronization - constant C_CLK_PER : time := 5.0 ns; - constant C_RST_TIME : time := 10 * C_CLK_PER + 1 ns; - - -- Number of independent write ports - constant WRITE_PORTS : integer := 5; - -- Set data width here - constant DATA_WIDTH : integer := 8; - -- Set number of items per ONE memory - -- Total size equals to WRITE_PORTS*ITEMS - constant ITEMS : integer := 4; - - constant ALMOST_FULL_OFFSET : integer := 8; - constant ALMOST_EMPTY_OFFSET : integer := 8; - - - -- Synchronization - signal clk : std_logic; - signal rst : std_logic; - - -- Write interface - signal fifo_data_in : slv_array_t(0 to WRITE_PORTS-1)(DATA_WIDTH-1 downto 0); -- Data input - signal fifo_src_rdy : std_logic; - signal fifo_we : std_logic_vector(WRITE_PORTS-1 downto 0); -- Write request - signal fifo_full : std_logic; -- FIFO is full - signal fifo_afull : std_logic; -- FIFO is almost full (see ALMOST_FULL_OFFSET) - - -- Read interface - signal fifo_data_out : std_logic_vector(DATA_WIDTH-1 downto 0); -- Data output - signal fifo_re : std_logic; -- Read request - signal fifo_empty : std_logic; -- FIFO is empty - signal fifo_aempty : std_logic; -- FIFO is almost empty (see ALMOST_EMPTY_OFFSET) - - - --- ---------------------------------------------------------------------------- --- Architecture body --- ---------------------------------------------------------------------------- - -begin - - -- ------------------------------------------------------------------------- - -- CROSSBAR SCHEDULER planner - -- ------------------------------------------------------------------------- - - uut: entity work.fifo_n1 - generic map( - -- Number of independent write ports - WRITE_PORTS => WRITE_PORTS, - -- Set data width here - DATA_WIDTH => DATA_WIDTH, - -- Set number of items per ONE memory - -- Total size equals to WRITE_PORTS*ITEMS - ITEMS => ITEMS, - - ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET, - ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET - - ) - port map( - CLK => clk, - RESET => rst, - - -- Write interface - DATA_IN => fifo_data_in, - WE => fifo_we and fifo_src_rdy, - FULL => fifo_full, - AFULL => fifo_afull, - - -- Read interface - DATA_OUT => fifo_data_out, - RE => fifo_re, - EMPTY => fifo_empty, - AEMPTY => fifo_aempty - ); - - -- ------------------------------------------------------------------------- - -- clk and reset generators - -- ------------------------------------------------------------------------- - - -- generating clk - clk_gen: process - begin - clk <= '1'; - wait for C_CLK_PER / 2; - clk <= '0'; - wait for C_CLK_PER / 2; - end process clk_gen; - - -- generating reset - rst_gen: process - begin - rst <= '1'; - wait for C_RST_TIME; - rst <= '0'; - wait; - end process rst_gen; - - -- ------------------------------------------------------------------------- - -- src_rdy and dst_rdy process - -- ------------------------------------------------------------------------- - - src_dstp: process - variable seed1 : positive := DATA_WIDTH; - variable seed2 : positive := WRITE_PORTS; - - variable rand : real; - variable a : integer; - begin - wait for C_CLK_PER - 1 ns; - uniform(seed1, seed2, rand); - a := integer(rand*1.0); - fifo_src_rdy <= '1' when (a = 1) else '0'; - - uniform(seed1, seed2, rand); - a := integer(rand*1.0); - fifo_re <= '1' when (a = 1) else '0'; - - wait for 1 ns; - end process; - -- ------------------------------------------------------------------------- - -- Testbench process - -- ------------------------------------------------------------------------- - - tb: process - begin - -- Wait for the reset - - fifo_data_in(0) <= "00000000"; - fifo_data_in(1) <= "00000000"; - fifo_data_in(2) <= "00000000"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00000000"; - - fifo_we <= "00000"; - - wait until rst = '0'; - wait for C_CLK_PER - 2 ns; - - -- Write - fifo_data_in(0) <= "00000001"; - fifo_data_in(1) <= "00000010"; - fifo_data_in(2) <= "00000011"; - fifo_data_in(3) <= "00000100"; - fifo_data_in(4) <= "00000101"; - - fifo_we <= "11111"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00000110"; - fifo_data_in(1) <= "00000000"; - fifo_data_in(2) <= "00000000"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00000000"; - - fifo_we <= "00001"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00000000"; - fifo_data_in(1) <= "00000111"; - fifo_data_in(2) <= "00000000"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00000000"; - - fifo_we <= "00010"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00000000"; - fifo_data_in(1) <= "00000000"; - fifo_data_in(2) <= "00000000"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00001000"; - - fifo_we <= "10000"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00001001"; - fifo_data_in(1) <= "00000000"; - fifo_data_in(2) <= "00000000"; - fifo_data_in(3) <= "00001010"; - fifo_data_in(4) <= "00001011"; - - fifo_we <= "11001"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00000000"; - fifo_data_in(1) <= "00001100"; - fifo_data_in(2) <= "00001101"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00001110"; - - fifo_we <= "10110"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00001111"; - fifo_data_in(1) <= "00000000"; - fifo_data_in(2) <= "00010000"; - fifo_data_in(3) <= "00010001"; - fifo_data_in(4) <= "00010010"; - - fifo_we <= "11101"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00010011"; - fifo_data_in(1) <= "00010100"; - fifo_data_in(2) <= "00010101"; - fifo_data_in(3) <= "00010110"; - fifo_data_in(4) <= "00000000"; - - fifo_we <= "01111"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - for i in 0 to 18-1 loop - -- No write - fifo_data_in(0) <= "00000000"; - fifo_data_in(1) <= "00000000"; - fifo_data_in(2) <= "00000000"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00000000"; - - fifo_we <= "00000"; - - wait for 1 ns; - wait for C_CLK_PER - 1 ns; - end loop; - - -- Write - fifo_data_in(0) <= "00010111"; - fifo_data_in(1) <= "00011000"; - fifo_data_in(2) <= "00011001"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00011010"; - - fifo_we <= "10111"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - -- Write - fifo_data_in(0) <= "00011011"; - fifo_data_in(1) <= "00011100"; - fifo_data_in(2) <= "00011101"; - fifo_data_in(3) <= "00000000"; - fifo_data_in(4) <= "00011110"; - - fifo_we <= "10111"; - - wait for 1 ns; - if (fifo_full = '1' or fifo_src_rdy = '0') then - wait until ((clk'event and clk = '1') and fifo_full = '0' and fifo_src_rdy = '1'); - end if; - wait for C_CLK_PER - 1 ns; - - wait; - end process; -end architecture behavioral; diff --git a/comp/base/fifo/fifo_n1/synth/Makefile b/comp/base/fifo/fifo_n1/synth/Makefile deleted file mode 100644 index 8ce92ff0d..000000000 --- a/comp/base/fifo/fifo_n1/synth/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Makefile: Makefile to compile module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=FIFO_N1 - -.PHONY: all -all: comp - -include ../../../../../build/Makefile diff --git a/comp/base/fifo/multi_fifo/Modules.tcl b/comp/base/fifo/multi_fifo/Modules.tcl deleted file mode 100644 index f87c44924..000000000 --- a/comp/base/fifo/multi_fifo/Modules.tcl +++ /dev/null @@ -1,16 +0,0 @@ -# Modules.tcl: Components include script -# Copyright (C) 2020 CESNET z. s. p. o. -# Author(s): Daniel Kříž -# -# SPDX-License-Identifier: BSD-3-Clause - -# Paths to components -set SDP_MEMX_BASE "$OFM_PATH/comp/base/mem/sdp_memx" - -# Components -set COMPONENTS [concat $COMPONENTS [list \ - [ list "SDP_MEMX" $SDP_MEMX_BASE "FULL" ] \ -]] - -# Source files for implemented component -set MOD "$MOD $ENTITY_BASE/multi_fifo.vhd" diff --git a/comp/base/fifo/multi_fifo/multi_fifo.vhd b/comp/base/fifo/multi_fifo/multi_fifo.vhd deleted file mode 100644 index 9b890450b..000000000 --- a/comp/base/fifo/multi_fifo/multi_fifo.vhd +++ /dev/null @@ -1,229 +0,0 @@ --- multi_fifo.vhd: Universal FIFO with multiple channels memory --- Copyright (C) 2020 CESNET z. s. p. o. --- Author(s): Daniel Kříž --- --- SPDX-License-Identifier: BSD-3-Clause - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.math_pack.all; -use work.type_pack.all; - --- README: --- This component is a universal FIFO with multiple channels. --- The FIFO is parametrically implemented in MEMX memory. --- Number of channels is generic. - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- - -entity MULTI_FIFO is - generic( - -- Data word width in bits. - DATA_WIDTH : natural := 64; - -- FIFO depth, number of data words - ITEMS : natural := 512; - -- Number of channels - CHANNELS : natural := 64 - - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - -- ======================================================================= - -- WRITE INTERFACE - -- ======================================================================= - RX_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - RX_CH : in std_logic_vector(log2(CHANNELS)-1 downto 0); - -- Write enable - RX_WR : in std_logic; - -- FIFO is full, react without latency - RX_FULL : out std_logic; - - -- ======================================================================= - -- READ INTERFACE - -- ======================================================================= - -- When TX_RD is set TX_RD = '1', valid data are read from FIFO - TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0); - TX_CH : in std_logic_vector(log2(CHANNELS)-1 downto 0); - -- Data on TX_DATA were read - TX_RD : in std_logic; - -- FIFO is empty, react without latency - TX_EMPTY : out std_logic; - - -- ======================================================================= - -- CLEAR INTERFACE - -- ======================================================================= - -- This signal clear FIFO - CLR : in std_logic_vector(CHANNELS-1 downto 0) - ); -end entity; - --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- - -architecture FULL of MULTI_FIFO is - - -- Write address pointer - signal wr_addr_ptr : slv_array_t(CHANNELS-1 downto 0)(log2(ITEMS+1)-1 downto 0); - signal wr_addr_ptr_en : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); - -- Read address pointer - signal rd_addr_ptr : slv_array_t(CHANNELS-1 downto 0)(log2(ITEMS+1)-1 downto 0); - signal rd_addr_ptr_en : std_logic_vector(CHANNELS-1 downto 0); - -- Full statement - signal full_i : std_logic_vector(CHANNELS-1 downto 0); - -- Empty statement - signal ptr_eq : std_logic_vector(CHANNELS-1 downto 0); - -- Data from memory - signal mem_out : std_logic_vector(DATA_WIDTH-1 downto 0); - -- When mem_vld = '1' then data from memory are valid (FIFO is not empty) - signal mem_vld : std_logic_vector(CHANNELS-1 downto 0); - -- Data in storage register - signal data_reg : slv_array_t(CHANNELS-1 downto 0)(DATA_WIDTH-1 downto 0); - -- Valid signal of storage register - signal reg_vld : std_logic_vector(CHANNELS-1 downto 0); - -- When data_out_vld = '1' then memory output data or register output data are valid - signal data_out_vld : std_logic_vector(CHANNELS-1 downto 0); - signal read_reg : std_logic_vector(CHANNELS-1 downto 0); - -- Is asserted when there are valid data (FIFO is not empty) and read is requested - signal read_internal : std_logic_vector(CHANNELS-1 downto 0); - -- Channels convert to integer - signal tx_ch_int : natural; - signal rx_ch_int : natural; - -begin - --- ---------------------------------------------------------------------------- --- MEMX MEMORY GENERATION --- ---------------------------------------------------------------------------- - memx_i : entity work.SDP_MEMX - generic map( - DATA_WIDTH => DATA_WIDTH, - ITEMS => CHANNELS*ITEMS, - OUTPUT_REG => false - ) - port map( - CLK => CLK, - RESET => RESET, - - WR_DATA => RX_DATA, - WR_ADDR => RX_CH & wr_addr_ptr(rx_ch_int)(log2(ITEMS)-1 downto 0), - WR_EN => wr_addr_ptr_en(rx_ch_int), - - RD_DATA => mem_out, - RD_ADDR => TX_CH & rd_addr_ptr(tx_ch_int)(log2(ITEMS)-1 downto 0), - RD_PIPE_EN => '1' - ); - - tx_ch_int <= to_integer(unsigned(TX_CH)); - rx_ch_int <= to_integer(unsigned(RX_CH)); - - -- Data at memory or in register are valid - TX_EMPTY <= not data_out_vld(tx_ch_int); - RX_FULL <= full_i(rx_ch_int); - - -- Set read_internal when output data are not valid or read is set - -- This proccess calculate counter enables and data valid signal - read_internal_gen : for i in CHANNELS-1 downto 0 generate - read_internal(i) <= '1' when ((TX_RD = '1' or data_out_vld(i) = '0') and (unsigned(TX_CH) = i or CHANNELS < 2) and CLR(i) = '0') else '0'; - rd_addr_ptr_en(i) <= (read_internal(i) and not ptr_eq(i)); - wr_addr_ptr_en(i) <= '1' when ((RX_WR = '1' and full_i(i) = '0') and (unsigned(RX_CH) = i or CHANNELS < 2)) else '0'; - data_out_vld(i) <= mem_vld(i) or reg_vld(i); - end generate ; - - -- mem_vld = '1' when data at memory are valid - mem_vld_reg_p : process (CLK) - begin - if (rising_edge(CLK)) then - for i in CHANNELS-1 downto 0 loop - if(RESET = '1') then - mem_vld(i) <= '0'; - end if; - mem_vld(i) <= '1' when ((ptr_eq(i) = '0') and (unsigned(TX_CH) = i or CHANNELS < 2)) else '0'; - end loop; - end if; - end process; - - -- Register for read statement - read_vld_reg_p : process (CLK) - begin - if (rising_edge(CLK)) then - for i in CHANNELS-1 downto 0 loop - read_reg(i) <= read_internal(i); - end loop; - end if; - end process; - - -- Storage register (Is used when read in previous clock drop and in memory are valid data) - strg_reg_p : process (CLK) - begin - if (rising_edge(CLK)) then - for i in CHANNELS-1 downto 0 loop - if (RESET = '1' or read_internal(i) = '1' or CLR(i) = '1') then - reg_vld(i) <= '0'; - elsif ((read_internal(i) /= read_reg(i)) and mem_vld(i) = '1' and read_internal(i) = '0') then - reg_vld(i) <= '1'; - data_reg(i) <= mem_out; - end if; - end loop; - end if; - end process; - - -- Input counter (Count write requests) - wr_addr_cnt_p : process (CLK) -- Input address incrementation - begin - if (rising_edge(CLK)) then - for i in CHANNELS-1 downto 0 loop - if (RESET = '1' or CLR(i) = '1') then - wr_addr_ptr(i) <= (others => '0'); - elsif (wr_addr_ptr_en(i) = '1') then - wr_addr_ptr(i) <= std_logic_vector(unsigned(wr_addr_ptr(i)) + 1); - end if; - end loop; - end if; - end process; - - -- Output counter (count read requests) - rd_addr_cnt_p : process (CLK) -- Output address incrementation - begin - if (rising_edge(CLK)) then - for i in CHANNELS-1 downto 0 loop - if (RESET = '1' or CLR(i) = '1') then - rd_addr_ptr(i) <= (others => '0'); - elsif (rd_addr_ptr_en(i) = '1') then - rd_addr_ptr(i) <= std_logic_vector(unsigned(rd_addr_ptr(i)) + 1); - end if; - end loop; - end if; - end process; - - -- When upper bits are not same and lower bits are same, then full statement is set to log 1 - comp_full_p : process (all) - begin - for i in CHANNELS-1 downto 0 loop - full_i(i) <= '0'; - if (wr_addr_ptr(i)(log2(ITEMS)) /= rd_addr_ptr(i)(log2(ITEMS)) and wr_addr_ptr(i)(log2(ITEMS)-1 downto 0 ) = rd_addr_ptr(i)(log2(ITEMS)-1 downto 0 )) then - full_i(i) <= '1'; - end if; - end loop; - end process; - - -- When upper and lower bits are same, then empty statement is set to log 0 - comp_empty_p : process (all) - begin - for i in CHANNELS-1 downto 0 loop - ptr_eq(i) <= '1'; - if (not (wr_addr_ptr(i)(log2(ITEMS)) = rd_addr_ptr(i)(log2(ITEMS)) and wr_addr_ptr(i)(log2(ITEMS)-1 downto 0 ) = rd_addr_ptr(i)(log2(ITEMS)-1 downto 0 ))) then - ptr_eq(i) <= '0'; - end if; - end loop; - end process; - - TX_DATA <= mem_out when (reg_vld(tx_ch_int) = '0') else data_reg(tx_ch_int); - -end architecture; diff --git a/comp/base/fifo/multi_fifo/synth/Makefile b/comp/base/fifo/multi_fifo/synth/Makefile deleted file mode 100644 index 36b6e9ca0..000000000 --- a/comp/base/fifo/multi_fifo/synth/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# Makefile: Makefile script to compile specified module -# Copyright (C) 2019 CESNET z. s. p. o. -# Author(s):Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=MULTI_FIFO -#SYNTH=quartus - -export CLK_PERIOD=2.0 -#export DEVICE=STRATIX10 - -all: comp - -include ../../../../../build/Makefile - -.PHONY: all diff --git a/comp/base/fifo/multi_fifo/ver/Modules.tcl b/comp/base/fifo/multi_fifo/ver/Modules.tcl deleted file mode 100644 index 975ff9c41..000000000 --- a/comp/base/fifo/multi_fifo/ver/Modules.tcl +++ /dev/null @@ -1,21 +0,0 @@ -# Modules.tcl: Components include script -# Copyright (C) 2020 CESNET z. s. p. o. -# Author(s): Daniel Kříž -# -# SPDX-License-Identifier: BSD-3-Clause - -# Set paths - -# Paths to components -set PKG_BASE "$OFM_PATH/comp/base/pkg" -set PACKAGES "$PACKAGES $PKG_BASE/math_pack.vhd" -set PACKAGES "$PACKAGES $PKG_BASE/type_pack.vhd" -set PACKAGES "$PACKAGES $PKG_BASE/dma_bus_pack.vhd" - -# Packages -set PACKAGES "$PACKAGES $OFM_PATH/comp/ver/vhdl_ver_tools/basics/basics_test_pkg.vhd" - -# Components -set COMPONENTS [concat $COMPONENTS [list \ - [ list "DUT" ".." "FULL" ] \ -]] diff --git a/comp/base/fifo/multi_fifo/ver/signals.fdo b/comp/base/fifo/multi_fifo/ver/signals.fdo deleted file mode 100644 index 792ca0b2c..000000000 --- a/comp/base/fifo/multi_fifo/ver/signals.fdo +++ /dev/null @@ -1,9 +0,0 @@ -# signals.fdo: Include file with signals -# Copyright (C) 2020 CESNET z. s. p. o. -# Author(s): Daniel Kříž -# -# SPDX-License-Identifier: BSD-3-Clause - -proc all {NAME PATH} { - add_wave "-group {$NAME} -noupdate -hex" $PATH/* -} diff --git a/comp/base/fifo/multi_fifo/ver/sim.fdo b/comp/base/fifo/multi_fifo/ver/sim.fdo deleted file mode 100644 index 297425b3c..000000000 --- a/comp/base/fifo/multi_fifo/ver/sim.fdo +++ /dev/null @@ -1,28 +0,0 @@ -# sim.fdo: Simulation script -# Copyright (C) 2020 CESNET z. s. p. o. -# Author(s): Daniel Kříž -# -# SPDX-License-Identifier: BSD-3-Clause - -# For whole design testing -set FIRMWARE_BASE "../../../../.." -set COMP_BASE "$FIRMWARE_BASE/comp" -set DUT_BASE "." - -set TB_FILE "./testbench.vhd" -set SIG_FILE "./sim_sig.fdo" - -# Modules definition -set COMPONENTS [list [list "DUT" $DUT_BASE "SIM"]] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run - -config wave -signalnamewidth 1 diff --git a/comp/base/fifo/multi_fifo/ver/sim_sig.fdo b/comp/base/fifo/multi_fifo/ver/sim_sig.fdo deleted file mode 100644 index 145270fc3..000000000 --- a/comp/base/fifo/multi_fifo/ver/sim_sig.fdo +++ /dev/null @@ -1,27 +0,0 @@ -# sim_sig.fdo : Include file with signals -# Copyright (C) 2020 CESNET z. s. p. o. -# Author(s): Daniel Kříž -# -# SPDX-License-Identifier: BSD-3-Clause - -# Paths -set TB_PATH "/testbench" - -# include signals -source "signals.fdo" - -puts "Numeric Std Warnings - Disabled" -set NumericStdNoWarnings 1 - -all TOP $TB_PATH/uut -all MEMX $TB_PATH/uut/memx_i -all testbench $TB_PATH -add_wave "-group {testbench} -noupdate -hex" $TB_PATH/fifo -#all testbench $TB_PATH/fifo_read_p -#all AVST2AXICQ $TB_PATH/pcie_avst2axicq_i -#all AXI2MI $TB_PATH/axi2mi_i -#all mi_int_i $TB_PATH/axi2mi_i/mi_int_i -#all cc_int_i $TB_PATH/axi2mi_i/cc_int_i -#all AXICC2AVST $TB_PATH/pcie_axicc2avst_i - -wave zoomrange 0 1000ns diff --git a/comp/base/fifo/multi_fifo/ver/testbench.vhd b/comp/base/fifo/multi_fifo/ver/testbench.vhd deleted file mode 100644 index 26f364b5f..000000000 --- a/comp/base/fifo/multi_fifo/ver/testbench.vhd +++ /dev/null @@ -1,235 +0,0 @@ --- testbench.vhd: Testbench of universal FIFO with multiple channels memory --- Copyright (C) 2020 CESNET z. s. p. o. --- Author(s): Daniel Kříž --- --- SPDX-License-Identifier: BSD-3-Clause - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.math_pack.all; -use work.type_pack.all; -use work.basics_test_pkg.all; -use std.env.stop; - --- ---------------------------------------------------------------------------- --- Entity declaration --- ---------------------------------------------------------------------------- -entity testbench is -end entity testbench; --- ---------------------------------------------------------------------------- --- Architecture declaration --- ---------------------------------------------------------------------------- -architecture behavioral of testbench is - - constant DATA_WIDTH : natural := 4; - constant ITEMS : natural := 8; - constant CHANNELS : natural := 4; - constant CLK_PERIOD : time := 10 ns; - constant K_W : natural := 70; - constant K_R : natural := 50; - constant VER_LENGTH : natural := 400; - constant VER_LENGTH_ENHC : natural := VER_LENGTH + ITEMS*CHANNELS+2; - - signal clk : std_logic; - signal rst : std_logic; - - signal rx_data : std_logic_vector(DATA_WIDTH-1 downto 0); - signal rx_ch : std_logic_vector(log2(CHANNELS)-1 downto 0); - signal rx_wr : std_logic; - signal rx_full : std_logic; - signal set_read : std_logic := '0'; - - signal tx_data : std_logic_vector(DATA_WIDTH-1 downto 0); - signal tx_rd : std_logic; - signal tx_ch : std_logic_vector(log2(CHANNELS)-1 downto 0); - signal tx_empty : std_logic; - - signal clr : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); - signal clr_reg : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); - signal asyn_clr : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); - - signal rx_data_reg : std_logic_vector(DATA_WIDTH-1 downto 0); - signal rx_ch_reg : integer := 0; - signal rx_wr_reg : std_logic; - signal rx_full_reg : std_logic; - - signal tx_empty_reg : std_logic; - signal tx_rd_reg : std_logic; - signal tx_data_reg : std_logic_vector(DATA_WIDTH-1 downto 0); - signal tx_ch_reg : integer := 0; - - shared variable seed1 : positive := 4; - shared variable seed2 : positive := 4; - shared variable X : integer; - shared variable tmp_data : std_logic_vector(DATA_WIDTH-1 downto 0); - - shared variable fifo : slv_fifo_array_t(CHANNELS-1 downto 0) - (fifo (ITEMS*2-1 downto 0)(DATA_WIDTH-1 downto 0)) := (others => - (fifo => (others => (others => 'U')), - fill => 0, - full => '0', - empty => '1', - fill_max => 0, - fill_sum => 0, - fill_num => 0)); - -begin - - uut : entity work.MULTI_FIFO - generic map ( - DATA_WIDTH => DATA_WIDTH, - ITEMS => ITEMS, - CHANNELS => CHANNELS - ) - port map( - CLK => clk, - RESET => rst, - - RX_DATA => rx_data, - RX_CH => rx_ch, - RX_WR => rx_wr, - RX_FULL => rx_full, - - TX_DATA => tx_data, - TX_CH => tx_ch, - TX_RD => tx_rd, - TX_EMPTY => tx_empty, - - CLR => asyn_clr - ); - - -- generate clk - clock_p : process - begin - for i in (VER_LENGTH_ENHC+4) downto 0 loop - clk <= '1'; - wait for CLK_PERIOD/2; - clk <= '0'; - wait for CLK_PERIOD/2; - end loop; - wait; - end process; - --- Clear FIFO at the end of the verification - fifo_emptying_p : process - begin - wait for VER_LENGTH*CLK_PERIOD; - set_read <= '1'; - wait for (ITEMS*CHANNELS+4)*CLK_PERIOD; - report "All items from fifo were successfully read"; - report "Verification finished successfully!"; - stop; - end process; - - -- generate rst - reset_p : process - begin - rst <= '1'; - wait for 3*CLK_PERIOD + 1 ns; - rst <= '0'; - wait; - end process; - --- Write data to verification FIFO and compare them with actual data in Multi FIFO - fifo_put_p : process(clk) - begin - if (rising_edge(clk)) then - if (rx_wr_reg = '1' and rx_full_reg = '0') then - slv_fifo_put(fifo(rx_ch_reg), rx_data_reg); - end if; - if (tx_rd_reg = '1' and tx_empty_reg = '0') then - slv_fifo_pop(fifo(tx_ch_reg), tmp_data); - if (tmp_data /= tx_data_reg) then - report "expected data " & integer'image(to_integer(unsigned(tmp_data))) & " received data " & integer'image(to_integer(unsigned(tx_data_reg))) severity failure; - end if; - end if; - end if; - end process; - --- Generate signals for verification and write them to Multi FIFO memory - fifo_write_p : process(clk) - begin - if (rising_edge(clk)) then - rx_ch <= random_vector(log2(CHANNELS), seed1); - randint(seed1, seed2, 0, 99, X); - if (X < K_W) then - rx_wr <= '1'; - else - rx_wr <= '0'; - end if; - rx_data <= random_vector(DATA_WIDTH, seed1); - rx_wr_reg <= rx_wr and not rst; - rx_full_reg <= rx_full; - rx_data_reg <= rx_data; - rx_ch_reg <= to_integer(unsigned(rx_ch)); - tx_ch_reg <= to_integer(unsigned(tx_ch)); - if (rst = '1') then - for i in CHANNELS-1 downto 0 loop - slv_fifo_new(fifo(i)); - end loop; - end if; - if (set_read = '1') then - rx_wr <= '0'; - end if; - end if; - end process; - --- Generate read and channel signal for verification - fifo_read_p : process(clk) - begin - if (rising_edge(clk)) then - tx_ch <= random_vector(log2(CHANNELS), seed1); - randint(seed1, seed2, 0, 99, X); - if (X < K_R) then - tx_rd <= '1'; - else - tx_rd <= '0'; - end if; - tx_data_reg <= tx_data; - tx_rd_reg <= tx_rd; - tx_empty_reg <= tx_empty; - if (clr_reg(to_integer(unsigned(tx_ch))) = '1') then - tx_empty_reg <= '1'; - end if; - if(set_read = '1') then - tx_ch <= std_logic_vector(unsigned(tx_ch)+1); - tx_rd <= '1'; - end if; - end if; - end process; - --- Generate clear signal - asyn_clear_p : process(all) - begin - asyn_clr <= clr; - if (rx_wr_reg = '1') then - asyn_clr(rx_ch_reg) <= '0'; - end if; - if (tx_rd_reg = '1') then - asyn_clr(tx_ch_reg) <= '0'; - end if; - end process; - - reg_clr_p : process(clk) - begin - if (rising_edge(clk)) then - clr <= random_vector(CHANNELS, seed1); - clr_reg <= asyn_clr; - end if; - end process; - --- Clear verification FIFO when clear is set - fifo_clr_p : process(clk) - begin - if (rising_edge(clk)) then - for i in CHANNELS-1 downto 0 loop - if(clr_reg(i) = '1') then - slv_fifo_new(fifo(i)); - end if; - end loop; - end if; - end process; - -end architecture behavioral; diff --git a/comp/debug/inspector/Modules.tcl b/comp/debug/inspector/Modules.tcl deleted file mode 100644 index a90391f4b..000000000 --- a/comp/debug/inspector/Modules.tcl +++ /dev/null @@ -1,21 +0,0 @@ -# Modules.tcl: Modules.tcl script to compile all design -# Copyright (C) 2016 CESNET -# Author: Martin Spinler -# -# SPDX-License-Identifier: BSD-3-Clause - - -# PACKAGES: -set PACKAGES "$PACKAGES $OFM_PATH/comp/base/pkg/math_pack.vhd" - -set DSP "$OFM_PATH/comp/base/dsp/dsp_counter" - -set COMPONENTS [list \ - [list "DSP" $DSP "FULL"] \ -] - -# MODULES: -if { $ARCHGRP == "FULL" } { - set MOD "$MOD $ENTITY_BASE/inspector_pkg.vhd" - set MOD "$MOD $ENTITY_BASE/inspector.vhd" -} diff --git a/comp/debug/inspector/inspector.vhd b/comp/debug/inspector/inspector.vhd deleted file mode 100644 index eaf2a1e9b..000000000 --- a/comp/debug/inspector/inspector.vhd +++ /dev/null @@ -1,238 +0,0 @@ --- inspector.vhd: debugger and analyser --- Copyright (C) 2016 CESNET --- Author(s): Martin Spinler --- --- SPDX-License-Identifier: BSD-3-Clause --- - -library IEEE; -use IEEE.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.math_pack.all; -use work.inspector_pkg.all; - -entity INSPECTOR is -generic ( - DEVICE : string := "ULTRASCALE"; - ENABLE : boolean := true; - IOBJ_COUNT : integer := 0; - - inspector_objects : t_inspector_objects_int := (0 => IOBJ_RESET, 1 => IOBJ_STROBE, others => IOBJ_NONE); - inspector_histogram_bucket_count : t_inspector_objects_int := (others => 0); - inspector_object_group : t_inspector_objects_int := (others => 0) - ); -port ( - --! \name CLOCK and RESET - CLK : in std_logic; - RESET : in std_logic; - - INPUT : in t_inspector_inputs (IOBJ_COUNT-1 downto 0); - OUTPUT : out t_inspector_outputs(IOBJ_COUNT-1 downto 0); - - --! \name MI32 interface - MI_DWR : in std_logic_vector(31 downto 0); - MI_ADDR : in std_logic_vector(31 downto 0); - MI_RD : in std_logic; - MI_WR : in std_logic; - MI_BE : in std_logic_vector(3 downto 0); - MI_DRD : out std_logic_vector(31 downto 0); - MI_ARDY : out std_logic := '0'; - MI_DRDY : out std_logic := '0' -); -end entity; - -architecture full of INSPECTOR is - - type t_object_mi_drd is array(IOBJ_COUNT-1 downto 0) of std_logic_vector(31 downto 0); - - signal object_mi_drd : t_object_mi_drd; - signal reg_input : t_inspector_inputs(IOBJ_COUNT-1 downto 0); - - signal mi_object : std_logic_vector(IOBJ_COUNT-1 downto 0); - signal group_reset : std_logic_vector(31 downto 0); - signal group_strobe : std_logic_vector(31 downto 0); - -begin - - reg_inputp : process(CLK) - begin - if(CLK'event and CLK = '1') then - reg_input <= INPUT; - end if; - end process; - - MI_ARDY <= MI_RD or MI_WR; - MI_DRDY <= MI_RD; - MI_DRD <= object_mi_drd(conv_integer(MI_ADDR(log2(IOBJ_COUNT)+2 downto 3))); - - gen_enable: if (ENABLE) generate - - addrdec_p: process(MI_ADDR, MI_WR) - begin - mi_object <= (others => '0'); - for i in 0 to IOBJ_COUNT-1 loop - if(i = MI_ADDR(log2(IOBJ_COUNT)+2 downto 3)) then - mi_object(i) <= '1'; - end if; - end loop; - end process; - - inspector_objects_gen : for i in 0 to IOBJ_COUNT-1 generate - - gen_reset : if(inspector_objects(i) = IOBJ_RESET) generate - reg_resetp : process(CLK) - begin - if(CLK'event and CLK = '1') then - if(mi_object(i) = '1' and MI_WR = '1') then - group_reset <= MI_DWR; - else - group_reset <= (others => '0'); - end if; - end if; - end process; - end generate; - - gen_strobe : if(inspector_objects(i) = IOBJ_STROBE) generate - reg_strobep : process(CLK) - begin - if(CLK'event and CLK = '1') then - if(mi_object(i) = '1' and MI_WR = '1') then - group_strobe <= MI_DWR; - else - group_strobe <= (others => '0'); - end if; - end if; - end process; - end generate; - - gen_outputreg : if(inspector_objects(i) = IOBJ_OUTPUTREG) generate - reg_outregp : process(CLK) - begin - if(CLK'event and CLK = '1') then - if(mi_object(i) = '1' and MI_WR = '1') then - if(MI_ADDR(2) = '1') then - OUTPUT(i).outputreg(63 downto 32) <= MI_DWR; - else - OUTPUT(i).outputreg(31 downto 0) <= MI_DWR; - end if; - end if; - end if; - end process; - end generate; - - gen_inputreg : if(inspector_objects(i) = IOBJ_INPUTREG) generate - signal inspector_inputreg_int : std_logic_vector(63 downto 0); - begin - object_mi_drd(i) <= inspector_inputreg_int(63 downto 32) when MI_ADDR(2) = '1' else - inspector_inputreg_int(31 downto 0); - reg_outregp : process(CLK) - begin - if(CLK'event and CLK = '1') then - if(reg_input(i).inputreg_we = '1') then - inspector_inputreg_int <= reg_input(i).inputreg; - end if; - end if; - end process; - end generate; - - gen_counter : if(inspector_objects(i) = IOBJ_COUNTER) generate - signal inspector_counter_reg : std_logic_vector(47 downto 0); - signal inspector_counter_value : std_logic_vector(47 downto 0); - signal inspector_counter_add : std_logic_vector(26 downto 0); - begin - - object_mi_drd(i) <= X"0000" & inspector_counter_reg(47 downto 32) when MI_ADDR(2) = '1' else - inspector_counter_reg(31 downto 0); - - inspector_counter_add <= conv_std_logic_vector(reg_input(i).counter_inc, 27); - - counter_i : entity work.DSP_COUNTER - generic map( - DEVICE => DEVICE, - INPUT_REGS => true , - INPUT_WIDTH => 27 , -- Maximum supported value - OUTPUT_WIDTH => 48 , - DSP_ENABLE => true - ) - port map( - CLK => CLK, - CLK_EN => reg_input(i).counter_ce, - RESET => group_reset(inspector_object_group(i)), - INCREMENT => inspector_counter_add, - MAX_VAL => (others => '1'), - RESULT => inspector_counter_value - ); - - reg_strobep : process(CLK) - begin - if(CLK'event and CLK = '1') then - if(group_strobe(inspector_object_group(i)) = '1') then - inspector_counter_reg <= inspector_counter_value; - end if; - end if; - end process; - end generate; - - gen_histogram : if(inspector_objects(i) = IOBJ_HISTOGRAM) generate - signal histogram_select : std_logic_vector(inspector_histogram_bucket_count(i)-1 downto 0); - signal histogram_select_ce : std_logic_vector(inspector_histogram_bucket_count(i)-1 downto 0); - signal histogram_select_mi : std_logic_vector(log2(inspector_histogram_bucket_count(i))-1 downto 0); - - type t_inspector_histogram_bucket_reg is array(inspector_histogram_bucket_count(i)-1 downto 0) of std_logic_vector(47 downto 0); - signal histogram_bucket_reg : t_inspector_histogram_bucket_reg; - signal histogram_bucket_value : t_inspector_histogram_bucket_reg; - - begin - object_mi_drd(i) <= X"0000" & histogram_bucket_reg(conv_integer(histogram_select_mi))(47 downto 32) when MI_ADDR(2) = '1' else - histogram_bucket_reg(conv_integer(histogram_select_mi))(31 downto 0); - - reg_bucketaddrp : process(CLK) - begin - if(CLK'event and CLK = '1') then - if(mi_object(i) = '1' and MI_WR = '1') then - histogram_select_mi <= MI_DWR(log2(inspector_histogram_bucket_count(i))-1 downto 0); - end if; - end if; - end process; - - gen_histogram_buckets : for j in 0 to inspector_histogram_bucket_count(i)-1 generate - signal ce : std_logic; - begin - ce <= '1' when reg_input(i).histogram_ce = '1' and reg_input(i).histogram_bucket = j else '0'; - - counter_i : entity work.DSP_COUNTER - generic map( - DEVICE => DEVICE, - INPUT_REGS => true , - INPUT_WIDTH => 1 , - OUTPUT_WIDTH => 48 , - DSP_ENABLE => true - ) - port map( - CLK => CLK, - CLK_EN => ce , - RESET => group_reset(inspector_object_group(i)), - INCREMENT => (others => '1'), - MAX_VAL => (others => '1'), - RESULT => histogram_bucket_value(j) - ); - - reg_histogramregp : process(CLK) - begin - if(CLK'event and CLK = '1') then - if(group_strobe(inspector_object_group(i)) = '1') then - histogram_bucket_reg(j) <= histogram_bucket_value(j); - end if; - end if; - end process; - - end generate; - - end generate; - - end generate; - - end generate; -end architecture; diff --git a/comp/debug/inspector/inspector_pkg.vhd b/comp/debug/inspector/inspector_pkg.vhd deleted file mode 100644 index d1342677f..000000000 --- a/comp/debug/inspector/inspector_pkg.vhd +++ /dev/null @@ -1,52 +0,0 @@ --- inspector_pkg.vhd: package for debugger and analyser --- Copyright (C) 2016 CESNET --- Author(s): Martin Spinler --- --- SPDX-License-Identifier: BSD-3-Clause --- - -library IEEE; -use IEEE.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -use work.math_pack.all; - -package inspector_pkg is - - -- Specify total number of inspected values. - constant IOBJ_COUNT_MAX : integer := 128; - - -- Enum of inspector value types. - constant IOBJ_NONE : integer := 0; - constant IOBJ_RESET : integer := 1; - constant IOBJ_STROBE : integer := 2; - constant IOBJ_OUTPUTREG : integer := 3; - constant IOBJ_INPUTREG : integer := 4; - constant IOBJ_COUNTER : integer := 5; - constant IOBJ_HISTOGRAM : integer := 6; - - type t_inspector_objects_int is array(IOBJ_COUNT_MAX-1 downto 0) of integer; - - type t_inspector_input is record - inputreg : std_logic_vector(63 downto 0); - inputreg_we : std_logic; - counter_inc : integer; - counter_ce : std_logic; - histogram_bucket : integer; - histogram_ce : std_logic; - end record; - - type t_inspector_output is record - outputreg : std_logic_vector(63 downto 0); - outputreg_we : std_logic; - end record; - - type t_inspector_inputs is array (natural range <>) of t_inspector_input; - type t_inspector_outputs is array (natural range <>) of t_inspector_output; - -end inspector_pkg; - -package body inspector_pkg is - -end inspector_pkg; diff --git a/comp/mi_tools/register_array/MI_register_array.vhd b/comp/mi_tools/register_array/MI_register_array.vhd deleted file mode 100644 index 496570ded..000000000 --- a/comp/mi_tools/register_array/MI_register_array.vhd +++ /dev/null @@ -1,251 +0,0 @@ --- MI_register_array.vhd --- # Copyright (C) 2014 CESNET --- # Author: Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; -use ieee.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.math_pack.all; - ---! register data type -use work.REG_PACK.all; - -entity MI_REGISTER_ARRAY is - generic ( - --! Data width mi_data - MI_WIDTH : integer := 32; - --! MI addres data width - MI_ADDR_WIDTH : integer := 32; - --! MI pipe - MI_PIPE : boolean := true; - --! addres first register in array - --! width must be (MI_ADDR_WIDTH-1 downto 0) - constant FIRST_ADDR : std_logic_vector; - --! significant bits of the address - SIGN_BITS_ADDR : integer; - --! number of regiters - NUM_REGS : integer := 1; - --! initialization values for registers, - --! width must be (NUM_REGS*MI_WIDTH-1 downto 0) - constant INICIAL : std_logic_vector; - --! registers generic data (array) - --! range must be (1 to NUM_REGS) - --! sample connections in /sim/testbench.vhd - GENER_REGS : REG_TYPE_ARRAY; - DEVICE : string := "7SERIES" - ); - port ( - --! Clock input - CLK : in std_logic; - --! Reset input - RESET : in std_logic; - - --! MI32 input interface ------------------------------------------------- - --! Input Data - MI_DWR : in std_logic_vector(MI_WIDTH-1 downto 0); - --! addres - MI_ADDR : in std_logic_vector(MI_ADDR_WIDTH-1 downto 0); - --! Read Request - MI_RD : in std_logic; - --! Write Request - MI_WR : in std_logic; - --! Byte Enable - MI_BE : in std_logic_vector(MI_WIDTH/8-1 downto 0); - --! Output Data - MI_DRD : out std_logic_vector(MI_WIDTH-1 downto 0); - --! Address Ready - MI_ARDY : out std_logic; - --! Data Ready - MI_DRDY : out std_logic; - - --! registers Data output - REG_DATA_OUT : out std_logic_vector((NUM_REGS*MI_WIDTH)-1 downto 0); - --! MI_WR signals - REG_WR_OUT : out std_logic_vector(NUM_REGS-1 downto 0); - --! MI_RD signals - REG_RD_OUT : out std_logic_vector(NUM_REGS-1 downto 0); - --! users data input - REG_DATA_IN : in std_logic_vector((NUM_REGS*MI_WIDTH)-1 downto 0); - --! users we signal - REG_WE_IN : in std_logic_vector(NUM_REGS-1 downto 0); - --! MI_ARDY signal from extern register - REG_ARDY_IN : in std_logic_vector(NUM_REGS-1 downto 0) - ); -end MI_REGISTER_ARRAY; - -architecture full of MI_REGISTER_ARRAY is - signal dec_out : std_logic_vector(NUM_REGS-1 downto 0); - signal mux_drd_in : std_logic_vector((NUM_REGS*MI_WIDTH)-1 downto 0); - signal mux_drd_out : std_logic_vector(MI_WIDTH-1 downto 0); - signal mux_ardy_in : std_logic_vector(NUM_REGS-1 downto 0); - signal mux_ardy_out : std_logic_vector(0 downto 0); - signal mux_drdy_in : std_logic_vector(NUM_REGS-1 downto 0); - signal mux_drdy_out : std_logic_vector(0 downto 0); - - signal mi_dwr_pipe : std_logic_vector(MI_WIDTH-1 downto 0); - signal mi_addr_pipe : std_logic_vector(MI_ADDR_WIDTH-1 downto 0); - signal mi_be_pipe : std_logic_vector(MI_WIDTH/8-1 downto 0); - signal mi_rd_pipe : std_logic; - signal mi_wr_pipe : std_logic; - signal mi_ardy_pipe : std_logic; - signal mi_drd_pipe : std_logic_vector(MI_WIDTH-1 downto 0); - signal mi_drdy_pipe : std_logic; - -begin - assert (MI_ADDR'length = FIRST_ADDR'length) report "range of signal FIRST_ADDR must be (MI_ADDR_WIDTH-1 downto 0)" severity failure; - assert (INICIAL'length = NUM_REGS*MI_WIDTH) report "range of signal INICIAL must be (NUM_REGS*MI_WIDTH-1 downto 0)" severity failure; - assert (MI_ADDR'length >= SIGN_BITS_ADDR) report "SIGN_BITS_ADDR must be less or equal than MI_ADDR" severity failure; - assert (GENER_REGS'length = NUM_REGS) report "SIGN_BITS_ADDR must be less or equal than MI_ADDR" severity failure; - - --! generate mi pipe - MI_PIPE_inst : entity work.MI_PIPE - generic map ( - DATA_WIDTH => MI_WIDTH, - ADDR_WIDTH => MI_ADDR_WIDTH, - USE_OUTREG => MI_PIPE, - FAKE_PIPE => not MI_PIPE, - DEVICE => DEVICE - ) - port map ( - -- Common interface ----------------------------------------------------- - CLK => CLK, - RESET => RESET, - - -- Input MI interface --------------------------------------------------- - IN_DWR => MI_DWR, - IN_ADDR => MI_ADDR, - IN_BE => MI_BE, - IN_RD => MI_RD, - IN_WR => MI_WR, - IN_ARDY => MI_ARDY, - IN_DRD => MI_DRD, - IN_DRDY => MI_DRDY, - - -- Output MI interface -------------------------------------------------- - OUT_DWR => mi_dwr_pipe, - OUT_ADDR => mi_addr_pipe, - OUT_BE => mi_be_pipe, - OUT_RD => mi_rd_pipe, - OUT_WR => mi_wr_pipe, - OUT_ARDY => mi_ardy_pipe, - OUT_DRD => mi_drd_pipe, - OUT_DRDY => mi_drdy_pipe - ); - - --! decode addres - process(mi_addr_pipe) - begin - dec_out <= (others => '0'); - - for i in 0 to (NUM_REGS-1) loop - if (mi_addr_pipe(SIGN_BITS_ADDR-1 downto 0) = std_logic_vector(resize(unsigned(FIRST_ADDR)+(i*4),SIGN_BITS_ADDR))) then - dec_out(i) <= '1'; - end if; - end loop; - end process; - - --! generate mux MI_DRD - MUX_DRD_inst : entity work.GEN_MUX_ONEHOT - generic map( - DATA_WIDTH => MI_WIDTH, - MUX_WIDTH => NUM_REGS - ) - port map( - DATA_IN => mux_drd_in, - SEL => dec_out, - DATA_OUT => mux_drd_out - ); - - --! generate mux MI_ARDY - MUX_ARDY_inst : entity work.GEN_MUX_ONEHOT - generic map( - DATA_WIDTH => 1, - MUX_WIDTH => NUM_REGS - ) - port map( - DATA_IN => mux_ardy_in, - SEL => dec_out, - DATA_OUT => mux_ardy_out - ); - - --! generate mux MI_DRDY - MUX_DRDY_inst : entity work.GEN_MUX_ONEHOT - generic map( - DATA_WIDTH => 1, - MUX_WIDTH => NUM_REGS - ) - port map( - DATA_IN => mux_drdy_in, - SEL => dec_out, - DATA_OUT => mux_drdy_out - ); - - mi_drd_pipe <= mux_drd_out; - mi_ardy_pipe <= mux_ardy_out(0); - mi_drdy_pipe <= mux_drdy_out(0); - - --! connect registers - GEN_REGS: for I in 1 to NUM_REGS generate - begin - MI_REG_inst : entity work.MI_REG - generic map ( - --! Data width mi_data - MI_WIDTH => MI_WIDTH, - --! Register data width - DATA_WIDTH => GENER_REGS(I).DATA_WIDTH, - --! inter/exter register - INTER => GENER_REGS(I).INTER, - --! mi read enable - MI_RD_EN => GENER_REGS(I).MI_RD_EN, - --! mi write enable - MI_WR_EN => GENER_REGS(I).MI_WR_EN, - --! usr write port enable - USR_WR_EN => GENER_REGS(I).USR_WR_EN, - --! reset enable - RST_EN => GENER_REGS(I).RST_EN, - --! be enable - BE_EN => GENER_REGS(I).BE_EN, - --! nicial value - INICIAL => INICIAL, - NUM_REG => I - ) - port map ( - --! Clock input - CLK => CLK, - --! Reset input - RESET => RESET, - --! Data output - DATA_OUT => REG_DATA_OUT(MI_WIDTH-1+((I-1)*MI_WIDTH) downto (I-1)*MI_WIDTH), - --! Enable from decoder - DEC_EN => dec_out(I-1), - - --! MI32 input interface ------------------------------------------------- - --! Input Data - MI_DWR => mi_dwr_pipe, - --! Read Request - MI_RD => mi_rd_pipe, - --! Write Request - MI_WR => mi_wr_pipe, - --! Byte Enable - MI_BE => mi_be_pipe, - --! Output Data - MI_DRD => mux_drd_in(MI_WIDTH-1+((I-1)*MI_WIDTH) downto (I-1)*MI_WIDTH), - --! Address Ready - MI_ARDY => mux_ardy_in(I-1), - --! Data Ready - MI_DRDY => mux_drdy_in(I-1), - - MI_RD_OUT => REG_RD_OUT(I-1), - MI_WR_OUT => REG_WR_OUT(I-1), - USR_DATA_IN => REG_DATA_IN(MI_WIDTH-1+((I-1)*MI_WIDTH) downto (I-1)*MI_WIDTH), - USR_DATA_EN => REG_WE_IN(I-1), - EXTER_ARDY => REG_ARDY_IN(I-1) - ); - end generate GEN_REGS; -end architecture; diff --git a/comp/mi_tools/register_array/Modules.tcl b/comp/mi_tools/register_array/Modules.tcl deleted file mode 100644 index 6208d3f74..000000000 --- a/comp/mi_tools/register_array/Modules.tcl +++ /dev/null @@ -1,20 +0,0 @@ -# Modules.tcl: Local include tcl script -# Copyright (C) 2014 CESNET -# Author: Mario Kuka -# -# SPDX-License-Identifier: BSD-3-Clause - -set PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd" -set MUX "$OFM_PATH/comp/base/logic/mux" -set MI_PIPE "$ENTITY_BASE/../pipe" - -set COMPONENTS [list \ - [list "GEN_MUX_ONEHOT" $MUX "FULL"] \ - [list "MI_PIPE" $MI_PIPE "FULL"] \ -] - -set MOD "$MOD $ENTITY_BASE/reg_type.vhd" -set MOD "$MOD $ENTITY_BASE/be_reg.vhd" -set MOD "$MOD $ENTITY_BASE/mi_reg.vhd" -set MOD "$MOD $ENTITY_BASE/MI_register_array.vhd" -set MOD "$MOD $ENTITY_BASE/synth/MI_register_array_top.vhd" diff --git a/comp/mi_tools/register_array/be_reg.vhd b/comp/mi_tools/register_array/be_reg.vhd deleted file mode 100644 index 40e7f88a0..000000000 --- a/comp/mi_tools/register_array/be_reg.vhd +++ /dev/null @@ -1,92 +0,0 @@ ---! \file: rw_registers.vhd ---! \brief: Memory register with support BE signal ---! \Author: Mario Kuka ---! \date 2014 ---! ---! \section License ---! ---! Copyright (C) 2014 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; - ---! generic register with support MI_BI -entity BE_REG is - generic ( - --! Data width max MI_WIDTH - MI_WIDTH : integer := 32; - DATA_WIDTH : integer := 32; - BE_ENABLE : boolean := true; - NUM_REG : integer; - constant INICIAL : std_logic_vector - ); - port ( - CLK : in std_logic; - --! MI32 BE signal - BE : in std_logic_vector(MI_WIDTH/8-1 downto 0); - --! input data - DATA : in std_logic_vector(DATA_WIDTH-1 downto 0); - --! enbale signal - ENABLE : in std_logic; - --! reset signal - RESET : in std_logic; - --! output data - P : out std_logic_vector(DATA_WIDTH-1 downto 0) := INICIAL((MI_WIDTH*(NUM_REG-1))+DATA_WIDTH-1 downto 0+(MI_WIDTH*(NUM_REG-1))) - ); -end BE_REG; - -architecture full of BE_REG is - constant d_div : integer := DATA_WIDTH/8; - constant d_mod : integer := DATA_WIDTH mod 8; - constant init_r : integer := MI_WIDTH*(NUM_REG-1); -begin - - GEN_REG_WITH_BE : if (BE_ENABLE = true) generate - begin - GEN_REG_DIV : for I in 0 to d_div-1 generate - begin - gen_regs_be: process(CLK) - begin - if(CLK'event) and (CLK='1') then - if (RESET = '1') then - P(7+(8*I) downto 0+(8*I)) <= INICIAL(7+(8*I)+init_r downto 0+(8*I)+init_r); - elsif (ENABLE = '1' and BE(I) = '1') then - P(7+(8*I) downto 0+(8*I)) <= DATA(7+(8*I) downto 0+(8*I)); - end if; - end if; - end process; - end generate; - - GEN_REG_MOD: if (d_mod /= 0) generate - begin - gen_reg_be: process(CLK) - begin - if(CLK'event) and (CLK='1') then - if (RESET = '1') then - P(DATA_WIDTH-1 downto DATA_WIDTH-d_mod) <= INICIAL(DATA_WIDTH-1+init_r downto DATA_WIDTH-d_mod+init_r); - elsif (ENABLE = '1' and BE(d_div) = '1') then - P(DATA_WIDTH-1 downto DATA_WIDTH-d_mod) <= DATA(DATA_WIDTH-1 downto DATA_WIDTH-d_mod); - end if; - end if; - end process; - end generate; - end generate; - - --! generate only register - GEN_REG_NO_BE : if (BE_ENABLE = false) generate - begin - gen_reg_be: process(CLK) - begin - if(CLK'event) and (CLK='1') then - if (RESET = '1') then - P <= INICIAL(DATA_WIDTH-1+init_r downto 0+init_r); - elsif (ENABLE = '1') then - P <= DATA; - end if; - end if; - end process; - end generate; -end full; diff --git a/comp/mi_tools/register_array/mi_reg.vhd b/comp/mi_tools/register_array/mi_reg.vhd deleted file mode 100644 index ed74f0124..000000000 --- a/comp/mi_tools/register_array/mi_reg.vhd +++ /dev/null @@ -1,299 +0,0 @@ --- mi_reg.vhd --- # Copyright (C) 2014 CESNET --- # Author: Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; -use ieee.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.math_pack.all; - -entity MI_REG is - generic ( - --! Data width mi_data - MI_WIDTH : integer := 32; - --! Register data width - DATA_WIDTH : integer := 32; - --! inter/exter register - INTER : boolean := true; - --! mi read enable - MI_RD_EN : boolean := true; - --! mi write enable - MI_WR_EN : boolean := true; - --! usr write port enable - USR_WR_EN : boolean := true; - --! reset enable - RST_EN : boolean := true; - --! be enable - BE_EN : boolean := true; - --! inicial value - constant INICIAL : std_logic_vector; - --! number of register - NUM_REG : integer - ); - port ( - --! Clock input - CLK : in std_logic; - --! Reset input - RESET : in std_logic; - --! Data output - DATA_OUT : out std_logic_vector(MI_WIDTH - 1 downto 0); - --! Enable from decoder - DEC_EN : in std_logic; - - --! MI32 input interface ------------------------------------------------- - --! Input Data - MI_DWR : in std_logic_vector(MI_WIDTH-1 downto 0); - --! Read Request - MI_RD : in std_logic; - --! Write Request - MI_WR : in std_logic; - --! Byte Enable - MI_BE : in std_logic_vector(MI_WIDTH/8-1 downto 0); - --! Output Data - MI_DRD : out std_logic_vector(MI_WIDTH-1 downto 0); - --! Address Ready - MI_ARDY : out std_logic; - --! Data Ready - MI_DRDY : out std_logic; - - MI_RD_OUT : out std_logic; - MI_WR_OUT : out std_logic; - USR_DATA_IN : in std_logic_vector(MI_WIDTH-1 downto 0); - USR_DATA_EN : in std_logic; - - EXTER_ARDY : in std_logic - ); -end MI_REG; - -architecture full of MI_REG is - signal rst_reg : std_logic; - signal data_reg_out : std_logic_vector(DATA_WIDTH-1 downto 0); - signal data_reg_in : std_logic_vector(DATA_WIDTH-1 downto 0); - signal rd_dec_en : std_logic; - signal wr_dec_en : std_logic; - signal reg_wr_en : std_logic; - signal be_p : std_logic_vector(MI_WIDTH/8-1 downto 0); -begin - --! generate inter register - GEN_INTER_REG : if (INTER = true) generate - begin - --! when RESET is enbale - GEN_RESET_ON : if (RST_EN = true) generate - begin - rst_reg <= RESET; - end generate; - - --! when RESET is disable - GEN_RESET_OFF : if (RST_EN = false) generate - begin - rst_reg <= '0'; - end generate; - - --! ARDY when MI_RD and MI_WR are enabled - GEN_ARDY_RDON_WRON: if (MI_RD_EN = true and MI_WR_EN = true) generate - begin - --! when signal from decoder is true - rd_dec_en <= MI_RD AND DEC_EN; - wr_dec_en <= MI_WR AND DEC_EN; - --! gen ardy, drdy - MI_ARDY <= rd_dec_en or wr_dec_en; - MI_DRDY <= rd_dec_en; - --! RD and WR for user - MI_RD_OUT <= rd_dec_en; - MI_WR_OUT <= wr_dec_en; - --! DRD data - MI_DRD(DATA_WIDTH-1 downto 0) <= data_reg_out; - MI_DRD(MI_WIDTH-1 downto DATA_WIDTH) <= (others => '0'); - end generate; - - --! ARDY when MI_RD is disable and MI_WR is enbale - GEN_ARDY_RDOFF_WRON: if (MI_RD_EN = false and MI_WR_EN = true) generate - begin - --! when signal from decoder is true - wr_dec_en <= MI_WR AND DEC_EN; - rd_dec_en <= '0'; - --! gen ardy, drdy - MI_ARDY <= wr_dec_en; - MI_DRDY <= '0'; - --! RD and WR for user - MI_RD_OUT <= 'U'; - MI_WR_OUT <= wr_dec_en; - --! DRD data - MI_DRD <= (others => '0'); - end generate; - - --! ARDY when MI_RD is enable and MI_WR is disable - GEN_ARDY_RDON_WROFF: if (MI_RD_EN = true and MI_WR_EN = false) generate - begin - --! when signal from decoder is true - rd_dec_en <= MI_RD AND DEC_EN; - wr_dec_en <= '0'; - --! gen ardy, drdy - MI_ARDY <= rd_dec_en; - MI_DRDY <= rd_dec_en; - --! RD and WR for user - MI_RD_OUT <= rd_dec_en; - MI_WR_OUT <= 'U'; - --! DRD data - MI_DRD(DATA_WIDTH-1 downto 0) <= data_reg_out; - GEN_FINISH_DRD: if MI_WIDTH /= DATA_WIDTH generate - MI_DRD(MI_WIDTH-1 downto DATA_WIDTH) <= (others => '0'); - end generate; - end generate; - - --! ARDY when MI_RD and MI_WR is disable - GEN_ARDY_RDOFF_WROFF: if (MI_RD_EN = false and MI_WR_EN = false) generate - begin - --! when signal from decoder is true - --! - --! gen ardy, drdy - MI_ARDY <= '0'; - MI_DRDY <= '0'; - --! RD and WR for user - MI_RD_OUT <= 'U'; - MI_WR_OUT <= 'U'; - --! DRD data - MI_DRD <= (others => '-'); - end generate; - - --! control write data to register when MI_WR and USR_WR are enabled - GEN_REGIN_DAT_MIWRON_USRWRON: if (MI_WR_EN = true and USR_WR_EN = true) generate - begin - --! switch data - data_reg_in <= MI_DWR(DATA_WIDTH-1 downto 0) when wr_dec_en = '1' else - USR_DATA_IN(DATA_WIDTH-1 downto 0); - --! control write enable - reg_wr_en <= wr_dec_en or USR_DATA_EN; - end generate; - - --! control write data to register when MI_WR is enbale and USR_WR is disable - GEN_REGIN_DAT_MIWRON_USRWROff: if (MI_WR_EN = true and USR_WR_EN = false) generate - begin - --! switch data - data_reg_in <= MI_DWR(DATA_WIDTH-1 downto 0); - --! control write enable - reg_wr_en <= wr_dec_en; - end generate; - - --! control write data to register when MI_WR is disable and USR_WR is enable - GEN_REGIN_DAT_MIWROFF_USRWRON: if (MI_WR_EN = false and USR_WR_EN = true) generate - begin - --! switch data - data_reg_in <= USR_DATA_IN(DATA_WIDTH-1 downto 0); - --! control write enable - reg_wr_en <= USR_DATA_EN; - end generate; - - --! control write data to register when MI_WR and USR_WR are disable - GEN_REGIN_DAT_MIWROFF_USRWROFF: if (MI_WR_EN = false and USR_WR_EN = false) generate - begin - data_reg_out <= INICIAL(DATA_WIDTH-1+MI_WIDTH*(NUM_REG-1) downto 0+MI_WIDTH*(NUM_REG-1)); - end generate; - - - GEN_BE : if(MI_WR_EN = true) generate - begin - be : process(wr_dec_en, MI_BE) - begin - if(wr_dec_en = '0') then - be_p <= (others => '1'); - else - be_p <= MI_BE; - end if; - end process; - end generate; - - GEN_BE_NO : if(MI_WR_EN = false) generate - begin - be_p <= (others => '1'); - end generate; - - GEN_REG: if (MI_WR_EN = true or USR_WR_EN = true) generate - begin - --! conect register - BE_REG_inst : entity work.BE_REG - generic map ( - DATA_WIDTH => DATA_WIDTH, - MI_WIDTH => MI_WIDTH, - BE_ENABLE => BE_EN, - NUM_REG => NUM_REG, - INICIAL => INICIAL - ) - port map ( - --! Clock input - CLK => CLK, - --! Reset input - RESET => rst_reg, - --! BE signal - BE => be_p, - --! in data - DATA => data_reg_in, - --! enable - ENABLE => reg_wr_en, - --! data out - P => data_reg_out - ); - end generate; - - --! output data - DATA_OUT(DATA_WIDTH-1 downto 0) <= data_reg_out; - GEN_FINISH_DATA_OUT: if MI_WIDTH /= DATA_WIDTH generate - DATA_OUT(MI_WIDTH-1 downto DATA_WIDTH) <= (others => '0'); - end generate; - end generate; - - --! generate exter register - GEN_EXTER_REG : if (INTER = false) generate - begin - --! ARDY when MI_RD and MI_WR are enabled - EXTERN_ARDY_RDON_WRON: if (MI_RD_EN = true and MI_WR_EN = true) generate - begin - --! when signal from decoder is true - MI_RD_OUT <= MI_RD AND DEC_EN; - MI_WR_OUT <= MI_WR AND DEC_EN; - --! DRD data - MI_DRD <= USR_DATA_IN; - end generate; - - --! ARDY when MI_RD is disable and MI_WR is enbale - EXTERN_ARDY_RDOFF_WRON: if (MI_RD_EN = false and MI_WR_EN = true) generate - begin - --! when signal from decoder is true - MI_WR_OUT <= MI_WR AND DEC_EN; - MI_RD_OUT <= 'U'; - --! DRD data - MI_DRD <= (others => '-'); - end generate; - - --! ARDY when MI_RD is enable and MI_WR is disable - EXTERN_ARDY_RDON_WROFF: if (MI_RD_EN = true and MI_WR_EN = false) generate - begin - --! when signal from decoder is true - MI_RD_OUT <= MI_RD AND DEC_EN; - MI_WR_OUT <= 'U'; - --! DRD data - MI_DRD <= USR_DATA_IN; - end generate; - - --! ARDY when MI_RD and MI_WR is disable - EXTERN_ARDY_RDOFF_WROFF: if (MI_RD_EN = false and MI_WR_EN = false) generate - begin - MI_RD_OUT <= 'U'; - MI_WR_OUT <= 'U'; - --! DRD data - MI_DRD <= (others => '-'); - end generate; - - DATA_OUT <= MI_DWR; - MI_ARDY <= EXTER_ARDY; - MI_DRDY <= USR_DATA_EN; - end generate; - -end full; - diff --git a/comp/mi_tools/register_array/reg_type.vhd b/comp/mi_tools/register_array/reg_type.vhd deleted file mode 100644 index 62cb964d3..000000000 --- a/comp/mi_tools/register_array/reg_type.vhd +++ /dev/null @@ -1,33 +0,0 @@ --- reg_type.vhd: register data type --- # Copyright (C) 2015 CESNET --- # Author: Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library IEEE; -use ieee.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.math_pack.all; - -package REG_PACK is - --! data type - type REG_TYPE is record - DATA_WIDTH : integer; - INTER : boolean; - MI_RD_EN : boolean; - MI_WR_EN : boolean; - USR_WR_EN : boolean; - RST_EN : boolean; - BE_EN : boolean; - end record; - --! array data type - type REG_TYPE_ARRAY - is array (integer range <>) of REG_TYPE; -end package REG_PACK; - -package body REG_PACK is -end package body REG_PACK; diff --git a/comp/mi_tools/register_array/sim/MI_register_array.fdo b/comp/mi_tools/register_array/sim/MI_register_array.fdo deleted file mode 100644 index a397ddf39..000000000 --- a/comp/mi_tools/register_array/sim/MI_register_array.fdo +++ /dev/null @@ -1,29 +0,0 @@ -# streaming_generator.fdo: Simulation script -# Copyright (C) 2014 CESNET -# Author: Mario Kuka -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# For whole design testing -set FIRMWARE_BASE "../../../.." -set STREAM_BASE ".." - -set TB_FILE "./testbench.vhd" -set SIG_FILE "./MI_register_array_sig.fdo" - -# Modules definition -set COMPONENTS [list \ - [list "MI_REGISTER_ARRAY" $STREAM_BASE "FULL"] \ - ] - -# Global include file for compilation -source "$FIRMWARE_BASE/build/Modelsim.inc.fdo" - -# Suppress warnings from arithm library -# puts "Std Arith Warnings - Disabled" -# set StdArithNoWarnings 1 - -# File with signals -nb_sim_run 1500ns diff --git a/comp/mi_tools/register_array/sim/MI_register_array_sig.fdo b/comp/mi_tools/register_array/sim/MI_register_array_sig.fdo deleted file mode 100644 index 01d614acc..000000000 --- a/comp/mi_tools/register_array/sim/MI_register_array_sig.fdo +++ /dev/null @@ -1,19 +0,0 @@ -# streaming_generator_sig.fdo : Include file with signals -# Copyright (C) 2014 CESNET -# Author: Mario Kuka -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -# Paths -set TB_PATH "/testbench" -set STREAM_PATH "/testbench/uut" - -# include signals -source "signals.fdo" - -add wave -noupdate -label RESET -color magenta $TB_PATH/reset -add wave -noupdate -label CLK -color magenta $TB_PATH/clk -blk_STREAM - diff --git a/comp/mi_tools/register_array/sim/signals.fdo b/comp/mi_tools/register_array/sim/signals.fdo deleted file mode 100644 index b33581b63..000000000 --- a/comp/mi_tools/register_array/sim/signals.fdo +++ /dev/null @@ -1,29 +0,0 @@ -# signals.fdo: Include file with signals -# Copyright (C) 2014 CESNET -# Author: Mario Kuka -# SPDX-License-Identifier: BSD-3-Clause -# -# $Id$ -# - -proc blk_STREAM { } { - - global STREAM_PATH - add wave -divider "MI_32" - add_wave "-noupdate -hex -label MI_DWR" /$STREAM_PATH/MI_DWR - add_wave "-noupdate -hex -label MI_ADDR" /$STREAM_PATH/MI_ADDR - add_wave "-noupdate -hex -label MI_RD" /$STREAM_PATH/MI_RD - add_wave "-noupdate -hex -label MI_WR" /$STREAM_PATH/MI_WR - add_wave "-noupdate -hex -label MI_BE" /$STREAM_PATH/MI_BE - add_wave "-noupdate -hex -label MI_DRD" /$STREAM_PATH/MI_DRD - add_wave "-noupdate -hex -label MI_ARDY" /$STREAM_PATH/MI_ARDY - add_wave "-noupdate -hex -label MI_DRDY" /$STREAM_PATH/MI_DRDY - add wave -divider "MI_32" - add_wave "-noupdate -hex -label REG_DATA_OUT" /$STREAM_PATH/REG_DATA_OUT - add_wave "-noupdate -hex -label REG_DATA_IN" /$STREAM_PATH/REG_DATA_IN - add_wave "-noupdate -hex -label REG_WE_IN" /$STREAM_PATH/REG_WE_IN - add_wave "-noupdate -hex -label REG_WR_OUT" /$STREAM_PATH/REG_WR_OUT - add_wave "-noupdate -hex -label REG_RD_OUT" /$STREAM_PATH/REG_RD_OUT - add_wave "-noupdate -hex -label REG_ARDY_IN" /$STREAM_PATH/REG_ARDY_IN - -} diff --git a/comp/mi_tools/register_array/sim/testbench.vhd b/comp/mi_tools/register_array/sim/testbench.vhd deleted file mode 100644 index c719b8e5a..000000000 --- a/comp/mi_tools/register_array/sim/testbench.vhd +++ /dev/null @@ -1,185 +0,0 @@ --- testbench.vhd: Testbench for streaming generator --- # Copyright (C) 2014 CESNET --- # Author: Mario Kuka --- --- SPDX-License-Identifier: BSD-3-Clause --- --- $Id$ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity testbench is - -end testbench; - -architecture behavioral of testbench is - signal CLK : std_logic; - signal RESET : std_logic; - signal REG_DATA_OUT : std_logic_vector(127 downto 0); - signal REG_DATA_IN : std_logic_vector(127 downto 0); - signal REG_WR_OUT : std_logic_vector(3 downto 0); - signal REG_RD_OUT : std_logic_vector(3 downto 0); - signal REG_WE_IN : std_logic_vector(3 downto 0); - signal REG_ARDY_IN : std_logic_vector(3 downto 0); - signal MI_DWR : std_logic_vector(31 downto 0); - signal MI_ADDR : std_logic_vector(31 downto 0); - signal MI_RD : std_logic; - signal MI_WR : std_logic; - signal MI_BE : std_logic_vector(3 downto 0); - signal MI_DRD : std_logic_vector(31 downto 0); - signal MI_ARDY : std_logic; - signal MI_DRDY : std_logic; - -begin - - uut : entity work.MI_REGISTER_ARRAY(full) - generic map( - --! mi pipe - MI_PIPE => true, - --! mi data width - MI_WIDTH => 32, - --! mi addres width - MI_ADDR_WIDTH => 32, - --! addres fisrt register, width -> (MI_ADDR_WIDTH-1 downto 0) - FIRST_ADDR(32-1 downto 0) => X"00000008", - --! significant bits of the mi address - SIGN_BITS_ADDR => 32, - --! number of registers - NUM_REGS => 4, - --! initialization values for registers, width -> (MI_WIDTH*NUM_REGS-1 downto 0) - INICIAL(4*32-1 downto 0)=> X"00000004000000030000000200000001", - - --! range must be "1 to NUM_REGS" - GENER_REGS(1 to 4) => ( --! registers data width - (DATA_WIDTH => 19, --! nastavujem generiky pre 1. register - --! true - inter , false - exter - INTER => true, - --! support MI read - MI_RD_EN => true, - --! support MI write - MI_WR_EN => true, - --! support user write - USR_WR_EN => true, - --! response to reset - RST_EN => false, - --! support MI_BE signal - BE_EN => true), - - (DATA_WIDTH => 19, --! nastavujem generiki pre 2. register - INTER => true, - MI_RD_EN => true, - MI_WR_EN => true, - USR_WR_EN => true, - RST_EN => true, - BE_EN => true), - - (DATA_WIDTH => 19, --! nastavujem generiki pre 3. register - INTER => true, - MI_RD_EN => true, - MI_WR_EN => false, - USR_WR_EN => false, - RST_EN => true, - BE_EN => false), - - (DATA_WIDTH => 19, --! nastavujem generiki pre 4. register - INTER => true, - MI_RD_EN => true, - MI_WR_EN => false, - USR_WR_EN => false, - RST_EN => true, - BE_EN => true) - ) - ) - port map ( - CLK => CLK, - RESET => RESET, - REG_DATA_OUT => REG_DATA_OUT, - REG_DATA_IN => REG_DATA_IN, - REG_WR_OUT => REG_WR_OUT, - REG_RD_OUT => REG_RD_OUT, - REG_WE_IN => REG_WE_IN, - REG_ARDY_IN => REG_ARDY_IN, - MI_DWR => MI_DWR, - MI_ADDR => MI_ADDR, - MI_RD => MI_RD, - MI_WR => MI_WR, - MI_BE => MI_BE, - MI_DRD => MI_DRD, - MI_ARDY => MI_ARDY, - MI_DRDY => MI_DRDY - ); - --! Simulating input flow - input_flow : process - begin - - wait for 1 ns; - - MI_DWR <= (others => '0'); - MI_ADDR <= (others => '0'); - MI_BE <= "0001"; - MI_RD <= '0'; - MI_WR <= '0'; - REG_DATA_IN <= (others => '0'); - REG_WE_IN <= (others => '0'); - REG_ARDY_IN <= (others => '0'); - - wait for 50 ns; - - MI_RD <= '1'; - MI_ADDR <= X"00000008"; - wait for 10 ns; - MI_ADDR <= X"0000000C"; - wait for 20 ns; - MI_RD <= '0'; - - - MI_ADDR <= X"00000008"; - MI_DWR <= X"FFFFFFFF"; - MI_WR <= '1'; - wait for 10 ns; - MI_ADDR <= X"0000000C"; - MI_DWR <= X"BBBBBBBB"; - wait for 10 ns; - MI_ADDR <= X"00000008"; - MI_DWR <= X"DDDDDDDD"; - wait for 10 ns; - - MI_WR <= '0'; - - MI_RD <= '1'; - wait for 10 ns; - MI_RD <= '0'; - wait for 30 ns; - - REG_DATA_IN <= X"000000000000000000000000AAAAAAAA"; - REG_WE_IN(0) <= '1'; - wait for 10 ns; - REG_WE_IN(0) <= '0'; - - MI_RD <= '1'; - wait for 10 ns; - MI_RD <= '0'; - - wait; - end process input_flow; - - clk_gen_p : process - begin - CLK <= '1'; - wait for 5 ns; - CLK <= '0'; - wait for 5 ns; - end process clk_gen_p; - - reset_gen : process - begin - RESET <= '1'; - wait for 40 ns; - RESET <= '0'; - wait for 200 ns; - end process; -end architecture; diff --git a/comp/mi_tools/register_array/synth/MI_register_array_top.vhd b/comp/mi_tools/register_array/synth/MI_register_array_top.vhd deleted file mode 100644 index ec9009297..000000000 --- a/comp/mi_tools/register_array/synth/MI_register_array_top.vhd +++ /dev/null @@ -1,129 +0,0 @@ ---! cmp48_top.vhd ---! ---! \file ---! \brief MUL implemented with Virtex-7 DSP slice ---! \Author: Mario Kuka ---! \date 2014 ---! ---! \section License ---! ---! Copyright (C) 2014 CESNET ---! ---! SPDX-License-Identifier: BSD-3-Clause ---! - -library IEEE; -use IEEE.std_logic_1164.all; - ---! \brief DSP slice ALU entity -entity MI_register_array_top is - generic ( - MI_WIDTH : integer := 32; - NUM_REGS : integer := 3; - MI_ADDR_WIDTH : integer := 32 - ); - port ( - --! Clock input - CLK : in std_logic; - --! Reset input - RESET : in std_logic; - - --! MI32 input interface ------------------------------------------------- - --! Input Data - MI_DWR : in std_logic_vector(MI_WIDTH-1 downto 0); - --! addres - MI_ADDR : in std_logic_vector(MI_ADDR_WIDTH-1 downto 0); - --! Read Request - MI_RD : in std_logic; - --! Write Request - MI_WR : in std_logic; - --! Byte Enable - MI_BE : in std_logic_vector(MI_WIDTH/8-1 downto 0); - --! Output Data - MI_DRD : out std_logic_vector(MI_WIDTH-1 downto 0); - --! Address Ready - MI_ARDY : out std_logic; - --! Data Ready - MI_DRDY : out std_logic; - - --! registers Data output - REG_DATA_OUT : out std_logic_vector((NUM_REGS*MI_WIDTH)-1 downto 0); - --! MI_WR signals - REG_WR_OUT : out std_logic_vector(NUM_REGS-1 downto 0); - --! MI_RD signals - REG_RD_OUT : out std_logic_vector(NUM_REGS-1 downto 0); - --! users data input - REG_DATA_IN : in std_logic_vector((NUM_REGS*MI_WIDTH)-1 downto 0); - --! users we signal - REG_WE_IN : in std_logic_vector(NUM_REGS-1 downto 0); - --! MI_ARDY signal from extern register - REG_ARDY_IN : in std_logic_vector(NUM_REGS-1 downto 0) - ); -end MI_register_array_top; - -architecture full of MI_register_array_top is -begin - - uut : entity work.MI_REGISTER_ARRAY(full) - generic map( - MI_WIDTH => MI_WIDTH, - MI_ADDR_WIDTH => MI_ADDR_WIDTH, - NUM_REGS => NUM_REGS, - SIGN_BITS_ADDR => 32, - MI_PIPE => false, - FIRST_ADDR => (MI_ADDR_WIDTH-1 downto 0 => '0'), - INICIAL => X"C0000003C0000002C0000001", - - --! range musi byt od "1 to (pocet registov)" - GENER_REGS(1 to 3) => ( --! registers data width - (DATA_WIDTH => 31, --! nastavujem generiky pre 1. register - --! true - inter , false - exter - INTER => true, - --! support MI read - MI_RD_EN => true, - --! support MI write - MI_WR_EN => true, - --! support user write - USR_WR_EN => true, - --! response to reset - RST_EN => true, - --! support MI_BE signal - BE_EN => true), - - (DATA_WIDTH => 32, --! nastavujem generiki pre 2. register - INTER => true, - MI_RD_EN => true, - MI_WR_EN => true, - USR_WR_EN => true, - RST_EN => true, - BE_EN => true), - - (DATA_WIDTH => 31, --! nastavujem generiki pre 3. register - INTER => false, - MI_RD_EN => true, - MI_WR_EN => true, - USR_WR_EN => true, - RST_EN => true, - BE_EN => false) - ) - ) - port map ( - CLK => CLK, - RESET => RESET, - REG_DATA_OUT => REG_DATA_OUT, - REG_DATA_IN => REG_DATA_IN, - REG_WR_OUT => REG_WR_OUT, - REG_RD_OUT => REG_RD_OUT, - REG_WE_IN => REG_WE_IN, - REG_ARDY_IN => REG_ARDY_IN, - MI_DWR => MI_DWR, - MI_ADDR => MI_ADDR, - MI_RD => MI_RD, - MI_WR => MI_WR, - MI_BE => MI_BE, - MI_DRD => MI_DRD, - MI_ARDY => MI_ARDY, - MI_DRDY => MI_DRDY - ); - -end full; diff --git a/comp/mi_tools/register_array/synth/Makefile b/comp/mi_tools/register_array/synth/Makefile deleted file mode 100644 index 4e1abc89d..000000000 --- a/comp/mi_tools/register_array/synth/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# Makefile: Makefile script to compile specified module -# Copyright (C) 2021 CESNET z. s. p. o. -# Author(s): Jakub Cabal -# -# SPDX-License-Identifier: BSD-3-Clause - -TOP_LEVEL_ENT=MI_register_array_top - -#SYNTH=quartus -export CLK_PERIOD=4.0 -#export DEVICE=ULTRASCALE - -all: comp -include ../../../../build/Makefile -.PHONY: all