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diff --git a/devel/_images/etile_network_module_core.svg b/devel/_images/etile_network_module_core.svg
diff --git a/devel/_images/ftile_network_module_core.svg b/devel/_images/ftile_network_module_core.svg
diff --git a/devel/_sources/ndk_core/intel/doc/eth.rst.txt b/devel/_sources/ndk_core/intel/doc/eth.rst.txt
@@ -180,7 +180,7 @@ Network Module Core
 
 The so-called Network Module Core is a subcomponent of the Network Module.
 It contains the required hard IP(s), appropriate adapters, and an MI component for reconfiguring the hard IP(s).
-Right now, the Network Module can use three different Ethernet hard IPs, for Intel FPGA, it is the E-tile or the F-Tile, and for the Xilinx FPGA, it is the CMAC. 
+Right now, the Network Module can use three different Ethernet hard IPs, for Intel FPGA, it is the E-tile or the F-Tile, and for the Xilinx FPGA, it is the CMAC.
 For the F-Tile, there are two variants of IP core: it is F-Tile and F-Tile_Multirate, which support different speeds for implemented IP.
 For the F-Tile_Multirate reconfiguration, use Dynamic Reconfiguration Controller.
 According to the selected NIC (and therefore the type of hard IP), one of the four architectures of the Network Module Core (with the proper hard IP) is used.
@@ -189,7 +189,7 @@ On the right side, it is connected to the Network Module Logic.
 All four architectures of the Network Module Core are displayed below.
 
 
-.. list-table:: 
+.. list-table::
 
     * - .. image:: img/etile_network_module_core.svg
             :align: center
@@ -225,6 +225,8 @@ F-tile hard IP cores always use the MAC segmented interface in our designs.
 CMAC’s client interface is the `LBUS interface <https://docs.xilinx.com/r/en-US/pg165-cmac/User-Side-LBUS-Interface>`_.
 The Network Module Core always uses the appropriate adapters (according to the hard IP).
 
+Each channel on both E-tile and F-tile architectures also includes a diagnostic post-MAC loopback module, which (when enabled via the MGMT) re-transmits received frames back to the link partner. We call this mode the "PCS reverse loopback". When the loopback is active, received frames are also passed to the Application as in normal mode. However, the frames transmitted from the Application are discarded.
+See the `nfb-eth tool <https://cesnet.github.io/ndk-sw/tools/nfb-eth.html>`_ documentation for instructions on how to turn the loopback on/off.
 
 .. _sw_access_reconfig_infs:
 

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diff --git a/devel/ndk_core/intel/doc/app.html b/devel/ndk_core/intel/doc/app.html
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diff --git a/devel/ndk_core/intel/doc/dma.html b/devel/ndk_core/intel/doc/dma.html
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diff --git a/devel/ndk_core/intel/doc/eth.html b/devel/ndk_core/intel/doc/eth.html
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@@ -168,8 +168,8 @@
 The MI PHY Splitter forwards requests to one or more instances of the Network Module Core.
 The MI Splitter forwards requests to one or more instances of Network Module Logic.
 The main blocks and their connection between address spaces are in the table below:</p>
-<table class="docutils align-center" id="id5">
-<caption><span class="caption-text">Tab. 1</span><a class="headerlink" href="#id5" title="Permalink to this table"></a></caption>
+<table class="docutils align-center" id="id6">
+<caption><span class="caption-text">Tab. 1</span><a class="headerlink" href="#id6" title="Permalink to this table"></a></caption>
 <colgroup>
 <col style="width: 13%" />
 <col style="width: 25%" />
@@ -345,8 +345,8 @@ <h2>SW access to the Network Module Cores and Network Module Logics<a class="hea
 <p>To get a complete register address in one of the components of the Network Module, you must add the appropriate base address of the Network Module (as defined in the <a class="reference internal" href="mi.html#ndk-mi"><span class="std std-ref">MI address space package</span></a>) to it.</p>
 </div>
 <p>The addressing of both main blocks is described in the tables below:</p>
-<table class="docutils align-center" id="id6">
-<caption><span class="caption-text">Tab. 2</span><a class="headerlink" href="#id6" title="Permalink to this table"></a></caption>
+<table class="docutils align-center" id="id7">
+<caption><span class="caption-text">Tab. 2</span><a class="headerlink" href="#id7" title="Permalink to this table"></a></caption>
 <colgroup>
 <col style="width: 15%" />
 <col style="width: 31%" />
@@ -380,8 +380,8 @@ <h2>SW access to the Network Module Cores and Network Module Logics<a class="hea
 <div class="line-block">
 <div class="line"><br /></div>
 </div>
-<table class="docutils align-center" id="id7">
-<caption><span class="caption-text">Tab. 3</span><a class="headerlink" href="#id7" title="Permalink to this table"></a></caption>
+<table class="docutils align-center" id="id8">
+<caption><span class="caption-text">Tab. 3</span><a class="headerlink" href="#id8" title="Permalink to this table"></a></caption>
 <colgroup>
 <col style="width: 15%" />
 <col style="width: 31%" />
@@ -458,6 +458,8 @@ <h2>SW access to the Network Module Cores and Network Module Logics<a class="hea
 F-tile hard IP cores always use the MAC segmented interface in our designs.
 CMAC’s client interface is the <a class="reference external" href="https://docs.xilinx.com/r/en-US/pg165-cmac/User-Side-LBUS-Interface">LBUS interface</a>.
 The Network Module Core always uses the appropriate adapters (according to the hard IP).</p>
+<p>Each channel on both E-tile and F-tile architectures also includes a diagnostic post-MAC loopback module, which (when enabled via the MGMT) re-transmits received frames back to the link partner. We call this mode the “PCS reverse loopback”. When the loopback is active, received frames are also passed to the Application as in normal mode. However, the frames transmitted from the Application are discarded.
+See the <a class="reference external" href="https://cesnet.github.io/ndk-sw/tools/nfb-eth.html">nfb-eth tool</a> documentation for instructions on how to turn the loopback on/off.</p>
 <section id="sw-access-to-the-reconfiguration-interfaces">
 <span id="sw-access-reconfig-infs"></span><h3>SW access to the reconfiguration interfaces<a class="headerlink" href="#sw-access-to-the-reconfiguration-interfaces" title="Permalink to this heading"></a></h3>
 <p>Software access is provided via the management unit (MGMT), which is instantiated per channel.
@@ -511,8 +513,8 @@ <h2>SW access to the Network Module Cores and Network Module Logics<a class="hea
 To create a complete address of a MAC Lite register, add the address of the register, the channel offset, the port offset, and the offset of the Network Module Logic (MI_ADC_PORT_NETMOD in the <a class="reference external" href="https://github.com/CESNET/ndk-core/blob/main/intel/src/mi_addr_space_pkg.vhd">MI address space package</a>).
 To show the connections of the MAC Lites, an example of the MAC Lite address spaces for a configuration with two 4x25 GE ports follows.</p>
 <p>Notation: TX_MAC_LITE(port_id)(channel_id), RX_MAC_LITE(port_id)(channel_id).</p>
-<table class="docutils align-center" id="id8">
-<caption><span class="caption-text">Tab. 4</span><a class="headerlink" href="#id8" title="Permalink to this table"></a></caption>
+<table class="docutils align-center" id="id9">
+<caption><span class="caption-text">Tab. 4</span><a class="headerlink" href="#id9" title="Permalink to this table"></a></caption>
 <colgroup>
 <col style="width: 29%" />
 <col style="width: 43%" />

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diff --git a/devel/ndk_core/intel/readme.html b/devel/ndk_core/intel/readme.html
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