From 4e84abf1694b192c8e33b8f24e6ca649a3fdea42 Mon Sep 17 00:00:00 2001 From: "David Benes (FEKT)" Date: Fri, 6 Dec 2024 09:45:56 +0000 Subject: [PATCH] feat(cards): add support for iwave g35p accelerator card --- apps/minimal/build/g35p/Makefile | 27 ++ apps/minimal/build/g35p/Vivado.tcl | 32 ++ apps/minimal/build/g35p/app_conf.tcl | 28 ++ .../tests/cocotb/top-level-sim.jenkinsfile | 2 +- cards/iwave/g35p/config/card_conf.tcl | 85 ++++++ cards/iwave/g35p/config/card_const.tcl | 50 +++ cards/iwave/g35p/constr/general.xdc | 17 ++ cards/iwave/g35p/constr/gty_loc.xdc | 21 ++ cards/iwave/g35p/constr/pcie.xdc | 88 ++++++ cards/iwave/g35p/constr/qsfp.xdc | 136 +++++++++ cards/iwave/g35p/readme.rst | 53 ++++ cards/iwave/g35p/src/Modules.tcl | 28 ++ cards/iwave/g35p/src/Vivado.inc.tcl | 49 +++ cards/iwave/g35p/src/card.mk | 44 +++ cards/iwave/g35p/src/fpga.vhd | 289 ++++++++++++++++++ .../ip/cmac_eth_1x100g/cmac_eth_1x100g.ip.tcl | 25 ++ .../pcie4_uscale_plus.ip.tcl | 86 ++++++ doc/source/index.rst | 1 + 18 files changed, 1060 insertions(+), 1 deletion(-) create mode 100644 apps/minimal/build/g35p/Makefile create mode 100644 apps/minimal/build/g35p/Vivado.tcl create mode 100644 apps/minimal/build/g35p/app_conf.tcl create mode 100644 cards/iwave/g35p/config/card_conf.tcl create mode 100644 cards/iwave/g35p/config/card_const.tcl create mode 100644 cards/iwave/g35p/constr/general.xdc create mode 100644 cards/iwave/g35p/constr/gty_loc.xdc create mode 100644 cards/iwave/g35p/constr/pcie.xdc create mode 100644 cards/iwave/g35p/constr/qsfp.xdc create mode 100644 cards/iwave/g35p/readme.rst create mode 100644 cards/iwave/g35p/src/Modules.tcl create mode 100644 cards/iwave/g35p/src/Vivado.inc.tcl create mode 100644 cards/iwave/g35p/src/card.mk create mode 100644 cards/iwave/g35p/src/fpga.vhd create mode 100644 cards/iwave/g35p/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.ip.tcl create mode 100644 cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl diff --git a/apps/minimal/build/g35p/Makefile b/apps/minimal/build/g35p/Makefile new file mode 100644 index 000000000..c034abeaf --- /dev/null +++ b/apps/minimal/build/g35p/Makefile @@ -0,0 +1,27 @@ +# Makefile: Makefile for iWave G35P Accelerator Card +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + + +# NOTE: Usage of the configuration parameters in this file is described +# in the Parametrization section of the NDK-CORE documentation. + +# Set path to top-level of NDK-FPGA repository +COMBO_BASE = ../../../.. +CARD_BASE = $(COMBO_BASE)/cards/iwave/g35p +APP_CONF = app_conf.tcl +OUTPUT_NAME = g35p-minimal + +.PHONY: all 100g2 + +all: 100g2 + +100g2: ETH_PORTS=2 +100g2: ETH_PORT_SPEED=100 +100g2: ETH_PORT_CHAN=1 +100g2: OUTPUT_NAME:=g35p-minimal-100g2 +100g2: build + +include $(CARD_BASE)/src/card.mk diff --git a/apps/minimal/build/g35p/Vivado.tcl b/apps/minimal/build/g35p/Vivado.tcl new file mode 100644 index 000000000..a40849df9 --- /dev/null +++ b/apps/minimal/build/g35p/Vivado.tcl @@ -0,0 +1,32 @@ +# Vivado.tcl: Vivado tcl script to compile whole FPGA design +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + + +# NOTE: The purpose of this file is described in the Parametrization section of +# the NDK-CORE documentation. + +# ----- Setting basic synthesis options --------------------------------------- +# Sourcing all configuration parameters +source $env(CARD_BASE)/src/Vivado.inc.tcl + +# Create only a Vivado project for further design flow driven from Vivado GUI +# "0" ... full design flow in command line +# "1" ... project composition only for further dedesign flow in GUI +set SYNTH_FLAGS(PROJ_ONLY) "0" + +# Associative array which is propagated to APPLICATION_CORE, add other +# parameters if necessary. +set APP_ARCHGRP(APP_CORE_ENABLE) $APP_CORE_ENABLE + +# Convert associative array to list +set APP_ARCHGRP_L [array get APP_ARCHGRP] + +# ----- Add application core to main component list --------------------------- +lappend HIERARCHY(COMPONENTS) \ + [list "APPLICATION_CORE" "$OFM_PATH/apps/minimal/top" $APP_ARCHGRP_L] + +# Call main function which handle targets +nb_main diff --git a/apps/minimal/build/g35p/app_conf.tcl b/apps/minimal/build/g35p/app_conf.tcl new file mode 100644 index 000000000..8350e39f5 --- /dev/null +++ b/apps/minimal/build/g35p/app_conf.tcl @@ -0,0 +1,28 @@ +# app_conf.tcl: Application specific parameters which can be changed by the user +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + + +# NOTE: The detailed description of the usage of this file can be viewed in the +# Parametrizing section of the NDK-CORE documentation. + +# NOTE: Use the PCIE_CONF make parameter to select the PCIe configuration. + +# ------------------------------------------------------------------------------ +# DMA parameters: +# ------------------------------------------------------------------------------ +# The minimum number of RX/TX DMA channels for this card is 16. +set DMA_RX_CHANNELS 16 +set DMA_TX_CHANNELS 16 +# In blocking mode, packets are dropped only when the RX DMA channel is off. +# In non-blocking mode, packets are dropped whenever they cannot be sent. +set DMA_RX_BLOCKING_MODE true + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +set PROJECT_NAME "NDK_MINIMAL" +set PROJECT_VARIANT "$ETH_PORT_SPEED(0)G$ETH_PORTS" +set PROJECT_VERSION [exec cat ../../../../VERSION] diff --git a/apps/minimal/tests/cocotb/top-level-sim.jenkinsfile b/apps/minimal/tests/cocotb/top-level-sim.jenkinsfile index 5973d30c2..0dcf9bee3 100644 --- a/apps/minimal/tests/cocotb/top-level-sim.jenkinsfile +++ b/apps/minimal/tests/cocotb/top-level-sim.jenkinsfile @@ -23,7 +23,7 @@ def common_card_test_run(CARD_NAME) { } } -def CARDS = ["alveo-u200", "alveo-u55c", "vcu118", "ia-420f", "n6010", "fb2cghh", "fb4cgg3", "nfb-200g2ql", "dk-dev-1sdx-p"] +def CARDS = ["alveo-u200", "alveo-u55c", "vcu118", "ia-420f", "n6010", "fb2cghh", "fb4cgg3", "nfb-200g2ql", "dk-dev-1sdx-p", "g35p"] node("preklad") { cleanWs() diff --git a/cards/iwave/g35p/config/card_conf.tcl b/cards/iwave/g35p/config/card_conf.tcl new file mode 100644 index 000000000..c5c2f71d2 --- /dev/null +++ b/cards/iwave/g35p/config/card_conf.tcl @@ -0,0 +1,85 @@ +# card_conf.tcl: Default parameters for iWave G35P +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + + +# NOTE: For the detailed description of this file, visit the Parametrization section +# in the documentation of the NDK-CORE repository. + +set PROJECT_NAME "" + +# ------------------------------------------------------------------------------ +# ETH parameters: +# ------------------------------------------------------------------------------ +# Number of Ethernet ports, must match number of items in list ETH_PORTS_SPEED! +# (with two QSFP). Set the correct number of ETH ports according to your card. +set ETH_PORTS $env(ETH_PORTS) +# Speed for each one of the ETH_PORTS (allowed values: 100) +# ETH_PORT_SPEED is an array where each index represents given ETH_PORT and +# each index has associated a required port speed. +# NOTE: at this moment, all ports must have same speed ! +set ETH_PORT_SPEED(0) $env(ETH_PORT_SPEED) +set ETH_PORT_SPEED(1) $env(ETH_PORT_SPEED) + +# Number of channels for each one of the ETH_PORTS (allowed values: 1 for ETH_PORT_SPEED=100, 4 for ETH_PORT_SPEED<100) +# ETH_PORT_CHAN is an array where each index represents given ETH_PORT and +# each index has associated a required number of channels this port has. +# NOTE: at this moment, all ports must have same number of channels ! +set ETH_PORT_CHAN(0) $env(ETH_PORT_CHAN) +set ETH_PORT_CHAN(1) $env(ETH_PORT_CHAN) + +# Number of lanes for each one of the ETH_PORTS +# Typical values: 4 (QSFP), 8 (QSFP-DD) +set ETH_PORT_LANES(0) 8 +set ETH_PORT_LANES(1) 8 + +# ------------------------------------------------------------------------------ +# PCIe parameters (not all combinations work): +# ------------------------------------------------------------------------------ +# Supported combinations for this card: +# 1x PCIe Gen3 x16 -- PCIE_ENDPOINT_MODE=0 (Note: default configuration) +# ------------------------------------------------------------------------------ + +# Set default PCIe configuration +set PCIE_CONF "1xGen3x16" +if { [info exist env(PCIE_CONF)] } { + set PCIE_CONF $env(PCIE_CONF) +} + +# Parsing PCIE_CONF string to list of parameters +set pcie_conf_list [ParsePcieConf $PCIE_CONF] + +# PCIe Generation: +# 3 = PCIe Gen3 +set PCIE_GEN [lindex $pcie_conf_list 1] +# PCIe endpoints: +# 1 = 1x PCIe x16 in one slot +set PCIE_ENDPOINTS [lindex $pcie_conf_list 0] +# PCIe endpoint mode: +# 0 = 1x16 lanes +set PCIE_ENDPOINT_MODE [lindex $pcie_conf_list 2] + +# ------------------------------------------------------------------------------ +# DMA parameters: +# ------------------------------------------------------------------------------ +# This variable can be set in COREs *.mk file or as a parameter when launching the make +set DMA_TYPE $env(DMA_TYPE) +# The minimum number of RX/TX DMA channels for this card is 16. +set DMA_RX_CHANNELS 16 +set DMA_TX_CHANNELS 16 +# In blocking mode, packets are dropped only when the RX DMA channel is off. +# In non-blocking mode, packets are dropped whenever they cannot be sent. +set DMA_RX_BLOCKING_MODE true + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +set TSU_ENABLE true + +# ------------------------------------------------------------------------------ +# DDR4 parameters: +# ------------------------------------------------------------------------------ +# External DDR4 memory settings. +set MEM_PORTS 0 diff --git a/cards/iwave/g35p/config/card_const.tcl b/cards/iwave/g35p/config/card_const.tcl new file mode 100644 index 000000000..96937b004 --- /dev/null +++ b/cards/iwave/g35p/config/card_const.tcl @@ -0,0 +1,50 @@ +# card_const.tcl: Card specific parameters (developer only) +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + + +# WARNING: The user should not deliberately change parameters in this file. For +# the description of this file, visit the Parametrization section in the +# documentation of the NDK-CORE repostiory + +set CARD_NAME "IWAVE-G35P" +# Achitecture of Clock generator +set CLOCK_GEN_ARCH "USP" +# Achitecture of PCIe module +set PCIE_MOD_ARCH "USP" +# Achitecture of SDM/SYSMON module +# TODO: ZYNQ_ULTRASCALE +set SDM_SYSMON_ARCH "EMPTY" +# Boot controller type +set BOOT_TYPE 0 +# Achitecture of Network module +set NET_MOD_ARCH "CMAC" + +# Total number of QSFP cages +set QSFP_CAGES 2 +# I2C address of each QSFP cage - There is no I2C connected to the QSFP cages (they are set to pull-up). +set QSFP_I2C_ADDR(0) "0xA0" +set QSFP_I2C_ADDR(1) "0xA0" + +# ------------------------------------------------------------------------------ +# Checking of parameter compatibility +# ------------------------------------------------------------------------------ + +if {!($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 3 && $PCIE_ENDPOINT_MODE == 0) } { + error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE! +Allowed PCIe configurations: +- 1xGen3x16 -- PCIE_GEN=3, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0" +} + +if {!($MEM_PORTS == 0) } { + error "Incompatible MEM_PORTS configuration: MEM_PORTS = $MEM_PORTS! +Allowed MEM_PORTS configurations: +- MEM_PORTS=0 -- External memory disabled, memory controllers are not instantiated." +} + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +set TSU_FREQUENCY 322265625 diff --git a/cards/iwave/g35p/constr/general.xdc b/cards/iwave/g35p/constr/general.xdc new file mode 100644 index 000000000..c57b7d979 --- /dev/null +++ b/cards/iwave/g35p/constr/general.xdc @@ -0,0 +1,17 @@ +# general.xdc +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# Bitstream configuration +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN enable [current_design] +set_property CONFIG_MODE B_SCAN [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN enable [current_design] + +# General pins +set_property PACKAGE_PIN AT22 [get_ports SYSCLK] +set_property IOSTANDARD DIFF_SSTL12 [get_ports SYSCLK] + +create_clock -period 3.333 -name sysclk [get_ports SYSCLK] diff --git a/cards/iwave/g35p/constr/gty_loc.xdc b/cards/iwave/g35p/constr/gty_loc.xdc new file mode 100644 index 000000000..4bc723af5 --- /dev/null +++ b/cards/iwave/g35p/constr/gty_loc.xdc @@ -0,0 +1,21 @@ +# qsfp_loc.xdc +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# LOC locations for CMAC interfaces +# ============================================================================== + +set_property LOC CMACE4_X0Y0 [get_cells -hierarchical -filter {NAME =~ *eth_core_g[0].network_mod_core_i/cmac_eth_1x100g_i/* && REF_NAME==CMACE4}] +set_property LOC GTYE4_CHANNEL_X0Y8 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[0]*" }] +set_property LOC GTYE4_CHANNEL_X0Y9 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[1]*" }] +set_property LOC GTYE4_CHANNEL_X0Y10 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[2]*" }] +set_property LOC GTYE4_CHANNEL_X0Y11 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[3]*" }] + +set_property LOC CMACE4_X0Y1 [get_cells -hierarchical -filter {NAME =~ *eth_core_g[1].network_mod_core_i/cmac_eth_1x100g_i/* && REF_NAME==CMACE4}] +set_property LOC GTYE4_CHANNEL_X0Y16 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[0]*" }] +set_property LOC GTYE4_CHANNEL_X0Y17 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[1]*" }] +set_property LOC GTYE4_CHANNEL_X0Y18 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[2]*" }] +set_property LOC GTYE4_CHANNEL_X0Y19 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[3]*" }] diff --git a/cards/iwave/g35p/constr/pcie.xdc b/cards/iwave/g35p/constr/pcie.xdc new file mode 100644 index 000000000..68ecf0a5f --- /dev/null +++ b/cards/iwave/g35p/constr/pcie.xdc @@ -0,0 +1,88 @@ +# pcie.xdc +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +set_property PACKAGE_PIN AD12 [get_ports {PCIE_SYSCLK_P}] +set_property PACKAGE_PIN AD11 [get_ports {PCIE_SYSCLK_N}] + +set_property PACKAGE_PIN D2 [get_ports {PCIE_SYSRST_N}] +set_property IOSTANDARD LVCMOS33 [get_ports {PCIE_SYSRST_N}] + +create_clock -period 10.000 -name pcie_clk_p -waveform {0.000 5.000} [get_ports {PCIE_SYSCLK_P}] + +set_property PACKAGE_PIN AM4 [get_ports {PCIE_RX_P[0]}] +set_property PACKAGE_PIN AL2 [get_ports {PCIE_RX_P[1]}] +set_property PACKAGE_PIN AK4 [get_ports {PCIE_RX_P[2]}] +set_property PACKAGE_PIN AJ2 [get_ports {PCIE_RX_P[3]}] +set_property PACKAGE_PIN AH4 [get_ports {PCIE_RX_P[4]}] +set_property PACKAGE_PIN AG2 [get_ports {PCIE_RX_P[5]}] +set_property PACKAGE_PIN AF4 [get_ports {PCIE_RX_P[6]}] +set_property PACKAGE_PIN AE2 [get_ports {PCIE_RX_P[7]}] +set_property PACKAGE_PIN AD4 [get_ports {PCIE_RX_P[8]}] +set_property PACKAGE_PIN AC2 [get_ports {PCIE_RX_P[9]}] +set_property PACKAGE_PIN AB4 [get_ports {PCIE_RX_P[10]}] +set_property PACKAGE_PIN AA2 [get_ports {PCIE_RX_P[11]}] +set_property PACKAGE_PIN Y4 [get_ports {PCIE_RX_P[12]}] +set_property PACKAGE_PIN W2 [get_ports {PCIE_RX_P[13]}] +set_property PACKAGE_PIN V4 [get_ports {PCIE_RX_P[14]}] +set_property PACKAGE_PIN U2 [get_ports {PCIE_RX_P[15]}] + +set_property PACKAGE_PIN AM3 [get_ports {PCIE_RX_N[0]}] +set_property PACKAGE_PIN AL1 [get_ports {PCIE_RX_N[1]}] +set_property PACKAGE_PIN AK3 [get_ports {PCIE_RX_N[2]}] +set_property PACKAGE_PIN AJ1 [get_ports {PCIE_RX_N[3]}] +set_property PACKAGE_PIN AH3 [get_ports {PCIE_RX_N[4]}] +set_property PACKAGE_PIN AG1 [get_ports {PCIE_RX_N[5]}] +set_property PACKAGE_PIN AF3 [get_ports {PCIE_RX_N[6]}] +set_property PACKAGE_PIN AE1 [get_ports {PCIE_RX_N[7]}] +set_property PACKAGE_PIN AD3 [get_ports {PCIE_RX_N[8]}] +set_property PACKAGE_PIN AC1 [get_ports {PCIE_RX_N[9]}] +set_property PACKAGE_PIN AB3 [get_ports {PCIE_RX_N[10]}] +set_property PACKAGE_PIN AA1 [get_ports {PCIE_RX_N[11]}] +set_property PACKAGE_PIN Y3 [get_ports {PCIE_RX_N[12]}] +set_property PACKAGE_PIN W1 [get_ports {PCIE_RX_N[13]}] +set_property PACKAGE_PIN V3 [get_ports {PCIE_RX_N[14]}] +set_property PACKAGE_PIN U1 [get_ports {PCIE_RX_N[15]}] + +set_property PACKAGE_PIN AL6 [get_ports {PCIE_TX_P[0]}] +set_property PACKAGE_PIN AK8 [get_ports {PCIE_TX_P[1]}] +set_property PACKAGE_PIN AJ6 [get_ports {PCIE_TX_P[2]}] +set_property PACKAGE_PIN AH8 [get_ports {PCIE_TX_P[3]}] +set_property PACKAGE_PIN AG6 [get_ports {PCIE_TX_P[4]}] +set_property PACKAGE_PIN AF8 [get_ports {PCIE_TX_P[5]}] +set_property PACKAGE_PIN AE6 [get_ports {PCIE_TX_P[6]}] +set_property PACKAGE_PIN AD8 [get_ports {PCIE_TX_P[7]}] +set_property PACKAGE_PIN AC6 [get_ports {PCIE_TX_P[8]}] +set_property PACKAGE_PIN AB8 [get_ports {PCIE_TX_P[9]}] +set_property PACKAGE_PIN AA6 [get_ports {PCIE_TX_P[10]}] +set_property PACKAGE_PIN Y8 [get_ports {PCIE_TX_P[11]}] +set_property PACKAGE_PIN W6 [get_ports {PCIE_TX_P[12]}] +set_property PACKAGE_PIN V8 [get_ports {PCIE_TX_P[13]}] +set_property PACKAGE_PIN U6 [get_ports {PCIE_TX_P[14]}] +set_property PACKAGE_PIN T8 [get_ports {PCIE_TX_P[15]}] + +set_property PACKAGE_PIN AL5 [get_ports {PCIE_TX_N[0]}] +set_property PACKAGE_PIN AK7 [get_ports {PCIE_TX_N[1]}] +set_property PACKAGE_PIN AJ5 [get_ports {PCIE_TX_N[2]}] +set_property PACKAGE_PIN AH7 [get_ports {PCIE_TX_N[3]}] +set_property PACKAGE_PIN AG5 [get_ports {PCIE_TX_N[4]}] +set_property PACKAGE_PIN AF7 [get_ports {PCIE_TX_N[5]}] +set_property PACKAGE_PIN AE5 [get_ports {PCIE_TX_N[6]}] +set_property PACKAGE_PIN AD7 [get_ports {PCIE_TX_N[7]}] +set_property PACKAGE_PIN AC5 [get_ports {PCIE_TX_N[8]}] +set_property PACKAGE_PIN AB7 [get_ports {PCIE_TX_N[9]}] +set_property PACKAGE_PIN AA5 [get_ports {PCIE_TX_N[10]}] +set_property PACKAGE_PIN Y7 [get_ports {PCIE_TX_N[11]}] +set_property PACKAGE_PIN W5 [get_ports {PCIE_TX_N[12]}] +set_property PACKAGE_PIN V7 [get_ports {PCIE_TX_N[13]}] +set_property PACKAGE_PIN U5 [get_ports {PCIE_TX_N[14]}] +set_property PACKAGE_PIN T7 [get_ports {PCIE_TX_N[15]}] + +#################################################################################### +# Processing System Peripherals IO Constraints +##################################################################################### + +# set_property PACKAGE_PIN B2 [get_ports PS_PCIE_RST] +# set_property PACKAGE_PIN B1 [get_ports PS_PCIE_INT] diff --git a/cards/iwave/g35p/constr/qsfp.xdc b/cards/iwave/g35p/constr/qsfp.xdc new file mode 100644 index 000000000..987e1c3e4 --- /dev/null +++ b/cards/iwave/g35p/constr/qsfp.xdc @@ -0,0 +1,136 @@ +# qsfp.xdc +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +##################################################################################### +# QSFP Clock +##################################################################################### +set_property PACKAGE_PIN N32 [get_ports {QSFP0_REFCLK_P}] +set_property PACKAGE_PIN N33 [get_ports {QSFP0_REFCLK_N}] + +set_property PACKAGE_PIN U32 [get_ports {QSFP1_REFCLK_P}] +set_property PACKAGE_PIN U33 [get_ports {QSFP1_REFCLK_N}] + +create_clock -period 6.4 [get_ports {QSFP0_REFCLK_P}] +create_clock -period 6.4 [get_ports {QSFP1_REFCLK_P}] + +##################################################################################### +# QSFP Data (Up to 200Gbps) - Line rate is 25Gbps +# Connector 1 +##################################################################################### +set_property PACKAGE_PIN G41 [get_ports {QSFP0_RX_P[0]}] +set_property PACKAGE_PIN F39 [get_ports {QSFP0_RX_P[1]}] +set_property PACKAGE_PIN E41 [get_ports {QSFP0_RX_P[2]}] +set_property PACKAGE_PIN D39 [get_ports {QSFP0_RX_P[3]}] +# set_property PACKAGE_PIN L41 [get_ports {QSFP0_RX_P[4]}] +# set_property PACKAGE_PIN K39 [get_ports {QSFP0_RX_P[5]}] +# set_property PACKAGE_PIN J41 [get_ports {QSFP0_RX_P[6]}] +# set_property PACKAGE_PIN H39 [get_ports {QSFP0_RX_P[7]}] + +set_property PACKAGE_PIN H34 [get_ports {QSFP0_TX_P[0]}] +set_property PACKAGE_PIN G36 [get_ports {QSFP0_TX_P[1]}] +set_property PACKAGE_PIN F34 [get_ports {QSFP0_TX_P[2]}] +set_property PACKAGE_PIN E36 [get_ports {QSFP0_TX_P[3]}] +# set_property PACKAGE_PIN M34 [get_ports {QSFP0_TX_P[4]}] +# set_property PACKAGE_PIN L36 [get_ports {QSFP0_TX_P[5]}] +# set_property PACKAGE_PIN K34 [get_ports {QSFP0_TX_P[6]}] +# set_property PACKAGE_PIN J36 [get_ports {QSFP0_TX_P[7]}] + +set_property PACKAGE_PIN G42 [get_ports {QSFP0_RX_N[0]}] +set_property PACKAGE_PIN F40 [get_ports {QSFP0_RX_N[1]}] +set_property PACKAGE_PIN E42 [get_ports {QSFP0_RX_N[2]}] +set_property PACKAGE_PIN D40 [get_ports {QSFP0_RX_N[3]}] +# set_property PACKAGE_PIN L42 [get_ports {QSFP0_RX_N[4]}] +# set_property PACKAGE_PIN K40 [get_ports {QSFP0_RX_N[5]}] +# set_property PACKAGE_PIN J42 [get_ports {QSFP0_RX_N[6]}] +# set_property PACKAGE_PIN H40 [get_ports {QSFP0_RX_N[7]}] + +set_property PACKAGE_PIN H35 [get_ports {QSFP0_TX_N[0]}] +set_property PACKAGE_PIN G37 [get_ports {QSFP0_TX_N[1]}] +set_property PACKAGE_PIN F35 [get_ports {QSFP0_TX_N[2]}] +set_property PACKAGE_PIN E37 [get_ports {QSFP0_TX_N[3]}] +# set_property PACKAGE_PIN M35 [get_ports {QSFP0_TX_N[4]}] +# set_property PACKAGE_PIN L37 [get_ports {QSFP0_TX_N[5]}] +# set_property PACKAGE_PIN K35 [get_ports {QSFP0_TX_N[6]}] +# set_property PACKAGE_PIN J37 [get_ports {QSFP0_TX_N[7]}] + +##################################################################################### +# QSFP Data (Up to 200Gbps) - Line rate is 25Gbps +# Connector 2 +##################################################################################### +set_property PACKAGE_PIN R41 [get_ports {QSFP1_RX_P[0]}] +set_property PACKAGE_PIN P39 [get_ports {QSFP1_RX_P[1]}] +set_property PACKAGE_PIN N41 [get_ports {QSFP1_RX_P[2]}] +set_property PACKAGE_PIN M39 [get_ports {QSFP1_RX_P[3]}] +# set_property PACKAGE_PIN W41 [get_ports {QSFP1_RX_P[4]}] +# set_property PACKAGE_PIN V39 [get_ports {QSFP1_RX_P[5]}] +# set_property PACKAGE_PIN U41 [get_ports {QSFP1_RX_P[6]}] +# set_property PACKAGE_PIN T39 [get_ports {QSFP1_RX_P[7]}] + +set_property PACKAGE_PIN T34 [get_ports {QSFP1_TX_P[0]}] +set_property PACKAGE_PIN R36 [get_ports {QSFP1_TX_P[1]}] +set_property PACKAGE_PIN P34 [get_ports {QSFP1_TX_P[2]}] +set_property PACKAGE_PIN N36 [get_ports {QSFP1_TX_P[3]}] +# set_property PACKAGE_PIN Y34 [get_ports {QSFP1_TX_P[4]}] +# set_property PACKAGE_PIN W36 [get_ports {QSFP1_TX_P[5]}] +# set_property PACKAGE_PIN V34 [get_ports {QSFP1_TX_P[6]}] +# set_property PACKAGE_PIN U36 [get_ports {QSFP1_TX_P[7]}] + +set_property PACKAGE_PIN R42 [get_ports {QSFP1_RX_N[0]}] +set_property PACKAGE_PIN P40 [get_ports {QSFP1_RX_N[1]}] +set_property PACKAGE_PIN N42 [get_ports {QSFP1_RX_N[2]}] +set_property PACKAGE_PIN M40 [get_ports {QSFP1_RX_N[3]}] +# set_property PACKAGE_PIN W42 [get_ports {QSFP1_RX_N[4]}] +# set_property PACKAGE_PIN V40 [get_ports {QSFP1_RX_N[5]}] +# set_property PACKAGE_PIN U42 [get_ports {QSFP1_RX_N[6]}] +# set_property PACKAGE_PIN T40 [get_ports {QSFP1_RX_N[7]}] + +set_property PACKAGE_PIN T35 [get_ports {QSFP1_TX_N[0]}] +set_property PACKAGE_PIN R37 [get_ports {QSFP1_TX_N[1]}] +set_property PACKAGE_PIN P35 [get_ports {QSFP1_TX_N[2]}] +set_property PACKAGE_PIN N37 [get_ports {QSFP1_TX_N[3]}] +# set_property PACKAGE_PIN Y35 [get_ports {QSFP1_TX_N[4]}] +# set_property PACKAGE_PIN W37 [get_ports {QSFP1_TX_N[5]}] +# set_property PACKAGE_PIN V35 [get_ports {QSFP1_TX_N[6]}] +# set_property PACKAGE_PIN U37 [get_ports {QSFP1_TX_N[7]}] + +##################################################################################### +# QSFP Control signals GPIO Constraints +##################################################################################### +set_property PACKAGE_PIN B8 [get_ports {QSFP0_MODSEL_N}] +set_property PACKAGE_PIN A8 [get_ports {QSFP0_RESET_N}] +set_property PACKAGE_PIN J9 [get_ports {QSFP0_LPMODE}] +set_property PACKAGE_PIN H9 [get_ports {QSFP0_INT_N}] +set_property PACKAGE_PIN C8 [get_ports {QSFP0_MODPRS_N}] + +set_property PACKAGE_PIN D8 [get_ports {QSFP1_MODSEL_N}] +set_property PACKAGE_PIN E9 [get_ports {QSFP1_RESET_N}] +set_property PACKAGE_PIN F9 [get_ports {QSFP1_LPMODE}] +set_property PACKAGE_PIN D9 [get_ports {QSFP1_INT_N}] +set_property PACKAGE_PIN C9 [get_ports {QSFP1_MODPRS_N}] + +# set_property PACKAGE_PIN E6 [get_ports {QSFP2_MODSEL_N}] +# set_property PACKAGE_PIN D6 [get_ports {QSFP2_RESET_N}] +# set_property PACKAGE_PIN F6 [get_ports {QSFP2_LPMODE}] +# set_property PACKAGE_PIN G6 [get_ports {QSFP2_INT_N}] +# set_property PACKAGE_PIN A5 [get_ports {QSFP2_MODPRS_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP0_MODSEL_N}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP0_RESET_N}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP0_LPMODE}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP0_INT_N}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP0_MODPRS_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP1_MODSEL_N}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP1_RESET_N}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP1_LPMODE}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP1_INT_N}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP1_MODPRS_N}] + +# set_property IOSTANDARD LVCMOS33 [get_ports {QSFP2_MODSEL_N}] +# set_property IOSTANDARD LVCMOS33 [get_ports {QSFP2_RESET_N}] +# set_property IOSTANDARD LVCMOS33 [get_ports {QSFP2_LPMODE}] +# set_property IOSTANDARD LVCMOS33 [get_ports {QSFP2_INT_N}] +# set_property IOSTANDARD LVCMOS33 [get_ports {QSFP2_MODPRS_N}] diff --git a/cards/iwave/g35p/readme.rst b/cards/iwave/g35p/readme.rst new file mode 100644 index 000000000..a0f1a6f10 --- /dev/null +++ b/cards/iwave/g35p/readme.rst @@ -0,0 +1,53 @@ +.. _card_g35p: + +iWave G35P +------------- + +- Card information: + - Vendor: iWave + - Name: G35P + - Ethernet ports: 3x QSFP-DD + - 2x 200G + - 1x 40G + - PCIe conectors: Edge connector + - `FPGA Card Website `_ +- FPGA specification: + - FPGA part number: ``xczu19eg-ffvc1760-2-i`` + - Ethernet Hard IP: CMAC (up to 100G Ethernet) + - PCIe Hard IP: USP (up to PCIe Gen3 x16) + +NDK firmware support +^^^^^^^^^^^^^^^^^^^^ + +- Ethernet cores that are supported in the NDK firmware: + - :ref:`CMAC in the Network Module ` +- PCIe cores that are supported in the NDK firmware: + - :ref:`USP in the PCIe Module ` + - See the ``/card/iwave/g35p/config/card_conf.tcl`` file for supported PCIe configurations. +- Makefile targets for building the NDK firmware (valid for Minimal app, may vary for other apps): + - Use ``make 100g2`` command for firmware with 2x100GbE (default). +- Support for booting the NDK firmware using the nfb-boot tool: + - NO. + +Boot instructions +^^^^^^^^^^^^^^^^^ + +- Set Switch 1 (SW1(3:0)) to SD1 mode: + - SW1(0) - ON + - SW1(1) - OFF + - SW1(2) - ON + - SW1(3) - OFF +- Note that default setting is set to SW1: OFF ON ON OFF +- Note that SW1 is present on the SOM module (under the heatsink) + +- Write the BOOT.bin file to the SD card: + - BOOT.bin can be generated by `AMD VitisTM ` + - In order to generate BOOT.bin, it is necessary to have the fsbl.elf file (first stage boot loader) and the generated bit stream. + - [bootloader] zynqmp_fsbl.elf + - [destination_device = pl] fpga.bit + +- Insert the SD card into the SD connector at the bottom of the FPGA card. + +.. note:: + + To build the NDK firmware for this card, you must have the Xilinx Vivado installed, including a valid license. diff --git a/cards/iwave/g35p/src/Modules.tcl b/cards/iwave/g35p/src/Modules.tcl new file mode 100644 index 000000000..00ca743fd --- /dev/null +++ b/cards/iwave/g35p/src/Modules.tcl @@ -0,0 +1,28 @@ +# Modules.tcl: script to compile iWave G35P +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# converting input list to associative array +array set ARCHGRP_ARR $ARCHGRP + +# Paths +set FPGA_COMMON_BASE "$ARCHGRP_ARR(CORE_BASE)/top" + +# Components +lappend COMPONENTS [list "FPGA_COMMON" $FPGA_COMMON_BASE $ARCHGRP] + +# IP components +source $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/common.tcl + +set ARCHGRP_ARR(IP_MODIFY_BASE) $ENTITY_BASE/ip +set ARCHGRP_ARR(USE_IP_SUBDIRS) true + +lappend IP_COMPONENTS [list "eth" "cmac_eth_1x100g" "cmac_eth_1x100g" 0 1] +lappend IP_COMPONENTS [list "pcie" "pcie4_uscale_plus" "pcie4_uscale_plus" 0 1] + +lappend MOD {*}[get_ip_mod_files $IP_COMPONENTS [array get ARCHGRP_ARR]] + +# Top-level +lappend MOD "$ENTITY_BASE/fpga.vhd" diff --git a/cards/iwave/g35p/src/Vivado.inc.tcl b/cards/iwave/g35p/src/Vivado.inc.tcl new file mode 100644 index 000000000..47e029fc8 --- /dev/null +++ b/cards/iwave/g35p/src/Vivado.inc.tcl @@ -0,0 +1,49 @@ +# Vivado.inc.tcl: Vivado.tcl include for iWave G35P +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + + +# Source configuration files(populates all variables from env) +source $env(CORE_BASE)/config/core_bootstrap.tcl + +# Include CORE script +source $CORE_BASE/Vivado.inc.tcl + +# Design parameters +set SYNTH_FLAGS(MODULE) "fpga" +set SYNTH_FLAGS(FPGA) "xczu19eg-ffvc1760-2-i" +#SMAPx8, SMAPx16, SMAPx32, SERIALx1, SPIx1, SPIx2, SPIx4, SPIx8, BPIx8, BPIx16. +set SYNTH_FLAGS(MCS_IFACE) "SPIx4" +set SYNTH_FLAGS(BOARD) $CARD_NAME + +# Optimization directives for implementation +set SYNTH_FLAGS(SOPT_DIRECTIVE) "Explore" +set SYNTH_FLAGS(PLACE_DIRECTIVE) "Explore" +set SYNTH_FLAGS(POPT_DIRECTIVE) "Explore" +set SYNTH_FLAGS(ROUTE_DIRECTIVE) "Explore" + +# Propagating card constants to the Modules.tcl files of the underlying components. +# The description of usage of this array is provided in the Parametrization section +# of the NDK-CORE repository documentation. +set CARD_ARCHGRP(CORE_BASE) $CORE_BASE +set CARD_ARCHGRP(IP_BUILD_DIR) $CARD_BASE/src/ip +set CARD_ARCHGRP(IP_GEN_FILES) false +set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE + +# make lists from associative arrays +set CARD_ARCHGRP_L [array get CARD_ARCHGRP] +set CORE_ARCHGRP_L [array get CORE_ARCHGRP] + +# concatenate lists to be handed as a part of the ARCHGRP to the TOPLEVEL +set ARCHGRP_ALL [concat $CARD_ARCHGRP_L $CORE_ARCHGRP_L] + +# Main component +lappend HIERARCHY(COMPONENTS) [list "TOPLEVEL" $CARD_BASE/src $ARCHGRP_ALL] + +# XDC constraints for specific parts of the design +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/general.xdc" +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pcie.xdc" +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/qsfp.xdc" +lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/gty_loc.xdc" diff --git a/cards/iwave/g35p/src/card.mk b/cards/iwave/g35p/src/card.mk new file mode 100644 index 000000000..43ec8aee7 --- /dev/null +++ b/cards/iwave/g35p/src/card.mk @@ -0,0 +1,44 @@ +# card.mk: Makefile include for iWave G35P +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + + +# Optional parameters (can be changed in user Makefile) +############################################################################### + +# Name for output files (rootname) +# This value is set as default in SYNTH_FLAGS(OUTPUT) +OUTPUT_NAME ?= IWAVE-G35P + +USER_ENV ?= + +# Private parameters (do not change these values in user Makefile) +############################################################################### + +# Get directory of this Makefile.inc +CARD_BASE_LOCAL := $(dir $(lastword $(MAKEFILE_LIST))) +CARD_BASE ?= $(CARD_BASE_LOCAL)/.. +CORE_BASE ?= $(COMBO_BASE)/core + +# Load correct paths to build system +include $(CORE_BASE)/ndk_paths.mk + +NETCOPE_ENV = \ + OFM_PATH=$(OFM_PATH)\ + COMBO_BASE=$(COMBO_BASE)\ + FIRMWARE_BASE=$(FIRMWARE_BASE)\ + CARD_BASE=$(CARD_BASE) \ + CORE_BASE=$(CORE_BASE) \ + APP_CONF=$(APP_CONF) \ + OUTPUT_NAME=$(OUTPUT_NAME) \ + ETH_PORTS=$(ETH_PORTS) \ + ETH_PORT_SPEED=$(ETH_PORT_SPEED) \ + ETH_PORT_CHAN=$(ETH_PORT_CHAN) \ + ETH_PORT_TYPE=$(ETH_PORT_TYPE) \ + DMA_TYPE=$(DMA_TYPE) \ + $(USER_ENV) + +include $(CORE_BASE)/core.mk +include $(OFM_PATH)/build/Makefile.Vivado.inc diff --git a/cards/iwave/g35p/src/fpga.vhd b/cards/iwave/g35p/src/fpga.vhd new file mode 100644 index 000000000..88302ed2a --- /dev/null +++ b/cards/iwave/g35p/src/fpga.vhd @@ -0,0 +1,289 @@ +-- fpga.vhd: iWave G35P card top-level entity and architecture +-- Copyright (C) 2024 BrnoLogic, Ltd. +-- Author(s): David Beneš +-- +-- SPDX-License-Identifier: BSD-3-Clause + +library ieee; +library unisim; +library xpm; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.combo_const.all; +use work.combo_user_const.all; + +use work.math_pack.all; +use work.type_pack.all; +use work.dma_bus_pack.all; + +use unisim.vcomponents.all; + +entity FPGA is +port ( + -- 300 Mhz external clock + SYSCLK : in std_logic; + + -- PCIe gen3x16 + PCIE_SYSCLK_P : in std_logic; + PCIE_SYSCLK_N : in std_logic; + PCIE_SYSRST_N : in std_logic; + PCIE_RX_P : in std_logic_vector(PCIE_LANES -1 downto 0); + PCIE_RX_N : in std_logic_vector(PCIE_LANES -1 downto 0); + PCIE_TX_P : out std_logic_vector(PCIE_LANES -1 downto 0); + PCIE_TX_N : out std_logic_vector(PCIE_LANES -1 downto 0); + + -- QSFP-DD Control signals + -- SCL & SDA are not supported + QSFP0_LPMODE : out std_logic; + QSFP0_RESET_N : out std_logic; + QSFP0_MODPRS_N : in std_logic; + QSFP0_INT_N : in std_logic; + QSFP0_MODSEL_N : out std_logic; + + QSFP1_LPMODE : out std_logic; + QSFP1_RESET_N : out std_logic; + QSFP1_MODPRS_N : in std_logic; + QSFP1_INT_N : in std_logic; + QSFP1_MODSEL_N : out std_logic; + + --QSFP data + QSFP0_REFCLK_P : in std_logic; + QSFP0_REFCLK_N : in std_logic; + QSFP0_RX_P : in std_logic_vector(3 downto 0); + QSFP0_RX_N : in std_logic_vector(3 downto 0); + QSFP0_TX_P : out std_logic_vector(3 downto 0); + QSFP0_TX_N : out std_logic_vector(3 downto 0); + + QSFP1_REFCLK_P : in std_logic; + QSFP1_REFCLK_N : in std_logic; + QSFP1_RX_P : in std_logic_vector(3 downto 0); + QSFP1_RX_N : in std_logic_vector(3 downto 0); + QSFP1_TX_P : out std_logic_vector(3 downto 0); + QSFP1_TX_N : out std_logic_vector(3 downto 0) +); +end entity; + +architecture FULL of FPGA is + constant PCIE_CLKS : integer := 1; + constant PCIE_CONS : integer := 1; + constant MISC_IN_WIDTH : integer := 0; + constant MISC_OUT_WIDTH : integer := 4; + constant ETH_LANES : integer := 4; + constant DMA_MODULES : integer := PCIE_ENDPOINTS; + constant DMA_ENDPOINTS : integer := PCIE_ENDPOINTS; + constant ETH_LANE_MAP : integer_vector(2*ETH_LANES-1 downto 0) := (3, 2, 1, 0, 3, 2, 1, 0); + constant ETH_LANE_RXPOLARITY : std_logic_vector(2*ETH_LANES-1 downto 0) := "00000000"; + constant ETH_LANE_TXPOLARITY : std_logic_vector(2*ETH_LANES-1 downto 0) := "00000000"; + constant DEVICE : string := "ULTRASCALE"; + + -- DDR constants -- + constant DDR_PORTS : integer := MEM_PORTS; + -- constant DDR_ADDR_WIDTH : integer := 29; + -- constant DDR_BYTES : integer := 9; + -- constant DDR_AXI_ADDR_WIDTH : integer := 32; + -- constant DDR_AXI_DATA_WIDTH : integer := 512; + -- constant DDR_FREQ : natural := 333333; + -- constant AMM_DATA_WIDTH : integer := 512; + -- constant AMM_BURST_COUNT_WIDTH : integer := 8; + -- constant AMM_ADDR_WIDTH : integer := 26; + -- constant REFR_PERIOD_WIDTH : integer := 32; + + signal sysclk_ibuf : std_logic; + signal sysclk_bufg : std_logic; + signal sysrst_cnt : unsigned(20 downto 0) := (others => '0'); + signal sysrst : std_logic := '1'; + + signal eth_refclk_p : std_logic_vector(2 - 1 downto 0); + signal eth_refclk_n : std_logic_vector(2 - 1 downto 0); + + signal eth_rx_p : std_logic_vector(2*ETH_LANES-1 downto 0); + signal eth_rx_n : std_logic_vector(2*ETH_LANES-1 downto 0); + + signal eth_tx_p : std_logic_vector(2*ETH_LANES-1 downto 0); + signal eth_tx_n : std_logic_vector(2*ETH_LANES-1 downto 0); + + signal qsfp_modsel_n : std_logic_vector(2 - 1 downto 0); + signal qsfp_lpmode : std_logic_vector(2 - 1 downto 0); + signal qsfp_reset_n : std_logic_vector(2 - 1 downto 0); + signal qsfp_modprs_n : std_logic_vector(2 - 1 downto 0); + signal qsfp_int_n : std_logic_vector(2 - 1 downto 0); + +begin + + sysclk_ibuf_i : IBUFG + port map ( + I => SYSCLK, + O => sysclk_ibuf + ); + + sysclk_bufg_i : BUFG + port map ( + I => sysclk_ibuf, + O => sysclk_bufg + ); + + -- reset after power up + process(sysclk_bufg) + begin + if rising_edge(sysclk_bufg) then + if (sysrst_cnt(sysrst_cnt'high) = '0') then + sysrst_cnt <= sysrst_cnt + 1; + end if; + sysrst <= not sysrst_cnt(sysrst_cnt'high); + end if; + end process; + + -- QSFP MAPPING ------------------------------------------------------------ + eth_refclk_p <= QSFP0_REFCLK_P & QSFP1_REFCLK_P; + eth_refclk_n <= QSFP0_REFCLK_N & QSFP1_REFCLK_N; + + eth_rx_p <= QSFP0_RX_P & QSFP1_RX_P; + eth_rx_n <= QSFP0_RX_N & QSFP1_RX_N; + + QSFP0_TX_P <= eth_tx_p(2*ETH_LANES - 1 downto 1*ETH_LANES); + QSFP0_TX_N <= eth_tx_n(2*ETH_LANES - 1 downto 1*ETH_LANES); + QSFP1_TX_P <= eth_tx_p(1*ETH_LANES - 1 downto 0*ETH_LANES); + QSFP1_TX_N <= eth_tx_n(1*ETH_LANES - 1 downto 0*ETH_LANES); + + QSFP1_MODSEL_N <= qsfp_modsel_n(0); + QSFP0_MODSEL_N <= qsfp_modsel_n(1); + QSFP1_LPMODE <= qsfp_lpmode(0); + QSFP0_LPMODE <= qsfp_lpmode(1); + QSFP1_RESET_N <= qsfp_reset_n(0); + QSFP0_RESET_N <= qsfp_reset_n(1); + + qsfp_modprs_n <= QSFP0_MODPRS_N & QSFP1_MODPRS_N; + qsfp_int_n <= QSFP0_INT_N & QSFP1_INT_N; + + -- FPGA COMMON ------------------------------------------------------------- + cm_i : entity work.FPGA_COMMON + generic map ( + SYSCLK_PERIOD => 4.0, + PLL_MULT_F => 48.0, + PLL_MASTER_DIV => 10, + PLL_OUT0_DIV_F => 3.0, + PLL_OUT1_DIV => 4, + PLL_OUT2_DIV => 6, + PLL_OUT3_DIV => 12, + + USE_PCIE_CLK => TRUE, + + PCIE_LANES => PCIE_LANES, + PCIE_CLKS => PCIE_CLKS, + PCIE_CONS => PCIE_CONS, + + ETH_CORE_ARCH => NET_MOD_ARCH, + ETH_PORTS => ETH_PORTS, + ETH_PORT_SPEED => ETH_PORT_SPEED, + ETH_PORT_CHAN => ETH_PORT_CHAN, + ETH_LANES => ETH_LANES, + ETH_LANE_MAP => ETH_LANE_MAP(ETH_PORTS*ETH_LANES-1 downto 0), + ETH_LANE_RXPOLARITY => ETH_LANE_RXPOLARITY(ETH_PORTS*ETH_LANES-1 downto 0), + ETH_LANE_TXPOLARITY => ETH_LANE_TXPOLARITY(ETH_PORTS*ETH_LANES-1 downto 0), + + QSFP_PORTS => ETH_PORTS, + QSFP_I2C_PORTS => 2, -- fake ports + ETH_PORT_LEDS => 2, -- fake leds + + STATUS_LEDS => 2, + + MISC_IN_WIDTH => MISC_IN_WIDTH, + MISC_OUT_WIDTH => MISC_OUT_WIDTH, + + PCIE_ENDPOINTS => PCIE_ENDPOINTS, + PCIE_ENDPOINT_TYPE => PCIE_MOD_ARCH, + PCIE_ENDPOINT_MODE => PCIE_ENDPOINT_MODE, + + DMA_ENDPOINTS => DMA_ENDPOINTS, + DMA_MODULES => DMA_MODULES, + + DMA_RX_CHANNELS => DMA_RX_CHANNELS/DMA_MODULES, + DMA_TX_CHANNELS => DMA_TX_CHANNELS/DMA_MODULES, + + BOARD => CARD_NAME, + DEVICE => DEVICE, + + --AMM_FREQ_KHZ => DDR_FREQ, + MEM_PORTS => DDR_PORTS + --MEM_ADDR_WIDTH => AMM_ADDR_WIDTH, + --MEM_DATA_WIDTH => AMM_DATA_WIDTH, + --MEM_BURST_WIDTH => AMM_BURST_COUNT_WIDTH, + ) + port map( + SYSCLK => sysclk_bufg, + SYSRST => sysrst, + + PCIE_SYSCLK_P(0) => PCIE_SYSCLK_P, + PCIE_SYSCLK_N(0) => PCIE_SYSCLK_N, + PCIE_SYSRST_N(0) => PCIE_SYSRST_N, + PCIE_RX_P => PCIE_RX_P, + PCIE_RX_N => PCIE_RX_N, + PCIE_TX_P => PCIE_TX_P, + PCIE_TX_N => PCIE_TX_N, + + ETH_REFCLK_P => eth_refclk_p(ETH_PORTS-1 downto 0), + ETH_REFCLK_N => eth_refclk_n(ETH_PORTS-1 downto 0), + + ETH_RX_P => eth_rx_p(ETH_PORTS*ETH_LANES-1 downto 0), + ETH_RX_N => eth_rx_n(ETH_PORTS*ETH_LANES-1 downto 0), + ETH_TX_P => eth_tx_p(ETH_PORTS*ETH_LANES-1 downto 0), + ETH_TX_N => eth_tx_n(ETH_PORTS*ETH_LANES-1 downto 0), + + ETH_LED_R => open, + ETH_LED_G => open, + + QSFP_MODSEL_N => qsfp_modsel_n(ETH_PORTS-1 downto 0), + QSFP_LPMODE => qsfp_lpmode(ETH_PORTS-1 downto 0), + QSFP_RESET_N => qsfp_reset_n(ETH_PORTS-1 downto 0), + QSFP_MODPRS_N => qsfp_modprs_n(ETH_PORTS-1 downto 0), + QSFP_INT_N => qsfp_int_n(ETH_PORTS-1 downto 0), + + MEM_CLK => (others => '0'), + MEM_RST => (others => '0'), + + -- Avalon interface to mem_tester + -- MEM_AVMM_READY => (others => '0'), + -- MEM_AVMM_READ => open, + -- MEM_AVMM_WRITE => open, + -- MEM_AVMM_ADDRESS => open, + -- MEM_AVMM_BURSTCOUNT => open, + -- MEM_AVMM_WRITEDATA => open, + -- MEM_AVMM_READDATA => (others => (others => '0')), + -- MEM_AVMM_READDATAVALID => (others => '0'), + + -- MEM_REFR_PERIOD => open, + -- MEM_REFR_REQ => open, + -- MEM_REFR_ACK => (others => '1'), + + -- EMIF_RST_REQ => open, + -- EMIF_RST_DONE => (others => '0'), + -- EMIF_CAL_SUCCESS => (others => '0'), + -- EMIF_ECC_USR_INT => (others => '0'), + -- EMIF_CAL_FAIL => (others => '0'), + -- EMIF_AUTO_PRECHARGE => open, + + STATUS_LED_G => open, + STATUS_LED_R => open, + + PCIE_CLK => open, + PCIE_RESET => open, + + BOOT_MI_CLK => open, + BOOT_MI_RESET => open, + BOOT_MI_DWR => open, + BOOT_MI_ADDR => open, + BOOT_MI_RD => open, + BOOT_MI_WR => open, + BOOT_MI_BE => open, + BOOT_MI_DRD => (others => '0'), + BOOT_MI_ARDY => '0', + BOOT_MI_DRDY => '0', + + MISC_IN => (others => '0'), + MISC_OUT => open + ); + + +end architecture; diff --git a/cards/iwave/g35p/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.ip.tcl b/cards/iwave/g35p/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.ip.tcl new file mode 100644 index 000000000..b0d7de829 --- /dev/null +++ b/cards/iwave/g35p/src/ip/cmac_eth_1x100g/cmac_eth_1x100g.ip.tcl @@ -0,0 +1,25 @@ +array set PARAMS $IP_PARAMS_L + +set IP_COMP_NAME $PARAMS(IP_COMP_NAME) +if {[get_ips -quiet $IP_COMP_NAME] eq ""} { + if {$PARAMS(IP_GEN_FILES) eq true} { + create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME -dir $PARAMS(IP_BUILD_DIR) -force + } else { + create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME + } +} + +set IP [get_ips $IP_COMP_NAME] + +set_property -dict [list \ + CONFIG.ADD_GT_CNRL_STS_PORTS {1} \ + CONFIG.CMAC_CAUI4_MODE {1} \ + CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y2} \ + CONFIG.GT_GROUP_SELECT {X0Y12~X0Y15} \ + CONFIG.GT_REF_CLK_FREQ {156.25} \ + CONFIG.INCLUDE_RS_FEC {1} \ + CONFIG.NUM_LANES {4x25} \ + CONFIG.RX_FLOW_CONTROL {0} \ + CONFIG.RX_MAX_PACKET_LEN {16383} \ + CONFIG.TX_FLOW_CONTROL {0} \ +] $IP diff --git a/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl new file mode 100644 index 000000000..8ab9078f8 --- /dev/null +++ b/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl @@ -0,0 +1,86 @@ +array set PARAMS $IP_PARAMS_L + +set IP_COMP_NAME $PARAMS(IP_COMP_NAME) +if {[get_ips -quiet $IP_COMP_NAME] eq ""} { + if {$PARAMS(IP_GEN_FILES) eq true} { + create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME -dir $PARAMS(IP_BUILD_DIR) -force + } else { + create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name $IP_COMP_NAME + } +} + +set IP [get_ips $IP_COMP_NAME] + +# ============================================================================== +# general settings for each card +# ============================================================================== + +set VENDOR_ID {18ec} +set PF0_DEVICE_ID {c000} + +# specialties for the selected card +set_property -dict [list \ + CONFIG.disable_gt_loc {true} \ + CONFIG.en_gt_selection {true} \ + CONFIG.pcie_blk_locn {X1Y1} \ +] $IP + +# ============================================================================== +# common properties they should be the same for all cards +# ============================================================================== + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.ext_pcie_cfg_space_enabled {true} \ + CONFIG.extended_tag_field {true} \ + CONFIG.plltype {QPLL1} \ + CONFIG.axisten_freq {250} \ + CONFIG.AXISTEN_IF_ENABLE_CLIENT_TAG {true} \ + CONFIG.pf0_dev_cap_max_payload {512_bytes} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {false} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {64} \ + CONFIG.pf0_bar2_64bit {true} \ + CONFIG.pf0_bar2_prefetchable {false} \ + CONFIG.pf0_bar2_enabled {true} \ + CONFIG.pf0_bar2_scale {Megabytes} \ + CONFIG.pf0_bar2_size {16} \ + CONFIG.pf0_rbar_cap_bar0 {0xffffffffffff} \ + CONFIG.pf0_dsn_enabled {true} \ + CONFIG.pf0_msi_enabled {false} \ + CONFIG.pf0_msix_enabled {true} \ + CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ + CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ + CONFIG.MSI_X_OPTIONS {MSI-X_External} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.type1_membase_memlimit_enable {Disabled} \ + CONFIG.type1_prefetchable_membase_memlimit {Disabled} \ +] $IP + +if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} { + # x8_low_latency properties + set_property -dict [list \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + ] $IP +} else { + # x16 properties + set_property -dict [list \ + CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {false} \ + CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ + CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ + CONFIG.axisten_if_width {512_bit} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ + ] $IP +} + +# set PCIE IDs, must be in last set_property +set_property -dict [list \ + CONFIG.PF0_DEVICE_ID [subst $PF0_DEVICE_ID] \ + CONFIG.PF0_SUBSYSTEM_ID [subst $PF0_DEVICE_ID] \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID [subst $VENDOR_ID] \ + CONFIG.vendor_id [subst $VENDOR_ID] \ +] $IP diff --git a/doc/source/index.rst b/doc/source/index.rst index ec02180e2..95cf2d390 100644 --- a/doc/source/index.rst +++ b/doc/source/index.rst @@ -109,6 +109,7 @@ support a subset of these cards. A complete list of supported FPGA cards can be extra/nfb-200g2ql/readme ndk_cards/prodesign/pd-falcon/readme ndk_cards/terasic/a2700/readme + ndk_cards/iwave/g35p/readme --------