From cea5eaafb4e9077c64bd15c9f40fb928a0c8fb08 Mon Sep 17 00:00:00 2001 From: Martin Spinler Date: Fri, 23 Aug 2024 15:30:29 +0200 Subject: [PATCH] update issue2: MTC big read transasction --- tests/cocotb/issues/issue2.py | 38 ++++++++++++++++------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/tests/cocotb/issues/issue2.py b/tests/cocotb/issues/issue2.py index 6a2e913ed..6a845f5a9 100644 --- a/tests/cocotb/issues/issue2.py +++ b/tests/cocotb/issues/issue2.py @@ -24,39 +24,35 @@ def ms_add_cursor(name, time=None): ms.cmd(f"wave cursor add") ms.cmd(f'wave cursor configure -name {{{name}}} -time {{{time}}} -lock 1') +async def get_dev_init(dut): + dev = NFBDevice(dut) + await dev.init() + return dev, dev.nfb -async def wr_rd(c, length): + +async def wr_rd(c, length, offset=0): data = bytes([(j%256) for j in range(length)]) - await e(c.write)(0, data) - rdata = await e(c.read)(0, length) + await e(c.write)(offset, data) + rdata = await e(c.read)(offset, length) assert rdata == data, f'writen: {list(data)}, readen: {list(rdata)}' -@cocotb.test() + +@cocotb.test(timeout_time=400, timeout_unit='us') async def mtc_big_write_tr(dut): - ms_add_cursor("CQ WR REQ", "0.1us") - ms_add_cursor("CQ RD REQ", "0.104us") - ms_add_cursor("bad cq_data ", "1.42us") + dev, nfb = await get_dev_init(dut) + c = nfb.comp_open("cesnet,ofm,mi_test_space") + + await wr_rd(c, 126, 3) - dev = NFBDevice(dut) - await dev.init() - c = dev.nfb.comp_open("cesnet,ofm,mi_test_space") - # This one will pass through - #await wr_rd(c, 32) - # This one transfers correctly 32B, 4B incorrectly and then stucks! - await with_timeout( - wr_rd(c, 36), - 10, 'us', - ) - ) core = NFBDevice.core_instance_from_top(cocotb.top) +core_path = ms.cocotb2path(core) pci_core = core.pcie_i.pcie_core_i - MiBus(core.pcie_i, 'MI', 0, label='MI_PCIe').add_wave() -ms.cmd(f"log -recursive {ms.cocotb2path(core)}/*") -ms.cmd('add wave sim:/fpga/cm_i/pcie_i/pcie_ctrl_g(0)/pcie_ctrl_i/mtc_i/*') +ms.cmd(f"log -recursive {core_path}/*") +ms.cmd(f'add wave {core_path}/pcie_i/pcie_ctrl_g(0)/pcie_ctrl_i/mtc_i/*')