From c7ea6b56a0766b88a21b400a11ef6dbe91be4a65 Mon Sep 17 00:00:00 2001 From: yunchih Date: Fri, 21 Aug 2020 21:32:43 +0800 Subject: [PATCH 1/4] fix wrong average queue waiting time The value will explode when there is actually no requests destined for that queue. Should do a sanity check --- src/ssd/Queue_Probe.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/ssd/Queue_Probe.cpp b/src/ssd/Queue_Probe.cpp index b281585b..66413fa6 100644 --- a/src/ssd/Queue_Probe.cpp +++ b/src/ssd/Queue_Probe.cpp @@ -171,16 +171,20 @@ namespace SSD_Components sim_time_type Queue_Probe::AvgWaitingTime() { - return (sim_time_type)((double)totalWaitingTime / (double)(nDepartures * 1000));//convert nano-seconds to micro-seconds + if(nDepartures) + return (sim_time_type)((double)totalWaitingTime / (double)(nDepartures * 1000));//convert nano-seconds to micro-seconds + return 0; } sim_time_type Queue_Probe::AvgWaitingTimeEpoch() { - return (sim_time_type)((double)totalWaitingTimeEpoch / (double)(nDeparturesEpoch * 1000)); + if(nDeparturesEpoch) + return (sim_time_type)((double)totalWaitingTimeEpoch / (double)(nDeparturesEpoch * 1000)); + return 0; } sim_time_type Queue_Probe::TotalWaitingTime() { return totalWaitingTime; } -} \ No newline at end of file +} From c5eb00a327951a96127bfd904b32aedd52ed126d Mon Sep 17 00:00:00 2001 From: yunchih Date: Sun, 23 Aug 2020 19:25:41 +0800 Subject: [PATCH 2/4] Fix divide by zero In the rare case that Simulator->Time() < SIM_TIME_TO_SECONDS_COEFF, the XML output will be inf due to dividing by zero --- src/host/IO_Flow_Base.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/host/IO_Flow_Base.cpp b/src/host/IO_Flow_Base.cpp index 8de25ea6..0aebe599 100644 --- a/src/host/IO_Flow_Base.cpp +++ b/src/host/IO_Flow_Base.cpp @@ -543,15 +543,15 @@ IO_Flow_Base::IO_Flow_Base(const sim_object_id_type &name, uint16_t flow_id, LHA xmlwriter.Write_attribute_string(attr, val); attr = "IOPS"; - val = std::to_string((double)STAT_generated_request_count / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); + val = std::to_string((double)STAT_generated_request_count / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); xmlwriter.Write_attribute_string(attr, val); attr = "IOPS_Read"; - val = std::to_string((double)STAT_generated_read_request_count / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); + val = std::to_string((double)STAT_generated_read_request_count / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); xmlwriter.Write_attribute_string(attr, val); attr = "IOPS_Write"; - val = std::to_string((double)STAT_generated_write_request_count / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); + val = std::to_string((double)STAT_generated_write_request_count / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); xmlwriter.Write_attribute_string(attr, val); attr = "Bytes_Transferred"; @@ -567,15 +567,15 @@ IO_Flow_Base::IO_Flow_Base(const sim_object_id_type &name, uint16_t flow_id, LHA xmlwriter.Write_attribute_string(attr, val); attr = "Bandwidth"; - val = std::to_string((double)STAT_transferred_bytes_total / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); + val = std::to_string((double)STAT_transferred_bytes_total / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); xmlwriter.Write_attribute_string(attr, val); attr = "Bandwidth_Read"; - val = std::to_string((double)STAT_transferred_bytes_read / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); + val = std::to_string((double)STAT_transferred_bytes_read / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); xmlwriter.Write_attribute_string(attr, val); attr = "Bandwidth_Write"; - val = std::to_string((double)STAT_transferred_bytes_write / (Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); + val = std::to_string((double)STAT_transferred_bytes_write / ((double)Simulator->Time() / SIM_TIME_TO_SECONDS_COEFF)); xmlwriter.Write_attribute_string(attr, val); From aa36326420fbf65e82e0877a80727a09cb1c6eae Mon Sep 17 00:00:00 2001 From: yunchih Date: Sun, 30 Aug 2020 12:22:50 +0800 Subject: [PATCH 3/4] Cache manager bug fix * The missing return causes the WRITE_CACHE switch branch to fall into the default branch, causing an error * Fix memory leak --- src/ssd/Data_Cache_Manager_Flash_Advanced.cpp | 2 +- src/ssd/Data_Cache_Manager_Flash_Simple.cpp | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ssd/Data_Cache_Manager_Flash_Advanced.cpp b/src/ssd/Data_Cache_Manager_Flash_Advanced.cpp index 60b9bb07..4629ed5e 100644 --- a/src/ssd/Data_Cache_Manager_Flash_Advanced.cpp +++ b/src/ssd/Data_Cache_Manager_Flash_Advanced.cpp @@ -85,7 +85,7 @@ namespace SSD_Components break; } - delete per_stream_cache; + delete[] per_stream_cache; delete[] dram_execution_queue; delete[] waiting_user_requests_queue_for_dram_free_slot; delete[] bloom_filter; diff --git a/src/ssd/Data_Cache_Manager_Flash_Simple.cpp b/src/ssd/Data_Cache_Manager_Flash_Simple.cpp index af158d7f..2083b8d8 100644 --- a/src/ssd/Data_Cache_Manager_Flash_Simple.cpp +++ b/src/ssd/Data_Cache_Manager_Flash_Simple.cpp @@ -96,6 +96,8 @@ namespace SSD_Components if (user_request->Transaction_list.size() > 0) { static_cast(nvm_firmware)->Address_Mapping_Unit->Translate_lpa_to_ppa_and_dispatch(user_request->Transaction_list); } + + return; } default: PRINT_ERROR("The specified caching mode is not not support in simple cache manager!") @@ -113,6 +115,8 @@ namespace SSD_Components if (user_request->Transaction_list.size() > 0) { waiting_user_requests_queue_for_dram_free_slot[user_request->Stream_id].push_back(user_request); } + + return; } default: PRINT_ERROR("The specified caching mode is not not support in simple cache manager!") From bebe6d66905628172920a641479e1cfa02588581 Mon Sep 17 00:00:00 2001 From: yunchih Date: Sun, 30 Aug 2020 22:59:24 +0800 Subject: [PATCH 4/4] Check if reading NO_LPA if the user attempts to read a page that has never been written before, its LPA might be overwritten by NO_LPA. Check this corner case --- src/ssd/NVM_PHY_ONFI_NVDDR2.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/ssd/NVM_PHY_ONFI_NVDDR2.cpp b/src/ssd/NVM_PHY_ONFI_NVDDR2.cpp index 93403acb..0b659d95 100644 --- a/src/ssd/NVM_PHY_ONFI_NVDDR2.cpp +++ b/src/ssd/NVM_PHY_ONFI_NVDDR2.cpp @@ -326,7 +326,9 @@ namespace SSD_Components { { int i = 0; for (auto &address : command->Address) { - if (address.PlaneID == read_transaction->Address.PlaneID) { + // check if we are not reading a page that has not been written before + if (address.PlaneID == read_transaction->Address.PlaneID && + command->Meta_data[i].LPA != NO_LPA) { read_transaction->LPA = command->Meta_data[i].LPA; } i++;