diff --git a/AnalogGym/Charge Pump/__pycache__/chargepump.cpython-310.pyc b/AnalogGym/Charge Pump/__pycache__/chargepump.cpython-310.pyc new file mode 100644 index 0000000..c3473e9 Binary files /dev/null and b/AnalogGym/Charge Pump/__pycache__/chargepump.cpython-310.pyc differ diff --git a/AnalogGym/Charge Pump/__pycache__/chargepump.cpython-311.pyc b/AnalogGym/Charge Pump/__pycache__/chargepump.cpython-311.pyc new file mode 100644 index 0000000..847c965 Binary files /dev/null and b/AnalogGym/Charge Pump/__pycache__/chargepump.cpython-311.pyc differ diff --git a/AnalogGym/Charge Pump/chargepump.py b/AnalogGym/Charge Pump/chargepump.py new file mode 100644 index 0000000..d87137f --- /dev/null +++ b/AnalogGym/Charge Pump/chargepump.py @@ -0,0 +1,241 @@ +import os +import shutil +import subprocess +# import pickle +# import time +import math +import numpy as np +import re + +class ChargePump: + def __init__(self, index=0): + self.name = "ChargePump" + self.suffix = "" + self.index = index + self.dir = os.path.dirname(__file__) + assert os.path.exists(os.path.join(self.dir, "circuit")) + # self.database = "ChargePump.pkl" + self.mode = "spice" # or "ocean" + self.del_folders = True + + # Design Variables + ## DX = [('name',L,U,step,init,[discrete list]),....] if there is no discrete, do not write + self.DX = [ + ('q_llower', 3e-6, 9e-6, 1.0e-8, 6.9e-6, 'NO'), + ('q_wlower', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_lupper', 1e-6, 2e-6, 1.0e-8, 1.5e-6, 'NO'), + ('q_wupper', 5e-6, 20e-6, 1.0e-8, 10e-6, 'NO'), + ('q_lc', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_wc', 5e-6, 20e-6, 1.0e-8, 10e-6, 'NO'), + ('q_lref', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_wref', 5e-6, 20e-6, 1.0e-8, 6e-6, 'NO'), + ('q_lq', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_wq', 5e-6, 20e-6, 1.0e-8, 6e-6, 'NO'), + ('lpdbin', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wpdbin', 4e-6, 15e-6, 1.0e-8, 10e-6, 'NO'), + ('lpdin', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wpdin', 2e-6, 6e-6, 1.0e-8, 3e-6, 'NO'), + ('luumid', 0.6e-6, 1.2e-6, 1.0e-8, 1e-6, 'NO'), + ('wuumid', 5e-6, 20e-6, 1.0e-8, 10e-6, 'NO'), + ('lumid', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wumid', 8e-6, 25e-6, 1.0e-8, 10e-6, 'NO'), + ('lp4', 0.5e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wp4', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('ln4', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wn4', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('lnsupp', 0.5e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wnsupp', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('lnsupp2', 0.8e-6, 2.4e-6, 1.0e-8, 1e-6, 'NO'), + ('wnsupp2', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('li10', 2e-6, 10e-6, 1.0e-8, 3e-6, 'NO'), + ('wi10', 0.8e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('lb1', 2e-6, 10e-6, 1.0e-8, 3e-6, 'NO'), + ('wb1', 5e-6, 25e-6, 1.0e-8, 10e-6, 'NO'), + ('lb2', 2e-6, 8e-6, 1.0e-8, 3e-6, 'NO'), + ('wb2', 1e-6, 3e-6, 1.0e-8, 2e-6, 'NO'), + ('lb3', 0.5e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wb3', 1e-6, 6e-6, 1.0e-8, 2e-6, 'NO'), + ('lb4', 0.55e-6, 3e-6, 1.0e-8, 1e-6, 'NO'), + ('wb4', 4e-6, 16e-6, 1.0e-8, 8e-6, 'NO'), + ] + + self.in_dim = len(self.DX) + self.real_init = np.array([dx[4] for dx in self.DX]) + self.real_lb = np.array([dx[1] for dx in self.DX]) + self.real_ub = np.array([dx[2] for dx in self.DX]) + self.init = (self.real_init-self.real_lb)/(self.real_ub - self.real_lb) + + self.run_file = "sim.sh" + self.result_file = "de_result.po" + + self.perform_setting = { + "diff1": ("<", 20, None, None, "diff1", 200, 10), + "diff2": ("<", 20, None, None, "diff2", 200, 10), + "diff3": ("<", 5, None, None, "diff3", 50, 10), + "diff4": ("<", 5, None, None, "diff4", 50, 10), + "deviation": ("<", 5, None, None, "deviation", 50, 10), + "obj": (None, None, None, None, "obj", 1000, None) + } + + self.fom_setting = (100, None) + + def cal_fom(self, meas_dict): + fom = meas_dict["obj"] + return fom + + def write_param(self, dx_real_dict): + if self.mode == "spice": + with open("param", "w") as handler: + for dx_name, dx_real in dx_real_dict.items(): + handler.write(".param {}={}\n".format(dx_name, dx_real)) + elif self.mode == "ocean": + handler.write('ocnxlSweepVar(\"' + str(dx_name) + '\" ' + '\"' + str(dx_real) + '\")\n') + else: + raise Exception("unknown self.mode") + + def extract_perf(self, file_name, perf): + pattern_str = perf+'\s*=\s*([\d.eE+\-]+)' + pattern = re.compile(pattern_str) + with open(file_name, 'r') as f: + lines = f.readlines() + for line in lines: + result = pattern.search(line) + if result: + val = result.group(1) + return float(val) + return False + + ################################################################## + + def set_name_suffix(self, suffix): + self.suffix = suffix + return self + + def __call__(self, x, realx=False, index=None): + # while(os.path.exists("index_lock")): + # print("index is locked, wait for 1s") + # time.sleep(1) + # open("index_lock", "a").close() + # if os.path.exists("index.pkl"): + # with open("index.pkl", "rb") as fr: + # old_index = pickle.load(fr) + # tmp_index = old_index + 1 + # else: + # tmp_index = 0 + # with open("index.pkl", "wb") as fw: + # pickle.dump(tmp_index, fw) + # os.remove("index_lock") + if index is None: # sequentially + tmp_index = self.index + self.index += 1 + else: # parallel with index updated in global + tmp_index = index + tmp_dir = "{}_{}_{}".format(self.name, self.suffix, tmp_index) + if os.path.exists(tmp_dir): + shutil.rmtree(tmp_dir) + cwd = os.getcwd() + shutil.copytree( + os.path.join(self.dir, "circuit"), + os.path.join(cwd, tmp_dir) + ) + print("{} is created, waiting for simulation".format(tmp_dir)) + os.chdir(tmp_dir) + if not realx: + x_01 = x + dx_real_dict = self.dx_map(x_01) + else: + x_real = x + x_name = [dx[0] for dx in self.DX] + dx_real_dict = dict(zip(x_name,x_real)) + self.write_param(dx_real_dict) + subprocess.Popen([self.run_file]).wait() + print("{} simulation done".format(tmp_dir)) + meas_dict = self.read_meas(self.result_file) + fom = self.cal_fom(meas_dict) + cost = self.cal_cost(meas_dict, fom) + print("{} get cost {}".format(tmp_dir, cost)) + os.chdir(cwd) + # self.update_database(tmp_index, dx_real_dict, meas_dict, fom, cost) + if self.del_folders: + shutil.rmtree(tmp_dir) + return cost + + def dx_map(self, x_01): + dx_real_dict = {} + for dx_tup, dx_01 in zip(self.DX, x_01): + dx_name = dx_tup[0] + dx_lb = dx_tup[1] + dx_ub = dx_tup[2] + dx_step = dx_tup[3] + dx_real_range = dx_01*(dx_ub-dx_lb) + plus = 1 if (dx_real_range%dx_step)/dx_step >= 0.5 else 0 + round_range = dx_real_range//dx_step*dx_step + plus*dx_step + dx_real = round_range + dx_lb + if dx_real > dx_ub: + dx_real = dx_ub + if dx_real < dx_lb: + dx_real = dx_lb + dx_real_dict[dx_name] = dx_real + return dx_real_dict + + def read_meas(self, file_name): + meas_dict = {} + for perform_name, perform_tup in self.perform_setting.items(): + perform_value = self.extract_perf(file_name, perform_tup[4]) + if not perform_value: + perform_value = perform_tup[5] + meas_dict[perform_name] = perform_value + return meas_dict + + def cal_cost(self, meas_dict, fom): + cons_list = [] + for perform_name, perform_value in meas_dict.items(): + tup = self.perform_setting[perform_name] + spec_weight= tup[-1] if tup[-1] else 1 + if "<" in tup: + if tup[1] != 0: + cons_list.append( + (perform_value - tup[1])/abs(tup[1])*spec_weight + ) + else: + cons_list.append( + (2/(1+math.exp(-1*perform_value))-1)*spec_weight + ) + if ">" in tup: + if tup[3] != 0: + cons_list.append( + -(perform_value - tup[3])/abs(tup[3])*spec_weight + ) + else: + cons_list.append( + -(2/(1+math.exp(-1*perform_value))+1)*spec_weight + ) + if ("<" not in tup) and (">" not in tup): + continue + cons_cost = sum([x if x>0 else 0 for x in cons_list]) + fom_weight = self.fom_setting[-1] if self.fom_setting[-1] else 1 + fom_cost = (fom - self.fom_setting[0])/abs(self.fom_setting[0])*fom_weight + cost = cons_cost + fom_cost + return cost + + # def update_database(self, index, dx_real_dict, meas_dict, fom, cost): + # # Prepare datas + # x_real = [dx_real for dx_real in dx_real_dict.values()] + # while(os.path.exists("database_lock")): + # print("database is locked, wait for 1s") + # time.sleep(1) + # open("database_lock", "a").close() + # if os.path.exists(self.database): + # with open(self.database, "rb") as fr: + # datas = pickle.load(fr) + # datas.append(dict(index=index, x_real=x_real, meas=meas_dict, fom=fom, cost=cost, time=time.time())) + # else: + # datas = [dict(index=index, x_real=x_real, meas=meas_dict, fom=fom, cost=cost, time=time.time())] + # with open(self.database, "wb") as fw: + # pickle.dump(datas, fw) + # os.remove("database_lock") + +if __name__ == '__main__': + accia = ACCIA() + accia(accia.real_init, realx=True) + accia([0.5]*accia.in_dim) diff --git a/AnalogGym/Charge Pump/circuit/clear.sh b/AnalogGym/Charge Pump/circuit/clear.sh new file mode 100644 index 0000000..ee567ee --- /dev/null +++ b/AnalogGym/Charge Pump/circuit/clear.sh @@ -0,0 +1,5 @@ +rm -f *.info *.mt* *.ma* *.ms* *.lis +rm -f chgp.* +rm -f run_sim.info +rm -f result.po +rm -f de_result.po diff --git a/AnalogGym/Charge Pump/circuit/measure.py b/AnalogGym/Charge Pump/circuit/measure.py new file mode 100644 index 0000000..100c5ff --- /dev/null +++ b/AnalogGym/Charge Pump/circuit/measure.py @@ -0,0 +1,92 @@ +import numpy as np +import re +import sys + + +def get_simple_mt(mtName): + ''' + read simulation result from one .mt* file + ''' + pattern = re.compile(r'[\s\t]*([\de.-]+)[\s\t]+([\de.-]+)[\s\t]+([\de.-]+)[\s\t]+([\de.-]+).+') + + with open(mtName) as f: + lines = f.readlines() + result0 = pattern.match(lines[4]) + result1 = pattern.match(lines[5]) + + up_imin = float(result0.group(1))*1e6 + up_iavg = float(result0.group(2))*1e6 + up_imax = float(result0.group(3))*1e6 + lo_imin = float(result0.group(4))*1e6 + lo_iavg = float(result1.group(1))*1e6 + lo_imax = float(result1.group(2))*1e6 + + const = 40 + diff1 = up_imax - up_iavg + diff2 = up_iavg - up_imin + diff3 = lo_imax - lo_iavg + diff4 = lo_iavg - lo_imin + diff = diff1+diff2+diff3+diff4 + deviation = abs(up_iavg-const) + abs(lo_iavg-const) + fom = 0.3*diff+0.5*deviation + return fom,diff1,diff2,diff3,diff4,deviation + + +def get_result_mt(mtNameBas, num): + results = np.zeros((num,5)) + for i in range(num): + mtName = mtNameBas + str(i) + fom,diff1,diff2,diff3,diff4,deviation = get_simple_mt(mtName) + + results[i,0] = diff1 + results[i,1] = diff2 + results[i,2] = diff3 + results[i,3] = diff4 + results[i,4] = deviation + + diff1 = max(results[:,0]) + diff2 = max(results[:,1]) + diff3 = max(results[:,2]) + diff4 = max(results[:,3]) + diff = diff1+diff2+diff3+diff4 + deviation = max(results[:,4]) + fom = 0.3*diff+0.5*deviation + return fom,diff1,diff2,diff3,diff4,deviation + + +def write_de_result(fom, diff1, diff2, diff3, diff4, deviation): + with open('de_result.po','w') as f: + f.write('obj= '+str(fom)+'\n') + f.write('diff1= '+str(diff1)+'\n') + f.write('diff2= '+str(diff2)+'\n') + f.write('diff3= '+str(diff3)+'\n') + f.write('diff4= '+str(diff4)+'\n') + f.write('dev= '+str(deviation)+'\n') + +def write_resultpo(fom, diff1, diff2, diff3, diff4, deviation): + fom_cons = fom + diff1_cons = diff1 - 20 + diff2_cons = diff2 - 20 + diff3_cons = diff3 - 5 + diff4_cons = diff4 - 5 + dev_cons = deviation - 5 + content = str(fom_cons) +' '+ str(diff1_cons) +' '+ str(diff2_cons) +' '+ str(diff3_cons) +' '+ str(diff4_cons) +' '+ str(dev_cons) + with open('result.po','w') as f: + f.write(content) + + +def get_result(cornerNum, resultForm='de'): + if cornerNum==1: + fom,diff1,diff2,diff3,diff4,deviation = get_simple_mt('chgp.mt0') + else: + fom,diff1,diff2,diff3,diff4,deviation = get_result_mt('chgp.mt', cornerNum) + if resultForm=='de': + write_de_result(fom, diff1, diff2, diff3, diff4, deviation) + elif resultForm=='weibo': + write_resultpo(fom, diff1, diff2, diff3, diff4, deviation) + + +argv = sys.argv[1:] +cornerNum = argv[0] +resultForm = argv[1] +get_result(int(cornerNum), resultForm) \ No newline at end of file diff --git a/AnalogGym/Charge Pump/circuit/netlist b/AnalogGym/Charge Pump/circuit/netlist new file mode 100644 index 0000000..1b1fd92 --- /dev/null +++ b/AnalogGym/Charge Pump/circuit/netlist @@ -0,0 +1,742 @@ +** Library name: S013G_PLL +** Cell name: PLL_INV_TFF +** View name: schematic +.subckt PLL_INV_TFF in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xnm0 out in vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_INV_TFF +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_LVL +** View name: schematic +.subckt PLL_LVL in out _net1 _net0 vss vss33 +xpm4 net18 out _net0 _net0 pod33ll_ckt L=300e-9 W=700e-9 AD=245e-15 AS=245e-15 PD=2.1e-6 PS=2.1e-6 M=1 +xpm3 out net18 _net0 _net0 pod33ll_ckt L=300e-9 W=700e-9 AD=245e-15 AS=245e-15 PD=2.1e-6 PS=2.1e-6 M=1 +xnm2 net18 in vss33 vss33 nod33ll_ckt L=350e-9 W=4e-6 AD=840e-15 AS=1.12e-12 PD=4.42e-6 PS=6.56e-6 M=4 +xnm5 out net24 vss33 vss33 nod33ll_ckt L=350e-9 W=4e-6 AD=840e-15 AS=1.12e-12 PD=4.42e-6 PS=6.56e-6 M=4 +xi47 in net24 _net1 vss PLL_INV_TFF +.ends PLL_LVL +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INV_V33 +** View name: schematic +.subckt PLL_INV_V33 in out _net0 vss33 +xnm0 out in vss33 vss33 nod33ll_ckt L=350e-9 W=1e-6 AD=210e-15 AS=350e-15 PD=1.42e-6 PS=2.7e-6 M=2 +xpm2 out in _net0 _net0 pod33ll_ckt L=300e-9 W=2e-6 AD=420e-15 AS=700e-15 PD=2.42e-6 PS=4.7e-6 M=2 +.ends PLL_INV_V33 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_phase_dumy +** View name: schematic +.subckt PLL_phase_dumy in _net0 vss +xpm0 _net0 in _net0 _net0 p11ll_ckt L=40e-9 W=4.5e-6 AD=1.485e-12 AS=1.485e-12 PD=9.66e-6 PS=9.66e-6 M=1 +xnm0 vss in vss vss n11ll_ckt L=40e-9 W=1.5e-6 AD=495e-15 AS=495e-15 PD=3.66e-6 PS=3.66e-6 M=1 +.ends PLL_phase_dumy +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INV12_3P0 +** View name: schematic +.subckt PLL_INV12_3P0 in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=3.8e-6 AD=1.254e-12 AS=1.254e-12 PD=8.26e-6 PS=8.26e-6 M=2 +xnm0 out in vss vss n11ll_ckt L=40e-9 W=3e-6 AD=990e-15 AS=990e-15 PD=6.66e-6 PS=6.66e-6 M=1 +.ends PLL_INV12_3P0 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INV12_1P5_DUMMY +** View name: schematic +.subckt PLL_INV12_1P5_DUMMY in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=4.5e-6 AD=1.485e-12 AS=1.485e-12 PD=9.66e-6 PS=9.66e-6 M=1 +xpm1 out in vss vss n11ll_ckt L=40e-9 W=1.5e-6 AD=495e-15 AS=495e-15 PD=3.66e-6 PS=3.66e-6 M=1 +.ends PLL_INV12_1P5_DUMMY +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INV_SMALL +** View name: schematic +.subckt PLL_INV_SMALL in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=900e-9 AD=297e-15 AS=297e-15 PD=2.46e-6 PS=2.46e-6 M=1 +xnm0 out in vss vss n11ll_ckt L=40e-9 W=300e-9 AD=99e-15 AS=99e-15 PD=1.26e-6 PS=1.26e-6 M=1 +.ends PLL_INV_SMALL +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_delay12 +** View name: schematic +.subckt PLL_delay12 in out _net0 vss +xpm0 in vss out _net0 p11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm0 out _net0 in vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_delay12 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INV12_1P0 +** View name: schematic +.subckt PLL_INV12_1P0 in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=3.1e-6 AD=1.023e-12 AS=1.023e-12 PD=6.86e-6 PS=6.86e-6 M=1 +xnm0 out in vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_INV12_1P0 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_DFF_balance +** View name: schematic +.subckt PLL_DFF_balance ckin d q _net0 vss +xi13 net085 ck_ _net0 vss PLL_delay12 +xi12 net087 ck _net0 vss PLL_INV12_1P0 +xi16 ckin net087 _net0 vss PLL_INV12_1P0 +xi17 ckin net085 _net0 vss PLL_INV12_1P0 +xpm0 d ck net21 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xpm1 net9 net21 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=513e-15 AS=891e-15 PD=3.08e-6 PS=6.06e-6 M=2 +xpm7 net24 net9 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm2 net9 net21 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=190e-15 AS=330e-15 PD=1.38e-6 PS=2.66e-6 M=2 +xpm9 net24 ck net21 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xpm3 net9 ck_ net20 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xpm4 q net20 _net0 _net0 p11ll_ckt L=40e-9 W=1.4e-6 AD=266e-15 AS=462e-15 PD=1.78e-6 PS=3.46e-6 M=2 +xpm5 _net0 q net12 _net0 p11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xpm6 net20 ck net12 _net0 p11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xpm8 net21 ck_ net24 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm0 d ck_ net21 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm1 net9 ck net20 vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm2 q net20 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=190e-15 AS=330e-15 PD=1.38e-6 PS=2.66e-6 M=2 +xnm3 vss q net12 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm4 net20 ck_ net12 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm5 net24 net9 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_DFF_balance +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_DIV2 +** View name: schematic +.subckt PLL_DIV2 in out _net0 vss +xi0 in d out _net0 vss PLL_DFF_balance +xi1 out d _net0 vss PLL_INV12_1P0 +.ends PLL_DIV2 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_nand_TFF +** View name: schematic +.subckt PLL_nand_TFF in1 in2 out _net0 vss +xpm0 out in1 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm1 out in2 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xnm0 out in2 net29 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm1 net29 in1 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_nand_TFF +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_DFF_TFF +** View name: schematic +.subckt PLL_DFF_TFF cp d q qn rn _net0 vss +xi11 cpn net0151 _net0 vss PLL_INV_TFF +xi10 cp cpn _net0 vss PLL_INV_TFF +xpm0 net51 net0151 net36 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm12 qn net25 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm7 net24 rn _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm8 q net24 _net0 _net0 p11ll_ckt L=40e-9 W=2.6e-6 AD=858e-15 AS=858e-15 PD=5.86e-6 PS=5.86e-6 M=1 +xpm11 net25 net0151 net40 _net0 p11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xpm9 net40 net24 _net0 _net0 p11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xpm5 net24 net25 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm4 net25 cpn net61 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm2 net43 net61 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm3 net51 cpn net43 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm1 net61 net51 _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm01 net51 rn _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm111 net36 d _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xnm3 net32 d net64 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm4 net64 rn vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm15 qn net25 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm12 q net24 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm14 net5 net24 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm11 net24 net25 net58 vss n11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xnm13 net25 cpn net5 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm10 net58 rn vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm9 net25 net0151 net61 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm8 net55 rn vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm7 net12 net61 net55 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm6 net51 net0151 net12 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm5 net61 net51 vss vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm2 net51 cpn net32 vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_DFF_TFF +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_TFF +** View name: schematic +.subckt PLL_TFF clk crn q qn t _net0 vss resetn +xi5 resetn d net034 _net0 vss PLL_nand_TFF +xi6 net034 net7 _net0 vss PLL_INV_TFF +xi4 t tn _net0 vss PLL_INV_TFF +xi0 clk net7 q qn crn _net0 vss PLL_DFF_TFF +xpm1 q t d _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm0 qn tn d _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xnm0 d t qn vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm1 d tn q vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_TFF +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_Counter5 +** View name: schematic +.subckt PLL_Counter5 c clk crn _net0 vss +xi4 q1 q0 net30 _net0 vss PLL_nand_TFF +xi39 q2 resetn _net0 vss PLL_INV_TFF +xi30 q2 net26 _net0 vss PLL_INV_TFF +xi9 net26 c _net0 vss PLL_INV_TFF +xi10 net30 net069 _net0 vss PLL_INV_TFF +xi2 clk crn q2 net033 net069 _net0 vss resetn PLL_TFF +xi1 clk crn q1 net045 q0 _net0 vss resetn PLL_TFF +xi0 clk crn q0 net050 _net0 _net0 vss resetn PLL_TFF +.ends PLL_Counter5 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_DIV10 +** View name: schematic +.subckt PLL_DIV10 clk co crn _net0 vss +xi3 c1 net29 _net0 vss PLL_INV_TFF +xi4 net29 co _net0 vss PLL_INV_TFF +xi1 clk crn c1 net25 c _net0 vss _net0 PLL_TFF +xi0 c clk crn _net0 vss PLL_Counter5 +.ends PLL_DIV10 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INV_dec +** View name: schematic +.subckt PLL_INV_dec in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm1 out in vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +.ends PLL_INV_dec +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INVX2_1 +** View name: schematic +.subckt PLL_INVX2_1 a _net0 vss y +xpm0 y a _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm1 y a vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +.ends PLL_INVX2_1 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INVX3 +** View name: schematic +.subckt PLL_INVX3 in out _net0 vss +xnm3 out in _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +xnm0 out in vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +.ends PLL_INVX3 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_DFFR +** View name: schematic +.subckt PLL_DFFR clk d q reset _net0 vss +xi80 reset reset_ _net0 vss PLL_INV_dec +xi66 clk clk_ _net0 vss PLL_INV_dec +xi84 net62 _net0 vss net062 PLL_INVX2_1 +xi85 net086 q _net0 vss PLL_INVX3 +xpm2 net62 clk_ net084 _net0 p11ll_ckt L=40e-9 W=400e-9 AD=132e-15 AS=132e-15 PD=1.46e-6 PS=1.46e-6 M=1 +xpm3 net086 clk net33 _net0 p11ll_ckt L=500e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm11 net33 q _net0 _net0 p11ll_ckt L=500e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm88 net086 reset_ _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm99 net084 net062 _net0 _net0 p11ll_ckt L=500e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm38 net062 clk_ net086 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=2 +xpm1 d clk net62 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=2 +xnm2 net62 clk net066 vss n11ll_ckt L=40e-9 W=200e-9 AD=92.4e-15 AS=92.4e-15 PD=1.26e-6 PS=1.26e-6 M=1 +xnm3 net086 clk_ net061 vss n11ll_ckt L=1e-6 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm0 net061 q vss vss n11ll_ckt L=1e-6 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm102 net066 net062 vss vss n11ll_ckt L=1e-6 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm101 net62 reset vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm39 net062 clk net086 vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=2 +xnm22 d clk_ net62 vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=2 +.ends PLL_DFFR +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_DIV2_DIGI +** View name: schematic +.subckt PLL_DIV2_DIGI in out _net0 vss +xi0 in d out vss _net0 vss PLL_DFFR +xi1 out d _net0 vss PLL_INV_dec +.ends PLL_DIV2_DIGI +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_INV_RESET +** View name: schematic +.subckt PLL_INV_RESET in out reset _net0 vss +xpm2 out reset net12 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm1 net12 in _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm0 out in vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +.ends PLL_INV_RESET +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_DIV2_DIGI_RESET +** View name: schematic +.subckt PLL_DIV2_DIGI_RESET in out outb reset _net0 vss +xi0 in outb out reset _net0 vss PLL_DFFR +xi1 out outb reset _net0 vss PLL_INV_RESET +.ends PLL_DIV2_DIGI_RESET +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_XOR_12 +** View name: schematic +.subckt PLL_XOR_12 in1 in2 out _net0 vss +xi0 in1 net5 _net0 vss PLL_INV_dec +xpm0 in2 in1 out _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm1 out in2 in1 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm2 in2 net5 out vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm3 out in2 net5 vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +.ends PLL_XOR_12 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_NAND3I +** View name: schematic +.subckt PLL_NAND3I in1 in2 in3 out _net0 vss +xpm2 out in3 _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm6 out in2 _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xpm3 out in1 _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm1 out in1 net026 vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +xnm0 net023 in3 vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +xnm5 net026 in2 net023 vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +.ends PLL_NAND3I +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_NOR3I +** View name: schematic +.subckt PLL_NOR3I in1 in2 in3 out _net0 vss +xpm4 net033 in1 _net0 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +xpm2 net030 in2 net033 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +xpm3 out in3 net030 _net0 p11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=3 +xnm5 out in3 vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm0 out in2 vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +xnm1 out in1 vss vss n11ll_ckt L=40e-9 W=280e-9 AD=92.4e-15 AS=92.4e-15 PD=1.22e-6 PS=1.22e-6 M=1 +.ends PLL_NOR3I +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_LOCK_DETECTOR +** View name: schematic +.subckt PLL_LOCK_DETECTOR ck_ref lock lock_ref reset _net0 vss +xi85 n8 re_ref _net0 vss PLL_DIV2_DIGI +xi29 ck_ref n2 _net0 vss PLL_DIV2_DIGI +xi30 n2 n4 _net0 vss PLL_DIV2_DIGI +xi31 n4 n8 _net0 vss PLL_DIV2_DIGI +xi38 lock_ref q1 nq1 re _net0 vss PLL_DIV2_DIGI_RESET +xi39 q1 q2 nq2 re _net0 vss PLL_DIV2_DIGI_RESET +xi40 q2 q3 nq3 re _net0 vss PLL_DIV2_DIGI_RESET +xi41 q3 q4 nq4 re _net0 vss PLL_DIV2_DIGI_RESET +xi42 q4 q5 nq5 re _net0 vss PLL_DIV2_DIGI_RESET +xi43 q5 q6 nq6 re _net0 vss PLL_DIV2_DIGI_RESET +xi44 q6 q7 nq7 re _net0 vss PLL_DIV2_DIGI_RESET +xi45 q7 q8 nq8 re _net0 vss PLL_DIV2_DIGI_RESET +xi46 q8 q9 nq9 re _net0 vss PLL_DIV2_DIGI_RESET +xi83 reset_n re_ref re _net0 vss PLL_XOR_12 +xi128 reset _net0 vss reset_n PLL_INVX2_1 +xi90 nq6 nq5 nq4 net042 _net0 vss PLL_NAND3I +xi106 nq3 q2 nq1 net071 _net0 vss PLL_NAND3I +xi89 nq9 q8 q7 net034 _net0 vss PLL_NAND3I +xi101 nq6 nq5 nq4 net048 _net0 vss PLL_NAND3I +xi105 _net0 _net0 _net0 net0106 _net0 vss PLL_NAND3I +xi126 _net0 _net0 _net0 net0109 _net0 vss PLL_NAND3I +xi87 nq9 q8 nq7 net059 _net0 vss PLL_NAND3I +xi86 q6 q5 q4 net063 _net0 vss PLL_NAND3I +xi102 nq9 q8 q7 net092 _net0 vss PLL_NAND3I +xi92 net034 net042 net071 net068 _net0 vss PLL_NOR3I +xi103 net092 net048 net0106 net0100 _net0 vss PLL_NOR3I +xi108 net0100 vss net080 net099 _net0 vss PLL_NOR3I +xi93 net059 net063 net0109 net080 _net0 vss PLL_NOR3I +xi98 net099 lock_1 _net0 vss PLL_INV_dec +xi129 lock_ref lock_1 lock_2 reset_n _net0 vss PLL_DFFR +xi81 re_ref lock_2 lock reset_n _net0 vss PLL_DFFR +.ends PLL_LOCK_DETECTOR +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_vco_buffer +** View name: schematic +.subckt PLL_vco_buffer inn inp outn outp _net0 vss +xpm22 outp net096 _net0 _net0 p11ll_ckt L=40e-9 W=800e-9 AD=152e-15 AS=208e-15 PD=1.18e-6 PS=1.72e-6 M=4 +xpm0 net14 inn _net0 _net0 p11ll_ckt L=40e-9 W=600e-9 AD=198e-15 AS=198e-15 PD=1.86e-6 PS=1.86e-6 M=1 +xpm17 outn net080 _net0 _net0 p11ll_ckt L=40e-9 W=800e-9 AD=152e-15 AS=208e-15 PD=1.18e-6 PS=1.72e-6 M=4 +xpm23 net096 net088 _net0 _net0 p11ll_ckt L=40e-9 W=800e-9 AD=152e-15 AS=264e-15 PD=1.18e-6 PS=2.26e-6 M=2 +xpm21 net088 inp _net0 _net0 p11ll_ckt L=40e-9 W=600e-9 AD=198e-15 AS=198e-15 PD=1.86e-6 PS=1.86e-6 M=1 +xpm1 net080 net14 _net0 _net0 p11ll_ckt L=40e-9 W=800e-9 AD=152e-15 AS=264e-15 PD=1.18e-6 PS=2.26e-6 M=2 +xnm1 net080 net14 vss vss n11ll_ckt L=40e-9 W=800e-9 AD=264e-15 AS=264e-15 PD=2.26e-6 PS=2.26e-6 M=1 +xnm28 outp net096 vss vss n11ll_ckt L=40e-9 W=800e-9 AD=152e-15 AS=264e-15 PD=1.18e-6 PS=2.26e-6 M=2 +xnm29 net088 inp vss vss n11ll_ckt L=40e-9 W=800e-9 AD=264e-15 AS=264e-15 PD=2.26e-6 PS=2.26e-6 M=1 +xnm27 net096 net088 vss vss n11ll_ckt L=40e-9 W=800e-9 AD=264e-15 AS=264e-15 PD=2.26e-6 PS=2.26e-6 M=1 +xnm23 outn net080 vss vss n11ll_ckt L=40e-9 W=800e-9 AD=152e-15 AS=264e-15 PD=1.18e-6 PS=2.26e-6 M=2 +xnm0 net14 inn vss vss n11ll_ckt L=40e-9 W=800e-9 AD=264e-15 AS=264e-15 PD=2.26e-6 PS=2.26e-6 M=1 +.ends PLL_vco_buffer +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_delay_cell +** View name: schematic +.subckt PLL_delay_cell inn inp outn outp vdd_delay vss_delay +xpm0 outn inp vdd_delay vdd_delay p11ll_ckt L=340e-9 W=2e-6 AD=380e-15 AS=660e-15 PD=2.38e-6 PS=4.66e-6 M=2 +xpm1 outp inn vdd_delay vdd_delay p11ll_ckt L=340e-9 W=2e-6 AD=380e-15 AS=660e-15 PD=2.38e-6 PS=4.66e-6 M=2 +xnm1 outn outp vss_delay vss_delay n11ll_ckt L=340e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm0 outn inp vss_delay vss_delay n11ll_ckt L=340e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm3 outp inn vss_delay vss_delay n11ll_ckt L=340e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm2 outp outn vss_delay vss_delay n11ll_ckt L=340e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_delay_cell +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_delay_cell_dummy +** View name: schematic +.subckt PLL_delay_cell_dummy inn inp outn outp vdd_delay vss_delay +xpm0 vdd_delay vdd_delay vdd_delay vdd_delay p11ll_ckt L=340e-9 W=2e-6 AD=380e-15 AS=660e-15 PD=2.38e-6 PS=4.66e-6 M=2 +xpm1 vdd_delay vdd_delay vdd_delay vdd_delay p11ll_ckt L=340e-9 W=2e-6 AD=380e-15 AS=660e-15 PD=2.38e-6 PS=4.66e-6 M=2 +xnm1 outn outp vss_delay vss_delay n11ll_ckt L=340e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +xnm0 outn inp vss_delay vss_delay n11ll_ckt L=340e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm3 outp inn vss_delay vss_delay n11ll_ckt L=340e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm2 outp outn vss_delay vss_delay n11ll_ckt L=340e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_delay_cell_dummy +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_delay_cell_reset +** View name: schematic +.subckt PLL_delay_cell_reset outn outp reset resetn vdd12 vdd_delay vss_delay +xpm0 outn vdd12 vdd_delay vdd_delay p11ll_ckt L=40e-9 W=4.5e-6 AD=1.485e-12 AS=1.485e-12 PD=9.66e-6 PS=9.66e-6 M=1 +xpm1 outp resetn vdd_delay vdd_delay p11ll_ckt L=40e-9 W=4.5e-6 AD=1.485e-12 AS=1.485e-12 PD=9.66e-6 PS=9.66e-6 M=1 +xnm1 outp vss_delay vss_delay vss_delay n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm0 outn reset vss_delay vss_delay n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +.ends PLL_delay_cell_reset +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_VCO_8PHASE +** View name: schematic +.subckt PLL_VCO_8PHASE out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vctrl _net0 _net1 vss vss33 +xi9_0 ph_0 ph_4 out_0 out_4 _net0 vss PLL_vco_buffer +xi9_1 ph_1 ph_5 out_1 out_5 _net0 vss PLL_vco_buffer +xi9_2 ph_2 ph_6 out_2 out_6 _net0 vss PLL_vco_buffer +xi9_3 ph_3 ph_7 out_3 out_7 _net0 vss PLL_vco_buffer +xi0_0 ph_4 ph_0 ph_5 ph_1 vcovdd vss33 PLL_delay_cell +xi0_1 ph_5 ph_1 ph_6 ph_2 vcovdd vss33 PLL_delay_cell +xi0_2 ph_6 ph_2 ph_7 ph_3 vcovdd vss33 PLL_delay_cell +xi0_3 ph_7 ph_3 ph_0 ph_4 vcovdd vss33 PLL_delay_cell +xi18_0 net0157_0 net0156_0 net0116_0 net0115_0 vcovdd vss33 PLL_delay_cell_dummy +xi18_1 net0157_1 net0156_1 net0116_1 net0115_1 vcovdd vss33 PLL_delay_cell_dummy +xi18_2 net0157_2 net0156_2 net0116_2 net0115_2 vcovdd vss33 PLL_delay_cell_dummy +xi18_3 net0157_3 net0156_3 net0116_3 net0115_3 vcovdd vss33 PLL_delay_cell_dummy +xi17_0 net0157_0 net0156_0 vss33 _net0 _net0 vcovdd vss33 PLL_delay_cell_reset +xi17_1 net0157_1 net0156_1 vss33 _net0 _net0 vcovdd vss33 PLL_delay_cell_reset +xi17_2 net0157_2 net0156_2 vss33 _net0 _net0 vcovdd vss33 PLL_delay_cell_reset +xi17_3 net0157_3 net0156_3 vss33 _net0 _net0 vcovdd vss33 PLL_delay_cell_reset +xi5 ph_3 ph_7 reset resetn _net0 vcovdd vss33 PLL_delay_cell_reset +xi4_0 ph_0 ph_4 vss33 _net0 _net0 vcovdd vss33 PLL_delay_cell_reset +xi4_1 ph_1 ph_5 vss33 _net0 _net0 vcovdd vss33 PLL_delay_cell_reset +xi4_2 ph_2 ph_6 vss33 _net0 _net0 vcovdd vss33 PLL_delay_cell_reset +xnm1 vss33 _net1 vss33 vss33 nod33ll_ckt L=10e-6 W=15e-6 AD=5.25e-12 AS=5.25e-12 PD=30.7e-6 PS=30.7e-6 M=1 +xnm7 _net1 vctrl vcovdd vcovdd nod33ll_ckt L=400e-9 W=W3 AD=2.56667e-12 AS=2.56667e-12 PD=13.8467e-6 PS=13.8467e-6 M=3 +xpm0 net80 vcovdd _net0 _net0 p11ll_ckt L=40e-9 W=600e-9 AD=198e-15 AS=198e-15 PD=1.86e-6 PS=1.86e-6 M=1 +xpm2 reset resetn _net0 _net0 p11ll_ckt L=40e-9 W=3e-6 AD=990e-15 AS=990e-15 PD=6.66e-6 PS=6.66e-6 M=1 +xpm1 resetn net80 _net0 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm2 vss _net0 vss vss n11ll_ckt L=7e-6 W=25e-6 AD=8.25e-12 AS=8.25e-12 PD=50.66e-6 PS=50.66e-6 M=1 +xnm22 vss _net0 vss vss n11ll_ckt L=3e-6 W=6e-6 AD=1.308e-12 AS=1.308e-12 PD=7.636e-6 PS=7.636e-6 M=5 +xnm0 vss _net0 vss vss n11ll_ckt L=5.5e-6 W=8e-6 AD=1.52e-12 AS=1.8e-12 PD=8.38e-6 PS=10.45e-6 M=8 +xnm8 vss vcovdd net80 vss n11ll_ckt L=40e-9 W=800e-9 AD=264e-15 AS=264e-15 PD=2.26e-6 PS=2.26e-6 M=1 +xnm11 vss resetn reset vss n11ll_ckt L=40e-9 W=1.5e-6 AD=495e-15 AS=495e-15 PD=3.66e-6 PS=3.66e-6 M=1 +xnm01 vss net80 resetn vss n11ll_ckt L=40e-9 W=1e-6 AD=330e-15 AS=330e-15 PD=2.66e-6 PS=2.66e-6 M=1 +.ends PLL_VCO_8PHASE +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_nand_PD_2 +** View name: schematic +.subckt PLL_nand_PD_2 in1 in2 out _net0 vss +xpm2 out in1 _net0 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xpm1 out in2 _net0 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm0 net29 in1 vss vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm1 out in2 net29 vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +.ends PLL_nand_PD_2 +** End of subcircuit definition. + +** Library name: smic13mmrf_1233 +** Cell name: rpposab_ckt +** View name: schematic +.subckt rpposab_ckt_pcell2460 minus plus +xr0 plus minus rpposab_2t_ckt m=1 l=segl w=segw +.ends rpposab_ckt_pcell2460 +** End of subcircuit definition. + +** Library name: smic13mmrf_1233 +** Cell name: rpposab_ckt +** View name: schematic +.subckt rpposab_ckt_pcell2461 minus plus +xr3 n3 minus rpposab_2t_ckt m=1 l=segl w=segw +xr2 n2 n3 rpposab_2t_ckt m=1 l=segl w=segw +xr1 n1 n2 rpposab_2t_ckt m=1 l=segl w=segw +xr0 plus n1 rpposab_2t_ckt m=1 l=segl w=segw +.ends rpposab_ckt_pcell2461 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_LOOP_FILTER +** View name: schematic +.subckt PLL_LOOP_FILTER cp_out out pdb reset _net0 _net1 vss vss33 pd_clk_ready +xi18 pd_clk_ready net5 _net0 _net1 vss vss33 PLL_LVL +xi17 net027 pd_clk_ready _net0 vss PLL_INV12_1P5_DUMMY +xi10 reset pdb net027 _net0 vss PLL_nand_PD_2 +xi93 net5 resetn _net1 vss33 PLL_INV_V33 +xnm8 vss33 _net1 vss33 vss33 nod33ll_ckt L=4e-6 W=24e-6 AD=8.4e-12 AS=8.4e-12 PD=48.7e-6 PS=48.7e-6 M=1 +xnm10 vss33 _net1 vss33 vss33 nod33ll_ckt L=10e-6 W=26e-6 AD=5.46e-12 AS=7.28e-12 PD=26.42e-6 PS=39.56e-6 M=4 +xnm7 vss33 _net1 vss33 vss33 nod33ll_ckt L=4e-6 W=9e-6 AD=3.15e-12 AS=3.15e-12 PD=18.7e-6 PS=18.7e-6 M=1 +xnm0 vss33 net14 vss33 vss33 nod33ll_ckt L=10e-6 W=24e-6 AD=5.712e-12 AS=5.712e-12 PD=29.276e-6 PS=29.276e-6 M=5 +xnm6 vss33 _net1 vss33 vss33 nod33ll_ckt L=4e-6 W=20e-6 AD=4.6e-12 AS=4.6e-12 PD=23.3171e-6 PS=23.3171e-6 M=7 +xnm1 vss33 net14 vss33 vss33 nod33ll_ckt L=10e-6 W=9e-6 AD=2.07e-12 AS=2.07e-12 PD=10.7457e-6 PS=10.7457e-6 M=7 +xnm2 vss33 out vss33 vss33 nod33ll_ckt L=10e-6 W=W2 AD=4.76e-12 AS=4.76e-12 PD=24.476e-6 PS=24.476e-6 M=5 +xnm5 vss33 net14 vss33 vss33 nod33ll_ckt L=10e-6 W=20e-6 AD=4.2e-12 AS=4.256e-12 PD=20.42e-6 PS=20.8256e-6 M=M1 +xnm11 vss33 cp_out vss33 vss33 nod33ll_ckt L=10e-6 W=W1 AD=4.76e-12 AS=4.76e-12 PD=24.476e-6 PS=24.476e-6 M=5 +xnm9 vss33 net14 vss33 vss33 nod33ll_ckt L=10e-6 W=20e-6 AD=4.2e-12 AS=4.27778e-12 PD=20.42e-6 PS=20.9833e-6 M=M2 +xnm3 cp_out resetn vss33 vss33 nod33ll_ckt L=2e-6 W=10e-6 AD=3.5e-12 AS=3.5e-12 PD=20.7e-6 PS=20.7e-6 M=1 +xr2 out cp_out rpposab_ckt_pcell2460 m=1 segl=lr2 segw=2e-6 +xr0 net14 cp_out rpposab_ckt_pcell2461 m=1 segl=lr0 segw=2e-6 +.ends PLL_LOOP_FILTER +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_QUENCH_v33 +** View name: schematic +.subckt PLL_QUENCH_v33 _net0 vin vout vref vss33 +xpm11 vout vout net18 net18 pod33ll_ckt L=q_lupper W=q_wupper AD=2.1e-12 AS=2.8e-12 PD=10.42e-6 PS=15.56e-6 M=4 +xpm10 n79 vin net18 net18 pod33ll_ckt L=q_lupper W=q_wupper AD=2.1e-12 AS=2.8e-12 PD=10.42e-6 PS=15.56e-6 M=4 +xnm1 vout n78 vss33 vss33 nod33ll_ckt L=q_llower W=q_wlower AD=420e-15 AS=700e-15 PD=2.42e-6 PS=4.7e-6 M=2 +xnm0 n79 n78 vss33 vss33 nod33ll_ckt L=q_llower W=q_wlower AD=420e-15 AS=513.333e-15 PD=2.42e-6 PS=3.18e-6 M=6 + +xpm12 _net0 vref _net0 _net0 pod33ll_ckt L=q_lc W=q_wc AD=3.5e-12 AS=3.5e-12 PD=20.7e-6 PS=20.7e-6 M=1 + +xpm7 n78 vref _net0 _net0 pod33ll_ckt L=q_lref W=q_wref AD=2.1e-12 AS=2.38e-12 PD=10.42e-6 PS=12.476e-6 M=10 +xpm8 net18 vref _net0 _net0 pod33ll_ckt L=q_lref W=q_wref AD=2.38e-12 AS=2.38e-12 PD=12.476e-6 PS=12.476e-6 M=5 + +xpm9 vss33 n79 n78 n78 pod33ll_ckt L=q_lq W=q_wq AD=2.1e-12 AS=3.5e-12 PD=10.42e-6 PS=20.7e-6 M=2 +.ends PLL_QUENCH_v33 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_CHARGEPUMP +** View name: schematic +.subckt PLL_CHARGEPUMP cp_out dn dnb i10u i5u pd pdb up upb _net0 vss33 +xi40 _net0 cp_out quench pb2 vss33 PLL_QUENCH_v33 + +xnm31 i5u pd vss33 vss33 nod33ll_ckt L=lpdin W=wpdin AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +xnm30 nb2 pd vss33 vss33 nod33ll_ckt L=lpdin W=wpdin AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +xpm29 pb1 pdb _net0 _net0 pod33ll_ckt L=lpdbin W=wpdbin AD=1.75e-12 AS=1.75e-12 PD=10.7e-6 PS=10.7e-6 M=1 +xpm22 pb2 pdb _net0 _net0 pod33ll_ckt L=lpdbin W=wpdbin AD=1.75e-12 AS=1.75e-12 PD=10.7e-6 PS=10.7e-6 M=1 + +xpm11 net35 pb2 _net0 _net0 pod33ll_ckt L=luumid W=wuumid AD=2.1e-12 AS=3.5e-12 PD=10.42e-6 PS=20.7e-6 M=2 +xpm12 net47 pb2 net79 _net0 pod33ll_ckt L=luumid W=wuumid AD=2.1e-12 AS=2.45e-12 PD=10.42e-6 PS=12.99e-6 M=8 + +xpm8 net98 pb1 net47 _net0 pod33ll_ckt L=lumid W=wumid AD=2.1e-12 AS=2.45e-12 PD=10.42e-6 PS=12.99e-6 M=8 +xpm10 pb2 pb1 net35 _net0 pod33ll_ckt L=lumid W=wumid AD=2.1e-12 AS=3.5e-12 PD=10.42e-6 PS=20.7e-6 M=2 + +xpm3 net91 dnb cp_out net98 pod33ll_ckt L=lp4 W=wp4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 +xpm1 net91 dn quench net98 pod33ll_ckt L=lp4 W=wp4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 +xpm2 quench up net98 net98 pod33ll_ckt L=lp4 W=wp4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 +xpm4 cp_out upb net98 net98 pod33ll_ckt L=lp4 W=wp4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 + +xnm5 cp_out dn net91 vss33 nod33ll_ckt L=ln4 W=wn4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 +xnm6 net98 up cp_out vss33 nod33ll_ckt L=ln4 W=wn4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 +xnm7 quench dnb net91 vss33 nod33ll_ckt L=ln4 W=wn4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 +xnm9 net98 upb quench vss33 nod33ll_ckt L=ln4 W=wn4 AD=420e-15 AS=420e-15 PD=3.1e-6 PS=3.1e-6 M=1 + +xnm14 pb2 i5u net62 vss33 nod33ll_ckt L=lnsupp W=wnsupp AD=420e-15 AS=700e-15 PD=2.42e-6 PS=4.7e-6 M=2 +xnm18 net91 i5u net58 vss33 nod33ll_ckt L=lnsupp W=wnsupp AD=420e-15 AS=490e-15 PD=2.42e-6 PS=2.99e-6 M=8 +xnm21 pb1 i5u net0124 vss33 nod33ll_ckt L=lnsupp W=wnsupp AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +xnm23 net0153 i5u net0119 vss33 nod33ll_ckt L=lnsupp W=wnsupp AD=420e-15 AS=700e-15 PD=2.42e-6 PS=4.7e-6 M=2 + +xnm15 net62 nb2 vss33 vss33 nod33ll_ckt L=lnsupp2 W=wnsupp2 AD=420e-15 AS=700e-15 PD=2.42e-6 PS=4.7e-6 M=2 +xnm17 net58 nb2 net78 vss33 nod33ll_ckt L=lnsupp2 W=wnsupp2 AD=420e-15 AS=490e-15 PD=2.42e-6 PS=2.99e-6 M=8 +xnm20 net0124 nb2 vss33 vss33 nod33ll_ckt L=lnsupp2 W=wnsupp2 AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +xnm24 net0119 net0153 vss33 vss33 nod33ll_ckt L=lnsupp2 W=wnsupp2 AD=420e-15 AS=700e-15 PD=2.42e-6 PS=4.7e-6 M=2 + +xnm33 nb2 i10u net0149 vss33 nod33ll_ckt L=li10 W=wi10 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm32 net0149 i10u net0153 vss33 nod33ll_ckt L=li10 W=wi10 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 + +xnm27 vss33 nb2 vss33 vss33 nod33ll_ckt L=lb1 W=wb1 AD=4.725e-12 AS=4.725e-12 PD=27.7e-6 PS=27.7e-6 M=1 +xnm13 i5u i5u vss33 vss33 nod33ll_ckt L=lb2 W=wb2 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm25 i10u i10u net0153 vss33 nod33ll_ckt L=lb3 W=wb3 AD=420e-15 AS=700e-15 PD=2.42e-6 PS=4.7e-6 M=2 +xpm19 pb1 pb1 _net0 _net0 pod33ll_ckt L=lb4 W=wb4 AD=1.75e-12 AS=1.75e-12 PD=10.7e-6 PS=10.7e-6 M=1 + +xnm26 vss33 i5u vss33 vss33 nod33ll_ckt L=lc1 W=wc1 AD=2.45e-12 AS=2.45e-12 PD=14.7e-6 PS=14.7e-6 M=1 +xpm28 _net0 pb2 _net0 _net0 pod33ll_ckt L=lc2 W=wc2 AD=3.5e-12 AS=3.5e-12 PD=20.7e-6 PS=20.7e-6 M=1 +xnm34 vss33 _net0 vss33 vss33 nod33ll_ckt L=lc3 W=wc3 AD=2.1e-12 AS=2.8e-12 PD=10.42e-6 PS=15.56e-6 M=4 + +vlower net78 vss33 DC=0 +vupper _net0 net79 DC=0 +.ends PLL_CHARGEPUMP +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_PFD_BUF +** View name: schematic +.subckt PLL_PFD_BUF dn dn33 dn33b up up33 up33b _net0 vss33 +xnm27 vss33 _net0 vss33 vss33 nod33ll_ckt L=5e-6 W=10e-6 AD=2.1e-12 AS=3.5e-12 PD=10.42e-6 PS=20.7e-6 M=2 +xnm28 vss33 _net0 vss33 vss33 nod33ll_ckt L=3.8e-6 W=6e-6 AD=1.26e-12 AS=2.1e-12 PD=6.42e-6 PS=12.7e-6 M=2 +xnm25 net1 _net0 up33 vss33 nod33ll_ckt L=350e-9 W=1e-6 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm26 net0118 _net0 dn33 vss33 nod33ll_ckt L=350e-9 W=1e-6 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm22 dn33b net0118 vss33 vss33 nod33ll_ckt L=350e-9 W=1e-6 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm23 net0118 net0114 vss33 vss33 nod33ll_ckt L=350e-9 W=1e-6 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm24 net0114 dn vss33 vss33 nod33ll_ckt L=350e-9 W=10e-6 AD=3.5e-12 AS=3.5e-12 PD=20.7e-6 PS=20.7e-6 M=1 +xnm19 up33b net1 vss33 vss33 nod33ll_ckt L=350e-9 W=1e-6 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm18 net1 net5 vss33 vss33 nod33ll_ckt L=350e-9 W=1e-6 AD=350e-15 AS=350e-15 PD=2.7e-6 PS=2.7e-6 M=1 +xnm17 net5 up vss33 vss33 nod33ll_ckt L=350e-9 W=10e-6 AD=3.5e-12 AS=3.5e-12 PD=20.7e-6 PS=20.7e-6 M=1 +xpm16 net5 up _net0 _net0 pod33ll_ckt L=300e-9 W=800e-9 AD=280e-15 AS=280e-15 PD=2.3e-6 PS=2.3e-6 M=1 +xpm0 net1 net5 _net0 _net0 pod33ll_ckt L=300e-9 W=3e-6 AD=1.05e-12 AS=1.05e-12 PD=6.7e-6 PS=6.7e-6 M=1 +xpm7 net1 vss33 up33 _net0 pod33ll_ckt L=350e-9 W=2e-6 AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +xpm8 net0118 vss33 dn33 _net0 pod33ll_ckt L=350e-9 W=2e-6 AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +xpm6 net0118 net0114 _net0 _net0 pod33ll_ckt L=300e-9 W=3e-6 AD=1.05e-12 AS=1.05e-12 PD=6.7e-6 PS=6.7e-6 M=1 +xpm4 dn33b net0118 _net0 _net0 pod33ll_ckt L=300e-9 W=2e-6 AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +xpm5 net0114 dn _net0 _net0 pod33ll_ckt L=300e-9 W=800e-9 AD=280e-15 AS=280e-15 PD=2.3e-6 PS=2.3e-6 M=1 +xpm1 up33b net1 _net0 _net0 pod33ll_ckt L=300e-9 W=2e-6 AD=700e-15 AS=700e-15 PD=4.7e-6 PS=4.7e-6 M=1 +.ends PLL_PFD_BUF +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_nand_PD_3 +** View name: schematic +.subckt PLL_nand_PD_3 in1 in2 in3 out _net0 vss +xpm0 out in1 _net0 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xpm2 out in2 _net0 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xpm1 out in3 _net0 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xnm2 net033 in3 vss vss n11ll_ckt L=40e-9 W=2.5e-6 AD=825e-15 AS=825e-15 PD=5.66e-6 PS=5.66e-6 M=1 +xnm1 net29 in1 net033 vss n11ll_ckt L=40e-9 W=2.5e-6 AD=825e-15 AS=825e-15 PD=5.66e-6 PS=5.66e-6 M=1 +xnm0 out in2 net29 vss n11ll_ckt L=40e-9 W=2.5e-6 AD=825e-15 AS=825e-15 PD=5.66e-6 PS=5.66e-6 M=1 +.ends PLL_nand_PD_3 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_NOR2 +** View name: schematic +.subckt PLL_NOR2 in1 in2 out _net0 vss +xpm0 net33 in1 _net0 _net0 p11ll_ckt L=40e-9 W=4e-6 AD=1.32e-12 AS=1.32e-12 PD=8.66e-6 PS=8.66e-6 M=1 +xpm1 out in2 net33 _net0 p11ll_ckt L=40e-9 W=4e-6 AD=1.32e-12 AS=1.32e-12 PD=8.66e-6 PS=8.66e-6 M=1 +xpm2 out in1 vss vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +xpm3 out in2 vss vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +.ends PLL_NOR2 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_invn_2 +** View name: schematic +.subckt PLL_invn_2 in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=2.7e-6 AD=891e-15 AS=891e-15 PD=6.06e-6 PS=6.06e-6 M=1 +xpm1 out in vss vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +.ends PLL_invn_2 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_invn_PD2 +** View name: schematic +.subckt PLL_invn_PD2 in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=2e-6 AD=473.333e-15 AS=473.333e-15 PD=3.14e-6 PS=3.14e-6 M=3 +xpm1 out in vss vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +.ends PLL_invn_PD2 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_invn_PD1 +** View name: schematic +.subckt PLL_invn_PD1 in out _net0 vss +xpm0 out in _net0 _net0 p11ll_ckt L=40e-9 W=4e-6 AD=1.32e-12 AS=1.32e-12 PD=8.66e-6 PS=8.66e-6 M=1 +xnm0 out in vss vss n11ll_ckt L=40e-9 W=2e-6 AD=660e-15 AS=660e-15 PD=4.66e-6 PS=4.66e-6 M=1 +.ends PLL_invn_PD1 +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: PLL_PFD +** View name: schematic +.subckt PLL_PFD ck_outm ck_ref down pd up _net0 vss +xi33 net91 net120 in10 net132 _net0 vss PLL_nand_PD_3 +xi34 net93 net123 in10 net129 _net0 vss PLL_nand_PD_3 +xi62 net061 net088 in1 _net0 vss PLL_NOR2 +xi58 pd net132 up _net0 vss PLL_NOR2 +xi59 pd net129 down _net0 vss PLL_NOR2 +xi55_0 in1 in2 _net0 vss PLL_invn_2 +xi55_1 in2 in3 _net0 vss PLL_invn_2 +xi55_2 in3 in4 _net0 vss PLL_invn_2 +xi55_3 in4 in5 _net0 vss PLL_invn_2 +xi55_4 in5 in6 _net0 vss PLL_invn_2 +xi55_5 in6 in7 _net0 vss PLL_invn_2 +xi55_6 in7 in8 _net0 vss PLL_invn_2 +xi55_7 in8 in9 _net0 vss PLL_invn_2 +xi55_8 in9 in10 _net0 vss PLL_invn_2 +xi21 ck_ref net116 _net0 vss PLL_invn_2 +xi22 ck_outm net118 _net0 vss PLL_invn_2 +xi60 net135 net120 net061 _net0 vss PLL_nand_PD_2 +xi61 net126 net123 net088 _net0 vss PLL_nand_PD_2 +xi24 net120 in10 net134 _net0 vss PLL_nand_PD_2 +xi25 net123 in10 net125 _net0 vss PLL_nand_PD_2 +xi26 net126 net125 net123 _net0 vss PLL_nand_PD_2 +xi27 net129 net118 net126 _net0 vss PLL_nand_PD_2 +xi20 net132 net116 net135 _net0 vss PLL_nand_PD_2 +xi23 net135 net134 net120 _net0 vss PLL_nand_PD_2 +xi29 net95 net91 _net0 vss PLL_invn_PD2 +xi31 net97 net93 _net0 vss PLL_invn_PD2 +xi28 net135 net95 _net0 vss PLL_invn_PD1 +xi30 net126 net97 _net0 vss PLL_invn_PD1 +.ends PLL_PFD +** End of subcircuit definition. + +** Library name: S013G_PLL +** Cell name: S013G_PLL_TOP +** View name: schematic +.subckt S013G_PLL_TOP ck_in in10u1 in5u1 lock out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 pd reset _net0 _net1 vss vss33 +xi94 pd pd1 _net0 _net1 vss vss33 PLL_LVL +xi76 pd1 pd1b _net1 vss33 PLL_INV_V33 +xi17 ckn ck_ref _net0 vss PLL_INV_TFF +xi24 out_2 _net0 vss PLL_phase_dumy +xi59 out_6 _net0 vss PLL_phase_dumy +xi28 out_7 _net0 vss PLL_phase_dumy +xi29 out_3 _net0 vss PLL_phase_dumy +xi25 out_5 _net0 vss PLL_phase_dumy +xi56 out_1 _net0 vss PLL_phase_dumy +xi12 net52 net73 _net0 vss PLL_INV12_3P0 +xi92 out_4 net55 _net0 vss PLL_INV12_1P5_DUMMY +xi91 net55 lock_ref _net0 vss PLL_INV12_1P5_DUMMY +xi13 out_0 net52 _net0 vss PLL_INV12_1P5_DUMMY +xi90 pd pdb _net0 vss PLL_INV_SMALL +xi16 ck_in ckn _net0 vss PLL_INV_SMALL +xi89 net68 net0134 _net0 vss PLL_DIV2 +xi19 div10 net68 _net0 vss PLL_DIV2 +xi11 net73 div10 pdb _net0 vss PLL_DIV10 +xi50 ck_in lock lock_ref pd_clk_ready _net0 vss PLL_LOCK_DETECTOR +xi60 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vctr _net0 _net1 vss vss33 PLL_VCO_8PHASE +xi71 cp_out vctr pdb reset _net0 _net1 vss vss33 pd_clk_ready PLL_LOOP_FILTER +xi66 cp_out dn dnb in10u1 in5u1 pd1 pd1b up upb _net1 vss33 PLL_CHARGEPUMP +xi93 dn12 dn dnb up12 up upb _net1 vss33 PLL_PFD_BUF +xi5 net0134 ck_ref dn12 pd up12 _net0 vss PLL_PFD +xnm4 vss33 _net1 vss33 vss33 nod33ll_ckt L=3e-6 W=20e-6 AD=4.2e-12 AS=4.6e-12 PD=20.42e-6 PS=23.3171e-6 M=14 +xnm3 vss33 _net1 vss33 vss33 nod33ll_ckt L=10e-6 W=20e-6 AD=4.2e-12 AS=4.32727e-12 PD=20.42e-6 PS=21.3418e-6 M=44 +.ends S013G_PLL_TOP +** End of subcircuit definition. + +** Library name: pll +** Cell name: PLL_CHARGEPUMP_TEST +** View name: schematic +xi0 vcp_net dn_net dnb_net i10u_net i5u_net 0 vdd33_net up_net upb_net vdd33_net 0 PLL_CHARGEPUMP + +i10 vdd33_net i10u_net DC=10e-6 +i5 vdd33_net i5u_net DC=5e-6 +v0 vdd33_net 0 DC=vdd33 +c0 vcp_net 0 1e9 + +vdn dn_net 0 PULSE 0 3.3 10e-9 10e-12 10e-12 10e-9 20e-9 +vdnb dnb_net 0 PULSE 0 3.3 0 10e-12 10e-12 10e-9 20e-9 +vupb upb_net 0 PULSE 0 3.3 0 10e-12 10e-12 10e-9 20e-9 +vup up_net 0 PULSE 0 3.3 10e-9 10e-12 10e-12 10e-9 20e-9 diff --git a/AnalogGym/Charge Pump/circuit/param b/AnalogGym/Charge Pump/circuit/param new file mode 100644 index 0000000..63aa0c4 --- /dev/null +++ b/AnalogGym/Charge Pump/circuit/param @@ -0,0 +1,36 @@ +.param q_llower = 3.2217407526890736e-06 +.param q_wlower = 8.236649046793489e-07 +.param q_lupper = 1.3380535250405056e-06 +.param q_wupper = 7.076992749573221e-06 +.param q_lc = 2.2775475745682356e-06 +.param q_wc = 2.3866132427433844e-05 +.param q_lref = 4.25640662508087e-06 +.param q_wref = 6.723239369777488e-06 +.param q_lq = 5.654377405899749e-07 +.param q_wq = 1.788908504591808e-05 +.param lpdbin = 2.0431151404311383e-06 +.param wpdbin = 1.0169990458123514e-05 +.param lpdin = 7.692879812432616e-07 +.param wpdin = 5.06138909621911e-06 +.param luumid = 6.125103859340603e-07 +.param wuumid = 1.63543942649338e-05 +.param lumid = 1.9866217840185627e-06 +.param wumid = 1.8092788719651868e-05 +.param lp4 = 6.963047716053019e-07 +.param wp4 = 3.7468680515633946e-06 +.param ln4 = 1.1317673679726693e-06 +.param wn4 = 2.8901740388048074e-06 +.param lnsupp = 2.27185214614107e-06 +.param wnsupp = 4.159349847092674e-06 +.param lnsupp2 = 1.2833318704819633e-06 +.param wnsupp2 = 2.0631309509467025e-06 +.param li10 = 1.2747084914962342e-05 +.param wi10 = 1.5111902717269288e-06 +.param lb1 = 3.5212215256855735e-06 +.param wb1 = 1.1627300363221344e-05 +.param lb2 = 6.436393065721794e-06 +.param wb2 = 1.6026239201347668e-06 +.param lb3 = 1.909994749967832e-06 +.param wb3 = 3.651698226422868e-06 +.param lb4 = 1.5515215731804651e-06 +.param wb4 = 5.124552535245568e-06 diff --git a/AnalogGym/Charge Pump/circuit/run_sim.sh~ b/AnalogGym/Charge Pump/circuit/run_sim.sh~ new file mode 100644 index 0000000..bd03cb0 --- /dev/null +++ b/AnalogGym/Charge Pump/circuit/run_sim.sh~ @@ -0,0 +1,4 @@ +#!/bin/bash +./clear.sh +hspice64 -i tran_27corner.sp -o chgp >chgp.info +python -u measure.py 27 de 1>run_sim.info diff --git a/AnalogGym/Charge Pump/circuit/sim.sh b/AnalogGym/Charge Pump/circuit/sim.sh new file mode 100644 index 0000000..70c6713 --- /dev/null +++ b/AnalogGym/Charge Pump/circuit/sim.sh @@ -0,0 +1,5 @@ +#!/bin/bash +./clear.sh +hspice64 -i tran_27corner.sp -o chgp >chgp.info +# $DE_PY_HOME/Dependence/glibc/lib/ld-2.22.so --library-path $DE_PY_HOME/Dependence/glibc/lib:$LD_LIBRARY_PATH `which python` -u measure.py 27 de 1>run_sim.info +python -u measure.py 27 de 1>run_sim.info diff --git a/AnalogGym/Charge Pump/circuit/tran_27corner.sp b/AnalogGym/Charge Pump/circuit/tran_27corner.sp new file mode 100644 index 0000000..a28e3a6 --- /dev/null +++ b/AnalogGym/Charge Pump/circuit/tran_27corner.sp @@ -0,0 +1,202 @@ +***simulation file*** +*.option +*+ fast +*+ post node list +*+ method=gear +*+ runlvl=6 +*+ probe=1 +*+ accurate=6 +*+ dcon=-1 +*+ modmonte=1 + +.inc 'netlist' + +.ic v(vcp_net)=vcp + +.inc 'param' + + +.lib './smic.40/hspice/v1p4/l0040ll_v1p4_1r.lib' TT +.lib './smic.40/hspice/v1p4/l0040ll_v1p4_1r.lib' RES_TT +.param vdd33 = 2.97 +.temp -40 + +.param vcp = 2.2 +.param lc1 = 7e-6 ; +.param wc1 = 7e-6 ; +.param lc2 = 7e-6 ; +.param wc2 = 10e-6; +.param lc3 = 5e-6 ; +.param wc3 = 10e-6; + +.op +.tran 2p 200n $ sweep monte=100 + +*.probe v(OUT_0) V(LOCK) v(XI0.CK_REF) V(XI0.net0134) v(xi0.net68) v(xi0.DIV10) v(xi0.UP) v(xi0.UPB) v(xi0.DNB) v(xi0.DN) v(xi0.DN12) v(xi0.UP12) V(xi0.CP_OUT) V(xi0.vctr) V(xi0.xi66.quench) v(xi0.pd_clk_ready) v(xi0.LOCK_REF) v(xi0.xi60.ph_3) v(xi0.xi60.ph_7) v(xi0.xi60.vcovdd) v(xi0.xi60.reset) v(xi0.xi60.resetn) + +*.print i(xi0.vupper) i(xi0.vlower) + +.measure tran up_imin min i(xi0.vupper) from=20e-9 to=100e-9 +.measure tran up_iavg avg i(xi0.vupper) from=20e-9 to=180e-9 +.measure tran up_imax max i(xi0.vupper) from=20e-9 to=100e-9 + +.measure tran lo_imin min i(xi0.vlower) from=20e-9 to=100e-9 +.measure tran lo_iavg avg i(xi0.vlower) from=20e-9 to=180e-9 +.measure tran lo_imax max i(xi0.vlower) from=20e-9 to=100e-9 + + + + +******2*** +.alter +.param vdd33 = 3.3 +.temp -40 + +******3*** +.alter +.param vdd33 = 3.63 +.temp -40 + +******4*** +.alter +.param vdd33 = 2.97 +.temp 125 + + +******5*** +.alter +.param vdd33 = 3.3 +.temp 125 + + +******6*** +.alter +.param vdd33 = 3.63 +.temp 125 + + +******7*** +.alter +.param vdd33 = 2.97 +.temp 25 + + +******8*** +.alter +.param vdd33 = 3.3 +.temp 25 + + +******9*** +.alter +.param vdd33 = 3.63 +.temp 25 + + +******10*** +.alter +.lib './smic.40/hspice/v1p4/l0040ll_v1p4_1r.lib' SS +.lib './smic.40/hspice/v1p4/l0040ll_v1p4_1r.lib' RES_SS +.param vdd33 = 2.97 +.temp -40 + +******11*** +.alter +.param vdd33 = 3.3 +.temp -40 + +******12*** +.alter +.param vdd33 = 3.63 +.temp -40 + +******13*** +.alter +.param vdd33 = 2.97 +.temp 125 + + +******14*** +.alter +.param vdd33 = 3.3 +.temp 125 + + +******15*** +.alter +.param vdd33 = 3.63 +.temp 125 + + +******16*** +.alter +.param vdd33 = 2.97 +.temp 25 + + +******17*** +.alter +.param vdd33 = 3.3 +.temp 25 + + +******18*** +.alter +.param vdd33 = 3.63 +.temp 25 + + + +******19*** +.alter +.lib './smic.40/hspice/v1p4/l0040ll_v1p4_1r.lib' FF +.lib './smic.40/hspice/v1p4/l0040ll_v1p4_1r.lib' RES_FF +.param vdd33 = 2.97 +.temp -40 + +******20*** +.alter +.param vdd33 = 3.3 +.temp -40 + +******21*** +.alter +.param vdd33 = 3.63 +.temp -40 + +******22*** +.alter +.param vdd33 = 2.97 +.temp 125 + + +******23*** +.alter +.param vdd33 = 3.3 +.temp 125 + + +******24*** +.alter +.param vdd33 = 3.63 +.temp 125 + +******25*** +.alter +.param vdd33 = 2.97 +.temp 25 + + +******26*** +.alter +.param vdd33 = 3.3 +.temp 25 + + +******27*** +.alter +.param vdd33 = 3.63 +.temp 25 + + +.end diff --git a/AnalogGym/Charge Pump/config.py b/AnalogGym/Charge Pump/config.py new file mode 100644 index 0000000..bbaeb66 --- /dev/null +++ b/AnalogGym/Charge Pump/config.py @@ -0,0 +1,199 @@ +# -*- coding: utf-8 -*- +""" + this module is written by users + this module defines Design Varas,circuit,and all settings... +""" +import re + +# Project +''' absolute path and dir of the whole circuit +''' +prj_path = "./" # prj_path doesn't matter fro now, see control.py +prj_name = "chargepump" # prj_name = Project name + +# Design Variables +DX = [('q_llower', 3e-6, 9e-6, 1.0e-8, 6.9e-6, 'NO'), + ('q_wlower', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_lupper', 1e-6, 2e-6, 1.0e-8, 1.5e-6, 'NO'), + ('q_wupper', 5e-6, 20e-6, 1.0e-8, 10e-6, 'NO'), + ('q_lc', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_wc', 5e-6, 20e-6, 1.0e-8, 10e-6, 'NO'), + ('q_lref', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_wref', 5e-6, 20e-6, 1.0e-8, 6e-6, 'NO'), + ('q_lq', 1e-6, 4e-6, 1.0e-8, 3e-6, 'NO'), + ('q_wq', 5e-6, 20e-6, 1.0e-8, 6e-6, 'NO'), + ('lpdbin', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wpdbin', 4e-6, 15e-6, 1.0e-8, 10e-6, 'NO'), + ('lpdin', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wpdin', 2e-6, 6e-6, 1.0e-8, 3e-6, 'NO'), + ('luumid', 0.6e-6, 1.2e-6, 1.0e-8, 1e-6, 'NO'), + ('wuumid', 5e-6, 20e-6, 1.0e-8, 10e-6, 'NO'), + ('lumid', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wumid', 8e-6, 25e-6, 1.0e-8, 10e-6, 'NO'), + ('lp4', 0.5e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wp4', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('ln4', 0.55e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wn4', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('lnsupp', 0.5e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wnsupp', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('lnsupp2', 0.8e-6, 2.4e-6, 1.0e-8, 1e-6, 'NO'), + ('wnsupp2', 1e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('li10', 2e-6, 10e-6, 1.0e-8, 3e-6, 'NO'), + ('wi10', 0.8e-6, 4e-6, 1.0e-8, 2e-6, 'NO'), + ('lb1', 2e-6, 10e-6, 1.0e-8, 3e-6, 'NO'), + ('wb1', 5e-6, 25e-6, 1.0e-8, 10e-6, 'NO'), + ('lb2', 2e-6, 8e-6, 1.0e-8, 3e-6, 'NO'), + ('wb2', 1e-6, 3e-6, 1.0e-8, 2e-6, 'NO'), + ('lb3', 0.5e-6, 2e-6, 1.0e-8, 1e-6, 'NO'), + ('wb3', 1e-6, 6e-6, 1.0e-8, 2e-6, 'NO'), + ('lb4', 0.55e-6, 3e-6, 1.0e-8, 1e-6, 'NO'), + ('wb4', 4e-6, 16e-6, 1.0e-8, 8e-6, 'NO'), + #('m',1,5,1,2,'NO'), + #('m2',1,5,1,2,'NO') + ] + +# DX = [('name',L,U,step,init,[discrete list]),....] if there is no discrete, do not write + +# setting +setting_1 = ['sim.sh', 'de_result.po', +[("diff1", "<", "20", None, None, "extract_diff1(file)", "10"), + ("diff2", "<", "20", None, None, "extract_diff2(file)", "10"), + ("diff3", "<", "5", None, None, "extract_diff3(file)", "10"), + ("diff4", "<", "5", None, None, "extract_diff4(file)", "10"), + ("deviation", "<", "5", None, None, "extract_deviation(file)", "10"), + ("obj", None, None, None, None, "extract_obj(file)", None) +] +] +#setting_1 = ['test1.sp', [("pm",None, None, ">","90","extract_pm(file)", "5"),]] +# setting_x = ['test name',[(per1, /empty/>=,num2, "extract function", weight),...]] +setting = [setting_1] +FOM = ['obj', "100", None] +#FOM = ['-pm', "-90", 10] +#FOM = ['-gain', "-95", None] +# FOM = ['fuc', num1/None, weight/None] :minimize FOM, if FOM has constraint, the form must be "FOM < num" + +# extract performance from .lis +def extract_obj(file): + pattern = re.compile(r'obj= *([\d.eE+\-]+)') + with open(file, 'r') as f: + lines = f.readlines() + for line in lines: + result = pattern.search(line) + if result: + return result.group(1) + return "1e3" + +def extract_diff1(file): + pattern = re.compile(r'diff1= *([\d.eE+\-]+)') + with open(file, 'r') as f: + lines = f.readlines() + for line in lines: + result = pattern.search(line) + if result: + return result.group(1) + return "1e3" + +def extract_diff2(file): + pattern = re.compile(r'diff2= *([\d.eE+\-]+)') + with open(file, 'r') as f: + lines = f.readlines() + for line in lines: + result = pattern.search(line) + if result: + return result.group(1) + return "1e3" + +def extract_diff3(file): + pattern = re.compile(r'diff3= *([\d.eE+\-]+)') + with open(file, 'r') as f: + lines = f.readlines() + for line in lines: + result = pattern.search(line) + if result: + return result.group(1) + return "1e3" + +def extract_diff4(file): + pattern = re.compile(r'diff4= *([\d.eE+\-]+)') + with open(file, 'r') as f: + lines = f.readlines() + for line in lines: + result = pattern.search(line) + if result: + return result.group(1) + return "1e3" + +def extract_deviation(file): + pattern = re.compile(r'dev= *([\d.eE+\-]+)') + with open(file, 'r') as f: + lines = f.readlines() + for line in lines: + result = pattern.search(line) + if result: + return result.group(1) + return "1e3" + + +# control prrameter +DEL_OUT_FOLDER = True +Mode = "Spice" +CPU_CORES = 1 +##for DE, GA, PSO, SA, turbo, this parameter can be more according to the Init_num + +# set the optimization algorithm +''' +# if using src/scripts/bak +def get_totNum(Init_num, Max_eval, Algorithm): + if Algorithm in ("Bayes", "BOc", "weibo_py", "bobyqa_py"): + totNum = Init_num + Max_eval + elif Algorithm in ("PSO", "GA"): + totNum = Init_num * (Max_eval+2) + elif Algorithm == "SA": + totNum = Init_num * Max_eval+1 + elif Algorithm == "pycma": + totNum = Init_num * Max_eval+2 + elif Algorithm == "DE": + totNum = Init_num * Max_eval * 2 + elif Algorithm in ("SQP", "bobyqa"): + totNum = 600 + elif Algorithm in ("random"): + totNum = Init_num * Max_eval + elif Algorithm in ("turbo"): + totNum = Init_num*Tr_num + Max_eval + elif Algorithm in ("pyVTS"): + totNum = Init_num + Max_eval + return totNum +''' + +# Algorithm +Algorithm = "turbo" +##"Bayes", "BOc", "weibo_py", "DE", "GA", "PSO", "SQP", "bobyqa", "SA", "random", "turbo", "pycma", "bobyqa_py", "pyVTS" +Init_num = 20 +Max_eval = 10 +Tr_num = 1 # for trust region related algorithms +##"Bayes": (20, 80), +##"BOc": (20, 80), +##"weibo_py": (20, 80), +##"DE": (20, 20), +##"GA": (20, 20), +##"PSO": (20, 20), +##"SQP": (200, 400), +##"bobyqa": (200, 400), +##"SA": (20, 20), +##"random": (100, 100), +##"turbo": (2*dim, 100) +##"pycma": (4+3*np.log(dim), 100+150*(dim+3)**2//init_num**0.5) +##"bobyqa_py": (2*dim+1, 100) +##"pyVTS": (2*dim, 100) +''' +# if using src/scripts/bak +TOT_NUM = get_totNum(Init_num, Max_eval, Algorithm) +''' +WITH_CONS = False +##for python algos this parameter can be True +##for cxx algos, this parameter is useless +##but note that BOc always carries out constrained optimization +##and note that turbo can only carry out cost optimization +WITH_INIT = True +##for python algos this parameter can be True +##for cxx algos, this parameter is useless (always False)