Skip to content

Latest commit

 

History

History
80 lines (50 loc) · 3.93 KB

hardware.md

File metadata and controls

80 lines (50 loc) · 3.93 KB
layout title
default
Hardware

Hardware

Moore's Law

In the future according to Moore's Law we with have computers with a huge amount of transistor and with many many cores. Today (2022) we have for instance a MacBook with 8 cores1. If every two years the amount of core doubles. Then we have in 10 years 256 cores and in 20 years 8192 cores. But in 40 (2062) years we break wall with (O 10^6) cores in a cpu.

Estimation of cores in future

   8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192  ..  ~1 mio
   o--------------------------------------------------------------> years
  Now                       +10                     +20  ..    +40

For these new very fast computers we need a different ways of programming2.

New Architectures needed

A computer with millions little and simple processors with its own memory like core memory.

You can programm each small processors and you can connect the output to input of other processors. While data is flowing from one i/o cell to the next.

            cell 1       connection       cell2
  IN --> [fn(x)(+ x 1)]  --------->  [fn(x y)(+ x y)] --> OUT

Each cell is a small lisp machine3 with memory to store the lisp environment. There are millions or billion of this. Each cell produce output from inputs and send the output to the connected cells and so on. Each cell runs independend and wait for input to produce output. So each cell runs parallel and not in a thread. Each cell is like a thread.

Architectures

Von Neumann Architecture

One problem with this architecture is the bottleneck.

Data-Flow Architecture

Preliminary Architecture for a Basic Data-Flow Processor4.

Processor is described which can achieve highly parallel execution of programs represented in data- flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor is a step toward a practical data-flow processor for a Fortran-level data-flow language. The processor has a unique archi- tecture which avoids the problems of processor switching and memory/processor interconnecion that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of struc- turing and managing a two-level memory system.

RISC Architecture

I should be a small fast, maybe a 64-Bit RISC architecture like MMIX5.

High-level Language Computer Architecture

Lisp Machine

Footnotes

  1. Apple MacBook Air "M1" 8 CPU/8 GPU 13" Specs ↩

  2. The Hundred-Year Language - Paul Graham ↩

  3. Lisp Machine ↩

  4. Preliminary Architecture for a Basic Data-Flow Processor - Jack Dennis ↩

  5. MMIX - A RISC Computer for the 3rd Millennium - Donald Knuth ↩