diff --git a/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts b/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts
index 9d6c690c3a03..ea50d423a3ba 100644
--- a/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts
+++ b/patch/kernel/archive/rockchip64-6.12/dt/rk3566-bigtreetech-cb2.dts
@@ -280,7 +280,6 @@
 
 	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
-	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
 	/* Reset time is 20ms, 100ms for rtl8211f */
 	//snps,reset-delays-us = <0 20000 100000>;
 	snps,reset-delays-us = <0 50000 200000>;
@@ -677,7 +676,9 @@
 };
 
 &pcie2x1 {
-	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
 };
@@ -780,6 +781,10 @@
 		pcie_drv: pcie-drv {
 			rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	edp {
diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts
index 0a2338f6ec42..c68a302c87cd 100644
--- a/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts
+++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-bigtreetech-cb2.dts
@@ -280,7 +280,6 @@
 
 	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
-	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
 	/* Reset time is 20ms, 100ms for rtl8211f */
 	//snps,reset-delays-us = <0 20000 100000>;
 	snps,reset-delays-us = <0 50000 200000>;
@@ -677,7 +676,9 @@
 };
 
 &pcie2x1 {
-	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
 };
@@ -780,6 +781,10 @@
 		pcie_drv: pcie-drv {
 			rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	edp {