Fix Yosys memory limit

[DanielleHuisman]

Yosys.js will run out of memory when synthesising larger designs. The memory limit should be increased or WebAssembly should be allowed to dynamically resize its memory.

Example design that runs out of memory:

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.6.2. DO NOT MODIFY.
*/
`timescale 100fs/100fs
module dotp
    ( // Inputs
      input [63:0] eta
    , input [63:0] eta1

      // Outputs
    , output wire signed [7:0] result
    );
  wire [63:0] c$app_arg;

  // zipWith start
  genvar i;
  generate
  for (i = 0; i < 8; i = i + 1) begin : zipWith
    wire signed [7:0] zipWith_in1;
    assign zipWith_in1 = eta[i*8+:8];
    wire signed [7:0] zipWith_in2;
    assign zipWith_in2 = eta1[i*8+:8];
    wire signed [7:0] c$n;
    assign c$n = zipWith_in1 * zipWith_in2;


    assign c$app_arg[i*8+:8] = c$n;
  end
  endgenerate
  // zipWith end

  wire [63:0] vec;
  wire signed [7:0] acc_3_0;
  wire signed [7:0] acc_1;
  wire signed [7:0] acc_2;
  wire signed [7:0] acc_3;
  wire signed [7:0] acc_4;
  wire signed [7:0] acc_5;
  wire signed [7:0] acc_6;
  wire signed [7:0] acc_7;
  wire signed [7:0] acc_8;
  wire signed [7:0] acc_1_0;
  wire signed [7:0] acc_1_1;
  wire signed [7:0] acc_1_2;
  wire signed [7:0] acc_1_3;
  wire signed [7:0] acc_2_0;
  wire signed [7:0] acc_2_1;
  assign result = acc_3_0;

  assign vec = c$app_arg;

  assign acc_1 = $signed(vec[63:56]);
  assign acc_2 = $signed(vec[55:48]);
  assign acc_3 = $signed(vec[47:40]);
  assign acc_4 = $signed(vec[39:32]);
  assign acc_5 = $signed(vec[31:24]);
  assign acc_6 = $signed(vec[23:16]);
  assign acc_7 = $signed(vec[15:8]);
  assign acc_8 = $signed(vec[7:0]);
  assign acc_1_0 = acc_1 + acc_2;
  assign acc_1_1 = acc_3 + acc_4;
  assign acc_1_2 = acc_5 + acc_6;
  assign acc_1_3 = acc_7 + acc_8;
  assign acc_2_0 = acc_1_0 + acc_1_1;
  assign acc_2_1 = acc_1_2 + acc_1_3;
  assign acc_3_0 = acc_2_0 + acc_2_1;
endmodule