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Plus +3 wiznet #1021
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Hi Alan, That's a great news! I'm experiencing extremely busy weeks recently, but I'll try to give it a go when the tide gets low again. I'm slightly confused that the change was introduced on the Thanks, |
I managed to squash the +3 kernel down enough to do an unbanked solution. Will look at spectra for straight 128K later |
Ok then, it means |
I think |
Strange things are happening when I'm trying to build the
can be addressed with a simple hack:
|
Should also be fixed. Things broke a bit from adding the 8080/5 native compiler set up. The Z80 one needs thought as the native and cross compilers are different so libc needs building twice somehow |
looking at the function stubs in the |
Not sure I understand the question. The stubs are expecting to be able to drive the Wiznet chip (presumably by switching all the memory maps back and forth) |
Well, the only WizNet device I have is the Spectranet. I could be wrong and maybe I'm seeing non-existing problem, but for me, it doesn't seem doable to talk to the chip directly bypassing CPLD. So unless those once mentioned changes in the Spectranet firmware are about facilitating that, or we're talking about some abstract WizNet device and Spectranet isn't just one of them, and I should rather look at the |
The CPLD doesn't appear to do anything magic. It's just mapping the device directly into the Z80 address space. The device has 3 modes
The wiznet using systems currently in the kernel use the few addresses mode and indexes. The CPLD merely maps the device 128K into a load of 4K pages in the spectranet space when paged in. Either way of accessing them should work although I imagine mapping it and writing directly will be faster than pinning the one page and using the indirect modes |
Plus 3 kernel squashed, now seems to fit networking and more. Need to write the low level wiznet glue including the crazy mode
bank flipping sequences.
@pawosm-arm FYI
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