diff --git a/.gitignore b/.gitignore index b5ed87f70..677cee747 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,5 @@ .pioenvs -*.v -*.pcf +*.out *.asc *.bin *.blif diff --git a/examples/example.ice b/examples/example.ice index bbbd294dd..8c6464e6a 100644 --- a/examples/example.ice +++ b/examples/example.ice @@ -1 +1 @@ -{"nodes":[],"connections":[]} \ No newline at end of file +{"nodes":[{"name":"","type":"driver0","value":0,"inline":"assign o0 = 1'b0;","id":11,"x":235,"y":151,"width":50,"outputConnectors":[{"name":"\"0\""}]},{"name":"","type":"output","value":"95","id":12,"x":403,"y":111,"width":60,"inputConnectors":[{"name":"95"}]},{"name":"","type":"output","value":"96","id":13,"x":396,"y":217,"width":60,"inputConnectors":[{"name":"96"}]}],"connections":[{"source":{"nodeID":11,"connectorIndex":0},"dest":{"nodeID":12,"connectorIndex":0}},{"source":{"nodeID":11,"connectorIndex":0},"dest":{"nodeID":13,"connectorIndex":0}}]} \ No newline at end of file diff --git a/gui/build.py b/gui/build.py index 2f7fee4ff..debca431b 100755 --- a/gui/build.py +++ b/gui/build.py @@ -153,14 +153,19 @@ def generate_verilog_main(name, nodes, connections): if node['type'] != 'input' and node['type'] != 'output': inline += node['type'] + 'x ' inline += node['type'] + str(node['id']) + ' (\n' + io = [] params = [] for index, connection in enumerate(connections): if node['id'] == connection['source']['nodeID']: param = 'o' + str(connection['source']['connectorIndex']) - params += [' .{0}(w{1})'.format(param, index)] + if param not in io: + io += [param] + params += [' .{0}(w{1})'.format(param, index)] if node['id'] == connection['dest']['nodeID']: param = 'i' + str(connection['dest']['connectorIndex']) - params += [' .{0}(w{1})'.format(param, index)] + if param not in io: + io += [param] + params += [' .{0}(w{1})'.format(param, index)] inline += ',\n'.join(params) + '\n' inline += ');\n' diff --git a/src/main.pcf b/src/main.pcf index e69de29bb..028504df6 100644 --- a/src/main.pcf +++ b/src/main.pcf @@ -0,0 +1,2 @@ +set_io output12 95 +set_io output13 96 diff --git a/src/main.v b/src/main.v index b5401b52e..c2d3a4901 100644 --- a/src/main.v +++ b/src/main.v @@ -1,4 +1,16 @@ // Generated verilog -module main(); +module driver0x(output o0); +assign o0 = 1'b0; +endmodule + +module main(output output12, output13); +wire w0; +wire w1; +assign output12 = w0; +assign output13 = w1; +assign w0 = w1; +driver0x driver011 ( + .o0(w0) +); endmodule