diff --git a/llvm/README.txt b/llvm/README.txt index b9b71a3b6daff..1598d75b02c11 100644 --- a/llvm/README.txt +++ b/llvm/README.txt @@ -15,3 +15,6 @@ documentation setup. If you are writing a package for LLVM, see docs/Packaging.rst for our suggestions. + +Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +Notified per clause 4(b) of the license. diff --git a/llvm/cmake/modules/HandleLLVMOptions.cmake b/llvm/cmake/modules/HandleLLVMOptions.cmake index dd20573c4e4a4..75da6385c26ad 100644 --- a/llvm/cmake/modules/HandleLLVMOptions.cmake +++ b/llvm/cmake/modules/HandleLLVMOptions.cmake @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # This CMake module is responsible for interpreting the user defined LLVM_ # options and executing the appropriate CMake commands to realize the users' # selections. diff --git a/llvm/cmake/modules/LLVMConfig.cmake.in b/llvm/cmake/modules/LLVMConfig.cmake.in index 4ead4f4198ff2..2080318ff9d40 100644 --- a/llvm/cmake/modules/LLVMConfig.cmake.in +++ b/llvm/cmake/modules/LLVMConfig.cmake.in @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # This file provides information and services to the final user. @LLVM_CONFIG_CODE@ diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index f661684d9b74c..d23913ef38c15 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -1371,6 +1371,9 @@ are deprecated and should not be used. ======== ============================== ====================================== "AMDGPU" ``NT_AMDGPU_METADATA`` Metadata in Message Pack [MsgPack]_ binary format. + "AMDGPU" ``NT_AMDGPU_LLPC_CACHE_HASH`` 16-bytes cache hash of ELF. + "AMDGPU" ``NT_AMDGPU_LLPC_VERSION`` LLPC version with 4-bytes major + and 4-bytes minor version numbers ======== ============================== ====================================== .. @@ -1383,6 +1386,8 @@ are deprecated and should not be used. ============================== ===== *reserved* 0-31 ``NT_AMDGPU_METADATA`` 32 + ``NT_AMDGPU_LLPC_CACHE_HASH`` 33 + ``NT_AMDGPU_LLPC_VERSION`` 34 ============================== ===== ``NT_AMDGPU_METADATA`` @@ -1392,6 +1397,14 @@ are deprecated and should not be used. :ref:`amdgpu-amdhsa-code-object-metadata-v4` for the map keys defined for the ``amdhsa`` OS. +``NT_AMDGPU_LLPC_CACHE_HASH`` + Specifies 16-bytes cache hash of the ELF. + +``NT_AMDGPU_LLPC_VERSION`` + LLPC version that consists of 4-bytes major and 4-bytes minor version numbers. + The version information can be used to explain what hash algorithm was used to + generate the cache hash specified by ``NT_AMDGPU_LLPC_CACHE_HASH``. + .. _amdgpu-symbols: Symbols diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h index 1552303b610ca..df4a2a086762f 100644 --- a/llvm/include/llvm/BinaryFormat/ELF.h +++ b/llvm/include/llvm/BinaryFormat/ELF.h @@ -1539,7 +1539,9 @@ enum { // AMDGPU specific notes. (Code Object V3) enum { // Note types with values between 0 and 31 (inclusive) are reserved. - NT_AMDGPU_METADATA = 32 + NT_AMDGPU_METADATA = 32, + NT_AMDGPU_LLPC_CACHE_HASH = 33, + NT_AMDGPU_LLPC_VERSION = 34, }; enum { diff --git a/llvm/include/llvm/Config/llvm-config.h.cmake b/llvm/include/llvm/Config/llvm-config.h.cmake index ca36f5071a9d7..3d21197731e9a 100644 --- a/llvm/include/llvm/Config/llvm-config.h.cmake +++ b/llvm/include/llvm/Config/llvm-config.h.cmake @@ -4,6 +4,8 @@ /* Exceptions. */ /* See https://llvm.org/LICENSE.txt for license information. */ /* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception */ +/* Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. */ +/* Notified per clause 4(b) of the license. */ /* */ /*===----------------------------------------------------------------------===*/ diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 3890e412d8da2..d6b0cd6498ffc 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 149cb498b48fa..813f0acf6a431 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // /// \file //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 3afa4a2ec6a28..fdfc7af8acc10 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td index 2c3b8cac9a075..7c74c36f4cfc5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp b/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp index 9c67b1029b9d7..37fb1002aca80 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp @@ -4,6 +4,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index de2ec282d8a83..8a5688aea6af6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //==-----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 6f8504fc8f120..82b898f289f05 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 025568e65613b..9349da4339213 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td index fd5a3ccbfba4a..caafd5acab933 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index aad1b921413ce..e453b06d1577d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// /// \file diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp index 9fc49fdff26cc..e3373ed34052b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp index 811f6104eeda2..36cd5c6ec611c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h index 8ce9fdc77e186..adbe02ea8c093 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 3d8434bbc54dd..b737ff6917ccc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// /// \file diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td index 74c81d31412f4..8c438b5ea38e0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 32d773a7f9c55..cf24b1b3be992 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h index 9ee6f62b7f251..e00e72a405e57 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //==-----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 79722af285f8c..eebb479f4c4ab 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index 8b167aedee2cd..b2b9b731b8b21 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index 1eca3db55dba4..6e82ba211a10a 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. add_llvm_component_group(AMDGPU) set(LLVM_TARGET_DEFINITIONS AMDGPU.td) diff --git a/llvm/lib/Target/AMDGPU/SIBufMemMerge.cpp b/llvm/lib/Target/AMDGPU/SIBufMemMerge.cpp index 5ce453041e237..714295721acf0 100644 --- a/llvm/lib/Target/AMDGPU/SIBufMemMerge.cpp +++ b/llvm/lib/Target/AMDGPU/SIBufMemMerge.cpp @@ -4,6 +4,8 @@ // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIFixScratchSize.cpp b/llvm/lib/Target/AMDGPU/SIFixScratchSize.cpp index d68a9312903fc..5060ddb00c00a 100644 --- a/llvm/lib/Target/AMDGPU/SIFixScratchSize.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixScratchSize.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 8bb7d5de5355a..bf177d9d341a3 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //==-----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index f1c7c817a0328..9107b1636b7eb 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIInsertScratchBounds.cpp b/llvm/lib/Target/AMDGPU/SIInsertScratchBounds.cpp index e5c805ff15435..1c2f58af1fc9f 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertScratchBounds.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertScratchBounds.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp index 13fce50c51c43..267828648ce6d 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp index d764570062804..fd0529ef3ab6a 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp @@ -4,6 +4,8 @@ // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index ab6a96ccea7a9..fc073bc2fce3a 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index e64c9e62ec793..3a17042e1cbb3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // This file was originally auto-generated from a GPU register header file and diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index 4998661f0e6f7..8f51b654d03e8 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index ca53eafa07660..0a1dd765dd367 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index e52f7baae84c0..bf69dc9d2c592 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp index 5a936079c4ed6..f0356432fdbe1 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll index 6b37ff394e500..235b792b21f3e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -o - %s | FileCheck %s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll index 20bff04c42e33..e5ec6b7f63c8a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10NSA %s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll index b545fdfea223d..1a4a337610d98 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10NSA %s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll index 57b6197c774b9..c6fdad7cab418 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll index 3cb16a5d8adb2..0c08191eb267a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX10,VI %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX10,GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll index 2780d99fcd446..52d9a2e7a54cd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index 4fba89bf5d104..c246071c8ab66 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll index cd88dcd7f79ad..f25f6e79a0456 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX89 %s diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll index e7893c7bd6933..372addd58f4e6 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll index ac88623fa1d81..66200a3f42211 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX7LESS %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll index 8a90d1fdbe21b..c478a7ff8b6aa 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-- -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX7 %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll index 7318e3963bf4e..ecf3e84cc8d3c 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll index 96113977ba6fa..251c48772c495 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll index 775baceff0dfe..d423a4b440c79 100644 --- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll +++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN-ISEL %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CISI %s diff --git a/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir index 32019ba0c2761..cd6d8d12de316 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s # # This is another example of a test giving "Couldn't join subrange!" diff --git a/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll b/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll index 83e1e753dc40d..11c931e4fac9d 100644 --- a/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll +++ b/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc --march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,KILL,DEMOTE %s ; Check that the branch is removed by the discard opt. diff --git a/llvm/test/CodeGen/AMDGPU/discard-optimization.ll b/llvm/test/CodeGen/AMDGPU/discard-optimization.ll index 39d214c044c8e..c6e1d7d5bf01b 100644 --- a/llvm/test/CodeGen/AMDGPU/discard-optimization.ll +++ b/llvm/test/CodeGen/AMDGPU/discard-optimization.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -amdgpu-conditional-discard-transformations=1 --march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,KILL %s ; RUN: llc -amdgpu-conditional-discard-transformations=1 -amdgpu-transform-discard-to-demote --march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,DEMOTE %s diff --git a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll index 05564735a64ae..cbc27703e3e19 100644 --- a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll index 8d0eb7046009b..2fccdcf7cf3e1 100644 --- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=SIVI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -denormal-fp-math=preserve-sign -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll index 6a09089460488..dfbc067320f1f 100644 --- a/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll index 879b862b8fae2..008b422fa6010 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX10 %s diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll index ea69e9c1ecbd2..4b8380cbc4476 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=TONGA %s ; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=GFX81 %s diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll index 686a4a09aad37..2bec2837f0120 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=VERDE %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6789 %s diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll index 7aa1597e20c7c..5d93bb083daa9 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: {{^}}test1: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll index e7150ec96b2c6..20de601fab296 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SI ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SI ;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=GFX10 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll index 6a920d843de69..a5f78d5f48e45 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CHECK %s ; Check that WQM is not triggered by the softwqm intrinsic alone. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll index 878a0b3f08257..3f1723fa43c45 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,PRE_GFX10,GCN-64 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9_UP,PRE_GFX10,GCN-64 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX9_UP,GCN-32 %s diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll index 6fc5fd6a0e4d9..3cec7db59f8ef 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-64,PRE-GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-64,PRE-GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GCN-32 %s diff --git a/llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll b/llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll index 9ff56e1d1f85f..52ad8ac805405 100644 --- a/llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll +++ b/llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; Where the mask of lanes wanting to exit the loop on this iteration is not diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll index 6fbf262ff3f45..88675bf599b7e 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -enable-misched=false < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-misched=false < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s ; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -enable-misched=false < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s diff --git a/llvm/test/CodeGen/AMDGPU/memory_clause.ll b/llvm/test/CodeGen/AMDGPU/memory_clause.ll index 8ccd313e02cde..2159a23e0186a 100644 --- a/llvm/test/CodeGen/AMDGPU/memory_clause.ll +++ b/llvm/test/CodeGen/AMDGPU/memory_clause.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx1030 -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SCRATCH %s diff --git a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll index 6ea6b7ae7815e..f7f78439a1b30 100644 --- a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll +++ b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir index fe14bf7cc4f0d..b4398ab905876 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -mtriple=amdgcn--amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir index af60c4c7232e5..0880e72af9cfe 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -mtriple=amdgcn--amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll b/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll index b5285509675d3..fcbb60a38dfd7 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll +++ b/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; ; This test was causing a "Use not jointly dominated by defs" when diff --git a/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir b/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir index 1c7962558e16a..3040668486ff3 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # diff --git a/llvm/test/CodeGen/AMDGPU/sbuff-merge.ll b/llvm/test/CodeGen/AMDGPU/sbuff-merge.ll index 933b8b075f628..86696c14a328a 100644 --- a/llvm/test/CodeGen/AMDGPU/sbuff-merge.ll +++ b/llvm/test/CodeGen/AMDGPU/sbuff-merge.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/scratch-bounds.ll b/llvm/test/CodeGen/AMDGPU/scratch-bounds.ll index 523830703a57d..81a757280f2bd 100644 --- a/llvm/test/CodeGen/AMDGPU/scratch-bounds.ll +++ b/llvm/test/CodeGen/AMDGPU/scratch-bounds.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16,+enable-scratch-bounds-checks < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=gfx1010 -mattr=+max-private-element-size-16,+enable-scratch-bounds-checks < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index edd48949e3ae7..5f274d74e5b41 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s diff --git a/llvm/test/CodeGen/AMDGPU/smrd.ll b/llvm/test/CodeGen/AMDGPU/smrd.ll index a1865aefefa50..36c12214835f2 100644 --- a/llvm/test/CodeGen/AMDGPU/smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/smrd.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck --check-prefixes=SI,GCN,SICIVI,SICI,SIVIGFX9_10 %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck --check-prefixes=CI,GCN,SICIVI,SICI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck --check-prefixes=VI,GCN,SICIVI,VIGFX9_10,SIVIGFX9_10 %s diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll index 26f62828a8b12..3a5a226d3e68c 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefixes=CHECK,GFX6 %s ; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=CHECK,GFX9-FLATSCR,FLATSCR %s diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index 93210eda40fad..0290ef67b7771 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll b/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll index 07342482de9f7..4626ee6a69a9c 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index c6257a748f378..c3c43d5714f37 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index 60e39b157056d..d663d0cff83fa 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s diff --git a/llvm/test/CodeGen/AMDGPU/wqm.ll b/llvm/test/CodeGen/AMDGPU/wqm.ll index 7dd91e940c94b..d396680518496 100644 --- a/llvm/test/CodeGen/AMDGPU/wqm.ll +++ b/llvm/test/CodeGen/AMDGPU/wqm.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll index 0193313ff213c..ba5ba0f9b047b 100644 --- a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll +++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O0 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O3 %s diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll index c991a337c3f04..4f091c7ce6a38 100644 --- a/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll index 155287c16e831..3331700222903 100644 --- a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll +++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s diff --git a/llvm/test/tools/llvm-readobj/ELF/note-amd.s b/llvm/test/tools/llvm-readobj/ELF/note-amd.s index 94feaa27d8a98..b74c4ef6ba196 100644 --- a/llvm/test/tools/llvm-readobj/ELF/note-amd.s +++ b/llvm/test/tools/llvm-readobj/ELF/note-amd.s @@ -12,6 +12,9 @@ // GNU-NEXT: AMD 0x00000000 NT_AMD_AMDGPU_ISA (ISA Version) // GNU-NEXT: ISA Version: // GNU-NEXT: {{^ +$}} +// GNU-NEXT: AMD 0x00000010 NT_AMDGPU_LLPC_CACHE_HASH (LLPC Cache Hash) +// GNU-NEXT: LLPC Cache Hash: +// GNU-NEXT: ddccbbaa 2211ffee 66554433 aa998877 // GNU-NEXT: Displaying notes found in: .note.desc // GNU-NEXT: Owner Data size Description // GNU-NEXT: AMD 0x0000000a NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata) @@ -23,6 +26,9 @@ // GNU-NEXT: Displaying notes found in: .note.other // GNU-NEXT: Owner Data size Description // GNU-NEXT: AMD 0x00000000 NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata) +// GNU-NEXT: AMD 0x00000008 NT_AMDGPU_LLPC_VERSION (LLPC Version) +// GNU-NEXT: LLPC Version: +// GNU-NEXT: 45.6 // LLVM: Notes [ // LLVM-NEXT: NoteSection { @@ -41,6 +47,12 @@ // LLVM-NEXT: Type: NT_AMD_AMDGPU_ISA (ISA Version) // LLVM-NEXT: ISA Version: // LLVM-NEXT: } +// LLVM-NEXT: Note { +// LLVM-NEXT: Owner: AMD +// LLVM-NEXT: Data size: 0x10 +// LLVM-NEXT: Type: NT_AMDGPU_LLPC_CACHE_HASH (LLPC Cache Hash) +// LLVM-NEXT: LLPC Cache Hash: ddccbbaa 2211ffee 66554433 aa998877 +// LLVM-NEXT: } // LLVM-NEXT: } // LLVM-NEXT: NoteSection { // LLVM-NEXT: Name: .note.desc @@ -68,6 +80,12 @@ // LLVM-NEXT: Data size: 0x0 // LLVM-NEXT: Type: NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata) // LLVM-NEXT: } +// LLVM-NEXT: Note { +// LLVM-NEXT: Owner: AMD +// LLVM-NEXT: Data size: 0x8 +// LLVM-NEXT: Type: NT_AMDGPU_LLPC_VERSION (LLPC Version) +// LLVM-NEXT: LLPC Version: 45.6 +// LLVM-NEXT: } // LLVM-NEXT: } // LLVM-NEXT: ] @@ -81,6 +99,14 @@ .long 0 /* descsz */ .long 11 /* type = NT_AMD_AMDGPU_ISA */ .asciz "AMD" + .long 4 /* namesz */ + .long 16 /* descsz */ + .long 33 /* type = NT_AMDGPU_LLPC_CACHE_HASH */ + .asciz "AMD" + .long 0xaabbccdd + .long 0xeeff1122 + .long 0x33445566 + .long 0x778899aa .section ".note.desc", "a" .align 4 .long 4 /* namesz */ @@ -105,3 +131,9 @@ end.isa: .long 0 /* descsz */ .long 12 /* type = NT_AMD_AMDGPU_PAL_METADATA */ .asciz "AMD" + .long 4 /* namesz */ + .long 8 /* descsz */ + .long 34 /* type = NT_AMDGPU_LLPC_VERSION */ + .asciz "AMD" + .long 45 + .long 6 diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp index f04dec998673b..2b6d24763c624 100644 --- a/llvm/tools/llvm-readobj/ELFDumper.cpp +++ b/llvm/tools/llvm-readobj/ELFDumper.cpp @@ -4922,6 +4922,23 @@ static AMDNote getAMDNote(uint32_t NoteType, ArrayRef Desc) { return { "ISA Version", std::string(reinterpret_cast(Desc.data()), Desc.size())}; + case ELF::NT_AMDGPU_LLPC_CACHE_HASH: { + std::string Hash; + raw_string_ostream StrOS(Hash); + StrOS << format_bytes(Desc); + return {"LLPC Cache Hash", Hash}; + } + case ELF::NT_AMDGPU_LLPC_VERSION: { + assert(Desc.size() == 8); + uint64_t MajorVersion = + decodeULEB128(Desc.data(), nullptr, Desc.data() + 4); + uint64_t MinorVersion = + decodeULEB128(Desc.data() + 4, nullptr, Desc.data() + 8); + std::string Version; + raw_string_ostream StrOS(Version); + StrOS << MajorVersion << "." << MinorVersion; + return {"LLPC Version", Version}; + } } } @@ -5067,6 +5084,9 @@ static const NoteType AMDNoteTypes[] = { {ELF::NT_AMD_AMDGPU_ISA, "NT_AMD_AMDGPU_ISA (ISA Version)"}, {ELF::NT_AMD_AMDGPU_PAL_METADATA, "NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata)"}, + {ELF::NT_AMDGPU_LLPC_CACHE_HASH, + "NT_AMDGPU_LLPC_CACHE_HASH (LLPC Cache Hash)"}, + {ELF::NT_AMDGPU_LLPC_VERSION, "NT_AMDGPU_LLPC_VERSION (LLPC Version)"}, }; static const NoteType AMDGPUNoteTypes[] = { diff --git a/llvm/utils/emacs/README b/llvm/utils/emacs/README deleted file mode 100644 index d0f2bfbbb3e58..0000000000000 --- a/llvm/utils/emacs/README +++ /dev/null @@ -1,27 +0,0 @@ --*- llvm/utils/emacs/README -*- - -These are syntax highlighting files for the Emacs and XEmacs editors. Included -are: - -* llvm-mode.el - - Syntax highlighting mode for LLVM assembly files. To use, add this code to - your ~/.emacs : - - (setq load-path - (cons (expand-file-name "path-to-llvm/utils/emacs") load-path)) - (require 'llvm-mode) - -* tablegen-mode.el - - Syntax highlighting mode for TableGen description files. To use, add this code - to your ~/.emacs: - - (setq load-path - (cons (expand-file-name "path-to-llvm/utils/emacs") load-path)) - (require 'tablegen-mode) - - -Note: If you notice missing or incorrect syntax highlighting, please contact -; if you wish to provide a patch to improve the -functionality, it will be most appreciated. Thank you. diff --git a/llvm/utils/emacs/emacs.el b/llvm/utils/emacs/emacs.el deleted file mode 100644 index 3a2b47cee1db1..0000000000000 --- a/llvm/utils/emacs/emacs.el +++ /dev/null @@ -1,32 +0,0 @@ -;; LLVM coding style guidelines in emacs -;; Maintainer: LLVM Team, http://llvm.org/ - -(defun llvm-lineup-statement (langelem) - (let ((in-assign (c-lineup-assignments langelem))) - (if (not in-assign) - '++ - (aset in-assign 0 - (+ (aref in-assign 0) - (* 2 c-basic-offset))) - in-assign))) - -;; Add a cc-mode style for editing LLVM C and C++ code -(c-add-style "llvm.org" - '("gnu" - (fill-column . 80) - (c++-indent-level . 2) - (c-basic-offset . 2) - (indent-tabs-mode . nil) - (c-offsets-alist . ((arglist-intro . ++) - (innamespace . 0) - (member-init-intro . ++) - (statement-cont . llvm-lineup-statement))))) - -;; Files with "llvm" in their names will automatically be set to the -;; llvm.org coding style. -(add-hook 'c-mode-common-hook - (function - (lambda nil - (if (string-match "llvm" buffer-file-name) - (progn - (c-set-style "llvm.org")))))) diff --git a/llvm/utils/emacs/llvm-mode.el b/llvm/utils/emacs/llvm-mode.el deleted file mode 100644 index bc24b12fb01fd..0000000000000 --- a/llvm/utils/emacs/llvm-mode.el +++ /dev/null @@ -1,104 +0,0 @@ -;;; llvm-mode.el --- Major mode for the LLVM assembler language. - -;; Maintainer: The LLVM team, http://llvm.org/ -;; Version: 1.0 - -;;; Commentary: - -;; Major mode for editing LLVM IR files. - -;;; Code: - -(defvar llvm-mode-syntax-table - (let ((table (make-syntax-table))) - (modify-syntax-entry ?% "_" table) - (modify-syntax-entry ?. "_" table) - (modify-syntax-entry ?\; "< " table) - (modify-syntax-entry ?\n "> " table) - table) - "Syntax table used while in LLVM mode.") - -(defvar llvm-font-lock-keywords - (list - ;; Attributes - `(,(regexp-opt - '("alwaysinline" "argmemonly" "builtin" "cold" "convergent" "inaccessiblememonly" - "inaccessiblemem_or_argmemonly" "inlinehint" "jumptable" "minsize" "mustprogress" "naked" "nobuiltin" - "noduplicate" "nofree" "noimplicitfloat" "noinline" "nonlazybind" "noredzone" "noreturn" - "norecurse" "noundef" "nounwind" "optnone" "optsize" "readnone" "readonly" "returns_twice" - "speculatable" "ssp" "sspreq" "sspstrong" "safestack" "sanitize_address" "sanitize_hwaddress" "sanitize_memtag" - "sanitize_thread" "sanitize_memory" "strictfp" "uwtable" "willreturn" "writeonly" "immarg") 'symbols) . font-lock-constant-face) - ;; Variables - '("%[-a-zA-Z$._][-a-zA-Z$._0-9]*" . font-lock-variable-name-face) - ;; Labels - '("[-a-zA-Z$._0-9]+:" . font-lock-variable-name-face) - ;; Unnamed variable slots - '("%[-]?[0-9]+" . font-lock-variable-name-face) - ;; Types - `(,(regexp-opt '("void" "i1" "i8" "i16" "i32" "i64" "i128" "float" "double" "type" "label" "opaque") 'symbols) . font-lock-type-face) - ;; Integer literals - '("\\b[-]?[0-9]+\\b" . font-lock-preprocessor-face) - ;; Floating point constants - '("\\b[-+]?[0-9]+.[0-9]*\\([eE][-+]?[0-9]+\\)?\\b" . font-lock-preprocessor-face) - ;; Hex constants - '("\\b0x[0-9A-Fa-f]+\\b" . font-lock-preprocessor-face) - ;; Keywords - `(,(regexp-opt - '(;; Toplevel entities - "declare" "define" "module" "target" "source_filename" "global" "constant" "const" - "attributes" "uselistorder" "uselistorder_bb" - ;; Linkage types - "private" "internal" "weak" "weak_odr" "linkonce" "linkonce_odr" "available_externally" "appending" "common" "extern_weak" "external" - "uninitialized" "implementation" "..." - ;; Values - "true" "false" "null" "undef" "zeroinitializer" "none" "c" "asm" "blockaddress" - - ;; Calling conventions - "ccc" "fastcc" "coldcc" "webkit_jscc" "anyregcc" "preserve_mostcc" "preserve_allcc" - "cxx_fast_tlscc" "swiftcc" - - "atomic" "volatile" "personality" "prologue" "section") 'symbols) . font-lock-keyword-face) - ;; Arithmetic and Logical Operators - `(,(regexp-opt '("add" "sub" "mul" "sdiv" "udiv" "urem" "srem" "and" "or" "xor" - "setne" "seteq" "setlt" "setgt" "setle" "setge") 'symbols) . font-lock-keyword-face) - ;; Floating-point operators - `(,(regexp-opt '("fadd" "fsub" "fneg" "fmul" "fdiv" "frem") 'symbols) . font-lock-keyword-face) - ;; Special instructions - `(,(regexp-opt '("phi" "tail" "call" "select" "to" "shl" "lshr" "ashr" "fcmp" "icmp" "va_arg" "landingpad" "freeze") 'symbols) . font-lock-keyword-face) - ;; Control instructions - `(,(regexp-opt '("ret" "br" "switch" "invoke" "resume" "unwind" "unreachable" "indirectbr" "callbr") 'symbols) . font-lock-keyword-face) - ;; Memory operators - `(,(regexp-opt '("malloc" "alloca" "free" "load" "store" "getelementptr" "fence" "cmpxchg" "atomicrmw") 'symbols) . font-lock-keyword-face) - ;; Casts - `(,(regexp-opt '("bitcast" "inttoptr" "ptrtoint" "trunc" "zext" "sext" "fptrunc" "fpext" "fptoui" "fptosi" "uitofp" "sitofp" "addrspacecast") 'symbols) . font-lock-keyword-face) - ;; Vector ops - `(,(regexp-opt '("extractelement" "insertelement" "shufflevector") 'symbols) . font-lock-keyword-face) - ;; Aggregate ops - `(,(regexp-opt '("extractvalue" "insertvalue") 'symbols) . font-lock-keyword-face) - ;; Metadata types - `(,(regexp-opt '("distinct") 'symbols) . font-lock-keyword-face) - ;; Use-list order directives - `(,(regexp-opt '("uselistorder" "uselistorder_bb") 'symbols) . font-lock-keyword-face)) - "Syntax highlighting for LLVM.") - -;; Emacs 23 compatibility. -(defalias 'llvm-mode-prog-mode - (if (fboundp 'prog-mode) - 'prog-mode - 'fundamental-mode)) - -;;;###autoload -(define-derived-mode llvm-mode llvm-mode-prog-mode "LLVM" - "Major mode for editing LLVM source files. -\\{llvm-mode-map} - Runs `llvm-mode-hook' on startup." - (setq font-lock-defaults `(llvm-font-lock-keywords)) - (setq-local comment-start ";")) - -;; Associate .ll files with llvm-mode -;;;###autoload -(add-to-list 'auto-mode-alist (cons "\\.ll\\'" 'llvm-mode)) - -(provide 'llvm-mode) - -;;; llvm-mode.el ends here diff --git a/llvm/utils/emacs/tablegen-mode.el b/llvm/utils/emacs/tablegen-mode.el deleted file mode 100644 index 572823fa56e13..0000000000000 --- a/llvm/utils/emacs/tablegen-mode.el +++ /dev/null @@ -1,129 +0,0 @@ -;;; tablegen-mode.el --- Major mode for TableGen description files (part of LLVM project) - -;; Maintainer: The LLVM team, http://llvm.org/ - -;;; Commentary: -;; A major mode for TableGen description files in LLVM. - -(require 'comint) -(require 'custom) -(require 'ansi-color) - -;; Create mode-specific tables. -;;; Code: - -(defvar td-decorators-face 'td-decorators-face - "Face method decorators.") -(make-face 'td-decorators-face) - -(defvar tablegen-font-lock-keywords - (let ((kw (regexp-opt '("class" "defm" "def" "field" "include" "in" - "let" "multiclass" "foreach" "if" "then" "else" - "defvar" "defset") - 'words)) - (type-kw (regexp-opt '("bit" "bits" "code" "dag" "int" "list" "string") - 'words)) - ) - (list - ;; Comments -;; '("\/\/" . font-lock-comment-face) - ;; Strings - '("\"[^\"]+\"" . font-lock-string-face) - ;; Hex constants - '("\\<0x[0-9A-Fa-f]+\\>" . font-lock-preprocessor-face) - ;; Binary constants - '("\\<0b[01]+\\>" . font-lock-preprocessor-face) - ;; Integer literals - '("\\<[-]?[0-9]+\\>" . font-lock-preprocessor-face) - ;; Floating point constants - '("\\<[-+]?[0-9]+\.[0-9]*\([eE][-+]?[0-9]+\)?\\>" . font-lock-preprocessor-face) - - '("^[ \t]*\\(@.+\\)" 1 'td-decorators-face) - ;; Keywords - kw - ;; Type keywords - type-kw - )) - "Additional expressions to highlight in TableGen mode.") -(put 'tablegen-mode 'font-lock-defaults '(tablegen-font-lock-keywords)) - -;; ---------------------- Syntax table --------------------------- - -(defvar tablegen-mode-syntax-table nil - "Syntax table used in `tablegen-mode' buffers.") -(when (not tablegen-mode-syntax-table) - (setq tablegen-mode-syntax-table (make-syntax-table)) - ;; whitespace (` ') - (modify-syntax-entry ?\ " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\t " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\r " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\n " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\f " " tablegen-mode-syntax-table) - ;; word constituents (`w') - (modify-syntax-entry ?\% "w" tablegen-mode-syntax-table) - (modify-syntax-entry ?\_ "w" tablegen-mode-syntax-table) - ;; comments - (modify-syntax-entry ?/ ". 124b" tablegen-mode-syntax-table) - (modify-syntax-entry ?* ". 23" tablegen-mode-syntax-table) - (modify-syntax-entry ?\n "> b" tablegen-mode-syntax-table) - ;; open paren (`(') - (modify-syntax-entry ?\( "(" tablegen-mode-syntax-table) - (modify-syntax-entry ?\[ "(" tablegen-mode-syntax-table) - (modify-syntax-entry ?\{ "(" tablegen-mode-syntax-table) - (modify-syntax-entry ?\< "(" tablegen-mode-syntax-table) - ;; close paren (`)') - (modify-syntax-entry ?\) ")" tablegen-mode-syntax-table) - (modify-syntax-entry ?\] ")" tablegen-mode-syntax-table) - (modify-syntax-entry ?\} ")" tablegen-mode-syntax-table) - (modify-syntax-entry ?\> ")" tablegen-mode-syntax-table) - ;; string quote ('"') - (modify-syntax-entry ?\" "\"" tablegen-mode-syntax-table) - ) - -;; --------------------- Abbrev table ----------------------------- - -(defvar tablegen-mode-abbrev-table nil - "Abbrev table used while in TableGen mode.") -(define-abbrev-table 'tablegen-mode-abbrev-table ()) - -(defvar tablegen-mode-hook nil) -(defvar tablegen-mode-map nil) ; Create a mode-specific keymap. - -(if (not tablegen-mode-map) - () ; Do not change the keymap if it is already set up. - (setq tablegen-mode-map (make-sparse-keymap)) - (define-key tablegen-mode-map "\t" 'tab-to-tab-stop) - (define-key tablegen-mode-map "\es" 'center-line) - (define-key tablegen-mode-map "\eS" 'center-paragraph)) - -;;;###autoload -(defun tablegen-mode () - "Major mode for editing TableGen description files. -\\{tablegen-mode-map} - Runs `tablegen-mode-hook' on startup." - (interactive) - (kill-all-local-variables) - (use-local-map tablegen-mode-map) ; Provides the local keymap. - (make-local-variable 'font-lock-defaults) - (setq major-mode 'tablegen-mode ; This is how describe-mode - ; finds the doc string to print. - mode-name "TableGen" ; This name goes into the modeline. - local-abbrev-table tablegen-mode-abbrev-table - font-lock-defaults `(tablegen-font-lock-keywords) - require-final-newline t - ) - - (set-syntax-table tablegen-mode-syntax-table) - (make-local-variable 'comment-start) - (setq comment-start "//") - (setq indent-tabs-mode nil) - (run-hooks 'tablegen-mode-hook)) ; Finally, this permits the user to - ; customize the mode with a hook. - -;; Associate .td files with tablegen-mode -;;;###autoload -(add-to-list 'auto-mode-alist (cons (purecopy "\\.td\\'") 'tablegen-mode)) - -(provide 'tablegen-mode) - -;;; tablegen-mode.el ends here