Set default generic value and fixed bugs in the one and two bit predictors

Author: vladglv

src/branch_prediction/bp_1bit_predictor.vhd

@@ -24,7 +24,6 @@ architecture arch of bp_1bit_predictor is
 
     signal bht_table           : bht_element_type;
     signal prediction_internal : std_logic := '0';
-    signal state               : std_logic := NotTaken;
 
 begin
     prediction <= prediction_internal;
@@ -33,23 +32,20 @@ begin
         variable idx : integer;
     begin
         if reset = '1' then
-            state <= NotTaken;
             for i in 0 to 2 ** BHT_BITS loop
-                bht_table(i) <= '0';
+                bht_table(i) <= NotTaken;
             end loop;
         elsif rising_edge(clock) then
             if update = '1' then
                 idx := to_integer(unsigned(previous_pc(BHT_BITS + 1 downto 2)));
-                case state is
+                case bht_table(idx) is
                     when NotTaken =>
                         if prediction_incorrect = '1' then
-                            state          <= Taken;
-                            bht_table(idx) <= NotTaken;
+                            bht_table(idx) <= Taken;
                         end if;
                     when Taken =>
                         if prediction_incorrect = '1' then
-                            state          <= NotTaken;
-                            bht_table(idx) <= Taken;
+                            bht_table(idx) <= NotTaken;
                         end if;
                     when others =>
                         null;

src/branch_prediction/bp_2bit_predictor.vhd

@@ -25,8 +25,7 @@ architecture arch of bp_2bit_predictor is
     constant NotTaken1 : std_logic_vector(1 downto 0) := "11";
 
     signal bht_table           : bht_element_type;
-    signal prediction_internal : std_logic                    := '0';
-    signal state               : std_logic_vector(1 downto 0) := NotTaken1;
+    signal prediction_internal : std_logic := '0';
 
 begin
     prediction <= prediction_internal;
@@ -35,38 +34,31 @@ begin
         variable idx : integer;
     begin
         if reset = '1' then
-            state <= NotTaken1;
             for i in 0 to 2 ** BHT_BITS loop
                 bht_table(i) <= NotTaken1;
             end loop;
         elsif rising_edge(clock) then
             if update = '1' then
                 idx := to_integer(unsigned(previous_pc(BHT_BITS + 1 downto 2)));
-                case state is
+                case bht_table(idx) is
                     when NotTaken0 =>
                         if prediction_incorrect = '1' then
-                            state          <= Taken1;
                             bht_table(idx) <= Taken1;
                         else
-                            state          <= NotTaken1;
                             bht_table(idx) <= NotTaken1;
                         end if;
                     when NotTaken1 =>
                         if prediction_incorrect = '1' then
-                            state          <= NotTaken0;
                             bht_table(idx) <= NotTaken0;
                         end if;
                     when Taken0 =>
                         if prediction_incorrect = '1' then
-                            state          <= NotTaken1;
                             bht_table(idx) <= NotTaken1;
                         else
-                            state          <= Taken1;
                             bht_table(idx) <= Taken1;
                         end if;
                     when Taken1 =>
                         if prediction_incorrect = '1' then
-                            state          <= Taken0;
                             bht_table(idx) <= Taken0;
                         end if;
                     when others =>

src/branch_prediction/branch_prediction.vhd

@@ -4,7 +4,7 @@ package branch_prediction is
     constant DEFAULT_BHT_BITS : integer := 12;
 
     component bp_2bit_predictor is
-        generic(BHT_BITS : integer);
+        generic(BHT_BITS : integer := DEFAULT_BHT_BITS);
         port(
             clock                : in  std_logic;
             reset                : in  std_logic;
@@ -18,7 +18,7 @@ package branch_prediction is
     end component bp_2bit_predictor;
 
     component bp_1bit_predictor is
-        generic(BHT_BITS : integer);
+        generic(BHT_BITS : integer := DEFAULT_BHT_BITS);
         port(
             clock                : in  std_logic;
             reset                : in  std_logic;

src/processor.vhd

@@ -289,8 +289,7 @@ begin
 
     if_pc_plus_four <= std_logic_vector(unsigned(pc) + 4);
 
-    branch_predictor : bp_2bit_predictor
-        generic map(BHT_BITS => DEFAULT_BHT_BITS)
+    branch_predictor : bp_1bit_predictor
         port map(clock                => clock,
                  reset                => reset,
                  pc                   => pc,