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Add interface parameters #2

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mksoc opened this issue Oct 23, 2024 · 1 comment
Open

Add interface parameters #2

mksoc opened this issue Oct 23, 2024 · 1 comment
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enhancement New feature or request

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@mksoc
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mksoc commented Oct 23, 2024

For interfaces like APB-RT, there are some parameters (SECDED, bit interleaving, ...) that need to be present in the generated Verilog and passed to all slaves.
@mksoc mksoc added the enhancement New feature or request label Oct 23, 2024
@benoitdenkinger
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This is already supported, no?

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add-secded HEP-SoC/PeakRDL-socgen
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