From 3883d335279c418aa71ec7ac987f0ff11273dacd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Risto=20Peja=C5=A1inovi=C4=87?= Date: Sun, 22 Dec 2024 00:28:07 +0100 Subject: [PATCH] fix docs --- docs/docs/examples/simulation.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/docs/examples/simulation.md b/docs/docs/examples/simulation.md index 72cc4d8..77fe63e 100644 --- a/docs/docs/examples/simulation.md +++ b/docs/docs/examples/simulation.md @@ -14,8 +14,8 @@ For this step make sure you have Iverilog and/or Verilator installed on your sys Lets create a simple verilog testbench file: import CodeBlock from '@theme/CodeBlock'; -export const tb_v = require('!!raw-loader!../../../examples/sim_example/tb.v')?.default; -export const cmakelists = require('!!raw-loader!../../../examples/sim_example/CMakeLists.txt')?.default; +export const tb_v = require('!!raw-loader!../../../examples/simple_verilog/tb.v')?.default; +export const cmakelists = require('!!raw-loader!../../../examples/simple_verilog/CMakeLists.txt')?.default; ## tb.v