From 3fc668222d31afda97da4ac4ead1e65e14a5f02d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Risto=20Peja=C5=A1inovi=C4=87?= Date: Sun, 22 Dec 2024 00:22:12 +0100 Subject: [PATCH] Refactor simulation examples Provided: * simple_verilog - Simple verilog only testbench for all simulators * simple_mixed_language - Verilog and VHDL tb for all capable sims * Remove modelsim and vcs examples --- examples/dpi-c/CMakeLists.txt | 21 ++++-- examples/dpi-c/hello/CMakeLists.txt | 4 +- examples/modelsim/simple/CMakeLists.txt | 20 ------ examples/sim_example/CMakeLists.txt | 19 ------ examples/sim_example/deps/CPM.cmake | 31 --------- examples/sim_example/deps/deps.cmake | 8 --- examples/sim_example/tb.v | 6 -- examples/simple_mixed_language/CMakeLists.txt | 32 ++++++++++ .../adder/CMakeLists.txt | 2 +- .../adder/adder.vhdl | 0 .../simple => simple_mixed_language}/tb.v | 19 ++++-- examples/simple_verilog/CMakeLists.txt | 41 ++++++++++++ examples/simple_verilog/adder/CMakeLists.txt | 6 ++ examples/simple_verilog/adder/adder.v | 8 +++ examples/simple_verilog/tb.v | 22 +++++++ examples/vcs/CMakeLists.txt | 51 --------------- examples/vcs/deps/CPM.cmake | 31 --------- examples/vcs/deps/deps.cmake | 8 --- examples/vcs/sc_main.cpp | 64 ------------------- examples/verilator/adder/CMakeLists.txt | 4 +- 20 files changed, 143 insertions(+), 254 deletions(-) delete mode 100644 examples/modelsim/simple/CMakeLists.txt delete mode 100644 examples/sim_example/CMakeLists.txt delete mode 100644 examples/sim_example/deps/CPM.cmake delete mode 100644 examples/sim_example/deps/deps.cmake delete mode 100644 examples/sim_example/tb.v create mode 100644 examples/simple_mixed_language/CMakeLists.txt rename examples/{modelsim/simple => simple_mixed_language}/adder/CMakeLists.txt (66%) rename examples/{modelsim/simple => simple_mixed_language}/adder/adder.vhdl (100%) rename examples/{modelsim/simple => simple_mixed_language}/tb.v (63%) create mode 100644 examples/simple_verilog/CMakeLists.txt create mode 100644 examples/simple_verilog/adder/CMakeLists.txt create mode 100644 examples/simple_verilog/adder/adder.v create mode 100644 examples/simple_verilog/tb.v delete mode 100644 examples/vcs/CMakeLists.txt delete mode 100644 examples/vcs/deps/CPM.cmake delete mode 100644 examples/vcs/deps/deps.cmake delete mode 100644 examples/vcs/sc_main.cpp diff --git a/examples/dpi-c/CMakeLists.txt b/examples/dpi-c/CMakeLists.txt index c3e7acc..ab05721 100644 --- a/examples/dpi-c/CMakeLists.txt +++ b/examples/dpi-c/CMakeLists.txt @@ -3,7 +3,10 @@ project(dpi_example NONE) include("../../SoCMakeConfig.cmake") -option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;verilator" "modelsim") +option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;vcs;verilator;all" "modelsim") +if(SIMULATOR STREQUAL "all") + set(ALL_SIMS TRUE) +endif() add_ip(tb DESCRIPTION "Simple verilog testbench" @@ -17,17 +20,23 @@ add_subdirectory(hello) ip_link(${IP} hello_dpi) -if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim") +if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS) modelsim(${IP}) +endif() -elseif(SIMULATOR STREQUAL "xcelium") +if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS) xcelium(${IP}) +endif() + +if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS) + vcs(${IP}) +endif() -elseif(SIMULATOR STREQUAL "verilator") +if(SIMULATOR STREQUAL "verilator" OR ALL_SIMS) enable_language(CXX) verilator(${IP}) - add_executable(main Vtb__main.cpp) - target_link_libraries(main tb__vlt) + add_executable(verilator_tb EXCLUDE_FROM_ALL Vtb__main.cpp ) + target_link_libraries(verilator_tb tb__vlt) endif() help() diff --git a/examples/dpi-c/hello/CMakeLists.txt b/examples/dpi-c/hello/CMakeLists.txt index 71d9b5a..a30eb4b 100644 --- a/examples/dpi-c/hello/CMakeLists.txt +++ b/examples/dpi-c/hello/CMakeLists.txt @@ -1,11 +1,13 @@ cmake_minimum_required(VERSION 3.25) project(hello_dpi CXX) +set(CMAKE_CXX_STANDARD 11) + add_library(hello_dpi SHARED ./hello.cpp ) -if(NOT SIMULATOR STREQUAL "verilator") +if(SIMULATOR STREQUAL "modelsim") target_compile_options(hello_dpi PRIVATE -m32) target_link_options(hello_dpi PRIVATE -m32) endif() diff --git a/examples/modelsim/simple/CMakeLists.txt b/examples/modelsim/simple/CMakeLists.txt deleted file mode 100644 index 65a6342..0000000 --- a/examples/modelsim/simple/CMakeLists.txt +++ /dev/null @@ -1,20 +0,0 @@ -cmake_minimum_required(VERSION 3.25) -project(example NONE) - -include("../../../SoCMakeConfig.cmake") - -add_ip(tb - DESCRIPTION "Simple verilog testbench" - ) - -ip_sources(${IP} VERILOG - ${PROJECT_SOURCE_DIR}/tb.v - ) - -add_subdirectory(adder) - -ip_link(${IP} adder) - -modelsim(${IP} TARGET_PER_IP) - -help() diff --git a/examples/sim_example/CMakeLists.txt b/examples/sim_example/CMakeLists.txt deleted file mode 100644 index cf960a7..0000000 --- a/examples/sim_example/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -cmake_minimum_required(VERSION 3.25) -project(example NONE) - -include("deps/deps.cmake") - -add_ip(cern::ip::tb::0.0.1 - DESCRIPTION "Simple verilog testbench" - ) - -ip_sources(${IP} VERILOG # Add source files to the VERILOG file set - ${PROJECT_SOURCE_DIR}/tb.v - ) - -iverilog(${IP}) - -verilator(${IP} # Create verilate target - MAIN) # Let Verilator create a main.cpp testbench - -help() diff --git a/examples/sim_example/deps/CPM.cmake b/examples/sim_example/deps/CPM.cmake deleted file mode 100644 index 5600efe..0000000 --- a/examples/sim_example/deps/CPM.cmake +++ /dev/null @@ -1,31 +0,0 @@ -if(CPM_SOURCE_CACHE) - set(CPM_DOWNLOAD_LOCATION "${CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake") -elseif(DEFINED ENV{CPM_SOURCE_CACHE}) - set(CPM_DOWNLOAD_LOCATION "$ENV{CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake") -else() - set(CPM_DOWNLOAD_LOCATION "${CMAKE_BINARY_DIR}/cmake/CPM_${CPM_DOWNLOAD_VERSION}.cmake") -endif() - -# Expand relative path. This is important if the provided path contains a tilde (~) -get_filename_component(CPM_DOWNLOAD_LOCATION ${CPM_DOWNLOAD_LOCATION} ABSOLUTE) - -function(download_cpm) - message(STATUS "Downloading CPM.cmake to ${CPM_DOWNLOAD_LOCATION}") - file(DOWNLOAD - https://github.com/cpm-cmake/CPM.cmake/releases/download/v${CPM_DOWNLOAD_VERSION}/CPM.cmake - ${CPM_DOWNLOAD_LOCATION} - ) -endfunction() - -if(NOT (EXISTS ${CPM_DOWNLOAD_LOCATION})) - download_cpm() -else() - # resume download if it previously failed - file(READ ${CPM_DOWNLOAD_LOCATION} check) - if("${check}" STREQUAL "") - download_cpm() - endif() - unset(check) -endif() - -include(${CPM_DOWNLOAD_LOCATION}) diff --git a/examples/sim_example/deps/deps.cmake b/examples/sim_example/deps/deps.cmake deleted file mode 100644 index 2659496..0000000 --- a/examples/sim_example/deps/deps.cmake +++ /dev/null @@ -1,8 +0,0 @@ -set(CPM_DOWNLOAD_VERSION 0.40.2) # Define CPM version to be downloaded -include(${CMAKE_CURRENT_LIST_DIR}/CPM.cmake) # Include the CPM.cmake downloader - -CPMAddPackage( # Add SoCMake as a package - NAME SoCMake - GIT_TAG develop # You can define GIT_TAG or VERSION for versioning - GIT_REPOSITORY "https://github.com/HEP-SoC/SoCMake.git" # GIT_REPOSITORY or URL - ) diff --git a/examples/sim_example/tb.v b/examples/sim_example/tb.v deleted file mode 100644 index 7d32df2..0000000 --- a/examples/sim_example/tb.v +++ /dev/null @@ -1,6 +0,0 @@ -module tb; - initial begin - $display("Hello world, from SoCMake build system\n"); - $finish(); - end - endmodule diff --git a/examples/simple_mixed_language/CMakeLists.txt b/examples/simple_mixed_language/CMakeLists.txt new file mode 100644 index 0000000..9ce3196 --- /dev/null +++ b/examples/simple_mixed_language/CMakeLists.txt @@ -0,0 +1,32 @@ +cmake_minimum_required(VERSION 3.25) +project(simple_mixed_language NONE) + +include("../../SoCMakeConfig.cmake") + +option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;vcs;all" "modelsim") +if(SIMULATOR STREQUAL "all") + set(ALL_SIMS TRUE) +endif() + +add_ip(tb + DESCRIPTION "Simple verilog testbench") + +ip_sources(${IP} VERILOG + tb.v) + +add_subdirectory(adder) +ip_link(${IP} adder) + +if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS) + modelsim(${IP}) +endif() + +if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS) + xcelium(${IP}) +endif() + +if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS) + vcs(${IP}) +endif() + +help() diff --git a/examples/modelsim/simple/adder/CMakeLists.txt b/examples/simple_mixed_language/adder/CMakeLists.txt similarity index 66% rename from examples/modelsim/simple/adder/CMakeLists.txt rename to examples/simple_mixed_language/adder/CMakeLists.txt index 307f212..5b4d612 100644 --- a/examples/modelsim/simple/adder/CMakeLists.txt +++ b/examples/simple_mixed_language/adder/CMakeLists.txt @@ -3,5 +3,5 @@ add_ip(adder DESCRIPTION "Just a simple adder") ip_sources(${IP} VHDL - ${CMAKE_CURRENT_LIST_DIR}/adder.vhdl + adder.vhdl ) diff --git a/examples/modelsim/simple/adder/adder.vhdl b/examples/simple_mixed_language/adder/adder.vhdl similarity index 100% rename from examples/modelsim/simple/adder/adder.vhdl rename to examples/simple_mixed_language/adder/adder.vhdl diff --git a/examples/modelsim/simple/tb.v b/examples/simple_mixed_language/tb.v similarity index 63% rename from examples/modelsim/simple/tb.v rename to examples/simple_mixed_language/tb.v index 99f03e0..1247c03 100644 --- a/examples/modelsim/simple/tb.v +++ b/examples/simple_mixed_language/tb.v @@ -1,10 +1,6 @@ module tb; - initial begin - $display("Hello world, from SoCMake build system\n"); - $finish(); - end - - wire [4:0] a, b, o; + reg [4:0] a, b; + wire [4:0] o; adder adder_i ( .NUM1(a), @@ -12,4 +8,15 @@ module tb; .SUM(o) ); + initial begin + a = 5; + b = 10; + #1; + + $display("Hello world, from SoCMake build system\n"); + $display("%d + %d = %d", a, b, o); + $finish(); + end + + endmodule diff --git a/examples/simple_verilog/CMakeLists.txt b/examples/simple_verilog/CMakeLists.txt new file mode 100644 index 0000000..20f9955 --- /dev/null +++ b/examples/simple_verilog/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required(VERSION 3.25) +project(simple_verilog_example NONE) + +include("../../SoCMakeConfig.cmake") + +option_enum(SIMULATOR "Which simulator to use" "iverilog;questa;modelsim;xcelium;vcs;verilator;all" "iverilog") +if(SIMULATOR STREQUAL "all") + set(ALL_SIMS TRUE) +endif() + +add_ip(tb + DESCRIPTION "Simple verilog testbench") + +ip_sources(${IP} VERILOG + tb.v) + +add_subdirectory(adder) +ip_link(${IP} adder) + + +if(SIMULATOR STREQUAL "iverilog" OR ALL_SIMS) + iverilog(${IP}) +endif() + +if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS) + modelsim(${IP}) +endif() + +if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS) + xcelium(${IP}) +endif() + +if(SIMULATOR STREQUAL "verilator" OR ALL_SIMS) + verilator(${IP} MAIN VERILATOR_ARGS --timing) +endif() + +if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS) + vcs(${IP}) +endif() + +help() diff --git a/examples/simple_verilog/adder/CMakeLists.txt b/examples/simple_verilog/adder/CMakeLists.txt new file mode 100644 index 0000000..f6cac6f --- /dev/null +++ b/examples/simple_verilog/adder/CMakeLists.txt @@ -0,0 +1,6 @@ +add_ip(adder + DESCRIPTION "Just a simple adder") + +ip_sources(${IP} VERILOG + adder.v + ) diff --git a/examples/simple_verilog/adder/adder.v b/examples/simple_verilog/adder/adder.v new file mode 100644 index 0000000..f635684 --- /dev/null +++ b/examples/simple_verilog/adder/adder.v @@ -0,0 +1,8 @@ +module adder( + input [4:0] NUM1, + input [4:0] NUM2, + output [4:0] SUM + ); + + assign SUM = NUM1 + NUM2; +endmodule diff --git a/examples/simple_verilog/tb.v b/examples/simple_verilog/tb.v new file mode 100644 index 0000000..1247c03 --- /dev/null +++ b/examples/simple_verilog/tb.v @@ -0,0 +1,22 @@ +module tb; + reg [4:0] a, b; + wire [4:0] o; + + adder adder_i ( + .NUM1(a), + .NUM2(b), + .SUM(o) + ); + + initial begin + a = 5; + b = 10; + #1; + + $display("Hello world, from SoCMake build system\n"); + $display("%d + %d = %d", a, b, o); + $finish(); + end + + + endmodule diff --git a/examples/vcs/CMakeLists.txt b/examples/vcs/CMakeLists.txt deleted file mode 100644 index afbf5d4..0000000 --- a/examples/vcs/CMakeLists.txt +++ /dev/null @@ -1,51 +0,0 @@ -include("deps/deps.cmake") - -if(SIM_VCS) - if(NOT VCS_HOME AND NOT ENV{VCS_HOME}) - set(VCS_HOME /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2) - endif() - vcs_init() -else() - set(VERILATOR_HOME /cerneda/various/RHELx86/verilator-4.228/) - set(SYSTEMC_HOME /scratch/rpejasin/socmake/SoCMake-Ibex/deps/_deps/verisc/open/systemc-2.3.3/) -endif() - -cmake_minimum_required(VERSION 3.25) -project(example CXX C) - -if(NOT SIM_VCS) - find_package(SystemCLanguage REQUIRED - HINTS ${SYSTEMC_HOME}/*/*/* - ) - set(CMAKE_CXX_STANDARD ${SystemC_CXX_STANDARD}) -endif() - -add_subdirectory(../verilator/adder "adder") - -add_executable(test sc_main.cpp) - -if(SIM_VCS) - vcs_vlogan(cern::ip::adder::0.0.1 - OUTDIR ${PROJECT_BINARY_DIR}) - - target_link_libraries(test - cern::ip::adder::0.0.1::vcs - vcs::libs - ) -else() - verilate(cern::ip::adder::0.0.1 - SYSTEMC - PREFIX adder - VERILATOR_ARGS --pins-bv 1 - ) - - target_link_libraries(test - cern::ip::adder::0.0.1::vlt - SystemC::systemc - ) -endif() - -target_compile_definitions(test PUBLIC - VERBOSE=1 - ) - diff --git a/examples/vcs/deps/CPM.cmake b/examples/vcs/deps/CPM.cmake deleted file mode 100644 index 5600efe..0000000 --- a/examples/vcs/deps/CPM.cmake +++ /dev/null @@ -1,31 +0,0 @@ -if(CPM_SOURCE_CACHE) - set(CPM_DOWNLOAD_LOCATION "${CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake") -elseif(DEFINED ENV{CPM_SOURCE_CACHE}) - set(CPM_DOWNLOAD_LOCATION "$ENV{CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake") -else() - set(CPM_DOWNLOAD_LOCATION "${CMAKE_BINARY_DIR}/cmake/CPM_${CPM_DOWNLOAD_VERSION}.cmake") -endif() - -# Expand relative path. This is important if the provided path contains a tilde (~) -get_filename_component(CPM_DOWNLOAD_LOCATION ${CPM_DOWNLOAD_LOCATION} ABSOLUTE) - -function(download_cpm) - message(STATUS "Downloading CPM.cmake to ${CPM_DOWNLOAD_LOCATION}") - file(DOWNLOAD - https://github.com/cpm-cmake/CPM.cmake/releases/download/v${CPM_DOWNLOAD_VERSION}/CPM.cmake - ${CPM_DOWNLOAD_LOCATION} - ) -endfunction() - -if(NOT (EXISTS ${CPM_DOWNLOAD_LOCATION})) - download_cpm() -else() - # resume download if it previously failed - file(READ ${CPM_DOWNLOAD_LOCATION} check) - if("${check}" STREQUAL "") - download_cpm() - endif() - unset(check) -endif() - -include(${CPM_DOWNLOAD_LOCATION}) diff --git a/examples/vcs/deps/deps.cmake b/examples/vcs/deps/deps.cmake deleted file mode 100644 index c95faf0..0000000 --- a/examples/vcs/deps/deps.cmake +++ /dev/null @@ -1,8 +0,0 @@ -set(CPM_DOWNLOAD_VERSION 0.40.2) -include(${CMAKE_CURRENT_LIST_DIR}/CPM.cmake) - -CPMAddPackage( - NAME SoCMake - GIT_TAG master - GIT_REPOSITORY "https://github.com/HEP-SoC/SoCMake.git" - ) diff --git a/examples/vcs/sc_main.cpp b/examples/vcs/sc_main.cpp deleted file mode 100644 index a4e2fbf..0000000 --- a/examples/vcs/sc_main.cpp +++ /dev/null @@ -1,64 +0,0 @@ -#include -#include - -#include "adder.h" - -using namespace sc_core; -using namespace sc_dt; - -SC_MODULE(TESTBENCH) { - sc_signal> a_in; - sc_signal> b_in; - sc_signal> out; - - adder dut{"dut"}; - - void stimulus() { - a_in.write(0); - b_in.write(50); - while (true) { - a_in.write(a_in.read().to_uint() + 1); - b_in.write(b_in.read().to_uint() + 2); - - wait(5, SC_NS); - } - } - - void checker() { -#ifdef VERBOSE - std::cout << "Value a_in: " << a_in.read().to_uint() - << " b_in: " << b_in.read().to_uint() - << " Out: " << out.read().to_uint() << "\n"; -#endif - if (a_in.read().to_uint() + b_in.read().to_uint() != out.read().to_uint()) { - std::cout << "Error in verilog\n"; - std::cout << "Value a_in: " << a_in.read().to_uint() - << " b_in: " << b_in.read().to_uint() - << " Out: " << out.read().to_uint() << "\n"; - exit(-1); - } - } - - - SC_CTOR(TESTBENCH) { - dut.a(a_in); - dut.b(b_in); - dut.o(out); - - SC_THREAD(stimulus); - - SC_METHOD(checker); - sensitive << out; - } -}; - -int sc_main(int argc, char **argv) { - std::cout << "Simple SystemC test with verilator dut\n"; - - TESTBENCH tb("tb"); - - sc_start(1000, SC_NS); - - return 0; -} - diff --git a/examples/verilator/adder/CMakeLists.txt b/examples/verilator/adder/CMakeLists.txt index bbacdf9..7a83c8b 100644 --- a/examples/verilator/adder/CMakeLists.txt +++ b/examples/verilator/adder/CMakeLists.txt @@ -5,6 +5,6 @@ add_ip(cern::ip::adder::0.0.1 DESCRIPTION "Just a simple adder" ) -ip_sources(adder VERILOG - ${PROJECT_SOURCE_DIR}/adder.v +ip_sources(${IP} VERILOG + adder.v )