-
Notifications
You must be signed in to change notification settings - Fork 2
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Refactor GHDL support, add simple VHDL simulation example
- Loading branch information
Showing
7 changed files
with
265 additions
and
86 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,36 @@ | ||
cmake_minimum_required(VERSION 3.25) | ||
project(simple_mixed_language NONE) | ||
|
||
include("../../SoCMakeConfig.cmake") | ||
|
||
option_enum(SIMULATOR "Which simulator to use" "ghdl;questa;modelsim;xcelium;vcs;all" "ghdl") | ||
if(SIMULATOR STREQUAL "all") | ||
set(ALL_SIMS TRUE) | ||
endif() | ||
|
||
add_ip(tb | ||
DESCRIPTION "Simple verilog testbench") | ||
|
||
ip_sources(${IP} VHDL | ||
tb.vhdl) | ||
|
||
add_subdirectory(adder) | ||
ip_link(${IP} adder) | ||
|
||
if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS) | ||
modelsim(${IP}) | ||
endif() | ||
|
||
if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS) | ||
xcelium(${IP} XMVHDL_ARGS -V200x) | ||
endif() | ||
|
||
if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS) | ||
vcs(${IP}) | ||
endif() | ||
|
||
if(SIMULATOR STREQUAL "ghdl" OR ALL_SIMS) | ||
ghdl(${IP}) | ||
endif() | ||
|
||
help() |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
|
||
add_ip(adder | ||
DESCRIPTION "Just a simple adder") | ||
|
||
ip_sources(${IP} VHDL | ||
adder.vhdl | ||
) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,16 @@ | ||
library IEEE; | ||
use IEEE.STD_LOGIC_1164.ALL; | ||
use IEEE.STD_LOGIC_UNSIGNED.ALL; | ||
|
||
entity adder is | ||
Port ( NUM1 : in STD_LOGIC_VECTOR (4 downto 0) := "00000"; | ||
NUM2 : in STD_LOGIC_VECTOR (4 downto 0) := "00000"; | ||
SUM : out STD_LOGIC_VECTOR (4 downto 0)); | ||
end adder; | ||
|
||
architecture Behavioral of adder is | ||
begin | ||
|
||
SUM <= NUM1 + NUM2; | ||
|
||
end Behavioral; |
Oops, something went wrong.