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newcpu.c
executable file
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newcpu.c
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/*
* UAE - The Un*x Amiga Emulator
*
* MC68000 emulation
*
* (c) 1995 Bernd Schmidt
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "events.h"
#include "uae.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cpu_prefetch.h"
#include "autoconf.h"
#include "traps.h"
#include "ersatz.h"
#include "debug.h"
#include "gui.h"
#include "savestate.h"
#include "blitter.h"
#include "ar.h"
#ifdef JIT
extern uae_u8* compiled_code;
#include "compemu.h"
#endif
//ric
#include "profiling.h"
#define PROFILINGINDEX 1100
//#undef PROFILING
//end ric
#define f_out fprintf
#define console_out printf
/* Opcode of faulting instruction */
static uae_u16 last_op_for_exception_3;
/* PC at fault time */
static uaecptr last_addr_for_exception_3;
/* Address that generated the exception */
static uaecptr last_fault_for_exception_3;
/* read (0) or write (1) access */
static int last_writeaccess_for_exception_3;
/* instruction (1) or data (0) access */
static int last_instructionaccess_for_exception_3;
unsigned long irqcycles[15];
int irqdelay[15];
const int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
const int imm8_table[] = { 8,1,2,3,4,5,6,7 };
int movem_index1[256];
int movem_index2[256];
int movem_next[256];
#ifdef FPUEMU
int fpp_movem_index1[256];
int fpp_movem_index2[256];
int fpp_movem_next[256];
#endif
cpuop_func *cpufunctbl[65536];
static int warned_cpu68020;
#define COUNT_INSTRS 0
#if COUNT_INSTRS
static unsigned long int instrcount[65536];
static uae_u16 opcodenums[65536];
static int compfn (const void *el1, const void *el2)
{
return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
}
static char *icountfilename (void)
{
char *name = getenv ("INSNCOUNT");
if (name)
return name;
return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
}
void dump_counts (void)
{
FILE *f = fopen (icountfilename (), "w");
unsigned long int total;
int i;
write_log ("Writing instruction count file...\n");
for (i = 0; i < 65536; i++) {
opcodenums[i] = i;
total += instrcount[i];
}
qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
fprintf (f, "Total: %lu\n", total);
for (i=0; i < 65536; i++) {
unsigned long int cnt = instrcount[opcodenums[i]];
struct instr *dp;
struct mnemolookup *lookup;
if (!cnt)
break;
dp = table68k + opcodenums[i];
for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
;
fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
}
fclose (f);
}
#else
void dump_counts (void)
{
}
#endif
STATIC_INLINE void count_instr (unsigned int opcode)
{
#if COUNT_INSTRS == 2
if (table68k[opcode].handler != -1)
instrcount[table68k[opcode].handler]++;
#elif COUNT_INSTRS == 1
instrcount[opcode]++;
#endif
}
static unsigned long op_illg_1 (uae_u32 opcode, struct regstruct *regs) REGPARAM;
static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode, struct regstruct *regs)
{
op_illg (opcode, regs);
return 4;
}
static void build_cpufunctbl (void)
{
int i, opcnt;
unsigned long opcode;
const struct cputbl *tbl = 0;
switch (currprefs.cpu_level) {
#ifdef CPUEMU_0
#ifndef CPUEMU_68000_ONLY
case 4:
case 6:
tbl = op_smalltbl_0_ff;
break;
case 3:
tbl = op_smalltbl_1_ff;
break;
case 2:
tbl = op_smalltbl_2_ff;
break;
case 1:
tbl = op_smalltbl_3_ff;
break;
#endif
#endif
case 0:
tbl = op_smalltbl_4_ff;
#ifdef CPUEMU_5
if (currprefs.cpu_compatible)
tbl = op_smalltbl_5_ff; /* prefetch */
#endif
#ifdef CPUEMU_6
if (currprefs.cpu_cycle_exact)
tbl = op_smalltbl_6_ff; /* prefetch and cycle-exact */
#endif
break;
}
if (tbl == 0) {
write_log ("no CPU emulation cores available!");
abort ();
}
for (opcode = 0; opcode < 65536; opcode++)
cpufunctbl[opcode] = op_illg_1;
for (i = 0; tbl[i].handler != NULL; i++)
cpufunctbl[tbl[i].opcode] = tbl[i].handler;
opcnt = 0;
for (opcode = 0; opcode < 65536; opcode++) {
cpuop_func *f;
if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
continue;
if (table68k[opcode].handler != -1) {
f = cpufunctbl[table68k[opcode].handler];
if (f == op_illg_1)
abort();
cpufunctbl[opcode] = f;
opcnt++;
}
}
write_log ("Building CPU function table, %d opcodes (%d %d %d).\n",
opcnt, currprefs.cpu_level,
currprefs.cpu_cycle_exact ? -1 : currprefs.cpu_compatible ? 1 : 0,
currprefs.address_space_24);
#ifdef JIT
build_comp ();
#endif
}
void fill_prefetch_slow (struct regstruct *regs)
{
#ifdef CPUEMU_6
if (currprefs.cpu_cycle_exact) {
regs->ir = get_word_ce (m68k_getpc (regs));
regs->irc = get_word_ce (m68k_getpc (regs) + 2);
} else {
#endif
regs->ir = get_word (m68k_getpc (regs));
regs->irc = get_word (m68k_getpc (regs) + 2);
#ifdef CPUEMU_6
}
#endif
}
unsigned long cycles_mask __attribute__((__section__(".sdata")));
unsigned long cycles_val __attribute__((__section__(".sdata")));
static void update_68k_cycles (void)
{
cycles_mask = 0;
cycles_val = currprefs.m68k_speed;
if (currprefs.m68k_speed < 1) {
cycles_mask = 0xFFFFFFFF;
cycles_val = 0;
}
}
void check_prefs_changed_cpu (void)
{
if (currprefs.cpu_level != changed_prefs.cpu_level
|| currprefs.cpu_compatible != changed_prefs.cpu_compatible
|| currprefs.cpu_cycle_exact != changed_prefs.cpu_cycle_exact) {
if (!currprefs.cpu_compatible && changed_prefs.cpu_compatible)
fill_prefetch_slow (®s);
currprefs.cpu_level = changed_prefs.cpu_level;
currprefs.cpu_compatible = changed_prefs.cpu_compatible;
currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
currprefs.blitter_cycle_exact = changed_prefs.cpu_cycle_exact;
build_cpufunctbl ();
}
if (currprefs.m68k_speed != changed_prefs.m68k_speed) {
currprefs.m68k_speed = changed_prefs.m68k_speed;
reset_frame_rate_hack ();
update_68k_cycles ();
}
if (currprefs.cpu_idle != changed_prefs.cpu_idle) {
currprefs.cpu_idle = changed_prefs.cpu_idle;
}
if (currprefs.dont_busy_wait != changed_prefs.dont_busy_wait) {
currprefs.dont_busy_wait = changed_prefs.dont_busy_wait;
}
}
void init_m68k (void)
{
int i;
update_68k_cycles ();
for (i = 0 ; i < 256 ; i++) {
int j;
for (j = 0 ; j < 8 ; j++) {
if (i & (1 << j)) break;
}
movem_index1[i] = j;
movem_index2[i] = 7-j;
movem_next[i] = i & (~(1 << j));
}
#ifdef FPUEMU
for (i = 0 ; i < 256 ; i++) {
int j;
for (j = 7 ; j >= 0 ; j--) {
if (i & (1 << j)) break;
}
fpp_movem_index1[i] = 7-j;
fpp_movem_index2[i] = j;
fpp_movem_next[i] = i & (~(1 << j));
}
#endif
#if COUNT_INSTRS
{
FILE *f = fopen (icountfilename (), "r");
memset (instrcount, 0, sizeof instrcount);
if (f) {
uae_u32 opcode, count, total;
char name[20];
write_log ("Reading instruction count file...\n");
fscanf (f, "Total: %lu\n", &total);
while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
instrcount[opcode] = count;
}
fclose(f);
}
}
#endif
write_log ("Building CPU table for configuration: 68");
regs.address_space_mask = 0xffffffff;
if (currprefs.cpu_compatible > 0) {
if (currprefs.address_space_24 && currprefs.cpu_level > 3)
currprefs.address_space_24 = 0;
if (currprefs.address_space_24 && currprefs.cpu_level > 1)
write_log ("EC");
}
switch (currprefs.cpu_level) {
case 1:
write_log ("010");
break;
case 2:
write_log ("020");
break;
case 3:
write_log ("020/881");
break;
case 4:
/* Who is going to miss the MMU anyway...? :-) */
write_log ("040");
break;
case 6:
/* Who is going to miss the MMU anyway...? :-) */
write_log ("060");
break;
default:
write_log ("000");
break;
}
if (currprefs.cpu_cycle_exact) {
if (currprefs.cpu_level == 0)
write_log (" prefetch and cycle-exact");
else
write_log (" ~cycle-exact");
} else if (currprefs.cpu_compatible)
write_log (" prefetch");
if (currprefs.address_space_24) {
regs.address_space_mask = 0x00ffffff;
write_log (" 24-bit addressing");
}
write_log ("\n");
read_table68k ();
do_merges ();
write_log ("%d CPU functions\n", nr_cpuop_funcs);
build_cpufunctbl ();
#ifdef JIT
/* We need to check whether NATMEM settings have changed
* before starting the CPU */
check_prefs_changed_comp ();
#endif
}
struct regstruct regs __attribute__((__section__(".sdata")));
static uae_s32 m68kpc_offset __attribute__((__section__(".sdata")));
#define get_ibyte_1(regs, o) get_byte((regs)->pc + ((regs)->pc_p - (regs)->pc_oldp) + (o) + 1)
#define get_iword_1(regs, o) get_word((regs)->pc + ((regs)->pc_p - (regs)->pc_oldp) + (o))
#define get_ilong_1(regs, o) get_long((regs)->pc + ((regs)->pc_p - (regs)->pc_oldp) + (o))
static uae_s32 ShowEA (void *f, uae_u16 opcode, int reg, amodes mode, wordsizes size, char *buf)
{
uae_u16 dp;
uae_s8 disp8;
uae_s16 disp16;
int r;
uae_u32 dispreg;
uaecptr addr;
uae_s32 offset = 0;
char buffer[80];
switch (mode){
case Dreg:
sprintf (buffer, "D%d", reg);
break;
case Areg:
sprintf (buffer, "A%d", reg);
break;
case Aind:
sprintf (buffer, "(A%d)", reg);
break;
case Aipi:
sprintf (buffer, "(A%d)+", reg);
break;
case Apdi:
sprintf (buffer, "-(A%d)", reg);
break;
case Ad16:
disp16 = get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2;
addr = m68k_areg (®s,reg) + (uae_s16)disp16;
sprintf (buffer, "(A%d,$%04x) == $%08x", reg, disp16 & 0xffff, addr);
break;
case Ad8r:
dp = get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2;
disp8 = dp & 0xFF;
r = (dp & 0x7000) >> 12;
dispreg = dp & 0x8000 ? m68k_areg (®s,r) : m68k_dreg (®s,r);
if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
dispreg <<= (dp >> 9) & 3;
if (dp & 0x100) {
uae_s32 outer = 0, disp = 0;
uae_s32 base = m68k_areg (®s,reg);
char name[10];
sprintf (name, "A%d, ", reg);
if (dp & 0x80) { base = 0; name[0] = 0; }
if (dp & 0x40) dispreg = 0;
if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (®s, m68kpc_offset); m68kpc_offset += 4; }
base += disp;
if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (®s, m68kpc_offset); m68kpc_offset += 4; }
if (!(dp & 4)) base += dispreg;
if (dp & 3) base = get_long (base);
if (dp & 4) base += dispreg;
addr = base + outer;
sprintf (buffer, "(%s%c%d.%c*%d+%d)+%d == $%08x", name,
dp & 0x8000 ? 'A' : 'D', r, dp & 0x800 ? 'L' : 'W',
1 << ((dp >> 9) & 3),
disp, outer, addr);
} else {
addr = m68k_areg (®s,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
sprintf (buffer, "(A%d, %c%d.%c*%d, $%02x) == $%08x", reg,
dp & 0x8000 ? 'A' : 'D', r, dp & 0x800 ? 'L' : 'W',
1 << ((dp >> 9) & 3), disp8, addr);
}
break;
case PC16:
addr = m68k_getpc (®s) + m68kpc_offset;
disp16 = get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2;
addr += (uae_s16)disp16;
sprintf (buffer, "(PC,$%04x) == $%08x", disp16 & 0xffff, addr);
break;
case PC8r:
addr = m68k_getpc (®s) + m68kpc_offset;
dp = get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2;
disp8 = dp & 0xFF;
r = (dp & 0x7000) >> 12;
dispreg = dp & 0x8000 ? m68k_areg (®s,r) : m68k_dreg (®s,r);
if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
dispreg <<= (dp >> 9) & 3;
if (dp & 0x100) {
uae_s32 outer = 0,disp = 0;
uae_s32 base = addr;
char name[10];
sprintf (name, "PC, ");
if (dp & 0x80) { base = 0; name[0] = 0; }
if (dp & 0x40) dispreg = 0;
if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (®s, m68kpc_offset); m68kpc_offset += 4; }
base += disp;
if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (®s, m68kpc_offset); m68kpc_offset += 2; }
if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (®s, m68kpc_offset); m68kpc_offset += 4; }
if (!(dp & 4)) base += dispreg;
if (dp & 3) base = get_long (base);
if (dp & 4) base += dispreg;
addr = base + outer;
sprintf (buffer, "(%s%c%d.%c*%d+%d)+%d == $%08x", name,
dp & 0x8000 ? 'A' : 'D', r, dp & 0x800 ? 'L' : 'W',
1 << ((dp >> 9) & 3),
disp, outer, addr);
} else {
addr += (uae_s32)((uae_s8)disp8) + dispreg;
sprintf (buffer, "(PC, %c%d.%c*%d, $%02x) == $%08x", dp & 0x8000 ? 'A' : 'D',
r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
disp8, addr);
}
break;
case absw:
sprintf (buffer, "$%08x", (unsigned int)(uae_s32)(uae_s16)get_iword_1 (®s, m68kpc_offset));
m68kpc_offset += 2;
break;
case absl:
sprintf (buffer, "$%08x", (unsigned int)get_ilong_1 (®s, m68kpc_offset));
m68kpc_offset += 4;
break;
case imm:
switch (size){
case sz_byte:
sprintf (buffer, "#$%02x", (unsigned int)(get_iword_1 (®s, m68kpc_offset) & 0xff));
m68kpc_offset += 2;
break;
case sz_word:
sprintf (buffer, "#$%04x", (unsigned int)(get_iword_1 (®s, m68kpc_offset) & 0xffff));
m68kpc_offset += 2;
break;
case sz_long:
sprintf (buffer, "#$%08x", (unsigned int)(get_ilong_1 (®s, m68kpc_offset) & 0xffffffff));
m68kpc_offset += 4;
break;
default:
break;
}
break;
case imm0:
offset = (uae_s32)(uae_s8)get_iword_1 (®s, m68kpc_offset);
m68kpc_offset += 2;
sprintf (buffer, "#$%02x", (unsigned int)(offset & 0xff));
break;
case imm1:
offset = (uae_s32)(uae_s16)get_iword_1 (®s, m68kpc_offset);
m68kpc_offset += 2;
buffer[0] = 0;
sprintf (buffer, "#$%04x", (unsigned int)(offset & 0xffff));
break;
case imm2:
offset = (uae_s32)get_ilong_1 (®s, m68kpc_offset);
m68kpc_offset += 4;
sprintf (buffer, "#$%08x", (unsigned int)offset);
break;
case immi:
offset = (uae_s32)(uae_s8)(reg & 0xff);
sprintf (buffer, "#$%08x", (unsigned int)offset);
break;
default:
break;
}
if (buf == 0)
f_out (f, "%s", buffer);
else
strcat (buf, buffer);
return offset;
}
uae_u32 REGPARAM2 get_disp_ea_020 (struct regstruct *regs, uae_u32 base, uae_u32 dp)
{
int reg = (dp >> 12) & 15;
uae_s32 regd = regs->regs[reg];
if ((dp & 0x800) == 0)
regd = (uae_s32)(uae_s16)regd;
regd <<= (dp >> 9) & 3;
if (dp & 0x100) {
uae_s32 outer = 0;
if (dp & 0x80) base = 0;
if (dp & 0x40) regd = 0;
if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16) next_iword (regs);
if ((dp & 0x30) == 0x30) base += next_ilong (regs);
if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16) next_iword (regs);
if ((dp & 0x3) == 0x3) outer = next_ilong (regs);
if ((dp & 0x4) == 0) base += regd;
if (dp & 0x3) base = get_long (base);
if (dp & 0x4) base += regd;
return base + outer;
} else {
return base + (uae_s32)((uae_s8)dp) + regd;
}
}
uae_u32 REGPARAM2 get_disp_ea_000 (struct regstruct *regs, uae_u32 base, uae_u32 dp)
{
int reg = (dp >> 12) & 15;
uae_s32 regd = regs->regs[reg];
#if 1
if ((dp & 0x800) == 0)
regd = (uae_s32)(uae_s16)regd;
return base + (uae_s8)dp + regd;
#else
/* Branch-free code... benchmark this again now that
* things are no longer inline. */
uae_s32 regd16;
uae_u32 mask;
mask = ((dp & 0x800) >> 11) - 1;
regd16 = (uae_s32)(uae_s16)regd;
regd16 &= mask;
mask = ~mask;
base += (uae_s8)dp;
regd &= mask;
regd |= regd16;
return base + regd;
#endif
}
void REGPARAM2 MakeSR (struct regstruct *regs)
{
#if 0
assert((regs.t1 & 1) == regs.t1);
assert((regs.t0 & 1) == regs.t0);
assert((regs.s & 1) == regs.s);
assert((regs.m & 1) == regs.m);
assert((XFLG & 1) == XFLG);
assert((NFLG & 1) == NFLG);
assert((ZFLG & 1) == ZFLG);
assert((VFLG & 1) == VFLG);
assert((CFLG & 1) == CFLG);
#endif
regs->sr = ((regs->t1 << 15) | (regs->t0 << 14)
| (regs->s << 13) | (regs->m << 12) | (regs->intmask << 8)
| (GET_XFLG(®s->ccrflags) << 4) | (GET_NFLG(®s->ccrflags) << 3)
| (GET_ZFLG(®s->ccrflags) << 2) | (GET_VFLG(®s->ccrflags) << 1)
| GET_CFLG(®s->ccrflags));
}
void REGPARAM2 MakeFromSR (struct regstruct *regs)
{
int oldm = regs->m;
int olds = regs->s;
SET_XFLG (®s->ccrflags, (regs->sr >> 4) & 1);
SET_NFLG (®s->ccrflags, (regs->sr >> 3) & 1);
SET_ZFLG (®s->ccrflags, (regs->sr >> 2) & 1);
SET_VFLG (®s->ccrflags, (regs->sr >> 1) & 1);
SET_CFLG (®s->ccrflags, regs->sr & 1);
if (regs->t1 == ((regs->sr >> 15) & 1) &&
regs->t0 == ((regs->sr >> 14) & 1) &&
regs->s == ((regs->sr >> 13) & 1) &&
regs->m == ((regs->sr >> 12) & 1) &&
regs->intmask == ((regs->sr >> 8) & 7))
return;
regs->t1 = (regs->sr >> 15) & 1;
regs->t0 = (regs->sr >> 14) & 1;
regs->s = (regs->sr >> 13) & 1;
regs->m = (regs->sr >> 12) & 1;
regs->intmask = (regs->sr >> 8) & 7;
if (currprefs.cpu_level >= 2) {
if (olds != regs->s) {
if (olds) {
if (oldm)
regs->msp = m68k_areg (regs, 7);
else
regs->isp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->usp;
} else {
regs->usp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->m ? regs->msp : regs->isp;
}
} else if (olds && oldm != regs->m) {
if (oldm) {
regs->msp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->isp;
} else {
regs->isp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->msp;
}
}
} else {
regs->t0 = regs->m = 0;
if (olds != regs->s) {
if (olds) {
regs->isp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->usp;
} else {
regs->usp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->isp;
}
}
}
set_special (regs, SPCFLAG_INT);
if (regs->t1 || regs->t0)
set_special (regs, SPCFLAG_TRACE);
else
/* Keep SPCFLAG_DOTRACE, we still want a trace exception for
SR-modifying instructions (including STOP). */
unset_special (regs, SPCFLAG_TRACE);
}
static void exception_trace (int nr)
{
unset_special (®s, SPCFLAG_TRACE | SPCFLAG_DOTRACE);
if (regs.t1 && !regs.t0) {
/* trace stays pending if exception is div by zero, chk,
* trapv or trap #x
*/
if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
set_special (®s, SPCFLAG_DOTRACE);
}
regs.t1 = regs.t0 = regs.m = 0;
}
static void exception_debug (int nr)
{
#ifdef DEBUGGER
if (!exception_debugging)
return;
console_out ("Exception %d, PC=%08x\n", nr, m68k_getpc (®s));
#endif
}
#ifdef CPUEMU_6
/* cycle-exact exception handler, 68000 only */
STATIC_INLINE void Exception_ce (int nr, struct regstruct *regs, uaecptr oldpc)
{
uae_u32 currpc = m68k_getpc (regs), newpc;
int c;
int sv = regs->s;
exception_debug (nr);
MakeSR (regs);
c = 0;
switch (nr)
{
case 2: /* bus */
case 3: /* address */
c = 6;
break;
case 4: /* illegal instruction */
c = 6;
break;
case 5: /* divide by zero */
c = 10;
break;
case 6: /* chk */
c = 12;
break;
case 7: /* trapv */
c = 6;
break;
case 8: /* privilege */
c = 6;
break;
case 9: /* trace */
c = 6;
break;
case 25: /* interrupts */
case 26:
case 27:
case 28:
case 29:
case 30:
case 31:
c = 12;
break;
case 32: /* traps */
case 33:
case 34:
case 35:
case 36:
case 37:
case 38:
case 39:
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
c = 6;
break;
}
/* some delays are interleaved with stack pushes, not bothered yet..
*/
if (c)
do_cycles (c * CYCLE_UNIT / 2);
if (!regs->s) {
regs->usp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->isp;
regs->s = 1;
}
if (nr == 2 || nr == 3) { /* 2=bus error,3=address error */
uae_u16 mode = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
mode |= last_writeaccess_for_exception_3 ? 0 : 16;
m68k_areg (regs, 7) -= 14;
/* fixme: bit3=I/N */
put_word_ce (m68k_areg (regs, 7) + 12, last_addr_for_exception_3);
put_word_ce (m68k_areg (regs, 7) + 8, regs->sr);
put_word_ce (m68k_areg (regs, 7) + 10, last_addr_for_exception_3 >> 16);
put_word_ce (m68k_areg (regs, 7) + 6, last_op_for_exception_3);
put_word_ce (m68k_areg (regs, 7) + 4, last_fault_for_exception_3);
put_word_ce (m68k_areg (regs, 7) + 0, mode);
put_word_ce (m68k_areg (regs, 7) + 2, last_fault_for_exception_3 >> 16);
write_log ("Exception %d at %08x -> %08x!\n", nr, currpc, get_long (4 * nr));
goto kludge_me_do;
}
m68k_areg (regs, 7) -= 6;
put_word_ce (m68k_areg (regs, 7) + 4, currpc);
put_word_ce (m68k_areg (regs, 7) + 0, regs->sr);
put_word_ce (m68k_areg (regs, 7) + 2, currpc >> 16);
kludge_me_do:
newpc = get_word_ce (4 * nr) << 16;
newpc |= get_word_ce (4 * nr + 2);
if (newpc & 1) {
if (nr == 2 || nr == 3)
uae_reset (1); /* there is nothing else we can do.. */
else
exception3 (regs->ir, m68k_getpc (regs), newpc);
return;
}
m68k_setpc (regs, newpc);
fill_prefetch_slow (regs);
set_special (regs, SPCFLAG_END_COMPILE);
exception_trace (nr);
}
#endif
STATIC_INLINE void Exception_normal (int nr, struct regstruct *regs, uaecptr oldpc)
{
uae_u32 currpc = m68k_getpc (regs), newpc;
int sv = regs->s;
exception_debug (nr);
MakeSR (regs);
if (!regs->s) {
regs->usp = m68k_areg (regs, 7);
if (currprefs.cpu_level >= 2)
m68k_areg (regs, 7) = regs->m ? regs->msp : regs->isp;
else
m68k_areg (regs, 7) = regs->isp;
regs->s = 1;
}
if (currprefs.cpu_level > 0) {
if (nr == 2 || nr == 3) {
int i;
if (currprefs.cpu_level >= 4) { /* 68040 */
if (nr == 2) {
for (i = 0 ; i < 18 ; i++) {
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
}
m68k_areg (regs, 7) -= 4;
put_long (m68k_areg (regs, 7), last_fault_for_exception_3);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0x0140 | (sv ? 6 : 2)); /* SSW */
m68k_areg (regs, 7) -= 4;
put_long (m68k_areg (regs, 7), last_addr_for_exception_3);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0x7000 + nr * 4);
} else {
m68k_areg (regs, 7) -= 4;
put_long (m68k_areg (regs, 7), last_fault_for_exception_3);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0x2000 + nr * 4);
}
} else {
uae_u16 ssw = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
ssw |= last_writeaccess_for_exception_3 ? 0 : 0x40;
ssw |= 0x20;
for (i = 0 ; i < 36; i++) {
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
}
m68k_areg (regs, 7) -= 4;
put_long (m68k_areg (regs, 7), last_fault_for_exception_3);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), ssw);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0xb000 + nr * 4);
}
write_log ("Exception %d (%08x) at %08x -> %08x!\n", nr, oldpc, currpc, get_long (regs->vbr + 4*nr));
} else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
m68k_areg (regs, 7) -= 4;
put_long (m68k_areg (regs, 7), oldpc);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0x2000 + nr * 4);
} else if (regs->m && nr >= 24 && nr < 32) { /* M + Interrupt */
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), nr * 4);
m68k_areg (regs, 7) -= 4;
put_long (m68k_areg (regs, 7), currpc);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), regs->sr);
regs->sr |= (1 << 13);
regs->msp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs->isp;
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), 0x1000 + nr * 4);
} else {
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), nr * 4);
}
} else if (nr == 2 || nr == 3) {
uae_u16 mode = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
mode |= last_writeaccess_for_exception_3 ? 0 : 16;
m68k_areg (regs, 7) -= 14;
/* fixme: bit3=I/N */
put_word (m68k_areg (regs, 7) + 0, mode);
put_long (m68k_areg (regs, 7) + 2, last_fault_for_exception_3);
put_word (m68k_areg (regs, 7) + 6, last_op_for_exception_3);
put_word (m68k_areg (regs, 7) + 8, regs->sr);
put_long (m68k_areg (regs, 7) + 10, last_addr_for_exception_3);
write_log ("Exception %d (%08x) at %08x -> %08x!\n", nr, oldpc, currpc, get_long (regs->vbr + 4*nr));
goto kludge_me_do;
}
m68k_areg (regs, 7) -= 4;
put_long (m68k_areg (regs, 7), currpc);
m68k_areg (regs, 7) -= 2;
put_word (m68k_areg (regs, 7), regs->sr);
kludge_me_do:
newpc = get_long (regs->vbr + 4 * nr);
if (newpc & 1) {
if (nr == 2 || nr == 3)
uae_reset (1); /* there is nothing else we can do.. */
else
exception3 (regs->ir, m68k_getpc (regs), newpc);
return;
}
m68k_setpc (regs, newpc);
set_special (regs, SPCFLAG_END_COMPILE);
fill_prefetch_slow (regs);
exception_trace (nr);
}
void REGPARAM2 Exception (int nr, struct regstruct *regs, uaecptr oldpc)
{
#if 0
if (1 || nr < 24)
write_log ("exception %2d %08x %08x (%04x %04x)\n",
nr, oldpc, m68k_getpc (regs), intena, intreq);
#endif
#ifdef CPUEMU_6
if (currprefs.cpu_cycle_exact && currprefs.cpu_level == 0)
Exception_ce (nr, regs, oldpc);
else
#endif
Exception_normal (nr, regs, oldpc);
}
STATIC_INLINE void do_interrupt (int nr, struct regstruct *regs)
{
#if 0
if (nr == 4)
write_log ("irq %2d at %08x (%04x)\n", nr, m68k_getpc (regs), intena & intreq);
#endif
regs->stopped = 0;
unset_special (regs, SPCFLAG_STOP);
assert (nr < 8 && nr >= 0);
Exception (nr + 24, regs, 0);
regs->intmask = nr;
set_special (regs, SPCFLAG_INT);
}
void Interrupt (int nr)
{
do_interrupt (nr, ®s);
}
static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp, buscr, pcr;
#ifndef CPUEMU_68000_ONLY
static int movec_illg (int regno)
{
int regno2 = regno & 0x7ff;
if (currprefs.cpu_level == 1) { /* 68010 */
if (regno2 < 2)
return 0;
return 1;
}
if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
if (regno == 3) return 1; /* 68040 only */
/* 4 is >=68040, but 0x804 is in 68020 */
if (regno2 < 4 || regno == 0x804)
return 0;
return 1;
}
if (currprefs.cpu_level >= 4) { /* 68040 */
if (regno == 0x802) return 1; /* 68020 only */
if (regno2 < 8) return 0;
if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
return 0;
return 1;
}
return 1;