diff --git a/src/microprobe/passes/register/__init__.py b/src/microprobe/passes/register/__init__.py
index 65c9ee77..99a01d45 100644
--- a/src/microprobe/passes/register/__init__.py
+++ b/src/microprobe/passes/register/__init__.py
@@ -52,6 +52,7 @@ class DefaultRegisterAllocationPass(microprobe.passes.Pass):
     """
 
     def __init__(self,
+                 rand: random.Random,
                  minimize=False,
                  value=None,
                  dd: Union[int, float] = 0,
@@ -64,6 +65,7 @@ def __init__(self,
 
         """
         super(DefaultRegisterAllocationPass, self).__init__()
+        self._rand = rand
         self._min = minimize
         if self._min:
             raise NotImplementedError("Feature changed need to be"
@@ -159,7 +161,8 @@ def __call__(self, building_block, target):
                                 LOG.warning("Operand set to: '%s'", value)
 
                         else:
-                            operand.set_value(operand.type.random_value())
+                            operand.set_value(operand.type.random_value(
+                                self._rand))
 
                     elif operand.type.address_relative:
                         LOG.warning(
@@ -349,7 +352,7 @@ class CycleMinimalAllocationPass(microprobe.passes.Pass):
 
     """
 
-    def __init__(self, size, reads, writes, value=None):
+    def __init__(self, size, reads, writes, rand: random.Random, value=None):
         """
 
         :param size:
@@ -363,6 +366,7 @@ def __init__(self, size, reads, writes, value=None):
         self._reads = reads  # max reads in a group to the same register
         self._writes = writes  # max writes in a group to the same register
         self._rdwr = min(reads, writes)
+        self._rand = rand
         if value is not None:
             self._immediate = value
         else:
@@ -482,7 +486,8 @@ def update_group(group):
                         else:
 
                             instroperands.append(
-                                operand.assembly(operand.random_value()))
+                                operand.assembly(operand.random_value(
+                                    self._rand)))
 
                     elif not operand.immediate():
 
@@ -1013,18 +1018,20 @@ class RandomAllocationPass(microprobe.passes.Pass):
 
     """
 
-    def __init__(self):
+    def __init__(self, rand: random.Random):
         """ """
         super(RandomAllocationPass, self).__init__()
         self._description = "Random Allocation of operands"
+        self._rand = rand
 
     def __call__(self, building_block, dummy_target):
 
         for bbl in building_block.cfg.bbls:
             for instr in bbl.instrs:
                 for operand in instr.operands():
-                    operand.set_value(operand.type.random_value())
+                    operand.set_value(operand.type.random_value(self._rand))
                     # TODO: This is a POWERPC hack (remove in future)
                     if operand.type.name == "BO_Values":
                         while operand.value in [17, 19, 21]:
-                            operand.set_value(operand.type.random_value())
+                            operand.set_value(operand.type.random_value(
+                                self._rand))
diff --git a/src/microprobe/passes/switch/__init__.py b/src/microprobe/passes/switch/__init__.py
index 141b7e61..81dfa095 100644
--- a/src/microprobe/passes/switch/__init__.py
+++ b/src/microprobe/passes/switch/__init__.py
@@ -192,7 +192,7 @@ class SwitchingInstructions(microprobe.passes.Pass):
 
     """
 
-    def __init__(self, replicate=1, strict=False):
+    def __init__(self, rand: random.Random, replicate=1, strict=False):
         """
 
         :param replicate:  (Default value = 1)
@@ -201,6 +201,7 @@ def __init__(self, replicate=1, strict=False):
         super(SwitchingInstructions, self).__init__()
         self._description = "Maximize switching factors on instruction "\
                             "operands"
+        self._rand = rand
         self._replicate = replicate
         self._strict = strict
 
@@ -560,7 +561,8 @@ def __call__(self, building_block, target):
                                     )
                                 else:
                                     opsize = \
-                                        operand.type.random_value().type.size
+                                        operand.type.random_value(
+                                            self._rand).type.size
                                     assert opsize % size == 0
                                     mult = int(opsize / size)
                                     switch_input = prefix + switch_input * mult
diff --git a/src/microprobe/target/isa/instruction.py b/src/microprobe/target/isa/instruction.py
index bfe67f24..9ba4001e 100644
--- a/src/microprobe/target/isa/instruction.py
+++ b/src/microprobe/target/isa/instruction.py
@@ -70,6 +70,9 @@ def import_definition(cls, filenames, args):
     LOG.debug("Start importing instruction definitions")
     iformats, defined_operands = args
 
+    rand = random.Random()
+    rand.seed(13)
+
     defined_memory_operands = []
     instructions = {}
 
@@ -106,7 +109,7 @@ def import_definition(cls, filenames, args):
                                        defined_operands)
 
             ioperands = _translate_ioperands(name, filename, ioperands,
-                                             defined_operands)
+                                             defined_operands, rand)
 
             moperands = _translate_moperands(name, filename, operands,
                                              ioperands, moperands,
@@ -369,7 +372,8 @@ def _translate_moperands(name, filename, operands, ioperands, moperands,
 
 
 @typeguard_testsuite
-def _translate_ioperands(name, filename, ioperands, defined_operands):
+def _translate_ioperands(name, filename, ioperands, defined_operands,
+                         rand: random.Random):
     """
 
     :param name:
@@ -393,7 +397,7 @@ def _translate_ioperands(name, filename, ioperands, defined_operands):
 
         try:
             if operand.constant:
-                reg = operand.random_value()
+                reg = operand.random_value(rand)
             else:
                 reg = [
                     value for value in operand.values()
diff --git a/src/microprobe/target/isa/operand.py b/src/microprobe/target/isa/operand.py
index c18c711f..e34d72ac 100644
--- a/src/microprobe/target/isa/operand.py
+++ b/src/microprobe/target/isa/operand.py
@@ -631,7 +631,7 @@ def filtered_values(
         raise NotImplementedError
 
     @abc.abstractmethod
-    def random_value(self):
+    def random_value(self, rand: random.Random):
         """Return a random possible value for the operand."""
         raise NotImplementedError
 
@@ -888,12 +888,12 @@ def codification(self, value):
         """
         return value.codification
 
-    def random_value(self):
+    def random_value(self, rand: random.Random):
         """Return a random possible value for the operand.
 
         :rtype: :class:`~.Register`
         """
-        return list(self._regs.keys())[random.randrange(0, len(self._regs))]
+        return list(self._regs.keys())[rand.randrange(0, len(self._regs))]
 
     def access(self, value):
         """
@@ -1013,21 +1013,21 @@ def set_valid_values(self, values):
         self._computed_values = values
         self._const = len(values) == 1
 
-    def random_value(self):
+    def random_value(self, rand: random.Random):
         """Return a random possible value for the operand.
 
         :rtype: ::class:`~.int`
         """
         if self._computed_values is not None:
-            return self._computed_values[random.randrange(
+            return self._computed_values[rand.randrange(
                 0, len(self._computed_values))]
 
-        value = random.randrange(self._min, self._max + 1, self._step)
+        value = rand.randrange(self._min, self._max + 1, self._step)
 
         if value not in self._novalues:
             return value
         else:
-            return self.random_value()
+            return self.random_value(rand)
 
     def representation(self, value):
         """
@@ -1174,12 +1174,12 @@ def codification(self, value):
         """
         return str(value)
 
-    def random_value(self):
+    def random_value(self, rand: random.Random):
         """Return a random possible value for the operand.
 
         :rtype: ::class:`~.int`
         """
-        return self._values[random.randrange(0, len(self._values))]
+        return self._values[rand.randrange(0, len(self._values))]
 
     def access(self, dummy):
         """
@@ -1271,7 +1271,7 @@ def codification(self, value):
         """
         return str(value)
 
-    def random_value(self):
+    def random_value(self, rand: random.Random):
         """Return a random possible value for the operand.
 
         :rtype: ::class:`~.int`
@@ -1368,7 +1368,7 @@ def filtered_values(
     ):
         return super().filtered_values(context, fieldname)
 
-    def random_value(self):
+    def random_value(self, rand: random.Random):
         """Return a random possible value for the operand.
 
         :rtype: :class:`~.Register`
@@ -1481,12 +1481,12 @@ def filtered_values(
     ):
         return super().filtered_values(context, fieldname)
 
-    def random_value(self):
+    def random_value(self, rand: random.Random):
         """Return a random possible value for the operand.
 
         :rtype: ::class:`~.int`
         """
-        value = random.randrange(self._mindispl, self._maxdispl) << self._shift
+        value = rand.randrange(self._mindispl, self._maxdispl) << self._shift
 
         if value <= (self._maxdispl << self._shift) and \
            value >= (self._mindispl << self._shift) and \
@@ -1494,7 +1494,7 @@ def random_value(self):
            value % self._step == 0:
             return value
         else:
-            return self.random_value()
+            return self.random_value(rand)
 
         return value
 
diff --git a/targets/generic/policies/debug.py b/targets/generic/policies/debug.py
index a16c6b74..90f666c2 100644
--- a/targets/generic/policies/debug.py
+++ b/targets/generic/policies/debug.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -62,6 +65,9 @@ def policy(target: Target, wrapper, **kwargs):
             "Policy '%s' not valid for target '%s'. Supported targets are:"
             " %s" % (NAME, target.name, ",".join(SUPPORTED_TARGETS)))
 
+    rand = random.Random()
+    rand.seed(13)
+
     sequence = [kwargs['instruction']]
     synth = microprobe.code.Synthesizer(target, wrapper)
     synth.add_pass(
@@ -76,7 +82,7 @@ def policy(target: Target, wrapper, **kwargs):
 
     synth.add_pass(microprobe.passes.register.NoHazardsAllocationPass())
     synth.add_pass(
-        microprobe.passes.register.DefaultRegisterAllocationPass(dd=99,
+        microprobe.passes.register.DefaultRegisterAllocationPass(rand, dd=99,
                                                                  relax=True))
     synth.add_pass(microprobe.passes.address.UpdateInstructionAddressesPass())
     synth.add_pass(microprobe.passes.symbol.ResolveSymbolicReferencesPass())
diff --git a/targets/generic/tests/targets/targets_tests.py b/targets/generic/tests/targets/targets_tests.py
index cc445fff..ca1e4897 100644
--- a/targets/generic/tests/targets/targets_tests.py
+++ b/targets/generic/tests/targets/targets_tests.py
@@ -134,6 +134,8 @@ def riscv_v22_function(self):
     """
     riscv_v22_function
     """
+    rand = random.Random()
+    rand.seed(13)
 
     target = self.target
     instr = target.instructions[self.instr_name]
@@ -153,7 +155,7 @@ def riscv_v22_function(self):
         microprobe.passes.instruction.SetInstructionTypeBySequencePass(
             sequence))
     # synth.add_pass(microprobe.passes.branch.BranchNextPass())
-    synth.add_pass(microprobe.passes.register.RandomAllocationPass())
+    synth.add_pass(microprobe.passes.register.RandomAllocationPass(rand))
     # synth.add_pass(microprobe.passes.register.NoHazardsAllocationPass())
     # synth.add_pass(
     #    microprobe.passes.register.DefaultRegisterAllocationPass(
@@ -317,7 +319,7 @@ def binary_benchmark(self, function):
             self.assertEqual(line_bin, asmline_bin)
 
 
-def self_codification_function(self):
+def self_codification_function(self, rand):
     """
     self_codification_function
     """
@@ -340,7 +342,7 @@ def self_codification_function(self):
 
                 for idx, operand in enumerate(instruction.operands()):
                     if idx >= len(values):
-                        values.append(operand.type.random_value())
+                        values.append(operand.type.random_value(rand))
                     operand.set_value(values[idx])
 
                 print("Operands to set: %s" % values)
@@ -388,6 +390,9 @@ def self_assembly_function(self):
     target = self.target
     instr = target.instructions[self.instr_name]
 
+    rand = random.Random()
+    rand.seed(13)
+
     repetition = 0
     while repetition < REPETITIONS:
         instruction = microprobe.code.ins.Instruction()
@@ -396,7 +401,7 @@ def self_assembly_function(self):
         print(instruction)
 
         for operand in instruction.operands():
-            operand.set_value(operand.type.random_value())
+            operand.set_value(operand.type.random_value(rand))
             print(operand)
 
         assembly = instruction.assembly()
@@ -693,7 +698,9 @@ def function_4(self):
                 """
                 function_4
                 """
-                return self_codification_function(self)
+                rand = random.Random()
+                rand.seed(13)
+                return self_codification_function(self, rand)
 
             setattr(newclass, f4name, copy_func(function_4, f4name))
 
diff --git a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_custom.py b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_custom.py
index f10c3f1c..2de1788b 100755
--- a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_custom.py
+++ b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_custom.py
@@ -24,6 +24,7 @@
 # Built-in modules
 import os
 import sys
+import random
 
 # Own modules
 import microprobe.code
@@ -123,6 +124,9 @@ def example_1():
                 ])):
             profile[instr] = 1
 
+    rand = random.Random()
+    rand.seed(13)
+
     cwrapper = microprobe.code.get_wrapper("CInfPpc")
     synth = microprobe.code.Synthesizer(TARGET, cwrapper())
 
@@ -139,7 +143,7 @@ def example_1():
         microprobe.passes.instruction.SetInstructionTypeByProfilePass(profile))
     synth.add_pass(microprobe.passes.memory.GenericMemoryModelPass(mmodel))
     synth.add_pass(
-        microprobe.passes.register.DefaultRegisterAllocationPass(dd=3))
+        microprobe.passes.register.DefaultRegisterAllocationPass(rand, dd=3))
 
     print_info("Generating %s..." % name)
     bench = synth.synthesize()
@@ -158,6 +162,9 @@ def example_2():
     cwrapper = microprobe.code.get_wrapper("CInfPpc")
     synth = microprobe.code.Synthesizer(TARGET, cwrapper())
 
+    rand = random.Random()
+    rand.seed(13)
+
     synth.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(value=RNDINT))
     synth.add_pass(
@@ -166,7 +173,7 @@ def example_2():
         microprobe.passes.instruction.SetInstructionTypeByElementPass(
             TARGET, [TARGET.elements['MUL_FXU0_Core0_SCM_Processor']], {}))
     synth.add_pass(
-        microprobe.passes.register.DefaultRegisterAllocationPass(dd=4))
+        microprobe.passes.register.DefaultRegisterAllocationPass(rand, dd=4))
 
     print_info("Generating %s..." % name)
     bench = synth.synthesize()
@@ -185,6 +192,9 @@ def example_3():
     cwrapper = microprobe.code.get_wrapper("CInfPpc")
     synth = microprobe.code.Synthesizer(TARGET, cwrapper())
 
+    rand = random.Random()
+    rand.seed(13)
+
     synth.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(value=RNDINT))
     synth.add_pass(
@@ -193,7 +203,7 @@ def example_3():
         microprobe.passes.instruction.SetInstructionTypeByElementPass(
             TARGET, [TARGET.elements['ALU_FXU0_Core0_SCM_Processor']], {}))
     synth.add_pass(
-        microprobe.passes.register.DefaultRegisterAllocationPass(dd=1))
+        microprobe.passes.register.DefaultRegisterAllocationPass(rand, dd=1))
 
     print_info("Generating %s..." % name)
     bench = synth.synthesize()
@@ -218,6 +228,9 @@ def example_4():
     cwrapper = microprobe.code.get_wrapper("CInfPpc")
     synth = microprobe.code.Synthesizer(TARGET, cwrapper())
 
+    rand = random.Random()
+    rand.seed(13)
+
     synth.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(value=RNDINT))
     synth.add_pass(
@@ -225,7 +238,7 @@ def example_4():
     synth.add_pass(
         microprobe.passes.instruction.SetInstructionTypeByProfilePass(profile))
     synth.add_pass(
-        microprobe.passes.register.DefaultRegisterAllocationPass(dd=10))
+        microprobe.passes.register.DefaultRegisterAllocationPass(rand, dd=10))
 
     print_info("Generating %s..." % name)
     bench = synth.synthesize()
@@ -250,6 +263,9 @@ def example_5():
     cwrapper = microprobe.code.get_wrapper("CInfPpc")
     synth = microprobe.code.Synthesizer(TARGET, cwrapper())
 
+    rand = random.Random()
+    rand.seed(13)
+
     synth.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(value=RNDINT))
     synth.add_pass(
@@ -257,7 +273,7 @@ def example_5():
     synth.add_pass(
         microprobe.passes.instruction.SetInstructionTypeByProfilePass(profile))
     synth.add_pass(
-        microprobe.passes.register.DefaultRegisterAllocationPass(dd=1))
+        microprobe.passes.register.DefaultRegisterAllocationPass(rand, dd=1))
 
     print_info("Generating %s..." % name)
     bench = synth.synthesize()
diff --git a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_fu_stress.py b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_fu_stress.py
index c2c9496a..e410ebda 100755
--- a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_fu_stress.py
+++ b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_fu_stress.py
@@ -28,6 +28,7 @@
 import os
 import sys
 import traceback
+import random
 
 # Own modules
 import microprobe.code.ins
@@ -222,6 +223,9 @@ def _generate_benchmark(target, output_prefix, args):
                                             cwrapper(),
                                             value=0b01010101)
 
+        rand = random.Random()
+        rand.seed(13)
+
         # Add the transformation passes
 
         #######################################################################
@@ -287,6 +291,7 @@ def _generate_benchmark(target, output_prefix, args):
         #######################################################################
         synth.add_pass(
             microprobe.passes.register.DefaultRegisterAllocationPass(
+                rand,
                 dd=distance))
 
         # Synthesize the microbenchmark.The synthesize applies the set of
diff --git a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_genetic.py b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_genetic.py
index c6c6ac5a..a1fe8b74 100755
--- a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_genetic.py
+++ b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_genetic.py
@@ -53,6 +53,7 @@
 import sys
 import time as runtime
 from typing import List, Tuple
+import random
 
 # Own modules
 import microprobe.code
@@ -156,6 +157,8 @@ def generate(name: str, dist: float, latency: float):
         """
         wrapper = microprobe.code.get_wrapper("CInfPpc")
         synth = microprobe.code.Synthesizer(TARGET, wrapper())
+        rand = random.Random()
+        rand.seed(13)
         synth.add_pass(
             microprobe.passes.initialization.InitializeRegistersPass(
                 value=RNDINT))
@@ -170,7 +173,8 @@ def generate(name: str, dist: float, latency: float):
                 avelatency=latency,
                 any_comp=any_comp))
         synth.add_pass(
-            microprobe.passes.register.DefaultRegisterAllocationPass(dd=dist))
+            microprobe.passes.register.DefaultRegisterAllocationPass(
+                rand, dd=dist))
         bench = synth.synthesize()
         synth.save(name, bench=bench)
 
diff --git a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_memory.py b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_memory.py
index 3636a895..b99fe3e7 100755
--- a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_memory.py
+++ b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_memory.py
@@ -182,6 +182,9 @@ def rnd():
     # Create the benchmark synthesizer
     synth = microprobe.code.Synthesizer(garch, cwrapper())
 
+    rand = random.Random()
+    rand.seed(13)
+
     ##########################################################################
     # Add the passes we want to apply to synthesize benchmarks               #
     ##########################################################################
@@ -212,7 +215,7 @@ def rnd():
     # remaining undefined instruction operands (register allocation,...)
     synth.add_pass(microprobe.passes.register.NoHazardsAllocationPass())
     synth.add_pass(
-        microprobe.passes.register.DefaultRegisterAllocationPass(dd=0))
+        microprobe.passes.register.DefaultRegisterAllocationPass(rand, dd=0))
 
     # Generate the benchmark (applies the passes).
     bench = synth.synthesize()
diff --git a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_profile.py b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_profile.py
index ee141821..eda83bda 100755
--- a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_profile.py
+++ b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_profile.py
@@ -27,6 +27,7 @@
 import os
 import sys
 import traceback
+import random
 
 # Third party modules
 
@@ -303,6 +304,9 @@ def _generate_benchmark(args):
                                             cwrapper(),
                                             value=0b01010101)
 
+        rand = random.Random()
+        rand.seed(13)
+
         # Add the transformation passes
 
         #######################################################################
@@ -405,7 +409,7 @@ def _generate_benchmark(args):
         #######################################################################
         synth.add_pass(
             microprobe.passes.register.DefaultRegisterAllocationPass(
-                dd=distance))
+                rand, dd=distance))
 
         # Synthesize the microbenchmark.The synthesize applies the set of
         # transformation passes added before and returns object representing
diff --git a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_random.py b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_random.py
index 15bc4e6e..11afcfe0 100755
--- a/targets/power/examples/power_v206_power7_ppc64_linux_gcc_random.py
+++ b/targets/power/examples/power_v206_power7_ppc64_linux_gcc_random.py
@@ -209,7 +209,7 @@ def rnd():
     #     distance is randomly picked
     synth.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=rand.randint(1, 20)))
+            rand, dd=rand.randint(1, 20)))
 
     # Generate the benchmark (applies the passes)
     # Since it is a randomly generated code, the generation might fail
diff --git a/targets/power/policies/epi.py b/targets/power/policies/epi.py
index 71d092d4..6e2f8341 100644
--- a/targets/power/policies/epi.py
+++ b/targets/power/policies/epi.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -97,6 +100,9 @@ def policy(target, wrapper, **kwargs):
                                               wrapper,
                                               value=0b01010101)
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(
             value=RNDINT()))
@@ -153,7 +159,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=kwargs['dependency_distance']))
+            rand, dd=kwargs['dependency_distance']))
 
     synthesizer.add_pass(
         microprobe.passes.address.UpdateInstructionAddressesPass())
diff --git a/targets/power/policies/epi_power10.py b/targets/power/policies/epi_power10.py
index 3a27538e..68cb27c3 100644
--- a/targets/power/policies/epi_power10.py
+++ b/targets/power/policies/epi_power10.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -112,6 +115,9 @@ def policy(target, wrapper, **kwargs):
                                               wrapper,
                                               value=kwargs['data_init'])
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.structure.SimpleBuildingBlockPass(
             kwargs['benchmark_size']))
@@ -204,7 +210,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=kwargs['dependency_distance'], value=kwargs['data_init']))
+            rand, dd=kwargs['dependency_distance'], value=kwargs['data_init']))
 
     synthesizer.add_pass(
         microprobe.passes.address.UpdateInstructionAddressesPass(force=True))
diff --git a/targets/power/policies/epi_power9.py b/targets/power/policies/epi_power9.py
index bf45b75c..77dbb124 100644
--- a/targets/power/policies/epi_power9.py
+++ b/targets/power/policies/epi_power9.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -108,6 +111,9 @@ def policy(target, wrapper, **kwargs):
                                               wrapper,
                                               value=kwargs['data_init'])
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(
             value=kwargs['data_init']))
@@ -178,7 +184,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=kwargs['dependency_distance'], value=kwargs['data_init']))
+            rand, dd=kwargs['dependency_distance'], value=kwargs['data_init']))
 
     synthesizer.add_pass(
         microprobe.passes.address.UpdateInstructionAddressesPass(force=True))
diff --git a/targets/power/policies/seq_power10.py b/targets/power/policies/seq_power10.py
index 1b87254f..924e8954 100644
--- a/targets/power/policies/seq_power10.py
+++ b/targets/power/policies/seq_power10.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -102,6 +105,9 @@ def policy(target, wrapper, **kwargs):
                                               wrapper,
                                               value=0b01010101)
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(value=RNDINT))
 
@@ -180,7 +186,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.switch.SwitchingInstructions(
-            strict=kwargs['force_switch']))
+            rand, strict=kwargs['force_switch']))
 
     if kwargs['dependency_distance'] < 1:
         synthesizer.add_pass(
@@ -188,7 +194,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=kwargs['dependency_distance']))
+            rand, dd=kwargs['dependency_distance']))
 
     synthesizer.add_pass(
         microprobe.passes.address.UpdateInstructionAddressesPass())
diff --git a/targets/power/policies/seq_power9.py b/targets/power/policies/seq_power9.py
index b8d47f1b..2bee94a8 100644
--- a/targets/power/policies/seq_power9.py
+++ b/targets/power/policies/seq_power9.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -102,6 +105,9 @@ def policy(target, wrapper, **kwargs):
                                               wrapper,
                                               value=0b01010101)
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(value=RNDINT))
 
@@ -180,7 +186,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.switch.SwitchingInstructions(
-            strict=kwargs['force_switch']))
+            rand, strict=kwargs['force_switch']))
 
     if kwargs['dependency_distance'] < 1:
         synthesizer.add_pass(
@@ -188,7 +194,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=kwargs['dependency_distance']))
+            rand, dd=kwargs['dependency_distance']))
 
     synthesizer.add_pass(
         microprobe.passes.address.UpdateInstructionAddressesPass())
diff --git a/targets/power/policies/seqtune_power10.py b/targets/power/policies/seqtune_power10.py
index 0e57b3c2..411799b4 100644
--- a/targets/power/policies/seqtune_power10.py
+++ b/targets/power/policies/seqtune_power10.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -100,6 +103,9 @@ def policy(target, wrapper, **kwargs):
                                               wrapper,
                                               value=0b01010101)
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.ReserveRegistersPass(["GPR0"]))
 
@@ -195,7 +201,8 @@ def policy(target, wrapper, **kwargs):
     synthesizer.add_pass(microprobe.passes.branch.BranchNextPass())
 
     if kwargs["data_switch"]:
-        synthesizer.add_pass(microprobe.passes.switch.SwitchingInstructions())
+        synthesizer.add_pass(microprobe.passes.switch.SwitchingInstructions(
+            rand))
 
     if kwargs['dependency_distance'] < 1:
         synthesizer.add_pass(
@@ -203,7 +210,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=kwargs['dependency_distance']))
+            rand, dd=kwargs['dependency_distance']))
 
     synthesizer.add_pass(
         microprobe.passes.address.UpdateInstructionAddressesPass())
diff --git a/targets/power/policies/seqtune_power9.py b/targets/power/policies/seqtune_power9.py
index 50a609b4..5f232b1b 100644
--- a/targets/power/policies/seqtune_power9.py
+++ b/targets/power/policies/seqtune_power9.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in modules
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -100,6 +103,9 @@ def policy(target, wrapper, **kwargs):
                                               wrapper,
                                               value=0b01010101)
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.ReserveRegistersPass(["GPR0"]))
 
@@ -195,7 +201,8 @@ def policy(target, wrapper, **kwargs):
     synthesizer.add_pass(microprobe.passes.branch.BranchNextPass())
 
     if kwargs["data_switch"]:
-        synthesizer.add_pass(microprobe.passes.switch.SwitchingInstructions())
+        synthesizer.add_pass(microprobe.passes.switch.SwitchingInstructions(
+            rand))
 
     if kwargs['dependency_distance'] < 1:
         synthesizer.add_pass(
@@ -203,7 +210,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
-            dd=kwargs['dependency_distance']))
+            rand, dd=kwargs['dependency_distance']))
 
     synthesizer.add_pass(
         microprobe.passes.address.UpdateInstructionAddressesPass())
diff --git a/targets/power/tests/targets/targets_tests.py b/targets/power/tests/targets/targets_tests.py
index 33ac77b0..3e53df1c 100644
--- a/targets/power/tests/targets/targets_tests.py
+++ b/targets/power/tests/targets/targets_tests.py
@@ -133,6 +133,8 @@ def power_v206_function(self):
     """
     power_v206_function
     """
+    rand = random.Random()
+    rand.seed(13)
 
     target = self.target
     instr = target.instructions[self.instr_name]
@@ -152,7 +154,7 @@ def power_v206_function(self):
         microprobe.passes.instruction.SetInstructionTypeBySequencePass(
             sequence))
     # synth.add_pass(microprobe.passes.branch.BranchNextPass())
-    synth.add_pass(microprobe.passes.register.RandomAllocationPass())
+    synth.add_pass(microprobe.passes.register.RandomAllocationPass(rand))
     # synth.add_pass(microprobe.passes.register.NoHazardsAllocationPass())
     # synth.add_pass(
     #     microprobe.passes.register.DefaultRegisterAllocationPass(
@@ -169,6 +171,8 @@ def power_v300_function(self):
     """
     power_v300_function
     """
+    rand = random.Random()
+    rand.seed(13)
 
     target = self.target
     instr = target.instructions[self.instr_name]
@@ -188,7 +192,7 @@ def power_v300_function(self):
         microprobe.passes.instruction.SetInstructionTypeBySequencePass(
             sequence))
     # synth.add_pass(microprobe.passes.branch.BranchNextPass())
-    synth.add_pass(microprobe.passes.register.RandomAllocationPass())
+    synth.add_pass(microprobe.passes.register.RandomAllocationPass(rand))
     # synth.add_pass(microprobe.passes.register.NoHazardsAllocationPass())
     # synth.add_pass(
     #    microprobe.passes.register.DefaultRegisterAllocationPass(
@@ -205,6 +209,8 @@ def power_v310_function(self):
     """
     power_v310_function
     """
+    rand = random.Random()
+    rand.seed(13)
 
     target = self.target
     instr = target.instructions[self.instr_name]
@@ -224,7 +230,7 @@ def power_v310_function(self):
         microprobe.passes.instruction.SetInstructionTypeBySequencePass(
             sequence))
     # synth.add_pass(microprobe.passes.branch.BranchNextPass())
-    synth.add_pass(microprobe.passes.register.RandomAllocationPass())
+    synth.add_pass(microprobe.passes.register.RandomAllocationPass(rand))
     # synth.add_pass(microprobe.passes.register.NoHazardsAllocationPass())
     # synth.add_pass(
     #    microprobe.passes.register.DefaultRegisterAllocationPass(
@@ -384,7 +390,7 @@ def binary_benchmark(self, function):
             self.assertEqual(line_bin, asmline_bin)
 
 
-def self_codification_function(self):
+def self_codification_function(self, rand: random.Random):
     """
     self_codification_function
     """
@@ -407,7 +413,7 @@ def self_codification_function(self):
 
                 for idx, operand in enumerate(instruction.operands()):
                     if idx >= len(values):
-                        values.append(operand.type.random_value())
+                        values.append(operand.type.random_value(rand))
                     operand.set_value(values[idx])
 
                 print("Operands to set: %s" % values)
@@ -455,6 +461,9 @@ def self_assembly_function(self):
     target = self.target
     instr = target.instructions[self.instr_name]
 
+    rand = random.Random()
+    rand.seed(13)
+
     repetition = 0
     while repetition < REPETITIONS:
         instruction = microprobe.code.ins.Instruction()
@@ -463,7 +472,7 @@ def self_assembly_function(self):
         print(instruction)
 
         for operand in instruction.operands():
-            operand.set_value(operand.type.random_value())
+            operand.set_value(operand.type.random_value(rand))
             print(operand)
 
         assembly = instruction.assembly()
@@ -828,7 +837,9 @@ def function_4(self):
                 """
                 function_4
                 """
-                return self_codification_function(self)
+                rand = random.Random()
+                rand.seed(13)
+                return self_codification_function(self, rand)
 
             setattr(newclass, f4name, copy_func(function_4, f4name))
 
diff --git a/targets/riscv/examples/riscv_branch.py b/targets/riscv/examples/riscv_branch.py
index d53596d7..3297b401 100755
--- a/targets/riscv/examples/riscv_branch.py
+++ b/targets/riscv/examples/riscv_branch.py
@@ -315,7 +315,7 @@ def emit(self):
         synth.add_pass(p)
 
         # Model dependency distance (no dependencies)
-        p = register.DefaultRegisterAllocationPass(dd=0)
+        p = register.DefaultRegisterAllocationPass(self._rand, dd=0)
         synth.add_pass(p)
 
         # Set target of branches (regarless of taken not taken,
diff --git a/targets/riscv/examples/riscv_ipc.py b/targets/riscv/examples/riscv_ipc.py
index f10f2c46..77fd00cf 100755
--- a/targets/riscv/examples/riscv_ipc.py
+++ b/targets/riscv/examples/riscv_ipc.py
@@ -147,7 +147,7 @@ def emit(self):
                     memory.GenericMemoryStreamsPass(
                         [[1, 4*1024*1024, 1, 128, 1, 0, (1, 0)]]
                     ),
-                    register.DefaultRegisterAllocationPass(dd=d)
+                    register.DefaultRegisterAllocationPass(self._rand, dd=d)
                 ]
 
                 for p in passes:
diff --git a/targets/riscv/examples/riscv_ipc_c.py b/targets/riscv/examples/riscv_ipc_c.py
index 8bf39341..162189bf 100755
--- a/targets/riscv/examples/riscv_ipc_c.py
+++ b/targets/riscv/examples/riscv_ipc_c.py
@@ -145,7 +145,7 @@ def emit(self):
                     memory.GenericMemoryStreamsPass(
                         [[0, 1024, 1, 32, 1, 0, (1, 0)]]
                     ),
-                    register.DefaultRegisterAllocationPass(dd=d)
+                    register.DefaultRegisterAllocationPass(self._rand, dd=d)
                 ]
 
                 for p in passes:
diff --git a/targets/riscv/examples/riscv_ipc_seq.py b/targets/riscv/examples/riscv_ipc_seq.py
index 74dba478..175bfd1c 100755
--- a/targets/riscv/examples/riscv_ipc_seq.py
+++ b/targets/riscv/examples/riscv_ipc_seq.py
@@ -124,6 +124,8 @@ def __init__(self):
             str.format("{}-{}-{}",
                        self.args.isa, self.args.uarch, self.args.env)
         )
+        self._rand = random.Random()
+        self._rand.seed(64)  # My favorite number ;)
 
     def emit(self):
         # Do not touch pointer registers
@@ -203,7 +205,7 @@ def emit(self):
                     memory.GenericMemoryStreamsPass(
                         [[0, 1024, 1, 32, 1, 0, (1, 0)]]
                     ),
-                    register.DefaultRegisterAllocationPass(dd=d)
+                    register.DefaultRegisterAllocationPass(self._rand, dd=d)
                 ]
 
                 for p in passes:
diff --git a/targets/riscv/policies/epi.py b/targets/riscv/policies/epi.py
index 43876bbb..c988a212 100644
--- a/targets/riscv/policies/epi.py
+++ b/targets/riscv/policies/epi.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -90,6 +93,9 @@ def policy(target, wrapper, **kwargs):
         target, wrapper, value=0b01010101
     )
 
+    rand = random.Random()
+    rand.seed(13)
+
     # synthesizer.add_pass(
     #     microprobe.passes.initialization.InitializeRegistersPass(
     #         value=RNDINT()
@@ -157,6 +163,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
+            rand,
             dd=kwargs['dependency_distance']
         )
     )
diff --git a/targets/riscv/policies/seq.py b/targets/riscv/policies/seq.py
index 843532c8..3eb5307b 100644
--- a/targets/riscv/policies/seq.py
+++ b/targets/riscv/policies/seq.py
@@ -17,6 +17,9 @@
 # Futures
 from __future__ import absolute_import
 
+# Built-in
+import random
+
 # Own modules
 import microprobe.code
 import microprobe.passes.address
@@ -95,6 +98,9 @@ def policy(target, wrapper, **kwargs):
         target, wrapper, value=0b01010101
     )
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(
             value=RNDINT()
@@ -172,6 +178,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.switch.SwitchingInstructions(
+          rand,
           strict=kwargs['force_switch']
         )
     )
@@ -182,6 +189,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
+            rand,
             dd=kwargs['dependency_distance']
         )
     )
diff --git a/targets/riscv/policies/seqtune.py b/targets/riscv/policies/seqtune.py
index 911837a3..7481362c 100644
--- a/targets/riscv/policies/seqtune.py
+++ b/targets/riscv/policies/seqtune.py
@@ -19,6 +19,7 @@
 
 # Built-in
 import warnings
+import random
 
 # Own modules
 import microprobe.code
@@ -104,6 +105,9 @@ def policy(target, wrapper, **kwargs):
         target, wrapper, value=0b01010101
     )
 
+    rand = random.Random()
+    rand.seed(13)
+
     synthesizer.add_pass(
         microprobe.passes.initialization.InitializeRegistersPass(
             value=RNDINT()
@@ -209,7 +213,7 @@ def policy(target, wrapper, **kwargs):
 
     if kwargs["data_switch"]:
         synthesizer.add_pass(
-            microprobe.passes.switch.SwitchingInstructions()
+            microprobe.passes.switch.SwitchingInstructions(rand)
         )
 
     if kwargs['dependency_distance'] < 1:
@@ -218,6 +222,7 @@ def policy(target, wrapper, **kwargs):
 
     synthesizer.add_pass(
         microprobe.passes.register.DefaultRegisterAllocationPass(
+            rand,
             dd=kwargs['dependency_distance']
         )
     )