diff --git a/iob_cache.py b/iob_cache.py
index 4473390..f15bb36 100755
--- a/iob_cache.py
+++ b/iob_cache.py
@@ -85,6 +85,7 @@ def _create_submodules_list(cls):
         super()._create_submodules_list(
             [
                 {"interface": "iob_s_port"},
+                {"interface": "iob_s_portmap"},
                 {"interface": "axi_m_port"},
                 {"interface": "axi_m_m_portmap"},
                 {"interface": "axi_m_write_port"},
@@ -412,6 +413,7 @@ def _setup_ios(cls):
 
     @classmethod
     def _setup_regs(cls):
+        cls.autoaddr = False
         cls.regs += [
             {
                 "name": "cache",
@@ -422,7 +424,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 1,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 0,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Write-through buffer empty (1) or non-empty (0).",
@@ -432,7 +434,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 1,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 1,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Write-through buffer full (1) or non-full (0).",
@@ -442,7 +444,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 32,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 4,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Read and write hit counter.",
@@ -452,7 +454,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 32,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 8,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Read and write miss counter.",
@@ -462,7 +464,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 32,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 12,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Read hit counter.",
@@ -472,7 +474,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 32,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 16,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Read miss counter.",
@@ -482,7 +484,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 32,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 20,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Write hit counter.",
@@ -492,7 +494,7 @@ def _setup_regs(cls):
                         "type": "R",
                         "n_bits": 32,
                         "rst_val": 0,
-                        "addr": -1,
+                        "addr": 24,
                         "log2n_items": 0,
                         "autologic": False,
                         "descr": "Write miss counter.",
diff --git a/submodules/LIB b/submodules/LIB
index 17aaab8..9a2ebfe 160000
--- a/submodules/LIB
+++ b/submodules/LIB
@@ -1 +1 @@
-Subproject commit 17aaab878dc2916e5f6fb68c52f1a2a5fc749178
+Subproject commit 9a2ebfe8bfec451c0ad465f4f391bcc990033153