From 9cc61acdc9b4217b544ae37a9a35ac0fceceb6b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Artur=20N=C3=B3brega?= <arturnobrega1999@gmail.com>
Date: Tue, 24 Oct 2023 19:02:14 +0100
Subject: [PATCH] fix(regs): Use `autoreg` field

---
 iob_cache.py   | 20 ++++++++++----------
 submodules/LIB |  2 +-
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/iob_cache.py b/iob_cache.py
index 44733901..08d161d1 100755
--- a/iob_cache.py
+++ b/iob_cache.py
@@ -424,7 +424,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Write-through buffer empty (1) or non-empty (0).",
                     },
                     {
@@ -434,7 +434,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Write-through buffer full (1) or non-full (0).",
                     },
                     {
@@ -444,7 +444,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Read and write hit counter.",
                     },
                     {
@@ -454,7 +454,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Read and write miss counter.",
                     },
                     {
@@ -464,7 +464,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Read hit counter.",
                     },
                     {
@@ -474,7 +474,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Read miss counter.",
                     },
                     {
@@ -484,7 +484,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Write hit counter.",
                     },
                     {
@@ -494,7 +494,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": -1,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Write miss counter.",
                     },
                     {
@@ -504,7 +504,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": 28,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Reset read/write hit/miss counters by writing any value to this register.",
                     },
                     {
@@ -514,7 +514,7 @@ def _setup_regs(cls):
                         "rst_val": 0,
                         "addr": 29,
                         "log2n_items": 0,
-                        "autologic": False,
+                        "autoreg": False,
                         "descr": "Invalidate the cache data contents by writing any value to this register.",
                     },
                 ],
diff --git a/submodules/LIB b/submodules/LIB
index 211b9628..28a12be3 160000
--- a/submodules/LIB
+++ b/submodules/LIB
@@ -1 +1 @@
-Subproject commit 211b962864f6a83facd48ef7464d28e0ebad22cf
+Subproject commit 28a12be36fc2c05a3978ca1b15b544feb2cd944a