diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index ff513498..47f55159 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -66,22 +66,22 @@ jobs: - name: icarus test run: nix-shell --run "make -C ../iob_soc_o* sim-run" - # verilator-baremetal: - # runs-on: self-hosted - # timeout-minutes: 90 - # # run even if previous job failed - # if: ${{ !cancelled() }} - # - # steps: - # - uses: actions/checkout@v4 - # with: - # submodules: 'recursive' - # - name: clean - # run: nix-shell --run "make clean" - # - name: setup no_init_mem ext_mem - # run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0" - # - name: verilator test - # run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator" + verilator-baremetal: + runs-on: self-hosted + timeout-minutes: 90 + # run even if previous job failed + if: ${{ !cancelled() }} + + steps: + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + - name: clean + run: nix-shell --run "make clean" + - name: setup no_init_mem ext_mem + run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0" + - name: verilator test + run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator" cyclonev: diff --git a/hardware/simulation/sim_build.mk b/hardware/simulation/sim_build.mk index 60803ab2..930ae77e 100644 --- a/hardware/simulation/sim_build.mk +++ b/hardware/simulation/sim_build.mk @@ -10,6 +10,12 @@ VTOP:=iob_soc_opencryptolinux_tb # SOURCES ifeq ($(SIMULATOR),verilator) +VSRC+=./src/iob_tasks.cpp + +ifeq ($(USE_ETHERNET),1) +VSRC+=./src/iob_eth_swreg_emb_verilator.c ./src/iob_eth_driver_tb.cpp +endif + # verilator top module VTOP:=iob_soc_opencryptolinux_sim_wrapper diff --git a/hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v b/hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v index ee765417..8a327542 100644 --- a/hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v +++ b/hardware/simulation/src/iob_soc_opencryptolinux_sim_wrapper.v @@ -13,101 +13,91 @@ `endif module iob_soc_opencryptolinux_sim_wrapper ( -`include "clk_rst_s_port.vs" - output trap_o, + `include "clk_rst_s_port.vs" + output trap_o, `ifdef IOB_SOC_OPENCRYPTOLINUX_USE_ETHERNET - // Ethernet for testbench - input ethernet_valid_i, - input [`IOB_ETH_SWREG_ADDR_W-1:0] ethernet_addr_i, - input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_wdata_i, - input [3:0] ethernet_wstrb_i, - output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_rdata_o, - output ethernet_ready_o, - output ethernet_rvalid_o, + // Ethernet for testbench + input ethernet_valid_i, + input [ `IOB_ETH_SWREG_ADDR_W-1:0] ethernet_addr_i, + input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_wdata_i, + input [ 3:0] ethernet_wstrb_i, + output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] ethernet_rdata_o, + output ethernet_ready_o, + output ethernet_rvalid_o, `endif - // UART for testbench - input uart_valid_i, - input [`IOB_UART_SWREG_ADDR_W-1:0] uart_addr_i, - input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_wdata_i, - input [3:0] uart_wstrb_i, - output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_rdata_o, - output uart_ready_o, - output uart_rvalid_o + // UART for testbench + input uart_valid_i, + input [ `IOB_UART_SWREG_ADDR_W-1:0] uart_addr_i, + input [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_wdata_i, + input [ 3:0] uart_wstrb_i, + output [`IOB_SOC_OPENCRYPTOLINUX_DATA_W-1:0] uart_rdata_o, + output uart_ready_o, + output uart_rvalid_o ); - localparam AXI_ID_W = 4; - localparam AXI_LEN_W = 8; - localparam AXI_ADDR_W = `DDR_ADDR_W; - localparam AXI_DATA_W = `DDR_DATA_W; + localparam AXI_ID_W = 4; + localparam AXI_LEN_W = 8; + localparam AXI_ADDR_W = `DDR_ADDR_W; + localparam AXI_DATA_W = `DDR_DATA_W; - `include "iob_soc_opencryptolinux_wrapper_pwires.vs" + `include "iob_soc_opencryptolinux_wrapper_pwires.vs" - ///////////////////////////////////////////// - // TEST PROCEDURE - // - initial begin -`ifdef VCD - $dumpfile("uut.vcd"); - $dumpvars(); -`endif - end - - // - // INSTANTIATE COMPONENTS - // + // + // INSTANTIATE COMPONENTS + // - // - // IOb-SoC-OpenCryptoLinux (may also include Unit Under Test) - // - iob_soc_opencryptolinux #( + // + // IOb-SoC-OpenCryptoLinux (may also include Unit Under Test) + // + iob_soc_opencryptolinux #( .AXI_ID_W (AXI_ID_W), .AXI_LEN_W (AXI_LEN_W), .AXI_ADDR_W(AXI_ADDR_W), .AXI_DATA_W(AXI_DATA_W) - ) soc0 ( + ) soc0 ( `include "iob_soc_opencryptolinux_pportmaps.vs" .clk_i (clk_i), .cke_i (1'b1), .arst_i(arst_i), .trap_o(trap_o) - ); + ); - // interconnect clk and arst - wire clk_interconnect; - wire arst_interconnect; - assign clk_interconnect = clk_i; - assign arst_interconnect = arst_i; + // interconnect clk and arst + wire clk_interconnect; + wire arst_interconnect; + assign clk_interconnect = clk_i; + assign arst_interconnect = arst_i; - `include "iob_soc_opencryptolinux_interconnect.vs" + `include "iob_soc_opencryptolinux_interconnect.vs" - //instantiate the axi memory - //IOb-SoC-OpenCryptoLinux and SUT access the same memory. - axi_ram #( + //instantiate the axi memory + //IOb-SoC-OpenCryptoLinux and SUT access the same memory. + axi_ram #( `ifdef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM .FILE ("init_ddr_contents"), //This file contains firmware for both systems `endif .ID_WIDTH (AXI_ID_W), .DATA_WIDTH(AXI_DATA_W), .ADDR_WIDTH(AXI_ADDR_W) - ) ddr_model_mem ( + ) ddr_model_mem ( `include "iob_memory_axi_s_portmap.vs" .clk_i(clk_i), .rst_i(arst_i) - ); + ); - //Manually added testbench uart core. RS232 pins attached to the same pins - //of the iob_soc UART0 instance to communicate with it - // The interface of iob_soc UART0 is assumed to be the first portmapped interface (UART_*) - iob_uart uart_tb ( + //Manually added testbench uart core. RS232 pins attached to the same pins + //of the iob_soc UART0 instance to communicate with it + // The interface of iob_soc UART0 is assumed to be the first portmapped interface (UART_*) + iob_uart uart_tb ( .clk_i (clk_i), .cke_i (1'b1), .arst_i(arst_i), - .iob_valid_i(uart_valid_i), + .iob_valid_i (uart_valid_i), .iob_addr_i (uart_addr_i), .iob_wdata_i (uart_wdata_i), .iob_wstrb_i (uart_wstrb_i), @@ -119,94 +109,93 @@ module iob_soc_opencryptolinux_sim_wrapper ( .rxd_i(uart_txd_o), .rts_o(uart_cts_i), .cts_i(uart_rts_o) - ); + ); - //Ethernet + //Ethernet `ifdef IOB_SOC_OPENCRYPTOLINUX_USE_ETHERNET - //ethernet clock: 4x slower than system clock - reg [1:0] eth_cnt = 2'b0; - reg eth_clk; - - always @(posedge clk_i) begin - eth_cnt <= eth_cnt + 1'b1; - eth_clk <= eth_cnt[1]; - end - - // Ethernet Interface signals - assign ETH0_MRxClk = eth_clk; - assign ETH0_MTxClk = eth_clk; - - //Manually added testbench ethernet core. MII pins attached to the same pins - //of the iob_soc ETH0 instance to communicate with it - // The interface of iob_soc ETH0 is assumed to be the first portmapped interface (ETH_*) - iob_eth - #( - .AXI_ID_W(AXI_ID_W), + //ethernet clock: 4x slower than system clock + reg [1:0] eth_cnt = 2'b0; + reg eth_clk; + + always @(posedge clk_i) begin + eth_cnt <= eth_cnt + 1'b1; + eth_clk <= eth_cnt[1]; + end + + // Ethernet Interface signals + assign ETH0_MRxClk = eth_clk; + assign ETH0_MTxClk = eth_clk; + + //Manually added testbench ethernet core. MII pins attached to the same pins + //of the iob_soc ETH0 instance to communicate with it + // The interface of iob_soc ETH0 is assumed to be the first portmapped interface (ETH_*) + iob_eth #( + .AXI_ID_W (AXI_ID_W), .AXI_ADDR_W(AXI_ADDR_W), .AXI_DATA_W(AXI_DATA_W), - .AXI_LEN_W(AXI_LEN_W) - ) eth_tb ( - .inta_o(), - .MTxClk(eth_clk), - .MTxD(ETH0_MRxD), - .MTxEn(ETH0_MRxDv), - .MTxErr(ETH0_MRxErr), - .MRxClk(eth_clk), - .MRxDv(ETH0_MTxEn), - .MRxD(ETH0_MTxD), - .MRxErr(ETH0_MTxErr), - .MColl(1'b0), - .MCrS(1'b0), - .MDC(), - .MDIO(), - .iob_valid_i(ethernet_valid_i), - .iob_addr_i (ethernet_addr_i), - .iob_wdata_i (ethernet_wdata_i), - .iob_wstrb_i (ethernet_wstrb_i), - .iob_rvalid_o(ethernet_rvalid_o), - .iob_rdata_o (ethernet_rdata_o), - .iob_ready_o (ethernet_ready_o), - .axi_awid_o (), - .axi_awaddr_o (), - .axi_awlen_o (), - .axi_awsize_o (), - .axi_awburst_o (), - .axi_awlock_o (), - .axi_awcache_o (), - .axi_awprot_o (), - .axi_awqos_o (), - .axi_awvalid_o (), - .axi_awready_i (1'b0), - .axi_wdata_o (), - .axi_wstrb_o (), - .axi_wlast_o (), - .axi_wvalid_o (), - .axi_wready_i (1'b0), - .axi_bid_i ({AXI_ID_W{1'b0}}), - .axi_bresp_i (2'b0), - .axi_bvalid_i (1'b0), - .axi_bready_o (), - .axi_arid_o (), - .axi_araddr_o (), - .axi_arlen_o (), - .axi_arsize_o (), - .axi_arburst_o (), - .axi_arlock_o (), - .axi_arcache_o (), - .axi_arprot_o (), - .axi_arqos_o (), - .axi_arvalid_o (), - .axi_arready_i (1'b0), - .axi_rid_i ({AXI_ID_W{1'b0}}), - .axi_rdata_i ({AXI_DATA_W{1'b0}}), - .axi_rresp_i (2'b0), - .axi_rlast_i (1'b0), - .axi_rvalid_i (1'b0), - .axi_rready_o (), - .clk_i(clk_i), - .arst_i(arst_i), - .cke_i(1'b1) - ); + .AXI_LEN_W (AXI_LEN_W) + ) eth_tb ( + .inta_o (), + .MTxClk (eth_clk), + .MTxD (ETH0_MRxD), + .MTxEn (ETH0_MRxDv), + .MTxErr (ETH0_MRxErr), + .MRxClk (eth_clk), + .MRxDv (ETH0_MTxEn), + .MRxD (ETH0_MTxD), + .MRxErr (ETH0_MTxErr), + .MColl (1'b0), + .MCrS (1'b0), + .MDC (), + .MDIO (), + .iob_valid_i (ethernet_valid_i), + .iob_addr_i (ethernet_addr_i), + .iob_wdata_i (ethernet_wdata_i), + .iob_wstrb_i (ethernet_wstrb_i), + .iob_rvalid_o (ethernet_rvalid_o), + .iob_rdata_o (ethernet_rdata_o), + .iob_ready_o (ethernet_ready_o), + .axi_awid_o (), + .axi_awaddr_o (), + .axi_awlen_o (), + .axi_awsize_o (), + .axi_awburst_o(), + .axi_awlock_o (), + .axi_awcache_o(), + .axi_awprot_o (), + .axi_awqos_o (), + .axi_awvalid_o(), + .axi_awready_i(1'b0), + .axi_wdata_o (), + .axi_wstrb_o (), + .axi_wlast_o (), + .axi_wvalid_o (), + .axi_wready_i (1'b0), + .axi_bid_i ({AXI_ID_W{1'b0}}), + .axi_bresp_i (2'b0), + .axi_bvalid_i (1'b0), + .axi_bready_o (), + .axi_arid_o (), + .axi_araddr_o (), + .axi_arlen_o (), + .axi_arsize_o (), + .axi_arburst_o(), + .axi_arlock_o (), + .axi_arcache_o(), + .axi_arprot_o (), + .axi_arqos_o (), + .axi_arvalid_o(), + .axi_arready_i(1'b0), + .axi_rid_i ({AXI_ID_W{1'b0}}), + .axi_rdata_i ({AXI_DATA_W{1'b0}}), + .axi_rresp_i (2'b0), + .axi_rlast_i (1'b0), + .axi_rvalid_i (1'b0), + .axi_rready_o (), + .clk_i (clk_i), + .arst_i (arst_i), + .cke_i (1'b1) + ); `endif `ifndef VERILATOR diff --git a/software/src/iob_soc_opencryptolinux_boot.c b/software/src/iob_soc_opencryptolinux_boot.c index 2b1fd1ad..7710b3dc 100644 --- a/software/src/iob_soc_opencryptolinux_boot.c +++ b/software/src/iob_soc_opencryptolinux_boot.c @@ -24,6 +24,7 @@ // NOTE: These functions are not compatible with malloc() and free(). // These are specifically made for use with the current iob-eth.c drivers. // (These assume that there is only one block allocated at a time) +// It allocates a block with required size at the end of the external memory region. static void *mem_alloc(size_t size) { return (void *)(EXT_MEM | (1 << IOB_SOC_OPENCRYPTOLINUX_MEM_ADDR_W)) - size; } diff --git a/submodules/ETHERNET b/submodules/ETHERNET index 497c7c9f..a0f9fedd 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit 497c7c9f609e5b241e87b49318c113411e08ea7c +Subproject commit a0f9feddddcb31897468bd17f81478a16b916637 diff --git a/submodules/IOBSOC b/submodules/IOBSOC index e877b4df..0829606b 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit e877b4dfa9be09b749bbf041a752a5055cee9a2a +Subproject commit 0829606b26afcba5e1a312eba426755cd5fa104f