From de9a3685d889a9e9e92b1909aca20c9e530cd604 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Mon, 19 Feb 2024 21:23:24 +0000 Subject: [PATCH 01/23] feat(sim): [WIP] Use ethernet in simulation --- software/src/iob_soc_opencryptolinux_boot.c | 4 ---- submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/software/src/iob_soc_opencryptolinux_boot.c b/software/src/iob_soc_opencryptolinux_boot.c index aa6338b4..90c1bc5c 100644 --- a/software/src/iob_soc_opencryptolinux_boot.c +++ b/software/src/iob_soc_opencryptolinux_boot.c @@ -146,12 +146,8 @@ int main() { for (i = 0; i < file_count; i++) { prog_start_addr = (char *)(EXT_MEM + file_address_array[i]); // Receive data from console via Ethernet -#ifndef SIMULATION file_size = uart_recvfile_ethernet(file_name_array[i]); eth_rcv_file(prog_start_addr,file_size); -#else - file_size = uart16550_recvfile(file_name_array[i], prog_start_addr); -#endif } // Check if running Linux diff --git a/submodules/ETHERNET b/submodules/ETHERNET index 54844d78..99b034eb 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit 54844d78cfe8c39557699a41960e286772304e70 +Subproject commit 99b034eb5d4653ac5ed03e0ff81641ff9a5f0050 diff --git a/submodules/IOBSOC b/submodules/IOBSOC index 98fa6513..a3b4e9ba 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit 98fa65138c29d45bee067969c4abe0bab50092c0 +Subproject commit a3b4e9bac910154d5892c64d580ad7365a682cc2 From da3cf960934052dcd5578b1c27ed2585a3d05d03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 21 Feb 2024 05:06:54 +0000 Subject: [PATCH 02/23] chore(submodules): update submodules --- submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/submodules/ETHERNET b/submodules/ETHERNET index 99b034eb..a9104afe 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit 99b034eb5d4653ac5ed03e0ff81641ff9a5f0050 +Subproject commit a9104afe12e2fbf7596596614635d6aebfeb4ebc diff --git a/submodules/IOBSOC b/submodules/IOBSOC index a3b4e9ba..d6bd8801 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit a3b4e9bac910154d5892c64d580ad7365a682cc2 +Subproject commit d6bd88014d9e812a56768ac312cbbfc4e151d9bf From 98f6986fa6958b89c578690fb55a4baac0090209 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Fri, 17 May 2024 04:42:46 +0100 Subject: [PATCH 03/23] chore(submodules): Update submodules --- iob_soc_opencryptolinux.py | 4 +++- submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index 601606b9..16311bbf 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -176,7 +176,7 @@ def _post_setup(cls): if cls.is_top_module: # Set ethernet MAC address append_str_config_build_mk( - """ + f""" ### Set Ethernet environment variables #Mac address of pc interface connected to ethernet peripheral (based on board name) $(if $(findstring sim,$(MAKECMDGOALS))$(SIMULATOR),$(eval BOARD=)) @@ -191,6 +191,8 @@ def _post_setup(cls): #Set correct environment if running on IObundle machines ifneq ($(filter pudim-flan sericaia,$(shell hostname)),) IOB_CONSOLE_PYTHON_ENV ?= /opt/pyeth3/bin/python +else +IOB_CONSOLE_PYTHON_ENV ?= ../{cls.name}/submodules/ETHERNET/scripts/pyRawWrapper/pyRawWrapper endif """, cls.build_dir, diff --git a/submodules/ETHERNET b/submodules/ETHERNET index a9104afe..a825d9d9 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit a9104afe12e2fbf7596596614635d6aebfeb4ebc +Subproject commit a825d9d9343cf769676528ea73c2792e45f49c2e diff --git a/submodules/IOBSOC b/submodules/IOBSOC index d6bd8801..601b3e17 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit d6bd88014d9e812a56768ac312cbbfc4e151d9bf +Subproject commit 601b3e17d2bae7ef1dbbf397a2023fb56ca618b1 From 2139a0f7b7e6f07285b18d284865e6079f381953 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Fri, 17 May 2024 19:25:30 +0100 Subject: [PATCH 04/23] fix(eth): Fix pyRawWrapper script path --- iob_soc_opencryptolinux.py | 2 +- submodules/IOBSOC | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index 16311bbf..f506e181 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -192,7 +192,7 @@ def _post_setup(cls): ifneq ($(filter pudim-flan sericaia,$(shell hostname)),) IOB_CONSOLE_PYTHON_ENV ?= /opt/pyeth3/bin/python else -IOB_CONSOLE_PYTHON_ENV ?= ../{cls.name}/submodules/ETHERNET/scripts/pyRawWrapper/pyRawWrapper +IOB_CONSOLE_PYTHON_ENV ?= {__class__.setup_dir}/submodules/ETHERNET/scripts/pyRawWrapper/pyRawWrapper endif """, cls.build_dir, diff --git a/submodules/IOBSOC b/submodules/IOBSOC index 601b3e17..c85612d2 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit 601b3e17d2bae7ef1dbbf397a2023fb56ca618b1 +Subproject commit c85612d29cf6d63e48c71c594b1502aa41274750 From e36fdac87e28d182f736af2b4d57dd1c57795ef1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 22 May 2024 05:15:51 +0100 Subject: [PATCH 05/23] chore(submodules): Update submodules Frames sent to loopback interface are correctly captured by eth2file, transfered to testbench ethernet core, and sent via ethernet to the SoC. Other way around is not tested. --- submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/submodules/ETHERNET b/submodules/ETHERNET index a825d9d9..3f0dae86 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit a825d9d9343cf769676528ea73c2792e45f49c2e +Subproject commit 3f0dae86e449e77db976bdc6de0e4dd13cc0079c diff --git a/submodules/IOBSOC b/submodules/IOBSOC index c85612d2..b3326877 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit c85612d29cf6d63e48c71c594b1502aa41274750 +Subproject commit b3326877aa4e6496cfff20ee41995f489806a21b From 22ef693c131aadf708f09fb35370ab283f4ad53d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 22 May 2024 20:36:55 +0100 Subject: [PATCH 06/23] feat(eth): Fix eth transfers from SoC to PC. Add debug frame in bootloader to be sent from SoC to PC. This frame is correctly captured in the loopback interface via wireshark during SoC boot in simulation. Update submodules. --- software/src/iob_soc_opencryptolinux_boot.c | 7 +++++++ submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/software/src/iob_soc_opencryptolinux_boot.c b/software/src/iob_soc_opencryptolinux_boot.c index 90c1bc5c..b4d760b2 100644 --- a/software/src/iob_soc_opencryptolinux_boot.c +++ b/software/src/iob_soc_opencryptolinux_boot.c @@ -91,6 +91,7 @@ int main() { } #ifndef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM + uart16550_puts("D1\n"); //DEBUG // Init ethernet and printf (for ethernet) printf_init(&uart16550_putc); eth_init(ETH0_BASE, &clear_cache); @@ -98,6 +99,12 @@ int main() { eth_init_mem_alloc(&mem_alloc, &mem_free); // Wait for PHY reset to finish eth_wait_phy_rst(); + uart16550_puts("D2\n"); //DEBUG + + //DEBUG + char eth_debug_data[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64}; + eth_send_frame(eth_debug_data, 64); + uart16550_puts("D3\n"); //DEBUG file_size = uart16550_recvfile("../iob_soc_opencryptolinux_mem.config", prog_start_addr); // compute_mem_load_txt diff --git a/submodules/ETHERNET b/submodules/ETHERNET index 3f0dae86..fe6b04a8 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit 3f0dae86e449e77db976bdc6de0e4dd13cc0079c +Subproject commit fe6b04a81b2966153d28b5fb2bdffe89c82c7b50 diff --git a/submodules/IOBSOC b/submodules/IOBSOC index b3326877..ef265837 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit b3326877aa4e6496cfff20ee41995f489806a21b +Subproject commit ef2658370de6b5f16a2f2d1b26a5ef0472d039c0 From d25bfc724756b2d74cb4d0a6ad3a27831976a688 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Thu, 23 May 2024 05:50:27 +0100 Subject: [PATCH 07/23] fix(eth): Fix multiple transfers from soc2eth. --- software/src/iob_soc_opencryptolinux_boot.c | 2 ++ submodules/ETHERNET | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/software/src/iob_soc_opencryptolinux_boot.c b/software/src/iob_soc_opencryptolinux_boot.c index b4d760b2..01014943 100644 --- a/software/src/iob_soc_opencryptolinux_boot.c +++ b/software/src/iob_soc_opencryptolinux_boot.c @@ -105,6 +105,8 @@ int main() { char eth_debug_data[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64}; eth_send_frame(eth_debug_data, 64); uart16550_puts("D3\n"); //DEBUG + eth_send_frame(eth_debug_data, 64); + uart16550_puts("D4\n"); //DEBUG file_size = uart16550_recvfile("../iob_soc_opencryptolinux_mem.config", prog_start_addr); // compute_mem_load_txt diff --git a/submodules/ETHERNET b/submodules/ETHERNET index fe6b04a8..9a060df7 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit fe6b04a81b2966153d28b5fb2bdffe89c82c7b50 +Subproject commit 9a060df74ee551b7f319a892fd5c09061cafc343 From 73523dd072f6975d466101cb09d44982ba21fc35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Sun, 26 May 2024 05:27:23 +0100 Subject: [PATCH 08/23] feat(eth): Update ethernet environment variables; Update submodules Ethernet transfers seem to be working well in simulation using the virtual network interface. --- iob_soc_opencryptolinux.py | 11 +++++++---- submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index f506e181..b9fd4ac5 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -178,15 +178,18 @@ def _post_setup(cls): append_str_config_build_mk( f""" ### Set Ethernet environment variables -#Mac address of pc interface connected to ethernet peripheral (based on board name) +#Eth interface address of pc connected to ethernet peripheral (based on board name) $(if $(findstring sim,$(MAKECMDGOALS))$(SIMULATOR),$(eval BOARD=)) ifeq ($(BOARD),AES-KU040-DB-G) -RMAC_ADDR ?=989096c0632c +ETH_IF ?=eno1 endif ifeq ($(BOARD),CYCLONEV-GT-DK) -RMAC_ADDR ?=309c231e624b +ETH_IF ?=enp3s0 endif -RMAC_ADDR ?=000000000000 +ETH_IF ?=eth10 +export ETH_IF +# Set a MAC address for console (randomly generated) +RMAC_ADDR ?=88431eafa897 export RMAC_ADDR #Set correct environment if running on IObundle machines ifneq ($(filter pudim-flan sericaia,$(shell hostname)),) diff --git a/submodules/ETHERNET b/submodules/ETHERNET index 9a060df7..2bb218f7 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit 9a060df74ee551b7f319a892fd5c09061cafc343 +Subproject commit 2bb218f72712b29da5b7e1b18c41940daf9ee4be diff --git a/submodules/IOBSOC b/submodules/IOBSOC index ef265837..d8a251bf 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit ef2658370de6b5f16a2f2d1b26a5ef0472d039c0 +Subproject commit d8a251bffc11820f6c1b4e8ec3ca288647221ee7 From 9e604a58ba2a489e0060c00531412116a788b415 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Sun, 26 May 2024 05:50:24 +0100 Subject: [PATCH 09/23] refactor(eth): Remove debug prints; Enable eth in simulation. Enabled example ethernet file transfer in firmware for simulation (previously only enabled for FPGA). Ethernet file transfer works in simulation (with Icarus). To run, use the following command: ``` make clean setup INIT_MEM=1 && make -C ../iob_soc_opencryptolinux_V0.70/ sim-run ``` Related to milestone 18. --- software/src/iob_soc_opencryptolinux_boot.c | 9 --------- software/src/iob_soc_opencryptolinux_firmware.c | 2 -- submodules/ETHERNET | 2 +- 3 files changed, 1 insertion(+), 12 deletions(-) diff --git a/software/src/iob_soc_opencryptolinux_boot.c b/software/src/iob_soc_opencryptolinux_boot.c index 01014943..90c1bc5c 100644 --- a/software/src/iob_soc_opencryptolinux_boot.c +++ b/software/src/iob_soc_opencryptolinux_boot.c @@ -91,7 +91,6 @@ int main() { } #ifndef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM - uart16550_puts("D1\n"); //DEBUG // Init ethernet and printf (for ethernet) printf_init(&uart16550_putc); eth_init(ETH0_BASE, &clear_cache); @@ -99,14 +98,6 @@ int main() { eth_init_mem_alloc(&mem_alloc, &mem_free); // Wait for PHY reset to finish eth_wait_phy_rst(); - uart16550_puts("D2\n"); //DEBUG - - //DEBUG - char eth_debug_data[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64}; - eth_send_frame(eth_debug_data, 64); - uart16550_puts("D3\n"); //DEBUG - eth_send_frame(eth_debug_data, 64); - uart16550_puts("D4\n"); //DEBUG file_size = uart16550_recvfile("../iob_soc_opencryptolinux_mem.config", prog_start_addr); // compute_mem_load_txt diff --git a/software/src/iob_soc_opencryptolinux_firmware.c b/software/src/iob_soc_opencryptolinux_firmware.c index 6a84890b..c7e0fcf7 100644 --- a/software/src/iob_soc_opencryptolinux_firmware.c +++ b/software/src/iob_soc_opencryptolinux_firmware.c @@ -99,7 +99,6 @@ int main() { eth_init(ETH0_BASE, &clear_cache); eth_wait_phy_rst(); -#ifndef SIMULATION char buffer[5096]; // Receive data from console via Ethernet uint32_t file_size = uart_recvfile_ethernet("../src/eth_example.txt"); @@ -107,7 +106,6 @@ int main() { uart16550_puts("\nFile received from console via ethernet:\n"); for(i=0; i Date: Sun, 26 May 2024 06:02:59 +0100 Subject: [PATCH 10/23] feat(Makefile): Add `sim-run` target --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 50d999ca..b7a1bbca 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,9 @@ endif setup: make build-setup SETUP_ARGS="$(SETUP_ARGS)" +sim-run: + nix-shell --run 'make clean setup INIT_MEM=$(INIT_MEM) && make -C ../$(CORE)_V*/ sim-run SIMULATOR=$(SIMULATOR)' + sim-test-linux: nix-shell --run "make clean" nix-shell --run "make setup INIT_MEM=1" @@ -56,4 +59,4 @@ test-linux-fpga-connect: build_dir_name -ln -s minicom_test1.txt $(BUILD_DIR)/hardware/fpga/minicom_linux_script.txt make fpga-connect RUN_LINUX=1 -.PHONY: sim-test fpga-test test-all test-linux-fpga-connect +.PHONY: setup sim-run sim-test fpga-test test-all test-linux-fpga-connect From 56753d0fc6f482954f32ada9664d6b3234d8e75e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 29 May 2024 02:41:35 +0100 Subject: [PATCH 11/23] chore(submodules): Update submodules Ethernet is still working in simulation. Use the following command to test it: ``` make sim-run INIT_MEM=1 SIMULATOR=icarus ``` --- submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/submodules/ETHERNET b/submodules/ETHERNET index e9285c5a..9ed74ff3 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit e9285c5aac67b2ccfcf9f2aad4c57a4494b89a77 +Subproject commit 9ed74ff32aa053c18f5704b259499e2165e8f24a diff --git a/submodules/IOBSOC b/submodules/IOBSOC index d8a251bf..82ff8ee5 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit d8a251bffc11820f6c1b4e8ec3ca288647221ee7 +Subproject commit 82ff8ee56271c4b8ce316189483a6def07c3f575 From 253566b98d034a0cc1076c34426e9e9e8cd02700 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Fri, 31 May 2024 07:43:01 +0100 Subject: [PATCH 12/23] chore(submodule): update ethernet submodule --- submodules/ETHERNET | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/submodules/ETHERNET b/submodules/ETHERNET index 9ed74ff3..e706057f 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit 9ed74ff32aa053c18f5704b259499e2165e8f24a +Subproject commit e706057f08159c9ac770f2e8d8ee7028e5328503 From 29dafe904f7f2ce2593d5e7c0fbc92fef77b6d70 Mon Sep 17 00:00:00 2001 From: PMiranda Date: Fri, 31 May 2024 15:28:47 +0100 Subject: [PATCH 13/23] fix(doc): update Ethernet submodule docs - update ETHERNET submodule with doc figure fix --- submodules/ETHERNET | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/submodules/ETHERNET b/submodules/ETHERNET index e706057f..b357bb1b 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit e706057f08159c9ac770f2e8d8ee7028e5328503 +Subproject commit b357bb1b608e0020629c82c862779f3e5a99ae03 From e5264a9ee4227756f8cfd550282e1dadec25d606 Mon Sep 17 00:00:00 2001 From: PMiranda Date: Mon, 3 Jun 2024 15:58:07 +0100 Subject: [PATCH 14/23] update(ethernet): update submodule --- submodules/ETHERNET | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/submodules/ETHERNET b/submodules/ETHERNET index b357bb1b..5658c8c7 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit b357bb1b608e0020629c82c862779f3e5a99ae03 +Subproject commit 5658c8c7908d637875699286122deac8457c85b1 From b81af6d877c8ae4f4b67e4f97887ddf28eecd355 Mon Sep 17 00:00:00 2001 From: PMiranda Date: Thu, 6 Jun 2024 19:48:28 +0100 Subject: [PATCH 15/23] fix(fpga): cyclonev synthesis working - still blocks running bootloader --- .../iob_soc_opencryptolinux_mwrap.v | 183 ++++++++++++++++++ hardware/fpga/Makefile | 1 + submodules/ETHERNET | 2 +- submodules/IOBSOC | 2 +- 4 files changed, 186 insertions(+), 2 deletions(-) create mode 100644 hardware/common_src/iob_soc_opencryptolinux_mwrap.v diff --git a/hardware/common_src/iob_soc_opencryptolinux_mwrap.v b/hardware/common_src/iob_soc_opencryptolinux_mwrap.v new file mode 100644 index 00000000..221683c0 --- /dev/null +++ b/hardware/common_src/iob_soc_opencryptolinux_mwrap.v @@ -0,0 +1,183 @@ +`timescale 1 ns / 1 ps + +`include "bsp.vh" +`include "iob_soc_opencryptolinux_conf.vh" +`include "iob_utils.vh" + +//Peripherals _swreg_def.vh file includes. +`include "iob_soc_opencryptolinux_periphs_swreg_def.vs" + +module iob_soc_opencryptolinux_mwrap #( + +`ifdef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM + parameter HEXFILE = "iob_soc_opencryptolinux_firmware", +`else + parameter HEXFILE = "none", +`endif + parameter BOOT_HEXFILE = "iob_soc_opencryptolinux_boot", + parameter MEM_NO_READ_ON_WRITE = 1, //no simultaneous read/write + `include "iob_soc_opencryptolinux_params.vs" +) ( + `include "iob_soc_opencryptolinux_io.vs" +); + +`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_EXTMEM + + `include "iob_mwrap_extmem_wires.vs" + + assign axi_awid_o = axi_awid; + assign axi_awaddr_o = axi_awaddr; + assign axi_awlen_o = axi_awlen; + assign axi_awsize_o = axi_awsize; + assign axi_awburst_o = axi_awburst; + assign axi_awlock_o = axi_awlock; + assign axi_awcache_o = axi_awcache; + assign axi_awprot_o = axi_awprot; + assign axi_awqos_o = axi_awqos; + assign axi_awvalid_o = axi_awvalid; + assign axi_awready = axi_awready_i; + assign axi_wdata_o = axi_wdata; + assign axi_wstrb_o = axi_wstrb; + assign axi_wlast_o = axi_wlast; + assign axi_wvalid_o = axi_wvalid; + assign axi_wready = axi_wready_i; + assign axi_bid = axi_bid_i; + assign axi_bresp = axi_bresp_i; + assign axi_bvalid = axi_bvalid_i; + assign axi_bready_o = axi_bready; + assign axi_arid_o = axi_arid; + assign axi_araddr_o = axi_araddr; + assign axi_arlen_o = axi_arlen; + assign axi_arsize_o = axi_arsize; + assign axi_arburst_o = axi_arburst; + assign axi_arlock_o = axi_arlock; + assign axi_arcache_o = axi_arcache; + assign axi_arprot_o = axi_arprot; + assign axi_arqos_o = axi_arqos; + assign axi_arvalid_o = axi_arvalid; + assign axi_arready = axi_arready_i; + assign axi_rid = axi_rid_i; + assign axi_rdata = axi_rdata_i; + assign axi_rresp = axi_rresp_i; + assign axi_rlast = axi_rlast_i; + assign axi_rvalid = axi_rvalid_i; + assign axi_rready_o = axi_rready; + + +`endif + + + +//rom wires +wire rom_r_valid; +wire [BOOTROM_ADDR_W-3:0] rom_r_addr; +wire [DATA_W-1:0] rom_r_rdata; + + +//ram wires +wire i_valid; +wire [SRAM_ADDR_W-3:0] i_addr; +wire [ DATA_W-1:0] i_wdata; +wire [ DATA_W/8-1:0] i_wstrb; +wire [ DATA_W-1:0] i_rdata; +wire d_valid; +wire [SRAM_ADDR_W-3:0] d_addr; +wire [ DATA_W-1:0] d_wdata; +wire [ DATA_W/8-1:0] d_wstrb; +wire [ DATA_W-1:0] d_rdata; +// + +`ifdef USE_SPRAM + wire spram_en; + wire [SRAM_ADDR_W-3:0] spram_addr; + wire [DATA_W/8-1:0] spram_we; + wire [DATA_W-1:0] spram_di; + wire [DATA_W-1:0] spram_do; +`endif + +iob_soc_opencryptolinux #( + `include "iob_soc_opencryptolinux_inst_params.vs" +)iob_soc_opencryptolinux( + `include "iob_soc_opencryptolinux_pportmaps.vs" + .clk_i( clk_i), + .cke_i( cke_i), + .arst_i( arst_i), + .trap_o( trap_o), +); + + + + `ifdef USE_SPRAM + iob_ram_sp_be #( + .HEXFILE(HEXFILE), + .ADDR_W (SRAM_ADDR_W - 2), + .DATA_W (DATA_W) + ) main_mem_byte ( + .clk_i(clk_i), + // data port + .en_i (spram_en), + .addr_i(spram_addr), + .we_i (spram_we), + .d_i (spram_di), + .dt_o (spram_do) + ); + `else + `ifdef IOB_MEM_NO_READ_ON_WRITE + iob_ram_dp_be #( + .HEXFILE (HEXFILE), + .ADDR_W (SRAM_ADDR_W - 2), + .DATA_W (DATA_W), + .MEM_NO_READ_ON_WRITE(1) + ) main_mem_byte ( + .clk_i(clk_i), + // data port + .enA_i (d_valid), + .addrA_i(d_addr), + .weA_i (d_wstrb), + .dA_i (d_wdata), + .dA_o (d_rdata), + + // instruction port + .enB_i (i_valid), + .addrB_i(i_addr), + .weB_i (i_wstrb), + .dB_i (i_wdata), + .dB_o (i_rdata) + ); + `else // !`ifdef IOB_MEM_NO_READ_ON_WRITE + iob_ram_dp_be_xil #( + .HEXFILE(HEXFILE), + .ADDR_W (SRAM_ADDR_W - 2), + .DATA_W (DATA_W) + ) main_mem_byte ( + .clk_i(clk_i), + + // data port + .enA_i (d_valid), + .addrA_i(d_addr), + .weA_i (d_wstrb), + .dA_i (d_wdata), + .dA_o (d_rdata), + // instruction port + .enB_i (i_valid), + .addrB_i(i_addr), + .weB_i (i_wstrb), + .dB_i (i_wdata), + .dB_o (i_rdata) + ); + `endif + `endif + + + //rom instatiation + iob_rom_sp #( + .DATA_W (DATA_W), + .ADDR_W (BOOTROM_ADDR_W - 2), + .HEXFILE({BOOT_HEXFILE, ".hex"}) + ) sp_rom0 ( + .clk_i (clk_i), + .r_en_i (rom_r_valid), + .addr_i (rom_r_addr), + .r_data_o(rom_r_rdata) + ); +endmodule diff --git a/hardware/fpga/Makefile b/hardware/fpga/Makefile index 951779ff..e391cb93 100644 --- a/hardware/fpga/Makefile +++ b/hardware/fpga/Makefile @@ -35,6 +35,7 @@ include $(FPGA_TOOL)/build.mk #include the module's headers and sources VHDR += $(wildcard ../src/*.vh) $(wildcard ./src/*.vh) VSRC += $(wildcard ../src/*.v) $(wildcard ./src/*.v) +VSRC += $(wildcard ../common_src/*.v) ifneq ($(wildcard $(FPGA_TOOL)/$(BOARD)/$(NAME)_fpga_wrapper.v),) VSRC+=$(FPGA_TOOL)/$(BOARD)/$(NAME)_fpga_wrapper.v diff --git a/submodules/ETHERNET b/submodules/ETHERNET index 8f45ec2d..497c7c9f 160000 --- a/submodules/ETHERNET +++ b/submodules/ETHERNET @@ -1 +1 @@ -Subproject commit 8f45ec2da9a69dd3778ce410e917396bbaacb261 +Subproject commit 497c7c9f609e5b241e87b49318c113411e08ea7c diff --git a/submodules/IOBSOC b/submodules/IOBSOC index 5869bbe9..c593b469 160000 --- a/submodules/IOBSOC +++ b/submodules/IOBSOC @@ -1 +1 @@ -Subproject commit 5869bbe96d875c25333430f30e86842b401f4f7a +Subproject commit c593b46904972e46506d7db7031fc3a1b3dec06d From b16e05592b1236aff7e109ea2eccc866983a2a99 Mon Sep 17 00:00:00 2001 From: P-Miranda Date: Fri, 7 Jun 2024 00:04:33 +0100 Subject: [PATCH 16/23] fix(sim): working icarus simulation - fix mwrap.v module - add instructions to setup dummy interfaces for each simulator - update simulation to use `eth-SIMULATOR` interface --- README.md | 11 +++++++++++ .../common_src/iob_soc_opencryptolinux_mwrap.v | 2 +- iob_soc_opencryptolinux.py | 17 +++++++++++++++-- 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index d283e70c..2ee7b5fd 100644 --- a/README.md +++ b/README.md @@ -46,6 +46,17 @@ make setup The first time it runs, `nix-shell` will automatically install all the required dependencies. This can take a couple of hours, but after that, you can enjoy IOb-SoC-OpenCryptoLinux and not worry about installing software tools. +## Ethernet simulation +The ethernet simulation requires setting up dummy interfaces with +`eth-[SIMULATOR]` that require `sudo`: +Setup the following interfaces with the commands: +```bash +sudo modprobe dummy +sudo ip link add eth-icarus type dummy +sudo ifconfig eth-icarus up +sudo ip link add eth-verilator type dummy +sudo ifconfig eth-verilator up +``` ## Dependencies diff --git a/hardware/common_src/iob_soc_opencryptolinux_mwrap.v b/hardware/common_src/iob_soc_opencryptolinux_mwrap.v index 221683c0..0836671d 100644 --- a/hardware/common_src/iob_soc_opencryptolinux_mwrap.v +++ b/hardware/common_src/iob_soc_opencryptolinux_mwrap.v @@ -102,7 +102,7 @@ iob_soc_opencryptolinux #( .clk_i( clk_i), .cke_i( cke_i), .arst_i( arst_i), - .trap_o( trap_o), + .trap_o( trap_o) ); diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index e68a66f5..551f1fd1 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -246,6 +246,21 @@ def _post_setup(cls): with open(cls.build_dir + "/hardware/fpga/fpga_build.mk", "w") as file: file.writelines(contents) + # Set ETH_IF in sim_build.mk + with open(cls.build_dir + "/hardware/simulation/sim_build.mk", "r") as file: + contents = file.readlines() + + contents.insert(0, "\n") + contents.insert( + 0, + """ +#Lines below were auto generated by iob_soc_opencryptolinux.py +ETH_IF ?= eth-$(SIMULATOR) +""", + ) + with open(cls.build_dir + "/hardware/simulation/sim_build.mk", "w") as file: + file.writelines(contents) + if cls.is_top_module: # Set ethernet MAC address append_str_config_build_mk( @@ -259,8 +274,6 @@ def _post_setup(cls): ifeq ($(BOARD),CYCLONEV-GT-DK) ETH_IF ?=enp3s0 endif -ETH_IF ?=eth10 -export ETH_IF # Set a MAC address for console (randomly generated) RMAC_ADDR ?=88431eafa897 export RMAC_ADDR From 2b6f6f2716ba50a5732a3df4899de83310d05524 Mon Sep 17 00:00:00 2001 From: PMiranda Date: Tue, 11 Jun 2024 20:11:05 +0100 Subject: [PATCH 17/23] fix(KU040): ethernet working for KU040 - use correct RMAC_ADDR for KU040 - update RMAC_ADDR for corresponding CYCLONEV-GT-DK interface, but not working --- .github/workflows/ci.yml | 2 +- iob_soc_opencryptolinux.py | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 478f850a..a6b6813e 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -116,7 +116,7 @@ jobs: - name: test baremetal run: make fpga-run RUN_LINUX=0 BOARD=AES-KU040-DB-G - name: test linux - run: make test-linux-fpga-connect BOARD=AES-KU040-DB-G BOOT_FLOW=FLASH_TO_EXTMEM + run: make test-linux-fpga-connect BOARD=AES-KU040-DB-G BOOT_FLOW=CONSOLE_TO_EXTMEM ## doc: ## runs-on: self-hosted diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index 551f1fd1..861a1770 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -270,9 +270,11 @@ def _post_setup(cls): $(if $(findstring sim,$(MAKECMDGOALS))$(SIMULATOR),$(eval BOARD=)) ifeq ($(BOARD),AES-KU040-DB-G) ETH_IF ?=eno1 +RMAC_ADDR ?= 989096c0632c endif ifeq ($(BOARD),CYCLONEV-GT-DK) -ETH_IF ?=enp3s0 +ETH_IF ?= enp3s0 +RMAC_ADDR ?= 309c231e624a endif # Set a MAC address for console (randomly generated) RMAC_ADDR ?=88431eafa897 From 2c097e06e15c4b5d1e73505757ab806961c74370 Mon Sep 17 00:00:00 2001 From: PMiranda Date: Tue, 11 Jun 2024 20:35:35 +0100 Subject: [PATCH 18/23] merge(main): update OS and main branch - update with main branch and with latest OS submodule - remove verilator test from CI (currently not supported by ethernet) --- .github/workflows/ci.yml | 32 ++++++++++++++++---------------- submodules/OS | 2 +- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index a6b6813e..fe7a0981 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -66,22 +66,22 @@ jobs: - name: icarus test run: nix-shell --run "make -C ../iob_soc_o* sim-run" - verilator-baremetal: - runs-on: self-hosted - timeout-minutes: 90 - # run even if previous job failed - if: ${{ !cancelled() }} - - steps: - - uses: actions/checkout@v4 - with: - submodules: 'recursive' - - name: clean - run: nix-shell --run "make clean" - - name: setup no_init_mem ext_mem - run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0" - - name: verilator test - run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator" + # verilator-baremetal: + # runs-on: self-hosted + # timeout-minutes: 90 + # # run even if previous job failed + # if: ${{ !cancelled() }} + # + # steps: + # - uses: actions/checkout@v4 + # with: + # submodules: 'recursive' + # - name: clean + # run: nix-shell --run "make clean" + # - name: setup no_init_mem ext_mem + # run: nix-shell --run "make setup INIT_MEM=0 RUN_LINUX=0" + # - name: verilator test + # run: nix-shell --run "make -C ../iob_soc_o* sim-run SIMULATOR=verilator" cyclonev: diff --git a/submodules/OS b/submodules/OS index 398df392..803a486e 160000 --- a/submodules/OS +++ b/submodules/OS @@ -1 +1 @@ -Subproject commit 398df3928926172a4e75f9411ca0c767b1bb5c86 +Subproject commit 803a486e10f64b9b079203bc08cee21d3f280f43 From 85996dbb663ea1342aea86f4066eb65f750a4a4b Mon Sep 17 00:00:00 2001 From: PMiranda Date: Tue, 11 Jun 2024 20:38:46 +0100 Subject: [PATCH 19/23] fix(CI): fix job dependencies --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index fe7a0981..ff513498 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -90,7 +90,7 @@ jobs: # run even if previous job failed if: ${{ !cancelled() }} # run after indicated job - needs: [ verilator-baremetal ] + needs: [ iverilog-baremetal ] steps: - uses: actions/checkout@v4 @@ -107,7 +107,7 @@ jobs: # run even if previous job failed if: ${{ !cancelled() }} # run after indicated job - needs: [ verilator-baremetal ] + needs: [ iverilog-baremetal ] steps: - uses: actions/checkout@v4 From 1dac8c2c40cbb43bf2b68d7b8b6a41c349d94def Mon Sep 17 00:00:00 2001 From: PMiranda Date: Wed, 12 Jun 2024 10:35:46 +0100 Subject: [PATCH 20/23] fix(cyclonev): add eth clock constraint, fix RMAC - use correct interface and RMAC for cyclonev host machine - add eth clock constraints for cyclonev --- .../iob_soc_opencryptolinux_fpga_wrapper_dev.sdc | 2 ++ iob_soc_opencryptolinux.py | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) create mode 100644 hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc diff --git a/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc b/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc new file mode 100644 index 00000000..4d0b59a6 --- /dev/null +++ b/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc @@ -0,0 +1,2 @@ +create_clock -name "clk" -period 20.0 [get_ports {clk}] +create_clock -period 40 [get_ports {ENET_RX_CLK}] diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index 4bacb8fc..28085bd7 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -281,8 +281,8 @@ def _post_setup(cls): RMAC_ADDR ?= 989096c0632c endif ifeq ($(BOARD),CYCLONEV-GT-DK) -ETH_IF ?= enp3s0 -RMAC_ADDR ?= 309c231e624a +ETH_IF ?= enp0s31f6 +RMAC_ADDR ?= 309c231e624b endif # Set a MAC address for console (randomly generated) RMAC_ADDR ?=88431eafa897 From 791e70765f4d751fd69e2fb169de4968bea464c5 Mon Sep 17 00:00:00 2001 From: PMiranda Date: Wed, 12 Jun 2024 12:27:55 +0100 Subject: [PATCH 21/23] fix(doc): add dummy interface instructions - update README with instructions to setup dummy eth-SIMULATOR interfaces on machine reboot --- README.md | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/README.md b/README.md index 2ee7b5fd..2fd83760 100644 --- a/README.md +++ b/README.md @@ -57,6 +57,24 @@ sudo ifconfig eth-icarus up sudo ip link add eth-verilator type dummy sudo ifconfig eth-verilator up ``` + +#### Make dummy interfaces permanent: +1. Add `dummy` to `/etc/modules` +2. Create `/etc/network/if-pre-up.d/dummy-eth-interfaces` with: +```bash +#!/usr/bin/env bash + +# Create eth-SIMULATOR dummy interfaces +ip link add eth-icarus type dummy +ifconfig eth-icarus up +ip link add eth-verilator type dummy +ifconfig eth-verilator up +``` +3. Set script as executable: +```bash +# Set script as executable +sudo chmod +x /etc/network/if-pre-up.d/dummy-eth-interfaces +``` ## Dependencies From d217c8ead0fee694faec0abfe7f510245e209bc2 Mon Sep 17 00:00:00 2001 From: PMiranda Date: Wed, 12 Jun 2024 15:27:48 +0100 Subject: [PATCH 22/23] fix(sim): run pyeth3 on feynman - update submodules with latest upstream master --- iob_soc_opencryptolinux.py | 2 +- submodules/VERSAT | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index 28085bd7..c55d325d 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -288,7 +288,7 @@ def _post_setup(cls): RMAC_ADDR ?=88431eafa897 export RMAC_ADDR #Set correct environment if running on IObundle machines -ifneq ($(filter pudim-flan sericaia,$(shell hostname)),) +ifneq ($(filter feynman pudim-flan sericaia,$(shell hostname)),) IOB_CONSOLE_PYTHON_ENV ?= /opt/pyeth3/bin/python else IOB_CONSOLE_PYTHON_ENV ?= {__class__.setup_dir}/submodules/ETHERNET/scripts/pyRawWrapper/pyRawWrapper diff --git a/submodules/VERSAT b/submodules/VERSAT index d7c7d0d5..7572c5fb 160000 --- a/submodules/VERSAT +++ b/submodules/VERSAT @@ -1 +1 @@ -Subproject commit d7c7d0d5c4b9b6d76f6e02063fc14c5d443219ec +Subproject commit 7572c5fbf52cb03653de0fadc633af07e71ac892 From 0bc20327000873e1336495d1b7247cb2d67de5dc Mon Sep 17 00:00:00 2001 From: PMiranda Date: Wed, 12 Jun 2024 17:05:25 +0100 Subject: [PATCH 23/23] feat(mac): all flows use fake RMAC - update makefiles to use fake RMAC - NOTE: requires configuring interface connected to board with promiscuous mode - update README with instructions --- README.md | 14 ++++++++++++++ iob_soc_opencryptolinux.py | 2 -- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 2fd83760..47a0e55e 100644 --- a/README.md +++ b/README.md @@ -75,6 +75,20 @@ ifconfig eth-verilator up # Set script as executable sudo chmod +x /etc/network/if-pre-up.d/dummy-eth-interfaces ``` + +## Ethernet Receiver MAC Address +The current ethernet setup uses a fake receiver MAC address (RMAC_ADDR) common +for all simulators and boards. To receive ethernet packets for any destination +address, the interface connected to the board needs to be in premiscuous mode. +Check premiscuous mode with the command: +```bash +ip -d link +# check for promiscuity 1 +``` +Set promiscuity to 1 with the command: +```bash +sudo ip link set [interface] promisc on +``` ## Dependencies diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py index c55d325d..578bcd3a 100755 --- a/iob_soc_opencryptolinux.py +++ b/iob_soc_opencryptolinux.py @@ -278,11 +278,9 @@ def _post_setup(cls): $(if $(findstring sim,$(MAKECMDGOALS))$(SIMULATOR),$(eval BOARD=)) ifeq ($(BOARD),AES-KU040-DB-G) ETH_IF ?=eno1 -RMAC_ADDR ?= 989096c0632c endif ifeq ($(BOARD),CYCLONEV-GT-DK) ETH_IF ?= enp0s31f6 -RMAC_ADDR ?= 309c231e624b endif # Set a MAC address for console (randomly generated) RMAC_ADDR ?=88431eafa897