diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index ac67601f..a03d0c22 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -29,8 +29,8 @@ jobs:
       - uses: actions/checkout@v3
         with:
           submodules: 'recursive'
-#      - name: test-clean
-#        run: make test-clean
+      - name: test-clean
+        run: make clean
       - name: test-pc-emul
         run: make pc-emul-run
 
@@ -45,8 +45,8 @@ jobs:
       - uses: actions/checkout@v3
         with:
           submodules: 'recursive'
-      #- name: test-clean
-      #  run: make test-clean
+      - name: test-clean
+        run: make clean
       - name: test-verilator
         run: make sim-run SIMULATOR=verilator VCD=0
 
@@ -59,8 +59,8 @@ jobs:
       - uses: actions/checkout@v3
         with:
           submodules: 'recursive'
-      #- name: test-clean
-      #  run: make test-clean
+      - name: test-clean
+        run: make clean
       - name: test-icarus
         run: make sim-run SIMULATOR=icarus VCD=0
 
diff --git a/Makefile b/Makefile
index dd7d9652..9a5e252a 100644
--- a/Makefile
+++ b/Makefile
@@ -27,8 +27,8 @@ TESTS+= AddRoundKey
 
 VERSAT_SPEC:=versatSpec.txt
 
-VCD ?= 1
-INIT_MEM ?= 1
+VCD ?= 0
+INIT_MEM ?= 0
 USE_EXTMEM ?= 1
 
 ifeq ($(INIT_MEM),1)
@@ -65,10 +65,10 @@ fpga-run:
 	make -C ../$(CORE)_V0.70_$(TEST)/ fpga-run BOARD=$(BOARD)
 
 sim-build:
-	+nix-shell --run 'make setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-build SIMULATOR=$(SIMULATOR) VCD=$(VCD)'
+	+nix-shell --run 'make setup INIT_MEM=1 USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-build SIMULATOR=$(SIMULATOR) VCD=$(VCD)'
 
 sim-run:
-	+nix-shell --run 'make setup INIT_MEM=$(INIT_MEM) USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-run SIMULATOR=$(SIMULATOR) VCD=$(VCD)'
+	+nix-shell --run 'make setup INIT_MEM=1 USE_EXTMEM=$(USE_EXTMEM) TEST=$(TEST) && make -C ../$(CORE)_V0.70_$(TEST)/ sim-run SIMULATOR=$(SIMULATOR) VCD=$(VCD)'
 
 fpga-run-only:
 	cp ./software/src/Tests/$(TEST).cpp ../$(CORE)_V0.70_$(TEST)/software/src/test.cpp
diff --git a/hardware/fpga/quartus/CYCLONEV-GT-DK/.gitkeep b/hardware/fpga/quartus/CYCLONEV-GT-DK/.gitkeep
new file mode 100644
index 00000000..e69de29b
diff --git a/versatSpec.txt b/versatSpec.txt
index 8ea5e0df..875af179 100644
--- a/versatSpec.txt
+++ b/versatSpec.txt
@@ -186,6 +186,10 @@ module TestMergeDelay2(){
    mem{5} -> output;
 }
 
+/*
+// Currently disabled since the generated accelerator uses the same name for different ports
+// and the fpga tools complain even when these are not used as top modules
+
 merge TestMergeDelay = TestMergeDelay1 | TestMergeDelay2;
 
 module TestMergeLargeDelay1(){
@@ -207,6 +211,7 @@ module TestMergeLargeDelay2(){
 }
 
 merge TestMergeLargeDelay = TestMergeLargeDelay1 | TestMergeLargeDelay2;
+*/
 
 module TestDoubleMerge00(){
    Const x00;