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Vivado.log critical errors related to the Ethernet and the "clk" constrains #611
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Is this fixed ? |
Hi professor, I do not think so. |
Please add command to reproduce |
We could solve both issues by generating iob-soc contrains with py2 scripts based on the values of |
Hello,
Issue Description:
There are a few critical warnings which I believe could be solved relatively easily.
A lot of the critical warnings present on the vivado.log file are related to the Ethernet constrains. This happens when the Ethernet is unused. The constraints are in the file iob_soc_fpga_wrapper_dev.sdc which is always included.
Another alarming warning is:
This is caused by the inclusion of the iob_soc_fpga_wrapper.sdc file even when the DDR is in use. On the Kintex UltraScale that makes the
create_clock -name "clk" -period $clk_period [get_ports "$clk_port"]
override the DDR clock constrains that are automatically created.Solution proposal:
Create a separate file for the Ethernet constrains. The constraints in no_ddr.sdc and in ddr.sdc ln.264 should also be removed.
Only add
create_clock -name "clk" -period $clk_period [get_ports "$clk_port"]
if USE_EXTMEM is not defined.The text was updated successfully, but these errors were encountered: