Testbench revamp

[jjts]

Let's formalize the test procedure instead of crafting a "testbench " for each IP core or IP (sub)system.

Before, we created the Tester system, now, we make the Test concept itself.

Applied to the Unit Under Test (UUT)

Using the Test Controller (TC: testbench or CPU) , with the aid of Test Instruments (TIs).

The TC connects to UUT and TIs using an AXI Interconnect (AXII).

UUT and TIs are connected as AXII slaves via an AXI-Lite bridge but can also be AXI masters of the AXII.

Testenches and Test Firmware may be generated from a common source.

Abstain from writing testbench code other than processor-like procedures. Instead, create an instrument that does what you need.

Perhaps the Testbench will be an IOb-FSM generated by py2 and synthesizable, in which case we can dispense with the CPU and run this synthesizable testbench in an FPGA.