forked from byungwoo733/riscv-ovpsim
-
Notifications
You must be signed in to change notification settings - Fork 0
/
riscvCSR.h
1460 lines (1200 loc) · 44.1 KB
/
riscvCSR.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied.
*
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#pragma once
// VMI header files
#include "vmi/vmiDbg.h"
#include "vmi/vmiTypes.h"
// model header files
#include "riscvMode.h"
#include "riscvRegisters.h"
#include "riscvTypeRefs.h"
#include "riscvVariant.h"
////////////////////////////////////////////////////////////////////////////////
// CSR ENUMERATION
////////////////////////////////////////////////////////////////////////////////
//
// Construct enumeration member name from register name
//
#define CSR_ID(_R) CSR_ID_##_R
//
// Construct enumeration member names from the given base and indices 0..9
//
#define CSR_ID_0_9(_R) \
CSR_ID(_R##0), \
CSR_ID(_R##1), \
CSR_ID(_R##2), \
CSR_ID(_R##3), \
CSR_ID(_R##4), \
CSR_ID(_R##5), \
CSR_ID(_R##6), \
CSR_ID(_R##7), \
CSR_ID(_R##8), \
CSR_ID(_R##9)
//
// Construct enumeration member names from the given base and indices 3..31
//
#define CSR_ID_3_31(_R) \
CSR_ID(_R##3), \
CSR_ID(_R##4), \
CSR_ID(_R##5), \
CSR_ID(_R##6), \
CSR_ID(_R##7), \
CSR_ID(_R##8), \
CSR_ID(_R##9), \
CSR_ID_0_9(_R##1), \
CSR_ID_0_9(_R##2), \
CSR_ID(_R##30), \
CSR_ID(_R##31)
//
// Construct enumeration member names from the given base and indices 0..3
//
#define CSR_ID_0_3(_R) \
CSR_ID(_R##0), \
CSR_ID(_R##1), \
CSR_ID(_R##2), \
CSR_ID(_R##3)
//
// Construct enumeration member names from the given base and indices 0..15
//
#define CSR_ID_0_15(_R) \
CSR_ID_0_9(_R), \
CSR_ID(_R##10), \
CSR_ID(_R##11), \
CSR_ID(_R##12), \
CSR_ID(_R##13), \
CSR_ID(_R##14), \
CSR_ID(_R##15)
//
// Identifiers for each implemented CSR
//
typedef enum riscvCSRIdE {
CSR_ID (ustatus), // 0x000
CSR_ID (fflags), // 0x001
CSR_ID (frm), // 0x002
CSR_ID (fcsr), // 0x003
CSR_ID (uie), // 0x004
CSR_ID (utvec), // 0x005
CSR_ID (vstart), // 0x008
CSR_ID (vxsat), // 0x009
CSR_ID (vxrm), // 0x00A
CSR_ID (vcsr), // 0x00F
CSR_ID (uscratch), // 0x040
CSR_ID (uepc), // 0x041
CSR_ID (ucause), // 0x042
CSR_ID (utval), // 0x043
CSR_ID (uip), // 0x044
CSR_ID (cycle), // 0xC00
CSR_ID (time), // 0xC01
CSR_ID (instret), // 0xC02
CSR_ID_3_31 (hpmcounter), // 0xC03-0xC1F
CSR_ID (vl), // 0xC20
CSR_ID (vtype), // 0xC21
CSR_ID (vlenb), // 0xC22
CSR_ID (cycleh), // 0xC80
CSR_ID (timeh), // 0xC80
CSR_ID (instreth), // 0xC80
CSR_ID_3_31 (hpmcounterh), // 0xC83-0xC9F
CSR_ID (sstatus), // 0x100
CSR_ID (sedeleg), // 0x102
CSR_ID (sideleg), // 0x103
CSR_ID (sie), // 0x104
CSR_ID (stvec), // 0x105
CSR_ID (scounteren), // 0x106
CSR_ID (sscratch), // 0x140
CSR_ID (sepc), // 0x141
CSR_ID (scause), // 0x142
CSR_ID (stval), // 0x143
CSR_ID (sip), // 0x144
CSR_ID (satp), // 0x180
CSR_ID (mvendorid), // 0xF11
CSR_ID (marchid), // 0xF12
CSR_ID (mimpid), // 0xF13
CSR_ID (mhartid), // 0xF14
CSR_ID (mstatus), // 0x300
CSR_ID (misa), // 0x301
CSR_ID (medeleg), // 0x302
CSR_ID (mideleg), // 0x303
CSR_ID (mie), // 0x304
CSR_ID (mtvec), // 0x305
CSR_ID (mcounteren), // 0x306
CSR_ID (mstatush), // 0x310
CSR_ID (mcountinhibit),// 0x320
CSR_ID (mscratch), // 0x340
CSR_ID (mepc), // 0x341
CSR_ID (mcause), // 0x342
CSR_ID (mtval), // 0x343
CSR_ID (mip), // 0x344
CSR_ID_0_3 (pmpcfg), // 0x3A0-0x3A3
CSR_ID_0_15 (pmpaddr), // 0x3B0-0x3BF
CSR_ID (mcycle), // 0xB00
CSR_ID (minstret), // 0xB02
CSR_ID_3_31 (mhpmcounter), // 0xB03-0xB1F
CSR_ID (mcycleh), // 0xB80
CSR_ID (minstreth), // 0xB82
CSR_ID_3_31 (mhpmcounterh), // 0xB83-0xB9F
CSR_ID_3_31 (mhpmevent), // 0x323-0x33F
CSR_ID (tselect), // 0x7A0
CSR_ID (tdata1), // 0x7A1
CSR_ID (tdata2), // 0x7A2
CSR_ID (tdata3), // 0x7A3
CSR_ID (dcsr), // 0x7B0
CSR_ID (dpc), // 0x7B1
CSR_ID (dscratch0), // 0x7B2
CSR_ID (dscratch1), // 0x7B3
// keep last (used to define size of the enumeration)
CSR_ID (LAST)
} riscvCSRId;
//
// CSRs in this range are accessible only in debug mode
//
#define CSR_DEGUG_START 0x7B0
#define CSR_DEGUG_END 0x7BF
#define IS_DEBUG_CSR(_NUM) (((_NUM)>=CSR_DEGUG_START) && ((_NUM)<=CSR_DEGUG_END))
////////////////////////////////////////////////////////////////////////////////
// INITIALIZATION
////////////////////////////////////////////////////////////////////////////////
//
// Initialize CSR state
//
void riscvCSRInit(riscvP riscv, Uns32 index);
//
// Free CSR state
//
void riscvCSRFree(riscvP riscv);
//
// Reset CSR state
//
void riscvCSRReset(riscvP riscv);
////////////////////////////////////////////////////////////////////////////////
// DISASSEMBLER INTERFACE ACCESS FUNCTIONS
////////////////////////////////////////////////////////////////////////////////
//
// Return CSR name for the given index number (or NULL if undefined)
//
const char *riscvGetCSRName(riscvP riscv, Uns32 csrNum);
////////////////////////////////////////////////////////////////////////////////
// DEBUG INTERFACE ACCESS FUNCTIONS
////////////////////////////////////////////////////////////////////////////////
//
// Read a CSR given its id
//
Bool riscvReadCSR(riscvCSRAttrsCP attrs, riscvP riscv, void *buffer);
//
// Write a CSR given its id
//
Bool riscvWriteCSR(riscvCSRAttrsCP attrs, riscvP riscv, const void *buffer);
////////////////////////////////////////////////////////////////////////////////
// MORPH-TIME INTERFACE ACCESS FUNCTIONS
////////////////////////////////////////////////////////////////////////////////
//
// Validate CSR with the given index can be accessed for read or write in the
// current processor mode, and return either a true CSR id or an error code id
//
riscvCSRAttrsCP riscvValidateCSRAccess(
riscvP riscv,
Uns32 csrNum,
Bool read,
Bool write
);
//
// Emit code to read a CSR
//
void riscvEmitCSRRead(
riscvCSRAttrsCP attrs,
riscvP riscv,
vmiReg rd,
Bool isWrite
);
//
// Emit code to write a CSR
//
void riscvEmitCSRWrite(
riscvCSRAttrsCP attrs,
riscvP riscv,
vmiReg rs,
vmiReg tmp
);
////////////////////////////////////////////////////////////////////////////////
// CSR ITERATOR AND REGISTRATION
////////////////////////////////////////////////////////////////////////////////
//
// Structure filled with CSR register details by riscvGetCSRDetails
//
typedef struct riscvCSRDetailsS {
riscvCSRAttrsCP attrs;
riscvMode mode;
Bool rdRaw;
Bool wrRaw;
Bool extension;
vmiReg raw;
vmiRegAccess access;
} riscvCSRDetails, *riscvCSRDetailsP;
//
// Iterator filling 'details' with the next CSR register details -
// 'details.name' should be initialized to NULL prior to the first call
//
Bool riscvGetCSRDetails(riscvP riscv, riscvCSRDetailsP details, Bool normal);
//
// Register new CSR
//
void riscvNewCSR(riscvCSRAttrsCP attrs, riscvP riscv);
////////////////////////////////////////////////////////////////////////////////
// COUNTER INHIBIT
////////////////////////////////////////////////////////////////////////////////
//
// Structure used when updating state when inhibit values change
//
typedef struct riscvCountStateS {
Bool inhibitCycle; // old value of cycle count inhibit
Bool inhibitInstret; // old value of retired instruction inhibit
Uns64 cycle; // cycle count before update
Uns64 instret; // retired instruction count before update
} riscvCountState, *riscvCountStateP;
//
// Get state before possible inhibit update
//
void riscvPreInhibit(riscvP riscv, riscvCountStateP state);
//
// Update state after possible inhibit update
//
void riscvPostInhibit(riscvP riscv, riscvCountStateP state, Bool preIncrement);
//
// Is cycle count inhibited?
//
Bool riscvInhibitCycle(riscvP riscv);
//
// Is retired instruction count inhibited?
//
Bool riscvInhibitInstret(riscvP riscv);
////////////////////////////////////////////////////////////////////////////////
// SAVE/RESTORE SUPPORT
////////////////////////////////////////////////////////////////////////////////
//
// Save CSR state not covered by register read/write API
//
void riscvCSRSave(
riscvP riscv,
vmiSaveContextP cxt,
vmiSaveRestorePhase phase
);
//
// Restore CSR state not covered by register read/write API
//
void riscvCSRRestore(
riscvP riscv,
vmiRestoreContextP cxt,
vmiSaveRestorePhase phase
);
////////////////////////////////////////////////////////////////////////////////
// POLYMORPHIC VECTOR BLOCK CONTROL
////////////////////////////////////////////////////////////////////////////////
//
// Refresh the vector polymorphic block key
//
void riscvRefreshVectorPMKey(riscvP riscv);
//
// Update vtype CSR
//
void riscvSetVType(riscvP riscv, Bool vill, Uns32 vsew, Uns32 vlmul);
//
// Update vl CSR and aliases of it
//
void riscvSetVL(riscvP riscv, Uns64 vl);
////////////////////////////////////////////////////////////////////////////////
// REGISTER DEFINITIONS
////////////////////////////////////////////////////////////////////////////////
//
// Use this to declare a 32-bit register type name
//
#define CSR_REG_TYPE_32(_N) riscvCSR32_##_N
//
// Use this to declare a 64-bit register type name
//
#define CSR_REG_TYPE_64(_N) riscvCSR64_##_N
//
// Use this to declare a register type name
//
#define CSR_REG_TYPE(_N) riscvCSR_##_N
//
// Use this to declare a register with 32-bit view only (zero-extended to 64)
//
#define CSR_REG_STRUCT_DECL_32(_N) typedef union { \
union { \
Uns32 bits; \
CSR_REG_TYPE_32(_N) fields; \
} u32; \
union { \
Uns64 bits; \
CSR_REG_TYPE_32(_N) fields; \
} u64; \
} CSR_REG_TYPE(_N)
//
// Use this to declare a register with 32-bit view equivalent to lower half of
// 64-bit view
//
#define CSR_REG_STRUCT_DECL_64(_N) typedef union { \
union { \
Uns32 bits; \
CSR_REG_TYPE_64(_N) fields; \
} u32; \
union { \
Uns64 bits; \
CSR_REG_TYPE_64(_N) fields; \
} u64; \
} CSR_REG_TYPE(_N)
//
// Use this to declare a register with distinct 32/64 bit views
//
#define CSR_REG_STRUCT_DECL_32_64(_N) typedef struct { \
union { \
Uns32 bits; \
CSR_REG_TYPE_32(_N) fields; \
} u32; \
union { \
Uns64 bits; \
CSR_REG_TYPE_64(_N) fields; \
} u64; \
} CSR_REG_TYPE(_N)
//
// Use this to declare a register with distinct 32/64 bit views handled as a
// union
//
#define CSR_REG_STRUCT_DECL_32_64_U(_N) typedef union { \
union { \
Uns32 bits; \
CSR_REG_TYPE_32(_N) fields; \
} u32; \
union { \
Uns64 bits; \
CSR_REG_TYPE_64(_N) fields; \
} u64; \
} CSR_REG_TYPE(_N)
// -----------------------------------------------------------------------------
// generic 32-bit register
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 value;
} CSR_REG_TYPE_32(generic32);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(generic32);
// -----------------------------------------------------------------------------
// generic XLEN-width register
// -----------------------------------------------------------------------------
// 64-bit view
typedef struct {
Uns64 value;
} CSR_REG_TYPE_64(genericXLEN);
// define 32/64 bit type
CSR_REG_STRUCT_DECL_64(genericXLEN);
// -----------------------------------------------------------------------------
// ustatus (id 0x000)
// sstatus (id 0x100)
// mstatus (id 0x300)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 UIE : 1; // User mode interrupt enable, N only
Uns32 SIE : 1; // Supervisor mode interrupt enable
Uns32 _u0 : 1;
Uns32 MIE : 1; // Machine mode interrupt enable
Uns32 UPIE : 1; // User mode interrupt enable (stacked), N only
Uns32 SPIE : 1; // Supervisor mode interrupt enable (stacked)
Uns32 UBE : 1; // User mode big-endian
Uns32 MPIE : 1; // Machine mode interrupt enable (stacked)
Uns32 SPP : 1; // Supervisor previous mode
Uns32 VS_9 : 2; // Vector Extension dirty state (version 0.9)
Uns32 MPP : 2; // Machine previous mode
Uns32 FS : 2; // Floating point dirty state
Uns32 XS : 2; // User extension dirty state
Uns32 MPRV : 1; // Modify privilege (requires U extension)
Uns32 SUM : 1; // Permit Supervisor User access (requires S extension)
Uns32 MXR : 1; // Make executable readable (requires S extension)
Uns32 TVM : 1; // Trap virtual memory (requires S extension)
Uns32 TW : 1; // Timeout wait (requires S extension)
Uns32 TSR : 1; // Trap SRET (requires S extension)
Uns32 VS_8 : 2; // Vector Extension dirty state (version 0.8)
Uns32 _u3 : 6;
Uns32 SD : 1; // Dirty state summary bit (read only)
} CSR_REG_TYPE_32(status);
// 64-bit view
typedef struct {
Uns64 UIE : 1; // User mode interrupt enable, N only
Uns64 SIE : 1; // Supervisor mode interrupt enable
Uns64 _u0 : 1;
Uns64 MIE : 1; // Machine mode interrupt enable
Uns64 UPIE : 1; // User mode interrupt enable (stacked), N only
Uns64 SPIE : 1; // Supervisor mode interrupt enable (stacked)
Uns64 UBE : 1; // User mode big-endian
Uns64 MPIE : 1; // Machine mode interrupt enable (stacked)
Uns64 SPP : 1; // Supervisor previous mode
Uns32 VS_9 : 2; // Vector Extension dirty state (version 0.9)
Uns64 MPP : 2; // Machine previous mode
Uns64 FS : 2; // Floating point dirty state
Uns64 XS : 2; // User extension dirty state
Uns64 MPRV : 1; // Modify privilege (requires U extension)
Uns64 SUM : 1; // Permit Supervisor User access (requires S extension)
Uns64 MXR : 1; // Make executable readable (requires S extension)
Uns64 TVM : 1; // Trap virtual memory (requires S extension)
Uns64 TW : 1; // Timeout wait (requires S extension)
Uns64 TSR : 1; // Trap SRET (requires S extension)
Uns32 VS_8 : 2; // Vector Extension dirty state (version 0.8)
Uns64 _u3 : 7;
Uns64 UXL : 2; // TODO: User mode XLEN
Uns64 SXL : 2; // TODO: Supervisor mode XLEN
Uns64 SBE : 1; // Supervisor mode big-endian
Uns64 MBE : 1; // Machine mode big-endian
Uns64 _u4 : 25;
Uns64 SD : 1; // Dirty state summary bit (read only)
} CSR_REG_TYPE_64(status);
// define 32/64 bit type
CSR_REG_STRUCT_DECL_32_64_U(status);
// define alias types
typedef CSR_REG_TYPE(status) CSR_REG_TYPE(ustatus);
typedef CSR_REG_TYPE(status) CSR_REG_TYPE(sstatus);
typedef CSR_REG_TYPE(status) CSR_REG_TYPE(mstatus);
// define alias masks
#define sstatus_AMASK 0x80000003818de133ULL
#define ustatus_AMASK 0x0000000000000011ULL
// define bit masks
#define WM_mstatus_FS (3<<13)
#define WM_mstatus_TVM (1<<20)
#define WM_mstatus_TW (1<<21)
#define WM_mstatus_TSR (1<<22)
#define WM_mstatus_VS_8 (3<<23)
#define WM_mstatus_VS_9 (3<<9)
#define WM_mstatus_IE 0xf
#define WM_mstatus_UBE (1<<6)
#define WM_mstatus_SBE (1ULL<<36)
#define WM_mstatus_MBE (1ULL<<37)
#define WM_mstatus_BE (WM_mstatus_UBE|WM_mstatus_SBE|WM_mstatus_MBE)
// -----------------------------------------------------------------------------
// mstatush (id 0x310)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 _u0 : 4;
Uns32 SBE : 1;
Uns32 MBE : 1;
Uns32 _u1 : 26;
} CSR_REG_TYPE_32(mstatush);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(mstatush);
// write masks
#define WM_mstatush_SBE (1ULL<<4)
#define WM_mstatush_MBE (1ULL<<5)
#define WM_mstatush_BE (WM_mstatush_SBE|WM_mstatush_MBE)
// -----------------------------------------------------------------------------
// fflags (id 0x001)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 NX : 1;
Uns32 UF : 1;
Uns32 OF : 1;
Uns32 DZ : 1;
Uns32 NV : 1;
Uns32 _u0 : 27;
} CSR_REG_TYPE_32(fflags);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(fflags);
// write masks
#define WM32_fflags 0x1f
// -----------------------------------------------------------------------------
// frm (id 0x002)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 frm : 3;
Uns32 _u0 : 29;
} CSR_REG_TYPE_32(frm);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(frm);
// write masks
#define WM32_frm 0x7
// -----------------------------------------------------------------------------
// fcsr (id 0x003)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 NX : 1;
Uns32 UF : 1;
Uns32 OF : 1;
Uns32 DZ : 1;
Uns32 NV : 1;
Uns32 frm : 3;
Uns32 vxsat : 1; // Vector Version 0.8 only
Uns32 vxrm : 2; // Vector Version 0.8 only
Uns32 _u0 : 21;
} CSR_REG_TYPE_32(fcsr);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(fcsr);
// write masks
#define WM32_fcsr_f 0x0ff
#define WM32_fcsr_v 0x700
#define WM32_fcsr_frm_msb 0x080
// -----------------------------------------------------------------------------
// misa (id 0x301)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns64 Extensions : 26;
Uns64 _u1 : 4;
Uns64 MXL : 2;
} CSR_REG_TYPE_32(isa);
// 64-bit view
typedef struct {
Uns64 Extensions : 26;
Uns64 _u1 : 36;
Uns64 MXL : 2;
} CSR_REG_TYPE_64(isa);
// define 32/64 bit type
CSR_REG_STRUCT_DECL_32_64(isa);
// define alias types
typedef CSR_REG_TYPE(isa) CSR_REG_TYPE(misa);
// -----------------------------------------------------------------------------
// sedeleg (id 0x102)
// medeleg (id 0x302)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 SynchronousExceptions;
} CSR_REG_TYPE_32(edeleg);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(edeleg);
// define alias types
typedef CSR_REG_TYPE(edeleg) CSR_REG_TYPE(sedeleg);
typedef CSR_REG_TYPE(edeleg) CSR_REG_TYPE(medeleg);
// -----------------------------------------------------------------------------
// sideleg (id 0x103)
// mideleg (id 0x303)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 Interrupts;
} CSR_REG_TYPE_32(ideleg);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(ideleg);
// define alias types
typedef CSR_REG_TYPE(ideleg) CSR_REG_TYPE(sideleg);
typedef CSR_REG_TYPE(ideleg) CSR_REG_TYPE(mideleg);
// -----------------------------------------------------------------------------
// uie (id 0x004)
// sie (id 0x104)
// mie (id 0x304)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 USIE : 1;
Uns32 SSIE : 1;
Uns32 _u0 : 1;
Uns32 MSIE : 1;
Uns32 UTIE : 1;
Uns32 STIE : 1;
Uns32 _u1 : 1;
Uns32 MTIE : 1;
Uns32 UEIE : 1;
Uns32 SEIE : 1;
Uns32 _u2 : 1;
Uns32 MEIE : 1;
} CSR_REG_TYPE_32(ie);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(ie);
// define alias types
typedef CSR_REG_TYPE(ie) CSR_REG_TYPE(uie);
typedef CSR_REG_TYPE(ie) CSR_REG_TYPE(sie);
typedef CSR_REG_TYPE(ie) CSR_REG_TYPE(mie);
// -----------------------------------------------------------------------------
// utvec (id 0x005)
// stvec (id 0x105)
// mtvec (id 0x305)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 MODE : 2;
Uns32 BASE : 30;
} CSR_REG_TYPE_32(tvec);
// 64-bit view
typedef struct {
Uns64 MODE : 2;
Uns64 BASE : 62;
} CSR_REG_TYPE_64(tvec);
// define 32/64 bit type
CSR_REG_STRUCT_DECL_32_64_U(tvec);
// define alias types
typedef CSR_REG_TYPE(tvec) CSR_REG_TYPE(utvec);
typedef CSR_REG_TYPE(tvec) CSR_REG_TYPE(stvec);
typedef CSR_REG_TYPE(tvec) CSR_REG_TYPE(mtvec);
// define write masks
#define WM32_utvec -3
#define WM32_stvec -3
#define WM32_mtvec -3
#define WM64_utvec -3
#define WM64_stvec -3
#define WM64_mtvec -3
// -----------------------------------------------------------------------------
// scounteren (id 0x106)
// mcounteren (id 0x306)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 CY : 1;
Uns32 TM : 1;
Uns32 IR : 1;
Uns32 HPM : 29;
} CSR_REG_TYPE_32(counteren);
// define 32 bit type
CSR_REG_STRUCT_DECL_32(counteren);
// define alias types
typedef CSR_REG_TYPE(counteren) CSR_REG_TYPE(scounteren);
typedef CSR_REG_TYPE(counteren) CSR_REG_TYPE(mcounteren);
// define write masks
#define WM32_counteren_CY 0x00000001
#define WM32_counteren_TM 0x00000002
#define WM32_counteren_IR 0x00000004
#define WM32_counteren_HPM 0xfffffff8
// -----------------------------------------------------------------------------
// mcountinhibit (id 0x320)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(counteren) CSR_REG_TYPE(mcountinhibit);
// -----------------------------------------------------------------------------
// mhpmevent (id 0x323-0x33F)
// -----------------------------------------------------------------------------
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(mhpmevent);
// -----------------------------------------------------------------------------
// uscratch (id 0x040)
// sscratch (id 0x140)
// mscratch (id 0x340)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(uscratch);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(sscratch);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(mscratch);
// -----------------------------------------------------------------------------
// uepc (id 0x041)
// sepc (id 0x141)
// mepc (id 0x341)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(uepc);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(sepc);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(mepc);
// -----------------------------------------------------------------------------
// ucause (id 0x042)
// scause (id 0x142)
// mcause (id 0x342)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 ExceptionCode : 31;
Uns32 Interrupt : 1;
} CSR_REG_TYPE_32(cause);
// 64-bit view
typedef struct {
Uns64 ExceptionCode : 63;
Uns64 Interrupt : 1;
} CSR_REG_TYPE_64(cause);
// define 32/64 bit type
CSR_REG_STRUCT_DECL_32_64(cause);
// define alias types
typedef CSR_REG_TYPE(cause) CSR_REG_TYPE(ucause);
typedef CSR_REG_TYPE(cause) CSR_REG_TYPE(scause);
typedef CSR_REG_TYPE(cause) CSR_REG_TYPE(mcause);
// -----------------------------------------------------------------------------
// utval (id 0x041)
// stval (id 0x141)
// mtval (id 0x341)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(utval);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(stval);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(mtval);
// -----------------------------------------------------------------------------
// uip (id 0x044)
// sip (id 0x144)
// mip (id 0x344)
// -----------------------------------------------------------------------------
// 64-bit view
typedef struct {
Uns32 USIP : 1;
Uns32 SSIP : 1;
Uns32 _u0 : 1;
Uns32 MSIP : 1;
Uns32 UTIP : 1;
Uns32 STIP : 1;
Uns32 _u1 : 1;
Uns32 MTIP : 1;
Uns32 UEIP : 1;
Uns32 SEIP : 1;
Uns32 _u2 : 1;
Uns32 MEIP : 1;
Uns32 _u3 : 4;
Uns64 LI : 48;
} CSR_REG_TYPE_64(ip);
// define 32 bit type
CSR_REG_STRUCT_DECL_64(ip);
// define alias types
typedef CSR_REG_TYPE(ip) CSR_REG_TYPE(uip);
typedef CSR_REG_TYPE(ip) CSR_REG_TYPE(sip);
typedef CSR_REG_TYPE(ip) CSR_REG_TYPE(mip);
// define write masks
#define WM32_ip 0x00000fff
#define WM32_mip 0x00000333
#define WM32_sip 0x00000103
#define WM32_uip 0x00000001
// -----------------------------------------------------------------------------
// pmpcfg (id 0x3A0-0x3A3)
// -----------------------------------------------------------------------------
// define write masks
#define WM64_pmpcfg 0x9f9f9f9f9f9f9f9fULL
// -----------------------------------------------------------------------------
// pmpaddr (id 0x3B0-0x3BF)
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// satp (id 0x180)
// -----------------------------------------------------------------------------
// 32-bit view
typedef struct {
Uns32 PPN : 22;
Uns32 ASID : 9;
Uns32 MODE : 1;
} CSR_REG_TYPE_32(atp);
// 64-bit view
typedef struct {
Uns64 PPN : 44;
Uns64 ASID : 16;
Uns64 MODE : 4;
} CSR_REG_TYPE_64(atp);
// define 32/64 bit type
CSR_REG_STRUCT_DECL_32_64(atp);
// define alias types
typedef CSR_REG_TYPE(atp) CSR_REG_TYPE(satp);
// -----------------------------------------------------------------------------
// mcycle (id 0xB00)
// cycle (id 0xC00)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(mcycle);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(cycle);
// -----------------------------------------------------------------------------
// time (id 0xC01)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(time);
// -----------------------------------------------------------------------------
// minstret (id 0xB02)
// instret (id 0xC02)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(minstret);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(instret);
// -----------------------------------------------------------------------------
// mhpmcounter (id 0xB03-0xB1F)
// hpmcounter (id 0xC03-0xC1F)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(mhpmcounter);
typedef CSR_REG_TYPE(genericXLEN) CSR_REG_TYPE(hpmcounter);
// -----------------------------------------------------------------------------
// mcycleh (id 0xB80)
// cycleh (id 0xC80)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(generic32) CSR_REG_TYPE(mcycleh);
typedef CSR_REG_TYPE(generic32) CSR_REG_TYPE(cycleh);
// -----------------------------------------------------------------------------
// timeh (id 0xC81)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(generic32) CSR_REG_TYPE(timeh);
// -----------------------------------------------------------------------------
// minstreth (id 0xB82)
// instreth (id 0xC82)
// -----------------------------------------------------------------------------
// define alias types
typedef CSR_REG_TYPE(generic32) CSR_REG_TYPE(minstreth);
typedef CSR_REG_TYPE(generic32) CSR_REG_TYPE(instreth);